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ASoC: sdp4430: Enable FM stereo pins
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
c8bf93f0
PU		 39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
4260393e
PU		 51#define MODE7_LTHR 10
52#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
53
76f47127
PU		 54#define BURST_BASEFREQ_HZ 49152000
55
f57d2cfa
PU		 56#define SAMPLES_TO_US(rate, samples) \
57 (1000000000 / ((rate * 1000) / samples))
58
59#define US_TO_SAMPLES(rate, us) \
d54e1f4f 60 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
f57d2cfa 61
a577b318
PU		 62#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
63 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
64
ad05c03b
PU		 65static void dac33_calculate_times(struct snd_pcm_substream *substream);
66static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 67
c8bf93f0
PU		 68enum dac33_state {
69 DAC33_IDLE = 0,
70 DAC33_PREFILL,
71 DAC33_PLAYBACK,
72 DAC33_FLUSH,
73};
74
7427b4b9
PU		 75enum dac33_fifo_modes {
76 DAC33_FIFO_BYPASS = 0,
77 DAC33_FIFO_MODE1,
28e05d98 78 DAC33_FIFO_MODE7,
7427b4b9
PU		 79 DAC33_FIFO_LAST_MODE,
80};
81
3a7aaed7
IK		 82#define DAC33_NUM_SUPPLIES 3
83static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
84 "AVDD",
85 "DVDD",
86 "IOVDD",
87};
88
c8bf93f0
PU		 89struct tlv320dac33_priv {
90 struct mutex mutex;
91 struct workqueue_struct *dac33_wq;
92 struct work_struct work;
f0fba2ad 93 struct snd_soc_codec *codec;
3a7aaed7 94 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 95 struct snd_pcm_substream *substream;
c8bf93f0
PU		 96 int power_gpio;
97 int chip_power;
98 int irq;
99 unsigned int refclk;
100
101 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
102 unsigned int nsample_min; /* nsample should not be lower than
103 * this */
104 unsigned int nsample_max; /* nsample should not be higher than
105 * this */
7427b4b9 106 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 107 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 108 int mode1_latency; /* latency caused by the i2c writes in
109 * us */
a577b318
PU		 110 int auto_fifo_config; /* Configure the FIFO based on the
111 * period size */
6aceabb4 112 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 113 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 114
eeb309a8
PU		 115 int keep_bclk; /* Keep the BCLK continuously running
116 * in FIFO modes */
f57d2cfa
PU		 117 spinlock_t lock;
118 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
119 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
120
121 unsigned int mode1_us_burst; /* Time to burst read n number of
122 * samples */
123 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 124
9d7db2b2
PU		 125 unsigned int uthr;
126
c8bf93f0 127 enum dac33_state state;
f0fba2ad
LG		 128 enum snd_soc_control_type control_type;
129 void *control_data;
c8bf93f0
PU		 130};
131
132static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1330x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1340x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1350x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1360x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1370x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1380x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1390x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1400x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1410x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1420x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1430x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1440x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1450x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1460x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1470x00, 0x00, /* 0x38 - 0x39 */
148/* Registers 0x3a - 0x3f are reserved */
149 0x00, 0x00, /* 0x3a - 0x3b */
1500x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
151
1520x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1530x00, 0x80, /* 0x44 - 0x45 */
154/* Registers 0x46 - 0x47 are reserved */
155 0x80, 0x80, /* 0x46 - 0x47 */
156
1570x80, 0x00, 0x00, /* 0x48 - 0x4a */
158/* Registers 0x4b - 0x7c are reserved */
159 0x00, /* 0x4b */
1600x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1610x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1620x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1630x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1640x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1650x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1660x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1670x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1680x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1690x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1700x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1710x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1720x00, /* 0x7c */
173
174 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
175};
176
177/* Register read and write */
178static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
179 unsigned reg)
180{
181 u8 *cache = codec->reg_cache;
182 if (reg >= DAC33_CACHEREGNUM)
183 return 0;
184
185 return cache[reg];
186}
187
188static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
189 u8 reg, u8 value)
190{
191 u8 *cache = codec->reg_cache;
192 if (reg >= DAC33_CACHEREGNUM)
193 return;
194
195 cache[reg] = value;
196}
197
198static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
199 u8 *value)
200{
b2c812e2 201 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 202 int val, ret = 0;
c8bf93f0
PU		 203
204 *value = reg & 0xff;
205
206 /* If powered off, return the cached value */
207 if (dac33->chip_power) {
208 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
209 if (val < 0) {
210 dev_err(codec->dev, "Read failed (%d)\n", val);
211 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 212 ret = val;
c8bf93f0
PU		 213 } else {
214 value[0] = val;
215 dac33_write_reg_cache(codec, reg, val);
216 }
217 } else {
218 value[0] = dac33_read_reg_cache(codec, reg);
219 }
220
911a0f0b 221 return ret;
c8bf93f0
PU		 222}
223
224static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
225 unsigned int value)
226{
b2c812e2 227 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 228 u8 data[2];
229 int ret = 0;
230
231 /*
232 * data is
233 * D15..D8 dac33 register offset
234 * D7...D0 register data
235 */
236 data[0] = reg & 0xff;
237 data[1] = value & 0xff;
238
239 dac33_write_reg_cache(codec, data[0], data[1]);
240 if (dac33->chip_power) {
241 ret = codec->hw_write(codec->control_data, data, 2);
242 if (ret != 2)
243 dev_err(codec->dev, "Write failed (%d)\n", ret);
244 else
245 ret = 0;
246 }
247
248 return ret;
249}
250
251static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
252 unsigned int value)
253{
b2c812e2 254 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 255 int ret;
256
257 mutex_lock(&dac33->mutex);
258 ret = dac33_write(codec, reg, value);
259 mutex_unlock(&dac33->mutex);
260
261 return ret;
262}
263
264#define DAC33_I2C_ADDR_AUTOINC 0x80
265static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
266 unsigned int value)
267{
b2c812e2 268 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 269 u8 data[3];
270 int ret = 0;
271
272 /*
273 * data is
274 * D23..D16 dac33 register offset
275 * D15..D8 register data MSB
276 * D7...D0 register data LSB
277 */
278 data[0] = reg & 0xff;
279 data[1] = (value >> 8) & 0xff;
280 data[2] = value & 0xff;
281
282 dac33_write_reg_cache(codec, data[0], data[1]);
283 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
284
285 if (dac33->chip_power) {
286 /* We need to set autoincrement mode for 16 bit writes */
287 data[0] |= DAC33_I2C_ADDR_AUTOINC;
288 ret = codec->hw_write(codec->control_data, data, 3);
289 if (ret != 3)
290 dev_err(codec->dev, "Write failed (%d)\n", ret);
291 else
292 ret = 0;
293 }
294
295 return ret;
296}
297
ef909d67 298static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 299{
b2c812e2 300 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 301
ef909d67 302 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 303 return;
304
ef909d67
PU		 305 /* 44-46: DAC Control Registers */
306 /* A : DAC sample rate Fsref/1.5 */
307 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
308 /* B : DAC src=normal, not muted */
309 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
310 DAC33_DACSRCL_LEFT);
311 /* C : (defaults) */
312 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
313
ef909d67
PU		 314 /* 73 : volume soft stepping control,
315 clock source = internal osc (?) */
316 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
317
ef909d67
PU		 318 /* Restore only selected registers (gains mostly) */
319 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
320 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
321 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
322 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
323
324 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
325 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
326 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
327 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 328}
329
911a0f0b 330static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 331{
911a0f0b 332 int i, ret = 0;
239fe55c
PU		 333 u8 reg;
334
911a0f0b
PU		 335 for (i = 0; i < 3; i++) {
336 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
337 if (ret < 0)
338 break;
339 }
340
341 return ret;
c8bf93f0
PU		 342}
343
344static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
345{
346 u8 reg;
347
348 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
349 if (power)
350 reg |= DAC33_PDNALLB;
351 else
c3746a07
PU		 352 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
353 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 354 dac33_write(codec, DAC33_PWR_CTRL, reg);
355}
356
3a7aaed7 357static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 358{
b2c812e2 359 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 360 int ret = 0;
c8bf93f0
PU		 361
362 mutex_lock(&dac33->mutex);
ad05c03b
PU		 363
364 /* Safety check */
365 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 366 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 367 power ? "ON" : "OFF");
368 goto exit;
369 }
370
c8bf93f0 371 if (power) {
3a7aaed7
IK		 372 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
373 dac33->supplies);
374 if (ret != 0) {
375 dev_err(codec->dev,
376 "Failed to enable supplies: %d\n", ret);
377 goto exit;
c8bf93f0 378 }
3a7aaed7
IK		 379
380 if (dac33->power_gpio >= 0)
381 gpio_set_value(dac33->power_gpio, 1);
382
383 dac33->chip_power = 1;
c8bf93f0
PU		 384 } else {
385 dac33_soft_power(codec, 0);
3a7aaed7 386 if (dac33->power_gpio >= 0)
c8bf93f0 387 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 388
389 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
390 dac33->supplies);
391 if (ret != 0) {
392 dev_err(codec->dev,
393 "Failed to disable supplies: %d\n", ret);
394 goto exit;
c8bf93f0 395 }
3a7aaed7
IK		 396
397 dac33->chip_power = 0;
c8bf93f0 398 }
c8bf93f0 399
3a7aaed7
IK		 400exit:
401 mutex_unlock(&dac33->mutex);
402 return ret;
c8bf93f0
PU		 403}
404
ad05c03b
PU		 405static int playback_event(struct snd_soc_dapm_widget *w,
406 struct snd_kcontrol *kcontrol, int event)
407{
408 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
409
410 switch (event) {
411 case SND_SOC_DAPM_PRE_PMU:
412 if (likely(dac33->substream)) {
413 dac33_calculate_times(dac33->substream);
414 dac33_prepare_chip(dac33->substream);
415 }
416 break;
417 }
418 return 0;
419}
420
c8bf93f0
PU		 421static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 426
427 ucontrol->value.integer.value[0] = dac33->nsample;
428
429 return 0;
430}
431
432static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
433 struct snd_ctl_elem_value *ucontrol)
434{
435 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 436 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 437 int ret = 0;
438
439 if (dac33->nsample == ucontrol->value.integer.value[0])
440 return 0;
441
442 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 443 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 444 ret = -EINVAL;
f57d2cfa 445 } else {
c8bf93f0 446 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 447 /* Re calculate the burst time */
448 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
449 dac33->nsample);
450 }
c8bf93f0
PU		 451
452 return ret;
453}
454
9d7db2b2
PU		 455static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
457{
458 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
459 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
460
461 ucontrol->value.integer.value[0] = dac33->uthr;
462
463 return 0;
464}
465
466static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_value *ucontrol)
468{
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
470 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
471 int ret = 0;
472
473 if (dac33->substream)
474 return -EBUSY;
475
476 if (dac33->uthr == ucontrol->value.integer.value[0])
477 return 0;
478
479 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
480 ucontrol->value.integer.value[0] > MODE7_UTHR)
481 ret = -EINVAL;
482 else
483 dac33->uthr = ucontrol->value.integer.value[0];
484
485 return ret;
486}
487
7427b4b9 488static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 489 struct snd_ctl_elem_value *ucontrol)
490{
491 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 492 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 493
7427b4b9 494 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 495
496 return 0;
497}
498
7427b4b9 499static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 500 struct snd_ctl_elem_value *ucontrol)
501{
502 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 503 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 504 int ret = 0;
505
7427b4b9 506 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 507 return 0;
508 /* Do not allow changes while stream is running*/
509 if (codec->active)
510 return -EPERM;
511
512 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 513 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 514 ret = -EINVAL;
515 else
7427b4b9 516 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 517
518 return ret;
519}
520
7427b4b9
PU		 521/* Codec operation modes */
522static const char *dac33_fifo_mode_texts[] = {
28e05d98 523 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 524};
525
526static const struct soc_enum dac33_fifo_mode_enum =
527 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
528 dac33_fifo_mode_texts);
529
cf4bb698
PU		 530/* L/R Line Output Gain */
531static const char *lr_lineout_gain_texts[] = {
532 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
533 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
534};
535
536static const struct soc_enum l_lineout_gain_enum =
537 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
538 ARRAY_SIZE(lr_lineout_gain_texts),
539 lr_lineout_gain_texts);
540
541static const struct soc_enum r_lineout_gain_enum =
542 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
543 ARRAY_SIZE(lr_lineout_gain_texts),
544 lr_lineout_gain_texts);
545
c8bf93f0
PU		 546/*
547 * DACL/R digital volume control:
548 * from 0 dB to -63.5 in 0.5 dB steps
549 * Need to be inverted later on:
550 * 0x00 == 0 dB
551 * 0x7f == -63.5 dB
552 */
553static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
554
555static const struct snd_kcontrol_new dac33_snd_controls[] = {
556 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
557 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
558 0, 0x7f, 1, dac_digivol_tlv),
559 SOC_DOUBLE_R("DAC Digital Playback Switch",
560 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
561 SOC_DOUBLE_R("Line to Line Out Volume",
562 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 563 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
564 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 565};
566
a577b318
PU		 567static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
568 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
569 dac33_get_fifo_mode, dac33_set_fifo_mode),
570};
571
572static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
c8bf93f0 573 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
a577b318 574 dac33_get_nsample, dac33_set_nsample),
9d7db2b2
PU		 575 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
576 dac33_get_uthr, dac33_set_uthr),
c8bf93f0
PU		 577};
578
579/* Analog bypass */
580static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
581 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
582
583static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
584 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
585
586static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
587 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
588 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
589
590 SND_SOC_DAPM_INPUT("LINEL"),
591 SND_SOC_DAPM_INPUT("LINER"),
592
76eac39c
PU		 593 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
594 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 595
596 /* Analog bypass */
597 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
598 &dac33_dapm_abypassl_control),
599 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
600 &dac33_dapm_abypassr_control),
601
9e87186f 602 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 603 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 604 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 605 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 606
76eac39c
PU		 607 SND_SOC_DAPM_SUPPLY("Left DAC Power",
608 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
609 SND_SOC_DAPM_SUPPLY("Right DAC Power",
610 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
611
ad05c03b 612 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
c8bf93f0
PU		 613};
614
615static const struct snd_soc_dapm_route audio_map[] = {
616 /* Analog bypass */
617 {"Analog Left Bypass", "Switch", "LINEL"},
618 {"Analog Right Bypass", "Switch", "LINER"},
619
9e87186f
PU		 620 {"Output Left Amplifier", NULL, "DACL"},
621 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 622
9e87186f
PU		 623 {"Output Left Amplifier", NULL, "Analog Left Bypass"},
624 {"Output Right Amplifier", NULL, "Analog Right Bypass"},
c8bf93f0 625
76eac39c
PU		 626 {"Output Left Amplifier", NULL, "Left DAC Power"},
627 {"Output Right Amplifier", NULL, "Right DAC Power"},
628
c8bf93f0 629 /* output */
9e87186f
PU		 630 {"LEFT_LO", NULL, "Output Left Amplifier"},
631 {"RIGHT_LO", NULL, "Output Right Amplifier"},
c8bf93f0
PU		 632};
633
634static int dac33_add_widgets(struct snd_soc_codec *codec)
635{
ce6120cc 636 struct snd_soc_dapm_context *dapm = &codec->dapm;
c8bf93f0 637
ce6120cc
LG		 638 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
639 ARRAY_SIZE(dac33_dapm_widgets));
c8bf93f0 640 /* set up audio path interconnects */
ce6120cc 641 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 642
643 return 0;
644}
645
646static int dac33_set_bias_level(struct snd_soc_codec *codec,
647 enum snd_soc_bias_level level)
648{
3ee4fe15 649 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7
IK		 650 int ret;
651
c8bf93f0
PU		 652 switch (level) {
653 case SND_SOC_BIAS_ON:
3e202345
PU		 654 if (!dac33->substream)
655 dac33_soft_power(codec, 1);
c8bf93f0
PU		 656 break;
657 case SND_SOC_BIAS_PREPARE:
658 break;
659 case SND_SOC_BIAS_STANDBY:
ce6120cc 660 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 661 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 662 ret = dac33_hard_power(codec, 1);
663 if (ret != 0)
664 return ret;
3a7aaed7 665
ad05c03b
PU		 666 dac33_init_chip(codec);
667 }
c8bf93f0
PU		 668 break;
669 case SND_SOC_BIAS_OFF:
2d4cdd6f 670 /* Do not power off, when the codec is already off */
ce6120cc 671 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2d4cdd6f 672 return 0;
3a7aaed7
IK		 673 ret = dac33_hard_power(codec, 0);
674 if (ret != 0)
675 return ret;
c8bf93f0
PU		 676 break;
677 }
ce6120cc 678 codec->dapm.bias_level = level;
c8bf93f0
PU		 679
680 return 0;
681}
682
d4f102d4
PU		 683static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
684{
f0fba2ad 685 struct snd_soc_codec *codec = dac33->codec;
84eae18c 686 unsigned int delay;
d4f102d4
PU		 687
688 switch (dac33->fifo_mode) {
689 case DAC33_FIFO_MODE1:
690 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 691 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 692
693 /* Take the timestamps */
694 spin_lock_irq(&dac33->lock);
695 dac33->t_stamp2 = ktime_to_us(ktime_get());
696 dac33->t_stamp1 = dac33->t_stamp2;
697 spin_unlock_irq(&dac33->lock);
698
d4f102d4
PU		 699 dac33_write16(codec, DAC33_PREFILL_MSB,
700 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 701 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 702 delay = SAMPLES_TO_US(dac33->burst_rate,
703 dac33->alarm_threshold) + 1000;
704 usleep_range(delay, delay + 500);
f4d59328 705 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 706 break;
28e05d98 707 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 708 /* Take the timestamp */
709 spin_lock_irq(&dac33->lock);
710 dac33->t_stamp1 = ktime_to_us(ktime_get());
711 /* Move back the timestamp with drain time */
712 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
713 spin_unlock_irq(&dac33->lock);
714
28e05d98 715 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 716 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 717
718 /* Enable Upper Threshold IRQ */
719 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 720 break;
d4f102d4
PU		 721 default:
722 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
723 dac33->fifo_mode);
724 break;
725 }
726}
727
728static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
729{
f0fba2ad 730 struct snd_soc_codec *codec = dac33->codec;
d4f102d4
PU		 731
732 switch (dac33->fifo_mode) {
733 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 734 /* Take the timestamp */
735 spin_lock_irq(&dac33->lock);
736 dac33->t_stamp2 = ktime_to_us(ktime_get());
737 spin_unlock_irq(&dac33->lock);
738
d4f102d4
PU		 739 dac33_write16(codec, DAC33_NSAMPLE_MSB,
740 DAC33_THRREG(dac33->nsample));
741 break;
28e05d98
PU		 742 case DAC33_FIFO_MODE7:
743 /* At the moment we are not using interrupts in mode7 */
744 break;
d4f102d4
PU		 745 default:
746 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
747 dac33->fifo_mode);
748 break;
749 }
750}
751
c8bf93f0
PU		 752static void dac33_work(struct work_struct *work)
753{
754 struct snd_soc_codec *codec;
755 struct tlv320dac33_priv *dac33;
756 u8 reg;
757
758 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 759 codec = dac33->codec;
c8bf93f0
PU		 760
761 mutex_lock(&dac33->mutex);
762 switch (dac33->state) {
763 case DAC33_PREFILL:
764 dac33->state = DAC33_PLAYBACK;
d4f102d4 765 dac33_prefill_handler(dac33);
c8bf93f0
PU		 766 break;
767 case DAC33_PLAYBACK:
d4f102d4 768 dac33_playback_handler(dac33);
c8bf93f0
PU		 769 break;
770 case DAC33_IDLE:
771 break;
772 case DAC33_FLUSH:
773 dac33->state = DAC33_IDLE;
774 /* Mask all interrupts from dac33 */
775 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
776
777 /* flush fifo */
778 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
779 reg |= DAC33_FIFOFLUSH;
780 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
781 break;
782 }
783 mutex_unlock(&dac33->mutex);
784}
785
786static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
787{
788 struct snd_soc_codec *codec = dev;
b2c812e2 789 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 790
f57d2cfa
PU		 791 spin_lock(&dac33->lock);
792 dac33->t_stamp1 = ktime_to_us(ktime_get());
793 spin_unlock(&dac33->lock);
c8bf93f0 794
f57d2cfa
PU		 795 /* Do not schedule the workqueue in Mode7 */
796 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
797 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 798
c8bf93f0 799 return IRQ_HANDLED;
c8bf93f0
PU		 800}
801
802static void dac33_oscwait(struct snd_soc_codec *codec)
803{
84eae18c 804 int timeout = 60;
c8bf93f0
PU		 805 u8 reg;
806
807 do {
84eae18c 808 usleep_range(1000, 2000);
c8bf93f0
PU		 809 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
810 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
811 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
812 dev_err(codec->dev,
813 "internal oscillator calibration failed\n");
814}
815
0b61d2b9
PU		 816static int dac33_startup(struct snd_pcm_substream *substream,
817 struct snd_soc_dai *dai)
818{
819 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 820 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 821 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
822
823 /* Stream started, save the substream pointer */
824 dac33->substream = substream;
825
826 return 0;
827}
828
829static void dac33_shutdown(struct snd_pcm_substream *substream,
830 struct snd_soc_dai *dai)
831{
832 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 833 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 834 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
835
836 dac33->substream = NULL;
f430a27f
PU		 837
838 /* Reset the nSample restrictions */
839 dac33->nsample_min = 0;
840 dac33->nsample_max = NSAMPLE_MAX;
0b61d2b9
PU		 841}
842
c8bf93f0
PU		 843static int dac33_hw_params(struct snd_pcm_substream *substream,
844 struct snd_pcm_hw_params *params,
845 struct snd_soc_dai *dai)
846{
847 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 848 struct snd_soc_codec *codec = rtd->codec;
c8bf93f0
PU		 849
850 /* Check parameters for validity */
851 switch (params_rate(params)) {
852 case 44100:
853 case 48000:
854 break;
855 default:
856 dev_err(codec->dev, "unsupported rate %d\n",
857 params_rate(params));
858 return -EINVAL;
859 }
860
861 switch (params_format(params)) {
862 case SNDRV_PCM_FORMAT_S16_LE:
863 break;
864 default:
865 dev_err(codec->dev, "unsupported format %d\n",
866 params_format(params));
867 return -EINVAL;
868 }
869
870 return 0;
871}
872
873#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 874 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 875#define CALC_RATIOSET(rate, refclk) ( \
876 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
877
878/*
879 * tlv320dac33 is strict on the sequence of the register writes, if the register
880 * writes happens in different order, than dac33 might end up in unknown state.
881 * Use the known, working sequence of register writes to initialize the dac33.
882 */
883static int dac33_prepare_chip(struct snd_pcm_substream *substream)
884{
885 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 886 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 887 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 888 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 889 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 890
891 switch (substream->runtime->rate) {
892 case 44100:
893 case 48000:
894 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
895 ratioset = CALC_RATIOSET(substream->runtime->rate,
896 dac33->refclk);
897 break;
898 default:
899 dev_err(codec->dev, "unsupported rate %d\n",
900 substream->runtime->rate);
901 return -EINVAL;
902 }
903
904
905 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
906 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 907 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 908 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 909 fifoctrl_a &= ~DAC33_FIFOFLUSH;
910
c8bf93f0
PU		 911 fifoctrl_a &= ~DAC33_WIDTH;
912 switch (substream->runtime->format) {
913 case SNDRV_PCM_FORMAT_S16_LE:
914 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
915 fifoctrl_a |= DAC33_WIDTH;
916 break;
917 default:
918 dev_err(codec->dev, "unsupported format %d\n",
919 substream->runtime->format);
920 return -EINVAL;
921 }
922
923 mutex_lock(&dac33->mutex);
ad05c03b
PU		 924
925 if (!dac33->chip_power) {
926 /*
927 * Chip is not powered yet.
928 * Do the init in the dac33_set_bias_level later.
929 */
930 mutex_unlock(&dac33->mutex);
931 return 0;
932 }
933
c3746a07 934 dac33_soft_power(codec, 0);
c8bf93f0
PU		 935 dac33_soft_power(codec, 1);
936
937 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
938 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
939
940 /* Write registers 0x08 and 0x09 (MSB, LSB) */
941 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
942
943 /* calib time: 128 is a nice number ;) */
944 dac33_write(codec, DAC33_CALIB_TIME, 128);
945
946 /* adjustment treshold & step */
947 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
948 DAC33_ADJSTEP(1));
949
950 /* div=4 / gain=1 / div */
951 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
952
953 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
954 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
955 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
956
957 dac33_oscwait(codec);
958
7427b4b9 959 if (dac33->fifo_mode) {
aec242dc 960 /* Generic for all FIFO modes */
c8bf93f0 961 /* 50-51 : ASRC Control registers */
fdb6b1e1 962 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 963 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
964
965 /* Write registers 0x34 and 0x35 (MSB, LSB) */
966 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
967
968 /* Set interrupts to high active */
969 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 970 } else {
aec242dc 971 /* FIFO bypass mode */
c8bf93f0
PU		 972 /* 50-51 : ASRC Control registers */
973 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
974 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
975 }
976
aec242dc
PU		 977 /* Interrupt behaviour configuration */
978 switch (dac33->fifo_mode) {
979 case DAC33_FIFO_MODE1:
980 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
981 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 982 break;
28e05d98 983 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 984 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
985 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 986 break;
aec242dc
PU		 987 default:
988 /* in FIFO bypass mode, the interrupts are not used */
989 break;
990 }
991
992 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
993
994 switch (dac33->fifo_mode) {
995 case DAC33_FIFO_MODE1:
996 /*
997 * For mode1:
998 * Disable the FIFO bypass (Enable the use of FIFO)
999 * Select nSample mode
1000 * BCLK is only running when data is needed by DAC33
1001 */
c8bf93f0 1002 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 1003 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 1004 if (dac33->keep_bclk)
1005 aictrl_b |= DAC33_BCLKON;
1006 else
1007 aictrl_b &= ~DAC33_BCLKON;
aec242dc 1008 break;
28e05d98
PU		 1009 case DAC33_FIFO_MODE7:
1010 /*
1011 * For mode1:
1012 * Disable the FIFO bypass (Enable the use of FIFO)
1013 * Select Threshold mode
1014 * BCLK is only running when data is needed by DAC33
1015 */
1016 fifoctrl_a &= ~DAC33_FBYPAS;
1017 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 1018 if (dac33->keep_bclk)
1019 aictrl_b |= DAC33_BCLKON;
1020 else
1021 aictrl_b &= ~DAC33_BCLKON;
28e05d98 1022 break;
aec242dc
PU		 1023 default:
1024 /*
1025 * For FIFO bypass mode:
1026 * Enable the FIFO bypass (Disable the FIFO use)
1027 * Set the BCLK as continous
1028 */
c8bf93f0 1029 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 1030 aictrl_b |= DAC33_BCLKON;
1031 break;
1032 }
c8bf93f0 1033
aec242dc 1034 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 1035 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 1036 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 1037
6aceabb4
PU		 1038 /*
1039 * BCLK divide ratio
1040 * 0: 1.5
1041 * 1: 1
1042 * 2: 2
1043 * ...
1044 * 254: 254
1045 * 255: 255
1046 */
6cd6cede 1047 if (dac33->fifo_mode)
6aceabb4
PU		 1048 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1049 dac33->burst_bclkdiv);
6cd6cede
PU		 1050 else
1051 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 1052
6cd6cede
PU		 1053 switch (dac33->fifo_mode) {
1054 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1055 dac33_write16(codec, DAC33_ATHR_MSB,
1056 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1057 break;
28e05d98
PU		 1058 case DAC33_FIFO_MODE7:
1059 /*
1060 * Configure the threshold levels, and leave 10 sample space
1061 * at the bottom, and also at the top of the FIFO
1062 */
9d7db2b2 1063 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
4260393e 1064 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 1065 break;
aec242dc 1066 default:
aec242dc 1067 break;
c8bf93f0
PU		 1068 }
1069
1070 mutex_unlock(&dac33->mutex);
1071
1072 return 0;
1073}
1074
1075static void dac33_calculate_times(struct snd_pcm_substream *substream)
1076{
1077 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1078 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1079 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1080 unsigned int period_size = substream->runtime->period_size;
1081 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1082 unsigned int nsample_limit;
1083
55abb59c
PU		 1084 /* In bypass mode we don't need to calculate */
1085 if (!dac33->fifo_mode)
1086 return;
1087
f57d2cfa
PU		 1088 switch (dac33->fifo_mode) {
1089 case DAC33_FIFO_MODE1:
f430a27f
PU		 1090 /* Number of samples under i2c latency */
1091 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1092 dac33->mode1_latency);
1bc13b2e
PU		 1093 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1094 dac33->alarm_threshold;
1095
a577b318
PU		 1096 if (dac33->auto_fifo_config) {
1097 if (period_size <= dac33->alarm_threshold)
1098 /*
1099 * Configure nSamaple to number of periods,
1100 * which covers the latency requironment.
1101 */
1102 dac33->nsample = period_size *
1103 ((dac33->alarm_threshold / period_size) +
1104 (dac33->alarm_threshold % period_size ?
1105 1 : 0));
1bc13b2e
PU		 1106 else if (period_size > nsample_limit)
1107 dac33->nsample = nsample_limit;
a577b318
PU		 1108 else
1109 dac33->nsample = period_size;
1110 } else {
1111 /* nSample time shall not be shorter than i2c latency */
1112 dac33->nsample_min = dac33->alarm_threshold;
1113 /*
1114 * nSample should not be bigger than alsa buffer minus
1115 * size of one period to avoid overruns
1116 */
1117 dac33->nsample_max = substream->runtime->buffer_size -
1118 period_size;
1bc13b2e 1119
a577b318
PU		 1120 if (dac33->nsample_max > nsample_limit)
1121 dac33->nsample_max = nsample_limit;
1122
1123 /* Correct the nSample if it is outside of the ranges */
1124 if (dac33->nsample < dac33->nsample_min)
1125 dac33->nsample = dac33->nsample_min;
1126 if (dac33->nsample > dac33->nsample_max)
1127 dac33->nsample = dac33->nsample_max;
1128 }
f430a27f 1129
f57d2cfa
PU		 1130 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1131 dac33->nsample);
1132 dac33->t_stamp1 = 0;
1133 dac33->t_stamp2 = 0;
1134 break;
1135 case DAC33_FIFO_MODE7:
a577b318
PU		 1136 if (dac33->auto_fifo_config) {
1137 dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1138 period_size,
1139 rate,
1140 dac33->burst_rate) + 9;
1141 if (dac33->uthr > MODE7_UTHR)
1142 dac33->uthr = MODE7_UTHR;
1143 if (dac33->uthr < (MODE7_LTHR + 10))
1144 dac33->uthr = (MODE7_LTHR + 10);
1145 }
f57d2cfa 1146 dac33->mode7_us_to_lthr =
9d7db2b2
PU		 1147 SAMPLES_TO_US(substream->runtime->rate,
1148 dac33->uthr - MODE7_LTHR + 1);
f57d2cfa
PU		 1149 dac33->t_stamp1 = 0;
1150 break;
1151 default:
1152 break;
1153 }
c8bf93f0 1154
c8bf93f0
PU		 1155}
1156
1157static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1158 struct snd_soc_dai *dai)
1159{
1160 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1161 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1162 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1163 int ret = 0;
1164
1165 switch (cmd) {
1166 case SNDRV_PCM_TRIGGER_START:
1167 case SNDRV_PCM_TRIGGER_RESUME:
1168 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1169 if (dac33->fifo_mode) {
c8bf93f0
PU		 1170 dac33->state = DAC33_PREFILL;
1171 queue_work(dac33->dac33_wq, &dac33->work);
1172 }
1173 break;
1174 case SNDRV_PCM_TRIGGER_STOP:
1175 case SNDRV_PCM_TRIGGER_SUSPEND:
1176 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1177 if (dac33->fifo_mode) {
c8bf93f0
PU		 1178 dac33->state = DAC33_FLUSH;
1179 queue_work(dac33->dac33_wq, &dac33->work);
1180 }
1181 break;
1182 default:
1183 ret = -EINVAL;
1184 }
1185
1186 return ret;
1187}
1188
f57d2cfa
PU		 1189static snd_pcm_sframes_t dac33_dai_delay(
1190 struct snd_pcm_substream *substream,
1191 struct snd_soc_dai *dai)
1192{
1193 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1194 struct snd_soc_codec *codec = rtd->codec;
f57d2cfa
PU		 1195 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1196 unsigned long long t0, t1, t_now;
9d7db2b2 1197 unsigned int time_delta, uthr;
f57d2cfa
PU		 1198 int samples_out, samples_in, samples;
1199 snd_pcm_sframes_t delay = 0;
1200
1201 switch (dac33->fifo_mode) {
1202 case DAC33_FIFO_BYPASS:
1203 break;
1204 case DAC33_FIFO_MODE1:
1205 spin_lock(&dac33->lock);
1206 t0 = dac33->t_stamp1;
1207 t1 = dac33->t_stamp2;
1208 spin_unlock(&dac33->lock);
1209 t_now = ktime_to_us(ktime_get());
1210
1211 /* We have not started to fill the FIFO yet, delay is 0 */
1212 if (!t1)
1213 goto out;
1214
1215 if (t0 > t1) {
1216 /*
1217 * Phase 1:
1218 * After Alarm threshold, and before nSample write
1219 */
1220 time_delta = t_now - t0;
1221 samples_out = time_delta ? US_TO_SAMPLES(
1222 substream->runtime->rate,
1223 time_delta) : 0;
1224
1225 if (likely(dac33->alarm_threshold > samples_out))
1226 delay = dac33->alarm_threshold - samples_out;
1227 else
1228 delay = 0;
1229 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1230 /*
1231 * Phase 2:
1232 * After nSample write (during burst operation)
1233 */
1234 time_delta = t_now - t0;
1235 samples_out = time_delta ? US_TO_SAMPLES(
1236 substream->runtime->rate,
1237 time_delta) : 0;
1238
1239 time_delta = t_now - t1;
1240 samples_in = time_delta ? US_TO_SAMPLES(
1241 dac33->burst_rate,
1242 time_delta) : 0;
1243
1244 samples = dac33->alarm_threshold;
1245 samples += (samples_in - samples_out);
1246
1247 if (likely(samples > 0))
1248 delay = samples;
1249 else
1250 delay = 0;
1251 } else {
1252 /*
1253 * Phase 3:
1254 * After burst operation, before next alarm threshold
1255 */
1256 time_delta = t_now - t0;
1257 samples_out = time_delta ? US_TO_SAMPLES(
1258 substream->runtime->rate,
1259 time_delta) : 0;
1260
1261 samples_in = dac33->nsample;
1262 samples = dac33->alarm_threshold;
1263 samples += (samples_in - samples_out);
1264
1265 if (likely(samples > 0))
1266 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1267 DAC33_BUFFER_SIZE_SAMPLES : samples;
1268 else
1269 delay = 0;
1270 }
1271 break;
1272 case DAC33_FIFO_MODE7:
1273 spin_lock(&dac33->lock);
1274 t0 = dac33->t_stamp1;
9d7db2b2 1275 uthr = dac33->uthr;
f57d2cfa
PU		 1276 spin_unlock(&dac33->lock);
1277 t_now = ktime_to_us(ktime_get());
1278
1279 /* We have not started to fill the FIFO yet, delay is 0 */
1280 if (!t0)
1281 goto out;
1282
1283 if (t_now <= t0) {
1284 /*
1285 * Either the timestamps are messed or equal. Report
1286 * maximum delay
1287 */
9d7db2b2 1288 delay = uthr;
f57d2cfa
PU		 1289 goto out;
1290 }
1291
1292 time_delta = t_now - t0;
1293 if (time_delta <= dac33->mode7_us_to_lthr) {
1294 /*
1295 * Phase 1:
1296 * After burst (draining phase)
1297 */
1298 samples_out = US_TO_SAMPLES(
1299 substream->runtime->rate,
1300 time_delta);
1301
9d7db2b2
PU		 1302 if (likely(uthr > samples_out))
1303 delay = uthr - samples_out;
f57d2cfa
PU		 1304 else
1305 delay = 0;
1306 } else {
1307 /*
1308 * Phase 2:
1309 * During burst operation
1310 */
1311 time_delta = time_delta - dac33->mode7_us_to_lthr;
1312
1313 samples_out = US_TO_SAMPLES(
1314 substream->runtime->rate,
1315 time_delta);
1316 samples_in = US_TO_SAMPLES(
1317 dac33->burst_rate,
1318 time_delta);
1319 delay = MODE7_LTHR + samples_in - samples_out;
1320
9d7db2b2
PU		 1321 if (unlikely(delay > uthr))
1322 delay = uthr;
f57d2cfa
PU		 1323 }
1324 break;
1325 default:
1326 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1327 dac33->fifo_mode);
1328 break;
1329 }
1330out:
1331 return delay;
1332}
1333
c8bf93f0
PU		 1334static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1335 int clk_id, unsigned int freq, int dir)
1336{
1337 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1338 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1339 u8 ioc_reg, asrcb_reg;
1340
1341 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1342 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1343 switch (clk_id) {
1344 case TLV320DAC33_MCLK:
1345 ioc_reg |= DAC33_REFSEL;
1346 asrcb_reg |= DAC33_SRCREFSEL;
1347 break;
1348 case TLV320DAC33_SLEEPCLK:
1349 ioc_reg &= ~DAC33_REFSEL;
1350 asrcb_reg &= ~DAC33_SRCREFSEL;
1351 break;
1352 default:
1353 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1354 break;
1355 }
1356 dac33->refclk = freq;
1357
1358 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1359 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1360
1361 return 0;
1362}
1363
1364static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1365 unsigned int fmt)
1366{
1367 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1368 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1369 u8 aictrl_a, aictrl_b;
1370
1371 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1372 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1373 /* set master/slave audio interface */
1374 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1375 case SND_SOC_DAIFMT_CBM_CFM:
1376 /* Codec Master */
1377 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1378 break;
1379 case SND_SOC_DAIFMT_CBS_CFS:
1380 /* Codec Slave */
adcb8bc0
PU		 1381 if (dac33->fifo_mode) {
1382 dev_err(codec->dev, "FIFO mode requires master mode\n");
1383 return -EINVAL;
1384 } else
1385 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1386 break;
1387 default:
1388 return -EINVAL;
1389 }
1390
1391 aictrl_a &= ~DAC33_AFMT_MASK;
1392 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1393 case SND_SOC_DAIFMT_I2S:
1394 aictrl_a |= DAC33_AFMT_I2S;
1395 break;
1396 case SND_SOC_DAIFMT_DSP_A:
1397 aictrl_a |= DAC33_AFMT_DSP;
1398 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1399 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1400 break;
1401 case SND_SOC_DAIFMT_RIGHT_J:
1402 aictrl_a |= DAC33_AFMT_RIGHT_J;
1403 break;
1404 case SND_SOC_DAIFMT_LEFT_J:
1405 aictrl_a |= DAC33_AFMT_LEFT_J;
1406 break;
1407 default:
1408 dev_err(codec->dev, "Unsupported format (%u)\n",
1409 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1410 return -EINVAL;
1411 }
1412
1413 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1414 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1415
1416 return 0;
1417}
1418
f0fba2ad 1419static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1420{
f0fba2ad 1421 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1422 int ret = 0;
1423
f0fba2ad
LG		 1424 codec->control_data = dac33->control_data;
1425 codec->hw_write = (hw_write_t) i2c_master_send;
ce6120cc 1426 codec->dapm.idle_bias_off = 1;
f0fba2ad 1427 dac33->codec = codec;
c8bf93f0 1428
f0fba2ad
LG		 1429 /* Read the tlv320dac33 ID registers */
1430 ret = dac33_hard_power(codec, 1);
1431 if (ret != 0) {
1432 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1433 goto err_power;
1434 }
911a0f0b 1435 ret = dac33_read_id(codec);
f0fba2ad 1436 dac33_hard_power(codec, 0);
c8bf93f0 1437
911a0f0b
PU		 1438 if (ret < 0) {
1439 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1440 ret = -ENODEV;
1441 goto err_power;
1442 }
1443
f0fba2ad
LG		 1444 /* Check if the IRQ number is valid and request it */
1445 if (dac33->irq >= 0) {
1446 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1447 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1448 codec->name, codec);
1449 if (ret < 0) {
1450 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1451 dac33->irq, ret);
1452 dac33->irq = -1;
1453 }
1454 if (dac33->irq != -1) {
1455 /* Setup work queue */
1456 dac33->dac33_wq =
1457 create_singlethread_workqueue("tlv320dac33");
1458 if (dac33->dac33_wq == NULL) {
1459 free_irq(dac33->irq, codec);
1460 return -ENOMEM;
1461 }
1462
1463 INIT_WORK(&dac33->work, dac33_work);
1464 }
c8bf93f0
PU		 1465 }
1466
1467 snd_soc_add_controls(codec, dac33_snd_controls,
1468 ARRAY_SIZE(dac33_snd_controls));
a577b318
PU		 1469 /* Only add the FIFO controls, if we have valid IRQ number */
1470 if (dac33->irq >= 0) {
1471 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1472 ARRAY_SIZE(dac33_mode_snd_controls));
1473 /* FIFO usage controls only, if autoio config is not selected */
1474 if (!dac33->auto_fifo_config)
1475 snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1476 ARRAY_SIZE(dac33_fifo_snd_controls));
1477 }
c8bf93f0
PU		 1478 dac33_add_widgets(codec);
1479
f0fba2ad 1480err_power:
c8bf93f0
PU		 1481 return ret;
1482}
1483
f0fba2ad 1484static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1485{
f0fba2ad 1486 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1487
1488 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1489
f0fba2ad
LG		 1490 if (dac33->irq >= 0) {
1491 free_irq(dac33->irq, dac33->codec);
1492 destroy_workqueue(dac33->dac33_wq);
1493 }
c8bf93f0
PU		 1494 return 0;
1495}
1496
f0fba2ad 1497static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
c8bf93f0 1498{
c8bf93f0
PU		 1499 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1500
1501 return 0;
1502}
1503
f0fba2ad 1504static int dac33_soc_resume(struct snd_soc_codec *codec)
c8bf93f0 1505{
c8bf93f0 1506 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1507
1508 return 0;
1509}
1510
f0fba2ad
LG		 1511static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1512 .read = dac33_read_reg_cache,
1513 .write = dac33_write_locked,
1514 .set_bias_level = dac33_set_bias_level,
1515 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1516 .reg_word_size = sizeof(u8),
1517 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1518 .probe = dac33_soc_probe,
1519 .remove = dac33_soc_remove,
1520 .suspend = dac33_soc_suspend,
1521 .resume = dac33_soc_resume,
1522};
c8bf93f0
PU		 1523
1524#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1525 SNDRV_PCM_RATE_48000)
1526#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1527
1528static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1529 .startup = dac33_startup,
c8bf93f0
PU		 1530 .shutdown = dac33_shutdown,
1531 .hw_params = dac33_hw_params,
c8bf93f0 1532 .trigger = dac33_pcm_trigger,
f57d2cfa 1533 .delay = dac33_dai_delay,
c8bf93f0
PU		 1534 .set_sysclk = dac33_set_dai_sysclk,
1535 .set_fmt = dac33_set_dai_fmt,
1536};
1537
f0fba2ad
LG		 1538static struct snd_soc_dai_driver dac33_dai = {
1539 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1540 .playback = {
1541 .stream_name = "Playback",
1542 .channels_min = 2,
1543 .channels_max = 2,
1544 .rates = DAC33_RATES,
1545 .formats = DAC33_FORMATS,},
1546 .ops = &dac33_dai_ops,
1547};
c8bf93f0 1548
735fe4cf
MB		 1549static int __devinit dac33_i2c_probe(struct i2c_client *client,
1550 const struct i2c_device_id *id)
c8bf93f0
PU		 1551{
1552 struct tlv320dac33_platform_data *pdata;
1553 struct tlv320dac33_priv *dac33;
3a7aaed7 1554 int ret, i;
c8bf93f0
PU		 1555
1556 if (client->dev.platform_data == NULL) {
1557 dev_err(&client->dev, "Platform data not set\n");
1558 return -ENODEV;
1559 }
1560 pdata = client->dev.platform_data;
1561
1562 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1563 if (dac33 == NULL)
1564 return -ENOMEM;
1565
f0fba2ad 1566 dac33->control_data = client;
c8bf93f0 1567 mutex_init(&dac33->mutex);
f57d2cfa 1568 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1569
1570 i2c_set_clientdata(client, dac33);
1571
1572 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1573 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1574 /* Pre calculate the burst rate */
1575 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1576 dac33->keep_bclk = pdata->keep_bclk;
a577b318 1577 dac33->auto_fifo_config = pdata->auto_fifo_config;
f430a27f
PU		 1578 dac33->mode1_latency = pdata->mode1_latency;
1579 if (!dac33->mode1_latency)
1580 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0
PU		 1581 dac33->irq = client->irq;
1582 dac33->nsample = NSAMPLE_MAX;
55abb59c 1583 dac33->nsample_max = NSAMPLE_MAX;
9d7db2b2 1584 dac33->uthr = MODE7_UTHR;
c8bf93f0 1585 /* Disable FIFO use by default */
7427b4b9 1586 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1587
c8bf93f0
PU		 1588 /* Check if the reset GPIO number is valid and request it */
1589 if (dac33->power_gpio >= 0) {
1590 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1591 if (ret < 0) {
f0fba2ad 1592 dev_err(&client->dev,
c8bf93f0
PU		 1593 "Failed to request reset GPIO (%d)\n",
1594 dac33->power_gpio);
f0fba2ad 1595 goto err_gpio;
c8bf93f0
PU		 1596 }
1597 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1598 }
1599
3a7aaed7
IK		 1600 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1601 dac33->supplies[i].supply = dac33_supply_names[i];
1602
f0fba2ad 1603 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1604 dac33->supplies);
1605
1606 if (ret != 0) {
f0fba2ad 1607 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1608 goto err_get;
1609 }
1610
f0fba2ad
LG		 1611 ret = snd_soc_register_codec(&client->dev,
1612 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1613 if (ret < 0)
1614 goto err_register;
c8bf93f0 1615
c8bf93f0 1616 return ret;
f0fba2ad 1617err_register:
3a7aaed7
IK		 1618 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1619err_get:
c8bf93f0
PU		 1620 if (dac33->power_gpio >= 0)
1621 gpio_free(dac33->power_gpio);
f0fba2ad 1622err_gpio:
c8bf93f0 1623 kfree(dac33);
c8bf93f0
PU		 1624 return ret;
1625}
1626
735fe4cf 1627static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1628{
f0fba2ad 1629 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1630
1631 if (unlikely(dac33->chip_power))
f0fba2ad 1632 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1633
1634 if (dac33->power_gpio >= 0)
1635 gpio_free(dac33->power_gpio);
c8bf93f0 1636
3a7aaed7
IK		 1637 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1638
f0fba2ad 1639 snd_soc_unregister_codec(&client->dev);
c8bf93f0 1640 kfree(dac33);
c8bf93f0
PU		 1641
1642 return 0;
1643}
1644
1645static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1646 {
1647 .name = "tlv320dac33",
1648 .driver_data = 0,
1649 },
1650 { },
1651};
1652
1653static struct i2c_driver tlv320dac33_i2c_driver = {
1654 .driver = {
f0fba2ad 1655 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1656 .owner = THIS_MODULE,
1657 },
1658 .probe = dac33_i2c_probe,
1659 .remove = __devexit_p(dac33_i2c_remove),
1660 .id_table = tlv320dac33_i2c_id,
1661};
1662
1663static int __init dac33_module_init(void)
1664{
1665 int r;
1666 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1667 if (r < 0) {
1668 printk(KERN_ERR "DAC33: driver registration failed\n");
1669 return r;
1670 }
1671 return 0;
1672}
1673module_init(dac33_module_init);
1674
1675static void __exit dac33_module_exit(void)
1676{
1677 i2c_del_driver(&tlv320dac33_i2c_driver);
1678}
1679module_exit(dac33_module_exit);
1680
1681
1682MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1683MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1684MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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