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ASoC: tlv320dac33: Remove manual FIFO configuration
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
c8bf93f0
PU		 39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
4260393e
PU		 49#define MODE7_LTHR 10
50#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
51
76f47127
PU		 52#define BURST_BASEFREQ_HZ 49152000
53
f57d2cfa
PU		 54#define SAMPLES_TO_US(rate, samples) \
55 (1000000000 / ((rate * 1000) / samples))
56
57#define US_TO_SAMPLES(rate, us) \
d54e1f4f 58 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
f57d2cfa 59
a577b318
PU		 60#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
61 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
62
ad05c03b
PU		 63static void dac33_calculate_times(struct snd_pcm_substream *substream);
64static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 65
c8bf93f0
PU		 66enum dac33_state {
67 DAC33_IDLE = 0,
68 DAC33_PREFILL,
69 DAC33_PLAYBACK,
70 DAC33_FLUSH,
71};
72
7427b4b9
PU		 73enum dac33_fifo_modes {
74 DAC33_FIFO_BYPASS = 0,
75 DAC33_FIFO_MODE1,
28e05d98 76 DAC33_FIFO_MODE7,
7427b4b9
PU		 77 DAC33_FIFO_LAST_MODE,
78};
79
3a7aaed7
IK		 80#define DAC33_NUM_SUPPLIES 3
81static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
82 "AVDD",
83 "DVDD",
84 "IOVDD",
85};
86
c8bf93f0
PU		 87struct tlv320dac33_priv {
88 struct mutex mutex;
89 struct workqueue_struct *dac33_wq;
90 struct work_struct work;
f0fba2ad 91 struct snd_soc_codec *codec;
3a7aaed7 92 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 93 struct snd_pcm_substream *substream;
c8bf93f0
PU		 94 int power_gpio;
95 int chip_power;
96 int irq;
97 unsigned int refclk;
98
99 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
7427b4b9 100 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 101 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 102 int mode1_latency; /* latency caused by the i2c writes in
103 * us */
6aceabb4 104 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 105 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 106
eeb309a8
PU		 107 int keep_bclk; /* Keep the BCLK continuously running
108 * in FIFO modes */
f57d2cfa
PU		 109 spinlock_t lock;
110 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
111 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
112
113 unsigned int mode1_us_burst; /* Time to burst read n number of
114 * samples */
115 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 116
9d7db2b2
PU		 117 unsigned int uthr;
118
c8bf93f0 119 enum dac33_state state;
f0fba2ad
LG		 120 enum snd_soc_control_type control_type;
121 void *control_data;
c8bf93f0
PU		 122};
123
124static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1250x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1260x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1270x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1280x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1290x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1300x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1310x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1320x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1330x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1340x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1350x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1360x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1370x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1380x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1390x00, 0x00, /* 0x38 - 0x39 */
140/* Registers 0x3a - 0x3f are reserved */
141 0x00, 0x00, /* 0x3a - 0x3b */
1420x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
143
1440x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1450x00, 0x80, /* 0x44 - 0x45 */
146/* Registers 0x46 - 0x47 are reserved */
147 0x80, 0x80, /* 0x46 - 0x47 */
148
1490x80, 0x00, 0x00, /* 0x48 - 0x4a */
150/* Registers 0x4b - 0x7c are reserved */
151 0x00, /* 0x4b */
1520x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1530x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1540x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1550x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1560x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1570x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1580x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1590x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1600x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1610x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1620x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1630x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1640x00, /* 0x7c */
165
166 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
167};
168
169/* Register read and write */
170static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
171 unsigned reg)
172{
173 u8 *cache = codec->reg_cache;
174 if (reg >= DAC33_CACHEREGNUM)
175 return 0;
176
177 return cache[reg];
178}
179
180static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
181 u8 reg, u8 value)
182{
183 u8 *cache = codec->reg_cache;
184 if (reg >= DAC33_CACHEREGNUM)
185 return;
186
187 cache[reg] = value;
188}
189
190static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
191 u8 *value)
192{
b2c812e2 193 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 194 int val, ret = 0;
c8bf93f0
PU		 195
196 *value = reg & 0xff;
197
198 /* If powered off, return the cached value */
199 if (dac33->chip_power) {
200 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
201 if (val < 0) {
202 dev_err(codec->dev, "Read failed (%d)\n", val);
203 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 204 ret = val;
c8bf93f0
PU		 205 } else {
206 value[0] = val;
207 dac33_write_reg_cache(codec, reg, val);
208 }
209 } else {
210 value[0] = dac33_read_reg_cache(codec, reg);
211 }
212
911a0f0b 213 return ret;
c8bf93f0
PU		 214}
215
216static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
217 unsigned int value)
218{
b2c812e2 219 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 220 u8 data[2];
221 int ret = 0;
222
223 /*
224 * data is
225 * D15..D8 dac33 register offset
226 * D7...D0 register data
227 */
228 data[0] = reg & 0xff;
229 data[1] = value & 0xff;
230
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 if (dac33->chip_power) {
233 ret = codec->hw_write(codec->control_data, data, 2);
234 if (ret != 2)
235 dev_err(codec->dev, "Write failed (%d)\n", ret);
236 else
237 ret = 0;
238 }
239
240 return ret;
241}
242
243static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
244 unsigned int value)
245{
b2c812e2 246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 247 int ret;
248
249 mutex_lock(&dac33->mutex);
250 ret = dac33_write(codec, reg, value);
251 mutex_unlock(&dac33->mutex);
252
253 return ret;
254}
255
256#define DAC33_I2C_ADDR_AUTOINC 0x80
257static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
258 unsigned int value)
259{
b2c812e2 260 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 261 u8 data[3];
262 int ret = 0;
263
264 /*
265 * data is
266 * D23..D16 dac33 register offset
267 * D15..D8 register data MSB
268 * D7...D0 register data LSB
269 */
270 data[0] = reg & 0xff;
271 data[1] = (value >> 8) & 0xff;
272 data[2] = value & 0xff;
273
274 dac33_write_reg_cache(codec, data[0], data[1]);
275 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
276
277 if (dac33->chip_power) {
278 /* We need to set autoincrement mode for 16 bit writes */
279 data[0] |= DAC33_I2C_ADDR_AUTOINC;
280 ret = codec->hw_write(codec->control_data, data, 3);
281 if (ret != 3)
282 dev_err(codec->dev, "Write failed (%d)\n", ret);
283 else
284 ret = 0;
285 }
286
287 return ret;
288}
289
ef909d67 290static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 291{
b2c812e2 292 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 293
ef909d67 294 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 295 return;
296
ef909d67
PU		 297 /* 44-46: DAC Control Registers */
298 /* A : DAC sample rate Fsref/1.5 */
299 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
300 /* B : DAC src=normal, not muted */
301 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
302 DAC33_DACSRCL_LEFT);
303 /* C : (defaults) */
304 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
305
ef909d67
PU		 306 /* 73 : volume soft stepping control,
307 clock source = internal osc (?) */
308 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
309
ef909d67
PU		 310 /* Restore only selected registers (gains mostly) */
311 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
312 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
313 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
314 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
315
316 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
317 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
318 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
319 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 320}
321
911a0f0b 322static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 323{
911a0f0b 324 int i, ret = 0;
239fe55c
PU		 325 u8 reg;
326
911a0f0b
PU		 327 for (i = 0; i < 3; i++) {
328 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
329 if (ret < 0)
330 break;
331 }
332
333 return ret;
c8bf93f0
PU		 334}
335
336static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
337{
338 u8 reg;
339
340 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
341 if (power)
342 reg |= DAC33_PDNALLB;
343 else
c3746a07
PU		 344 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
345 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 346 dac33_write(codec, DAC33_PWR_CTRL, reg);
347}
348
a6cea965
PU		 349static inline void dac33_disable_digital(struct snd_soc_codec *codec)
350{
351 u8 reg;
352
353 /* Stop the DAI clock */
354 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
355 reg &= ~DAC33_BCLKON;
356 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
357
358 /* Power down the Oscillator, and DACs */
359 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
360 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
361 dac33_write(codec, DAC33_PWR_CTRL, reg);
362}
363
3a7aaed7 364static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 365{
b2c812e2 366 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 367 int ret = 0;
c8bf93f0
PU		 368
369 mutex_lock(&dac33->mutex);
ad05c03b
PU		 370
371 /* Safety check */
372 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 373 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 374 power ? "ON" : "OFF");
375 goto exit;
376 }
377
c8bf93f0 378 if (power) {
3a7aaed7
IK		 379 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
380 dac33->supplies);
381 if (ret != 0) {
382 dev_err(codec->dev,
383 "Failed to enable supplies: %d\n", ret);
384 goto exit;
c8bf93f0 385 }
3a7aaed7
IK		 386
387 if (dac33->power_gpio >= 0)
388 gpio_set_value(dac33->power_gpio, 1);
389
390 dac33->chip_power = 1;
c8bf93f0
PU		 391 } else {
392 dac33_soft_power(codec, 0);
3a7aaed7 393 if (dac33->power_gpio >= 0)
c8bf93f0 394 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 395
396 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
397 dac33->supplies);
398 if (ret != 0) {
399 dev_err(codec->dev,
400 "Failed to disable supplies: %d\n", ret);
401 goto exit;
c8bf93f0 402 }
3a7aaed7
IK		 403
404 dac33->chip_power = 0;
c8bf93f0 405 }
c8bf93f0 406
3a7aaed7
IK		 407exit:
408 mutex_unlock(&dac33->mutex);
409 return ret;
c8bf93f0
PU		 410}
411
a6cea965 412static int dac33_playback_event(struct snd_soc_dapm_widget *w,
ad05c03b
PU		 413 struct snd_kcontrol *kcontrol, int event)
414{
415 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
416
417 switch (event) {
418 case SND_SOC_DAPM_PRE_PMU:
419 if (likely(dac33->substream)) {
420 dac33_calculate_times(dac33->substream);
421 dac33_prepare_chip(dac33->substream);
422 }
423 break;
a6cea965
PU		 424 case SND_SOC_DAPM_POST_PMD:
425 dac33_disable_digital(w->codec);
426 break;
ad05c03b
PU		 427 }
428 return 0;
429}
430
7427b4b9 431static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 432 struct snd_ctl_elem_value *ucontrol)
433{
434 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 435 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 436
7427b4b9 437 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 438
439 return 0;
440}
441
7427b4b9 442static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 443 struct snd_ctl_elem_value *ucontrol)
444{
445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 447 int ret = 0;
448
7427b4b9 449 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 450 return 0;
451 /* Do not allow changes while stream is running*/
452 if (codec->active)
453 return -EPERM;
454
455 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 456 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 457 ret = -EINVAL;
458 else
7427b4b9 459 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 460
461 return ret;
462}
463
7427b4b9
PU		 464/* Codec operation modes */
465static const char *dac33_fifo_mode_texts[] = {
28e05d98 466 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 467};
468
469static const struct soc_enum dac33_fifo_mode_enum =
470 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
471 dac33_fifo_mode_texts);
472
cf4bb698
PU		 473/* L/R Line Output Gain */
474static const char *lr_lineout_gain_texts[] = {
475 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
476 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
477};
478
479static const struct soc_enum l_lineout_gain_enum =
480 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
481 ARRAY_SIZE(lr_lineout_gain_texts),
482 lr_lineout_gain_texts);
483
484static const struct soc_enum r_lineout_gain_enum =
485 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
486 ARRAY_SIZE(lr_lineout_gain_texts),
487 lr_lineout_gain_texts);
488
c8bf93f0
PU		 489/*
490 * DACL/R digital volume control:
491 * from 0 dB to -63.5 in 0.5 dB steps
492 * Need to be inverted later on:
493 * 0x00 == 0 dB
494 * 0x7f == -63.5 dB
495 */
496static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
497
498static const struct snd_kcontrol_new dac33_snd_controls[] = {
499 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
500 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
501 0, 0x7f, 1, dac_digivol_tlv),
502 SOC_DOUBLE_R("DAC Digital Playback Switch",
503 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
504 SOC_DOUBLE_R("Line to Line Out Volume",
505 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 506 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
507 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 508};
509
a577b318
PU		 510static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
511 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
512 dac33_get_fifo_mode, dac33_set_fifo_mode),
513};
514
c8bf93f0
PU		 515/* Analog bypass */
516static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
517 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
518
519static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
520 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
521
522static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
523 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
524 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
525
526 SND_SOC_DAPM_INPUT("LINEL"),
527 SND_SOC_DAPM_INPUT("LINER"),
528
76eac39c
PU		 529 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
530 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 531
532 /* Analog bypass */
533 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
534 &dac33_dapm_abypassl_control),
535 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
536 &dac33_dapm_abypassr_control),
537
9e87186f 538 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 539 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 540 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 541 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 542
76eac39c
PU		 543 SND_SOC_DAPM_SUPPLY("Left DAC Power",
544 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
545 SND_SOC_DAPM_SUPPLY("Right DAC Power",
546 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
547
a6cea965
PU		 548 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
549 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
c8bf93f0
PU		 550};
551
552static const struct snd_soc_dapm_route audio_map[] = {
553 /* Analog bypass */
554 {"Analog Left Bypass", "Switch", "LINEL"},
555 {"Analog Right Bypass", "Switch", "LINER"},
556
9e87186f
PU		 557 {"Output Left Amplifier", NULL, "DACL"},
558 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 559
9e87186f
PU		 560 {"Output Left Amplifier", NULL, "Analog Left Bypass"},
561 {"Output Right Amplifier", NULL, "Analog Right Bypass"},
c8bf93f0 562
76eac39c
PU		 563 {"Output Left Amplifier", NULL, "Left DAC Power"},
564 {"Output Right Amplifier", NULL, "Right DAC Power"},
565
c8bf93f0 566 /* output */
9e87186f
PU		 567 {"LEFT_LO", NULL, "Output Left Amplifier"},
568 {"RIGHT_LO", NULL, "Output Right Amplifier"},
c8bf93f0
PU		 569};
570
571static int dac33_add_widgets(struct snd_soc_codec *codec)
572{
ce6120cc 573 struct snd_soc_dapm_context *dapm = &codec->dapm;
c8bf93f0 574
ce6120cc
LG		 575 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
576 ARRAY_SIZE(dac33_dapm_widgets));
c8bf93f0 577 /* set up audio path interconnects */
ce6120cc 578 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 579
580 return 0;
581}
582
583static int dac33_set_bias_level(struct snd_soc_codec *codec,
584 enum snd_soc_bias_level level)
585{
3ee4fe15 586 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7
IK		 587 int ret;
588
c8bf93f0
PU		 589 switch (level) {
590 case SND_SOC_BIAS_ON:
3e202345
PU		 591 if (!dac33->substream)
592 dac33_soft_power(codec, 1);
c8bf93f0
PU		 593 break;
594 case SND_SOC_BIAS_PREPARE:
595 break;
596 case SND_SOC_BIAS_STANDBY:
ce6120cc 597 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 598 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 599 ret = dac33_hard_power(codec, 1);
600 if (ret != 0)
601 return ret;
3a7aaed7 602
ad05c03b
PU		 603 dac33_init_chip(codec);
604 }
c8bf93f0
PU		 605 break;
606 case SND_SOC_BIAS_OFF:
2d4cdd6f 607 /* Do not power off, when the codec is already off */
ce6120cc 608 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2d4cdd6f 609 return 0;
3a7aaed7
IK		 610 ret = dac33_hard_power(codec, 0);
611 if (ret != 0)
612 return ret;
c8bf93f0
PU		 613 break;
614 }
ce6120cc 615 codec->dapm.bias_level = level;
c8bf93f0
PU		 616
617 return 0;
618}
619
d4f102d4
PU		 620static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
621{
f0fba2ad 622 struct snd_soc_codec *codec = dac33->codec;
84eae18c 623 unsigned int delay;
d4f102d4
PU		 624
625 switch (dac33->fifo_mode) {
626 case DAC33_FIFO_MODE1:
627 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 628 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 629
630 /* Take the timestamps */
631 spin_lock_irq(&dac33->lock);
632 dac33->t_stamp2 = ktime_to_us(ktime_get());
633 dac33->t_stamp1 = dac33->t_stamp2;
634 spin_unlock_irq(&dac33->lock);
635
d4f102d4
PU		 636 dac33_write16(codec, DAC33_PREFILL_MSB,
637 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 638 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 639 delay = SAMPLES_TO_US(dac33->burst_rate,
640 dac33->alarm_threshold) + 1000;
641 usleep_range(delay, delay + 500);
f4d59328 642 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 643 break;
28e05d98 644 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 645 /* Take the timestamp */
646 spin_lock_irq(&dac33->lock);
647 dac33->t_stamp1 = ktime_to_us(ktime_get());
648 /* Move back the timestamp with drain time */
649 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
650 spin_unlock_irq(&dac33->lock);
651
28e05d98 652 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 653 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 654
655 /* Enable Upper Threshold IRQ */
656 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 657 break;
d4f102d4
PU		 658 default:
659 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
660 dac33->fifo_mode);
661 break;
662 }
663}
664
665static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
666{
f0fba2ad 667 struct snd_soc_codec *codec = dac33->codec;
d4f102d4
PU		 668
669 switch (dac33->fifo_mode) {
670 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 671 /* Take the timestamp */
672 spin_lock_irq(&dac33->lock);
673 dac33->t_stamp2 = ktime_to_us(ktime_get());
674 spin_unlock_irq(&dac33->lock);
675
d4f102d4
PU		 676 dac33_write16(codec, DAC33_NSAMPLE_MSB,
677 DAC33_THRREG(dac33->nsample));
678 break;
28e05d98
PU		 679 case DAC33_FIFO_MODE7:
680 /* At the moment we are not using interrupts in mode7 */
681 break;
d4f102d4
PU		 682 default:
683 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
684 dac33->fifo_mode);
685 break;
686 }
687}
688
c8bf93f0
PU		 689static void dac33_work(struct work_struct *work)
690{
691 struct snd_soc_codec *codec;
692 struct tlv320dac33_priv *dac33;
693 u8 reg;
694
695 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 696 codec = dac33->codec;
c8bf93f0
PU		 697
698 mutex_lock(&dac33->mutex);
699 switch (dac33->state) {
700 case DAC33_PREFILL:
701 dac33->state = DAC33_PLAYBACK;
d4f102d4 702 dac33_prefill_handler(dac33);
c8bf93f0
PU		 703 break;
704 case DAC33_PLAYBACK:
d4f102d4 705 dac33_playback_handler(dac33);
c8bf93f0
PU		 706 break;
707 case DAC33_IDLE:
708 break;
709 case DAC33_FLUSH:
710 dac33->state = DAC33_IDLE;
711 /* Mask all interrupts from dac33 */
712 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
713
714 /* flush fifo */
715 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
716 reg |= DAC33_FIFOFLUSH;
717 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
718 break;
719 }
720 mutex_unlock(&dac33->mutex);
721}
722
723static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
724{
725 struct snd_soc_codec *codec = dev;
b2c812e2 726 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 727
f57d2cfa
PU		 728 spin_lock(&dac33->lock);
729 dac33->t_stamp1 = ktime_to_us(ktime_get());
730 spin_unlock(&dac33->lock);
c8bf93f0 731
f57d2cfa
PU		 732 /* Do not schedule the workqueue in Mode7 */
733 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
734 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 735
c8bf93f0 736 return IRQ_HANDLED;
c8bf93f0
PU		 737}
738
739static void dac33_oscwait(struct snd_soc_codec *codec)
740{
84eae18c 741 int timeout = 60;
c8bf93f0
PU		 742 u8 reg;
743
744 do {
84eae18c 745 usleep_range(1000, 2000);
c8bf93f0
PU		 746 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
747 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
748 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
749 dev_err(codec->dev,
750 "internal oscillator calibration failed\n");
751}
752
0b61d2b9
PU		 753static int dac33_startup(struct snd_pcm_substream *substream,
754 struct snd_soc_dai *dai)
755{
756 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 757 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 758 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
759
760 /* Stream started, save the substream pointer */
761 dac33->substream = substream;
762
763 return 0;
764}
765
766static void dac33_shutdown(struct snd_pcm_substream *substream,
767 struct snd_soc_dai *dai)
768{
769 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 770 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 771 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
772
773 dac33->substream = NULL;
774}
775
c8bf93f0
PU		 776static int dac33_hw_params(struct snd_pcm_substream *substream,
777 struct snd_pcm_hw_params *params,
778 struct snd_soc_dai *dai)
779{
780 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 781 struct snd_soc_codec *codec = rtd->codec;
c8bf93f0
PU		 782
783 /* Check parameters for validity */
784 switch (params_rate(params)) {
785 case 44100:
786 case 48000:
787 break;
788 default:
789 dev_err(codec->dev, "unsupported rate %d\n",
790 params_rate(params));
791 return -EINVAL;
792 }
793
794 switch (params_format(params)) {
795 case SNDRV_PCM_FORMAT_S16_LE:
796 break;
797 default:
798 dev_err(codec->dev, "unsupported format %d\n",
799 params_format(params));
800 return -EINVAL;
801 }
802
803 return 0;
804}
805
806#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 807 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 808#define CALC_RATIOSET(rate, refclk) ( \
809 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
810
811/*
812 * tlv320dac33 is strict on the sequence of the register writes, if the register
813 * writes happens in different order, than dac33 might end up in unknown state.
814 * Use the known, working sequence of register writes to initialize the dac33.
815 */
816static int dac33_prepare_chip(struct snd_pcm_substream *substream)
817{
818 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 819 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 820 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 821 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 822 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 823
824 switch (substream->runtime->rate) {
825 case 44100:
826 case 48000:
827 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
828 ratioset = CALC_RATIOSET(substream->runtime->rate,
829 dac33->refclk);
830 break;
831 default:
832 dev_err(codec->dev, "unsupported rate %d\n",
833 substream->runtime->rate);
834 return -EINVAL;
835 }
836
837
838 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
839 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 840 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 841 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 842 fifoctrl_a &= ~DAC33_FIFOFLUSH;
843
c8bf93f0
PU		 844 fifoctrl_a &= ~DAC33_WIDTH;
845 switch (substream->runtime->format) {
846 case SNDRV_PCM_FORMAT_S16_LE:
847 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
848 fifoctrl_a |= DAC33_WIDTH;
849 break;
850 default:
851 dev_err(codec->dev, "unsupported format %d\n",
852 substream->runtime->format);
853 return -EINVAL;
854 }
855
856 mutex_lock(&dac33->mutex);
ad05c03b
PU		 857
858 if (!dac33->chip_power) {
859 /*
860 * Chip is not powered yet.
861 * Do the init in the dac33_set_bias_level later.
862 */
863 mutex_unlock(&dac33->mutex);
864 return 0;
865 }
866
c3746a07 867 dac33_soft_power(codec, 0);
c8bf93f0
PU		 868 dac33_soft_power(codec, 1);
869
870 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
871 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
872
873 /* Write registers 0x08 and 0x09 (MSB, LSB) */
874 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
875
876 /* calib time: 128 is a nice number ;) */
877 dac33_write(codec, DAC33_CALIB_TIME, 128);
878
879 /* adjustment treshold & step */
880 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
881 DAC33_ADJSTEP(1));
882
883 /* div=4 / gain=1 / div */
884 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
885
886 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
887 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
888 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
889
890 dac33_oscwait(codec);
891
7427b4b9 892 if (dac33->fifo_mode) {
aec242dc 893 /* Generic for all FIFO modes */
c8bf93f0 894 /* 50-51 : ASRC Control registers */
fdb6b1e1 895 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 896 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
897
898 /* Write registers 0x34 and 0x35 (MSB, LSB) */
899 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
900
901 /* Set interrupts to high active */
902 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 903 } else {
aec242dc 904 /* FIFO bypass mode */
c8bf93f0
PU		 905 /* 50-51 : ASRC Control registers */
906 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
907 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
908 }
909
aec242dc
PU		 910 /* Interrupt behaviour configuration */
911 switch (dac33->fifo_mode) {
912 case DAC33_FIFO_MODE1:
913 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
914 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 915 break;
28e05d98 916 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 917 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
918 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 919 break;
aec242dc
PU		 920 default:
921 /* in FIFO bypass mode, the interrupts are not used */
922 break;
923 }
924
925 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
926
927 switch (dac33->fifo_mode) {
928 case DAC33_FIFO_MODE1:
929 /*
930 * For mode1:
931 * Disable the FIFO bypass (Enable the use of FIFO)
932 * Select nSample mode
933 * BCLK is only running when data is needed by DAC33
934 */
c8bf93f0 935 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 936 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 937 if (dac33->keep_bclk)
938 aictrl_b |= DAC33_BCLKON;
939 else
940 aictrl_b &= ~DAC33_BCLKON;
aec242dc 941 break;
28e05d98
PU		 942 case DAC33_FIFO_MODE7:
943 /*
944 * For mode1:
945 * Disable the FIFO bypass (Enable the use of FIFO)
946 * Select Threshold mode
947 * BCLK is only running when data is needed by DAC33
948 */
949 fifoctrl_a &= ~DAC33_FBYPAS;
950 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 951 if (dac33->keep_bclk)
952 aictrl_b |= DAC33_BCLKON;
953 else
954 aictrl_b &= ~DAC33_BCLKON;
28e05d98 955 break;
aec242dc
PU		 956 default:
957 /*
958 * For FIFO bypass mode:
959 * Enable the FIFO bypass (Disable the FIFO use)
960 * Set the BCLK as continous
961 */
c8bf93f0 962 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 963 aictrl_b |= DAC33_BCLKON;
964 break;
965 }
c8bf93f0 966
aec242dc 967 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 968 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 969 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 970
6aceabb4
PU		 971 /*
972 * BCLK divide ratio
973 * 0: 1.5
974 * 1: 1
975 * 2: 2
976 * ...
977 * 254: 254
978 * 255: 255
979 */
6cd6cede 980 if (dac33->fifo_mode)
6aceabb4
PU		 981 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
982 dac33->burst_bclkdiv);
6cd6cede
PU		 983 else
984 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 985
6cd6cede
PU		 986 switch (dac33->fifo_mode) {
987 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 988 dac33_write16(codec, DAC33_ATHR_MSB,
989 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 990 break;
28e05d98
PU		 991 case DAC33_FIFO_MODE7:
992 /*
993 * Configure the threshold levels, and leave 10 sample space
994 * at the bottom, and also at the top of the FIFO
995 */
9d7db2b2 996 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
4260393e 997 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 998 break;
aec242dc 999 default:
aec242dc 1000 break;
c8bf93f0
PU		 1001 }
1002
1003 mutex_unlock(&dac33->mutex);
1004
1005 return 0;
1006}
1007
1008static void dac33_calculate_times(struct snd_pcm_substream *substream)
1009{
1010 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1011 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1012 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1013 unsigned int period_size = substream->runtime->period_size;
1014 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1015 unsigned int nsample_limit;
1016
55abb59c
PU		 1017 /* In bypass mode we don't need to calculate */
1018 if (!dac33->fifo_mode)
1019 return;
1020
f57d2cfa
PU		 1021 switch (dac33->fifo_mode) {
1022 case DAC33_FIFO_MODE1:
f430a27f
PU		 1023 /* Number of samples under i2c latency */
1024 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1025 dac33->mode1_latency);
1bc13b2e
PU		 1026 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1027 dac33->alarm_threshold;
1028
3591f4cd 1029 if (period_size <= dac33->alarm_threshold)
a577b318 1030 /*
3591f4cd
PU		 1031 * Configure nSamaple to number of periods,
1032 * which covers the latency requironment.
a577b318 1033 */
3591f4cd
PU		 1034 dac33->nsample = period_size *
1035 ((dac33->alarm_threshold / period_size) +
1036 (dac33->alarm_threshold % period_size ?
1037 1 : 0));
1038 else if (period_size > nsample_limit)
1039 dac33->nsample = nsample_limit;
1040 else
1041 dac33->nsample = period_size;
f430a27f 1042
f57d2cfa
PU		 1043 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1044 dac33->nsample);
1045 dac33->t_stamp1 = 0;
1046 dac33->t_stamp2 = 0;
1047 break;
1048 case DAC33_FIFO_MODE7:
3591f4cd
PU		 1049 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1050 dac33->burst_rate) + 9;
1051 if (dac33->uthr > MODE7_UTHR)
1052 dac33->uthr = MODE7_UTHR;
1053 if (dac33->uthr < (MODE7_LTHR + 10))
1054 dac33->uthr = (MODE7_LTHR + 10);
1055
f57d2cfa 1056 dac33->mode7_us_to_lthr =
9d7db2b2
PU		 1057 SAMPLES_TO_US(substream->runtime->rate,
1058 dac33->uthr - MODE7_LTHR + 1);
f57d2cfa
PU		 1059 dac33->t_stamp1 = 0;
1060 break;
1061 default:
1062 break;
1063 }
c8bf93f0 1064
c8bf93f0
PU		 1065}
1066
1067static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1068 struct snd_soc_dai *dai)
1069{
1070 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1071 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1072 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1073 int ret = 0;
1074
1075 switch (cmd) {
1076 case SNDRV_PCM_TRIGGER_START:
1077 case SNDRV_PCM_TRIGGER_RESUME:
1078 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1079 if (dac33->fifo_mode) {
c8bf93f0
PU		 1080 dac33->state = DAC33_PREFILL;
1081 queue_work(dac33->dac33_wq, &dac33->work);
1082 }
1083 break;
1084 case SNDRV_PCM_TRIGGER_STOP:
1085 case SNDRV_PCM_TRIGGER_SUSPEND:
1086 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1087 if (dac33->fifo_mode) {
c8bf93f0
PU		 1088 dac33->state = DAC33_FLUSH;
1089 queue_work(dac33->dac33_wq, &dac33->work);
1090 }
1091 break;
1092 default:
1093 ret = -EINVAL;
1094 }
1095
1096 return ret;
1097}
1098
f57d2cfa
PU		 1099static snd_pcm_sframes_t dac33_dai_delay(
1100 struct snd_pcm_substream *substream,
1101 struct snd_soc_dai *dai)
1102{
1103 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1104 struct snd_soc_codec *codec = rtd->codec;
f57d2cfa
PU		 1105 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1106 unsigned long long t0, t1, t_now;
9d7db2b2 1107 unsigned int time_delta, uthr;
f57d2cfa
PU		 1108 int samples_out, samples_in, samples;
1109 snd_pcm_sframes_t delay = 0;
1110
1111 switch (dac33->fifo_mode) {
1112 case DAC33_FIFO_BYPASS:
1113 break;
1114 case DAC33_FIFO_MODE1:
1115 spin_lock(&dac33->lock);
1116 t0 = dac33->t_stamp1;
1117 t1 = dac33->t_stamp2;
1118 spin_unlock(&dac33->lock);
1119 t_now = ktime_to_us(ktime_get());
1120
1121 /* We have not started to fill the FIFO yet, delay is 0 */
1122 if (!t1)
1123 goto out;
1124
1125 if (t0 > t1) {
1126 /*
1127 * Phase 1:
1128 * After Alarm threshold, and before nSample write
1129 */
1130 time_delta = t_now - t0;
1131 samples_out = time_delta ? US_TO_SAMPLES(
1132 substream->runtime->rate,
1133 time_delta) : 0;
1134
1135 if (likely(dac33->alarm_threshold > samples_out))
1136 delay = dac33->alarm_threshold - samples_out;
1137 else
1138 delay = 0;
1139 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1140 /*
1141 * Phase 2:
1142 * After nSample write (during burst operation)
1143 */
1144 time_delta = t_now - t0;
1145 samples_out = time_delta ? US_TO_SAMPLES(
1146 substream->runtime->rate,
1147 time_delta) : 0;
1148
1149 time_delta = t_now - t1;
1150 samples_in = time_delta ? US_TO_SAMPLES(
1151 dac33->burst_rate,
1152 time_delta) : 0;
1153
1154 samples = dac33->alarm_threshold;
1155 samples += (samples_in - samples_out);
1156
1157 if (likely(samples > 0))
1158 delay = samples;
1159 else
1160 delay = 0;
1161 } else {
1162 /*
1163 * Phase 3:
1164 * After burst operation, before next alarm threshold
1165 */
1166 time_delta = t_now - t0;
1167 samples_out = time_delta ? US_TO_SAMPLES(
1168 substream->runtime->rate,
1169 time_delta) : 0;
1170
1171 samples_in = dac33->nsample;
1172 samples = dac33->alarm_threshold;
1173 samples += (samples_in - samples_out);
1174
1175 if (likely(samples > 0))
1176 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1177 DAC33_BUFFER_SIZE_SAMPLES : samples;
1178 else
1179 delay = 0;
1180 }
1181 break;
1182 case DAC33_FIFO_MODE7:
1183 spin_lock(&dac33->lock);
1184 t0 = dac33->t_stamp1;
9d7db2b2 1185 uthr = dac33->uthr;
f57d2cfa
PU		 1186 spin_unlock(&dac33->lock);
1187 t_now = ktime_to_us(ktime_get());
1188
1189 /* We have not started to fill the FIFO yet, delay is 0 */
1190 if (!t0)
1191 goto out;
1192
1193 if (t_now <= t0) {
1194 /*
1195 * Either the timestamps are messed or equal. Report
1196 * maximum delay
1197 */
9d7db2b2 1198 delay = uthr;
f57d2cfa
PU		 1199 goto out;
1200 }
1201
1202 time_delta = t_now - t0;
1203 if (time_delta <= dac33->mode7_us_to_lthr) {
1204 /*
1205 * Phase 1:
1206 * After burst (draining phase)
1207 */
1208 samples_out = US_TO_SAMPLES(
1209 substream->runtime->rate,
1210 time_delta);
1211
9d7db2b2
PU		 1212 if (likely(uthr > samples_out))
1213 delay = uthr - samples_out;
f57d2cfa
PU		 1214 else
1215 delay = 0;
1216 } else {
1217 /*
1218 * Phase 2:
1219 * During burst operation
1220 */
1221 time_delta = time_delta - dac33->mode7_us_to_lthr;
1222
1223 samples_out = US_TO_SAMPLES(
1224 substream->runtime->rate,
1225 time_delta);
1226 samples_in = US_TO_SAMPLES(
1227 dac33->burst_rate,
1228 time_delta);
1229 delay = MODE7_LTHR + samples_in - samples_out;
1230
9d7db2b2
PU		 1231 if (unlikely(delay > uthr))
1232 delay = uthr;
f57d2cfa
PU		 1233 }
1234 break;
1235 default:
1236 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1237 dac33->fifo_mode);
1238 break;
1239 }
1240out:
1241 return delay;
1242}
1243
c8bf93f0
PU		 1244static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1245 int clk_id, unsigned int freq, int dir)
1246{
1247 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1248 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1249 u8 ioc_reg, asrcb_reg;
1250
1251 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1252 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1253 switch (clk_id) {
1254 case TLV320DAC33_MCLK:
1255 ioc_reg |= DAC33_REFSEL;
1256 asrcb_reg |= DAC33_SRCREFSEL;
1257 break;
1258 case TLV320DAC33_SLEEPCLK:
1259 ioc_reg &= ~DAC33_REFSEL;
1260 asrcb_reg &= ~DAC33_SRCREFSEL;
1261 break;
1262 default:
1263 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1264 break;
1265 }
1266 dac33->refclk = freq;
1267
1268 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1269 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1270
1271 return 0;
1272}
1273
1274static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1275 unsigned int fmt)
1276{
1277 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1278 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1279 u8 aictrl_a, aictrl_b;
1280
1281 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1282 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1283 /* set master/slave audio interface */
1284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1285 case SND_SOC_DAIFMT_CBM_CFM:
1286 /* Codec Master */
1287 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1288 break;
1289 case SND_SOC_DAIFMT_CBS_CFS:
1290 /* Codec Slave */
adcb8bc0
PU		 1291 if (dac33->fifo_mode) {
1292 dev_err(codec->dev, "FIFO mode requires master mode\n");
1293 return -EINVAL;
1294 } else
1295 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1296 break;
1297 default:
1298 return -EINVAL;
1299 }
1300
1301 aictrl_a &= ~DAC33_AFMT_MASK;
1302 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1303 case SND_SOC_DAIFMT_I2S:
1304 aictrl_a |= DAC33_AFMT_I2S;
1305 break;
1306 case SND_SOC_DAIFMT_DSP_A:
1307 aictrl_a |= DAC33_AFMT_DSP;
1308 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1309 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1310 break;
1311 case SND_SOC_DAIFMT_RIGHT_J:
1312 aictrl_a |= DAC33_AFMT_RIGHT_J;
1313 break;
1314 case SND_SOC_DAIFMT_LEFT_J:
1315 aictrl_a |= DAC33_AFMT_LEFT_J;
1316 break;
1317 default:
1318 dev_err(codec->dev, "Unsupported format (%u)\n",
1319 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1320 return -EINVAL;
1321 }
1322
1323 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1324 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1325
1326 return 0;
1327}
1328
f0fba2ad 1329static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1330{
f0fba2ad 1331 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1332 int ret = 0;
1333
f0fba2ad
LG		 1334 codec->control_data = dac33->control_data;
1335 codec->hw_write = (hw_write_t) i2c_master_send;
ce6120cc 1336 codec->dapm.idle_bias_off = 1;
f0fba2ad 1337 dac33->codec = codec;
c8bf93f0 1338
f0fba2ad
LG		 1339 /* Read the tlv320dac33 ID registers */
1340 ret = dac33_hard_power(codec, 1);
1341 if (ret != 0) {
1342 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1343 goto err_power;
1344 }
911a0f0b 1345 ret = dac33_read_id(codec);
f0fba2ad 1346 dac33_hard_power(codec, 0);
c8bf93f0 1347
911a0f0b
PU		 1348 if (ret < 0) {
1349 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1350 ret = -ENODEV;
1351 goto err_power;
1352 }
1353
f0fba2ad
LG		 1354 /* Check if the IRQ number is valid and request it */
1355 if (dac33->irq >= 0) {
1356 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1357 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1358 codec->name, codec);
1359 if (ret < 0) {
1360 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1361 dac33->irq, ret);
1362 dac33->irq = -1;
1363 }
1364 if (dac33->irq != -1) {
1365 /* Setup work queue */
1366 dac33->dac33_wq =
1367 create_singlethread_workqueue("tlv320dac33");
1368 if (dac33->dac33_wq == NULL) {
1369 free_irq(dac33->irq, codec);
1370 return -ENOMEM;
1371 }
1372
1373 INIT_WORK(&dac33->work, dac33_work);
1374 }
c8bf93f0
PU		 1375 }
1376
1377 snd_soc_add_controls(codec, dac33_snd_controls,
1378 ARRAY_SIZE(dac33_snd_controls));
a577b318 1379 /* Only add the FIFO controls, if we have valid IRQ number */
3591f4cd 1380 if (dac33->irq >= 0)
a577b318
PU		 1381 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1382 ARRAY_SIZE(dac33_mode_snd_controls));
3591f4cd 1383
c8bf93f0
PU		 1384 dac33_add_widgets(codec);
1385
f0fba2ad 1386err_power:
c8bf93f0
PU		 1387 return ret;
1388}
1389
f0fba2ad 1390static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1391{
f0fba2ad 1392 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1393
1394 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1395
f0fba2ad
LG		 1396 if (dac33->irq >= 0) {
1397 free_irq(dac33->irq, dac33->codec);
1398 destroy_workqueue(dac33->dac33_wq);
1399 }
c8bf93f0
PU		 1400 return 0;
1401}
1402
f0fba2ad 1403static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
c8bf93f0 1404{
c8bf93f0
PU		 1405 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1406
1407 return 0;
1408}
1409
f0fba2ad 1410static int dac33_soc_resume(struct snd_soc_codec *codec)
c8bf93f0 1411{
c8bf93f0 1412 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1413
1414 return 0;
1415}
1416
f0fba2ad
LG		 1417static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1418 .read = dac33_read_reg_cache,
1419 .write = dac33_write_locked,
1420 .set_bias_level = dac33_set_bias_level,
1421 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1422 .reg_word_size = sizeof(u8),
1423 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1424 .probe = dac33_soc_probe,
1425 .remove = dac33_soc_remove,
1426 .suspend = dac33_soc_suspend,
1427 .resume = dac33_soc_resume,
1428};
c8bf93f0
PU		 1429
1430#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1431 SNDRV_PCM_RATE_48000)
1432#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1433
1434static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1435 .startup = dac33_startup,
c8bf93f0
PU		 1436 .shutdown = dac33_shutdown,
1437 .hw_params = dac33_hw_params,
c8bf93f0 1438 .trigger = dac33_pcm_trigger,
f57d2cfa 1439 .delay = dac33_dai_delay,
c8bf93f0
PU		 1440 .set_sysclk = dac33_set_dai_sysclk,
1441 .set_fmt = dac33_set_dai_fmt,
1442};
1443
f0fba2ad
LG		 1444static struct snd_soc_dai_driver dac33_dai = {
1445 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1446 .playback = {
1447 .stream_name = "Playback",
1448 .channels_min = 2,
1449 .channels_max = 2,
1450 .rates = DAC33_RATES,
1451 .formats = DAC33_FORMATS,},
1452 .ops = &dac33_dai_ops,
1453};
c8bf93f0 1454
735fe4cf
MB		 1455static int __devinit dac33_i2c_probe(struct i2c_client *client,
1456 const struct i2c_device_id *id)
c8bf93f0
PU		 1457{
1458 struct tlv320dac33_platform_data *pdata;
1459 struct tlv320dac33_priv *dac33;
3a7aaed7 1460 int ret, i;
c8bf93f0
PU		 1461
1462 if (client->dev.platform_data == NULL) {
1463 dev_err(&client->dev, "Platform data not set\n");
1464 return -ENODEV;
1465 }
1466 pdata = client->dev.platform_data;
1467
1468 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1469 if (dac33 == NULL)
1470 return -ENOMEM;
1471
f0fba2ad 1472 dac33->control_data = client;
c8bf93f0 1473 mutex_init(&dac33->mutex);
f57d2cfa 1474 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1475
1476 i2c_set_clientdata(client, dac33);
1477
1478 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1479 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1480 /* Pre calculate the burst rate */
1481 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1482 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1483 dac33->mode1_latency = pdata->mode1_latency;
1484 if (!dac33->mode1_latency)
1485 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0 1486 dac33->irq = client->irq;
c8bf93f0 1487 /* Disable FIFO use by default */
7427b4b9 1488 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1489
c8bf93f0
PU		 1490 /* Check if the reset GPIO number is valid and request it */
1491 if (dac33->power_gpio >= 0) {
1492 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1493 if (ret < 0) {
f0fba2ad 1494 dev_err(&client->dev,
c8bf93f0
PU		 1495 "Failed to request reset GPIO (%d)\n",
1496 dac33->power_gpio);
f0fba2ad 1497 goto err_gpio;
c8bf93f0
PU		 1498 }
1499 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1500 }
1501
3a7aaed7
IK		 1502 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1503 dac33->supplies[i].supply = dac33_supply_names[i];
1504
f0fba2ad 1505 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1506 dac33->supplies);
1507
1508 if (ret != 0) {
f0fba2ad 1509 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1510 goto err_get;
1511 }
1512
f0fba2ad
LG		 1513 ret = snd_soc_register_codec(&client->dev,
1514 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1515 if (ret < 0)
1516 goto err_register;
c8bf93f0 1517
c8bf93f0 1518 return ret;
f0fba2ad 1519err_register:
3a7aaed7
IK		 1520 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1521err_get:
c8bf93f0
PU		 1522 if (dac33->power_gpio >= 0)
1523 gpio_free(dac33->power_gpio);
f0fba2ad 1524err_gpio:
c8bf93f0 1525 kfree(dac33);
c8bf93f0
PU		 1526 return ret;
1527}
1528
735fe4cf 1529static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1530{
f0fba2ad 1531 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1532
1533 if (unlikely(dac33->chip_power))
f0fba2ad 1534 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1535
1536 if (dac33->power_gpio >= 0)
1537 gpio_free(dac33->power_gpio);
c8bf93f0 1538
3a7aaed7
IK		 1539 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1540
f0fba2ad 1541 snd_soc_unregister_codec(&client->dev);
c8bf93f0 1542 kfree(dac33);
c8bf93f0
PU		 1543
1544 return 0;
1545}
1546
1547static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1548 {
1549 .name = "tlv320dac33",
1550 .driver_data = 0,
1551 },
1552 { },
1553};
1554
1555static struct i2c_driver tlv320dac33_i2c_driver = {
1556 .driver = {
f0fba2ad 1557 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1558 .owner = THIS_MODULE,
1559 },
1560 .probe = dac33_i2c_probe,
1561 .remove = __devexit_p(dac33_i2c_remove),
1562 .id_table = tlv320dac33_i2c_id,
1563};
1564
1565static int __init dac33_module_init(void)
1566{
1567 int r;
1568 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1569 if (r < 0) {
1570 printk(KERN_ERR "DAC33: driver registration failed\n");
1571 return r;
1572 }
1573 return 0;
1574}
1575module_init(dac33_module_init);
1576
1577static void __exit dac33_module_exit(void)
1578{
1579 i2c_del_driver(&tlv320dac33_i2c_driver);
1580}
1581module_exit(dac33_module_exit);
1582
1583
1584MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1585MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1586MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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