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ASoC: tlv320dac33: BCLK divider fix
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
53static struct snd_soc_codec *tlv320dac33_codec;
54
55enum dac33_state {
56 DAC33_IDLE = 0,
57 DAC33_PREFILL,
58 DAC33_PLAYBACK,
59 DAC33_FLUSH,
60};
61
7427b4b9
PU		 62enum dac33_fifo_modes {
63 DAC33_FIFO_BYPASS = 0,
64 DAC33_FIFO_MODE1,
28e05d98 65 DAC33_FIFO_MODE7,
7427b4b9
PU		 66 DAC33_FIFO_LAST_MODE,
67};
68
3a7aaed7
IK		 69#define DAC33_NUM_SUPPLIES 3
70static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
71 "AVDD",
72 "DVDD",
73 "IOVDD",
74};
75
c8bf93f0
PU		 76struct tlv320dac33_priv {
77 struct mutex mutex;
78 struct workqueue_struct *dac33_wq;
79 struct work_struct work;
80 struct snd_soc_codec codec;
3a7aaed7 81 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 82 int power_gpio;
83 int chip_power;
84 int irq;
85 unsigned int refclk;
86
87 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
88 unsigned int nsample_min; /* nsample should not be lower than
89 * this */
90 unsigned int nsample_max; /* nsample should not be higher than
91 * this */
7427b4b9 92 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0
PU		 93 unsigned int nsample; /* burst read amount from host */
94
95 enum dac33_state state;
96};
97
98static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
990x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1000x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1010x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1020x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1030x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1040x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1050x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1060x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1070x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1080x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1090x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1100x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1110x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1120x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1130x00, 0x00, /* 0x38 - 0x39 */
114/* Registers 0x3a - 0x3f are reserved */
115 0x00, 0x00, /* 0x3a - 0x3b */
1160x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
117
1180x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1190x00, 0x80, /* 0x44 - 0x45 */
120/* Registers 0x46 - 0x47 are reserved */
121 0x80, 0x80, /* 0x46 - 0x47 */
122
1230x80, 0x00, 0x00, /* 0x48 - 0x4a */
124/* Registers 0x4b - 0x7c are reserved */
125 0x00, /* 0x4b */
1260x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1270x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1280x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1290x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1300x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1310x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1320x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1330x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1340x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1350x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1360x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1370x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1380x00, /* 0x7c */
139
140 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
141};
142
143/* Register read and write */
144static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
145 unsigned reg)
146{
147 u8 *cache = codec->reg_cache;
148 if (reg >= DAC33_CACHEREGNUM)
149 return 0;
150
151 return cache[reg];
152}
153
154static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
155 u8 reg, u8 value)
156{
157 u8 *cache = codec->reg_cache;
158 if (reg >= DAC33_CACHEREGNUM)
159 return;
160
161 cache[reg] = value;
162}
163
164static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
165 u8 *value)
166{
167 struct tlv320dac33_priv *dac33 = codec->private_data;
168 int val;
169
170 *value = reg & 0xff;
171
172 /* If powered off, return the cached value */
173 if (dac33->chip_power) {
174 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
175 if (val < 0) {
176 dev_err(codec->dev, "Read failed (%d)\n", val);
177 value[0] = dac33_read_reg_cache(codec, reg);
178 } else {
179 value[0] = val;
180 dac33_write_reg_cache(codec, reg, val);
181 }
182 } else {
183 value[0] = dac33_read_reg_cache(codec, reg);
184 }
185
186 return 0;
187}
188
189static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
190 unsigned int value)
191{
192 struct tlv320dac33_priv *dac33 = codec->private_data;
193 u8 data[2];
194 int ret = 0;
195
196 /*
197 * data is
198 * D15..D8 dac33 register offset
199 * D7...D0 register data
200 */
201 data[0] = reg & 0xff;
202 data[1] = value & 0xff;
203
204 dac33_write_reg_cache(codec, data[0], data[1]);
205 if (dac33->chip_power) {
206 ret = codec->hw_write(codec->control_data, data, 2);
207 if (ret != 2)
208 dev_err(codec->dev, "Write failed (%d)\n", ret);
209 else
210 ret = 0;
211 }
212
213 return ret;
214}
215
216static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
217 unsigned int value)
218{
219 struct tlv320dac33_priv *dac33 = codec->private_data;
220 int ret;
221
222 mutex_lock(&dac33->mutex);
223 ret = dac33_write(codec, reg, value);
224 mutex_unlock(&dac33->mutex);
225
226 return ret;
227}
228
229#define DAC33_I2C_ADDR_AUTOINC 0x80
230static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
231 unsigned int value)
232{
233 struct tlv320dac33_priv *dac33 = codec->private_data;
234 u8 data[3];
235 int ret = 0;
236
237 /*
238 * data is
239 * D23..D16 dac33 register offset
240 * D15..D8 register data MSB
241 * D7...D0 register data LSB
242 */
243 data[0] = reg & 0xff;
244 data[1] = (value >> 8) & 0xff;
245 data[2] = value & 0xff;
246
247 dac33_write_reg_cache(codec, data[0], data[1]);
248 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
249
250 if (dac33->chip_power) {
251 /* We need to set autoincrement mode for 16 bit writes */
252 data[0] |= DAC33_I2C_ADDR_AUTOINC;
253 ret = codec->hw_write(codec->control_data, data, 3);
254 if (ret != 3)
255 dev_err(codec->dev, "Write failed (%d)\n", ret);
256 else
257 ret = 0;
258 }
259
260 return ret;
261}
262
263static void dac33_restore_regs(struct snd_soc_codec *codec)
264{
265 struct tlv320dac33_priv *dac33 = codec->private_data;
266 u8 *cache = codec->reg_cache;
267 u8 data[2];
268 int i, ret;
269
270 if (!dac33->chip_power)
271 return;
272
273 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
274 data[0] = i;
275 data[1] = cache[i];
276 /* Skip the read only registers */
277 if ((i >= DAC33_INT_OSC_STATUS &&
278 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
279 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
280 i == DAC33_DAC_STATUS_FLAGS ||
281 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
282 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
283 continue;
284 ret = codec->hw_write(codec->control_data, data, 2);
285 if (ret != 2)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 }
288 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
289 data[0] = i;
290 data[1] = cache[i];
291 ret = codec->hw_write(codec->control_data, data, 2);
292 if (ret != 2)
293 dev_err(codec->dev, "Write failed (%d)\n", ret);
294 }
295 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
296 data[0] = i;
297 data[1] = cache[i];
298 ret = codec->hw_write(codec->control_data, data, 2);
299 if (ret != 2)
300 dev_err(codec->dev, "Write failed (%d)\n", ret);
301 }
302}
303
304static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
305{
306 u8 reg;
307
308 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
309 if (power)
310 reg |= DAC33_PDNALLB;
311 else
312 reg &= ~DAC33_PDNALLB;
313 dac33_write(codec, DAC33_PWR_CTRL, reg);
314}
315
3a7aaed7 316static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0
PU		 317{
318 struct tlv320dac33_priv *dac33 = codec->private_data;
3a7aaed7 319 int ret;
c8bf93f0
PU		 320
321 mutex_lock(&dac33->mutex);
322 if (power) {
3a7aaed7
IK		 323 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
324 dac33->supplies);
325 if (ret != 0) {
326 dev_err(codec->dev,
327 "Failed to enable supplies: %d\n", ret);
328 goto exit;
c8bf93f0 329 }
3a7aaed7
IK		 330
331 if (dac33->power_gpio >= 0)
332 gpio_set_value(dac33->power_gpio, 1);
333
334 dac33->chip_power = 1;
335
336 /* Restore registers */
337 dac33_restore_regs(codec);
338
c8bf93f0
PU		 339 dac33_soft_power(codec, 1);
340 } else {
341 dac33_soft_power(codec, 0);
3a7aaed7 342 if (dac33->power_gpio >= 0)
c8bf93f0 343 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 344
345 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
346 dac33->supplies);
347 if (ret != 0) {
348 dev_err(codec->dev,
349 "Failed to disable supplies: %d\n", ret);
350 goto exit;
c8bf93f0 351 }
3a7aaed7
IK		 352
353 dac33->chip_power = 0;
c8bf93f0 354 }
c8bf93f0 355
3a7aaed7
IK		 356exit:
357 mutex_unlock(&dac33->mutex);
358 return ret;
c8bf93f0
PU		 359}
360
361static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
365 struct tlv320dac33_priv *dac33 = codec->private_data;
366
367 ucontrol->value.integer.value[0] = dac33->nsample;
368
369 return 0;
370}
371
372static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374{
375 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
376 struct tlv320dac33_priv *dac33 = codec->private_data;
377 int ret = 0;
378
379 if (dac33->nsample == ucontrol->value.integer.value[0])
380 return 0;
381
382 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
383 ucontrol->value.integer.value[0] > dac33->nsample_max)
384 ret = -EINVAL;
385 else
386 dac33->nsample = ucontrol->value.integer.value[0];
387
388 return ret;
389}
390
7427b4b9 391static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 392 struct snd_ctl_elem_value *ucontrol)
393{
394 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
395 struct tlv320dac33_priv *dac33 = codec->private_data;
396
7427b4b9 397 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 398
399 return 0;
400}
401
7427b4b9 402static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 403 struct snd_ctl_elem_value *ucontrol)
404{
405 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
406 struct tlv320dac33_priv *dac33 = codec->private_data;
407 int ret = 0;
408
7427b4b9 409 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 410 return 0;
411 /* Do not allow changes while stream is running*/
412 if (codec->active)
413 return -EPERM;
414
415 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 416 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 417 ret = -EINVAL;
418 else
7427b4b9 419 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 420
421 return ret;
422}
423
7427b4b9
PU		 424/* Codec operation modes */
425static const char *dac33_fifo_mode_texts[] = {
28e05d98 426 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 427};
428
429static const struct soc_enum dac33_fifo_mode_enum =
430 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
431 dac33_fifo_mode_texts);
432
c8bf93f0
PU		 433/*
434 * DACL/R digital volume control:
435 * from 0 dB to -63.5 in 0.5 dB steps
436 * Need to be inverted later on:
437 * 0x00 == 0 dB
438 * 0x7f == -63.5 dB
439 */
440static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
441
442static const struct snd_kcontrol_new dac33_snd_controls[] = {
443 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
444 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
445 0, 0x7f, 1, dac_digivol_tlv),
446 SOC_DOUBLE_R("DAC Digital Playback Switch",
447 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
448 SOC_DOUBLE_R("Line to Line Out Volume",
449 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
450};
451
452static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
453 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
454 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 455 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
456 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 457};
458
459/* Analog bypass */
460static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
461 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
462
463static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
464 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
465
466static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
467 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
468 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
469
470 SND_SOC_DAPM_INPUT("LINEL"),
471 SND_SOC_DAPM_INPUT("LINER"),
472
473 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
474 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
475
476 /* Analog bypass */
477 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
478 &dac33_dapm_abypassl_control),
479 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
480 &dac33_dapm_abypassr_control),
481
482 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
483 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
484 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
485 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
486};
487
488static const struct snd_soc_dapm_route audio_map[] = {
489 /* Analog bypass */
490 {"Analog Left Bypass", "Switch", "LINEL"},
491 {"Analog Right Bypass", "Switch", "LINER"},
492
493 {"Output Left Amp Power", NULL, "DACL"},
494 {"Output Right Amp Power", NULL, "DACR"},
495
496 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
497 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
498
499 /* output */
500 {"LEFT_LO", NULL, "Output Left Amp Power"},
501 {"RIGHT_LO", NULL, "Output Right Amp Power"},
502};
503
504static int dac33_add_widgets(struct snd_soc_codec *codec)
505{
506 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
507 ARRAY_SIZE(dac33_dapm_widgets));
508
509 /* set up audio path interconnects */
510 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 511
512 return 0;
513}
514
515static int dac33_set_bias_level(struct snd_soc_codec *codec,
516 enum snd_soc_bias_level level)
517{
3a7aaed7
IK		 518 int ret;
519
c8bf93f0
PU		 520 switch (level) {
521 case SND_SOC_BIAS_ON:
522 dac33_soft_power(codec, 1);
523 break;
524 case SND_SOC_BIAS_PREPARE:
525 break;
526 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 527 if (codec->bias_level == SND_SOC_BIAS_OFF) {
528 ret = dac33_hard_power(codec, 1);
529 if (ret != 0)
530 return ret;
531 }
532
c8bf93f0
PU		 533 dac33_soft_power(codec, 0);
534 break;
535 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 536 ret = dac33_hard_power(codec, 0);
537 if (ret != 0)
538 return ret;
539
c8bf93f0
PU		 540 break;
541 }
542 codec->bias_level = level;
543
544 return 0;
545}
546
d4f102d4
PU		 547static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
548{
549 struct snd_soc_codec *codec;
550
551 codec = &dac33->codec;
552
553 switch (dac33->fifo_mode) {
554 case DAC33_FIFO_MODE1:
555 dac33_write16(codec, DAC33_NSAMPLE_MSB,
556 DAC33_THRREG(dac33->nsample));
557 dac33_write16(codec, DAC33_PREFILL_MSB,
558 DAC33_THRREG(dac33->alarm_threshold));
559 break;
28e05d98
PU		 560 case DAC33_FIFO_MODE7:
561 dac33_write16(codec, DAC33_PREFILL_MSB,
a5b5a064 562 DAC33_THRREG(10));
28e05d98 563 break;
d4f102d4
PU		 564 default:
565 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
566 dac33->fifo_mode);
567 break;
568 }
569}
570
571static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
572{
573 struct snd_soc_codec *codec;
574
575 codec = &dac33->codec;
576
577 switch (dac33->fifo_mode) {
578 case DAC33_FIFO_MODE1:
579 dac33_write16(codec, DAC33_NSAMPLE_MSB,
580 DAC33_THRREG(dac33->nsample));
581 break;
28e05d98
PU		 582 case DAC33_FIFO_MODE7:
583 /* At the moment we are not using interrupts in mode7 */
584 break;
d4f102d4
PU		 585 default:
586 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
587 dac33->fifo_mode);
588 break;
589 }
590}
591
c8bf93f0
PU		 592static void dac33_work(struct work_struct *work)
593{
594 struct snd_soc_codec *codec;
595 struct tlv320dac33_priv *dac33;
596 u8 reg;
597
598 dac33 = container_of(work, struct tlv320dac33_priv, work);
599 codec = &dac33->codec;
600
601 mutex_lock(&dac33->mutex);
602 switch (dac33->state) {
603 case DAC33_PREFILL:
604 dac33->state = DAC33_PLAYBACK;
d4f102d4 605 dac33_prefill_handler(dac33);
c8bf93f0
PU		 606 break;
607 case DAC33_PLAYBACK:
d4f102d4 608 dac33_playback_handler(dac33);
c8bf93f0
PU		 609 break;
610 case DAC33_IDLE:
611 break;
612 case DAC33_FLUSH:
613 dac33->state = DAC33_IDLE;
614 /* Mask all interrupts from dac33 */
615 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
616
617 /* flush fifo */
618 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
619 reg |= DAC33_FIFOFLUSH;
620 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
621 break;
622 }
623 mutex_unlock(&dac33->mutex);
624}
625
626static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
627{
628 struct snd_soc_codec *codec = dev;
629 struct tlv320dac33_priv *dac33 = codec->private_data;
630
631 queue_work(dac33->dac33_wq, &dac33->work);
632
633 return IRQ_HANDLED;
634}
635
636static void dac33_shutdown(struct snd_pcm_substream *substream,
637 struct snd_soc_dai *dai)
638{
639 struct snd_soc_pcm_runtime *rtd = substream->private_data;
640 struct snd_soc_device *socdev = rtd->socdev;
641 struct snd_soc_codec *codec = socdev->card->codec;
642 struct tlv320dac33_priv *dac33 = codec->private_data;
643 unsigned int pwr_ctrl;
644
645 /* Stop pending workqueue */
7427b4b9 646 if (dac33->fifo_mode)
c8bf93f0
PU		 647 cancel_work_sync(&dac33->work);
648
649 mutex_lock(&dac33->mutex);
650 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
651 pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
652 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
653 mutex_unlock(&dac33->mutex);
654}
655
656static void dac33_oscwait(struct snd_soc_codec *codec)
657{
658 int timeout = 20;
659 u8 reg;
660
661 do {
662 msleep(1);
663 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
664 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
665 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
666 dev_err(codec->dev,
667 "internal oscillator calibration failed\n");
668}
669
670static int dac33_hw_params(struct snd_pcm_substream *substream,
671 struct snd_pcm_hw_params *params,
672 struct snd_soc_dai *dai)
673{
674 struct snd_soc_pcm_runtime *rtd = substream->private_data;
675 struct snd_soc_device *socdev = rtd->socdev;
676 struct snd_soc_codec *codec = socdev->card->codec;
677
678 /* Check parameters for validity */
679 switch (params_rate(params)) {
680 case 44100:
681 case 48000:
682 break;
683 default:
684 dev_err(codec->dev, "unsupported rate %d\n",
685 params_rate(params));
686 return -EINVAL;
687 }
688
689 switch (params_format(params)) {
690 case SNDRV_PCM_FORMAT_S16_LE:
691 break;
692 default:
693 dev_err(codec->dev, "unsupported format %d\n",
694 params_format(params));
695 return -EINVAL;
696 }
697
698 return 0;
699}
700
701#define CALC_OSCSET(rate, refclk) ( \
702 ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
703#define CALC_RATIOSET(rate, refclk) ( \
704 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
705
706/*
707 * tlv320dac33 is strict on the sequence of the register writes, if the register
708 * writes happens in different order, than dac33 might end up in unknown state.
709 * Use the known, working sequence of register writes to initialize the dac33.
710 */
711static int dac33_prepare_chip(struct snd_pcm_substream *substream)
712{
713 struct snd_soc_pcm_runtime *rtd = substream->private_data;
714 struct snd_soc_device *socdev = rtd->socdev;
715 struct snd_soc_codec *codec = socdev->card->codec;
716 struct tlv320dac33_priv *dac33 = codec->private_data;
717 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 718 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 719
720 switch (substream->runtime->rate) {
721 case 44100:
722 case 48000:
723 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
724 ratioset = CALC_RATIOSET(substream->runtime->rate,
725 dac33->refclk);
726 break;
727 default:
728 dev_err(codec->dev, "unsupported rate %d\n",
729 substream->runtime->rate);
730 return -EINVAL;
731 }
732
733
734 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
735 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
736 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
737 fifoctrl_a &= ~DAC33_WIDTH;
738 switch (substream->runtime->format) {
739 case SNDRV_PCM_FORMAT_S16_LE:
740 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
741 fifoctrl_a |= DAC33_WIDTH;
742 break;
743 default:
744 dev_err(codec->dev, "unsupported format %d\n",
745 substream->runtime->format);
746 return -EINVAL;
747 }
748
749 mutex_lock(&dac33->mutex);
750 dac33_soft_power(codec, 1);
751
752 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
753 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
754
755 /* Write registers 0x08 and 0x09 (MSB, LSB) */
756 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
757
758 /* calib time: 128 is a nice number ;) */
759 dac33_write(codec, DAC33_CALIB_TIME, 128);
760
761 /* adjustment treshold & step */
762 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
763 DAC33_ADJSTEP(1));
764
765 /* div=4 / gain=1 / div */
766 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
767
768 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
769 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
770 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
771
772 dac33_oscwait(codec);
773
7427b4b9 774 if (dac33->fifo_mode) {
aec242dc 775 /* Generic for all FIFO modes */
c8bf93f0
PU		 776 /* 50-51 : ASRC Control registers */
777 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
778 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
779
780 /* Write registers 0x34 and 0x35 (MSB, LSB) */
781 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
782
783 /* Set interrupts to high active */
784 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 785 } else {
aec242dc 786 /* FIFO bypass mode */
c8bf93f0
PU		 787 /* 50-51 : ASRC Control registers */
788 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
789 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
790 }
791
aec242dc
PU		 792 /* Interrupt behaviour configuration */
793 switch (dac33->fifo_mode) {
794 case DAC33_FIFO_MODE1:
795 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
796 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
797 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
798 break;
28e05d98
PU		 799 case DAC33_FIFO_MODE7:
800 /* Disable all interrupts */
801 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
802 break;
aec242dc
PU		 803 default:
804 /* in FIFO bypass mode, the interrupts are not used */
805 break;
806 }
807
808 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
809
810 switch (dac33->fifo_mode) {
811 case DAC33_FIFO_MODE1:
812 /*
813 * For mode1:
814 * Disable the FIFO bypass (Enable the use of FIFO)
815 * Select nSample mode
816 * BCLK is only running when data is needed by DAC33
817 */
c8bf93f0 818 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc
PU		 819 fifoctrl_a &= ~DAC33_FAUTO;
820 aictrl_b &= ~DAC33_BCLKON;
821 break;
28e05d98
PU		 822 case DAC33_FIFO_MODE7:
823 /*
824 * For mode1:
825 * Disable the FIFO bypass (Enable the use of FIFO)
826 * Select Threshold mode
827 * BCLK is only running when data is needed by DAC33
828 */
829 fifoctrl_a &= ~DAC33_FBYPAS;
830 fifoctrl_a |= DAC33_FAUTO;
831 aictrl_b &= ~DAC33_BCLKON;
832 break;
aec242dc
PU		 833 default:
834 /*
835 * For FIFO bypass mode:
836 * Enable the FIFO bypass (Disable the FIFO use)
837 * Set the BCLK as continous
838 */
c8bf93f0 839 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 840 aictrl_b |= DAC33_BCLKON;
841 break;
842 }
c8bf93f0 843
aec242dc 844 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 845 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 846 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 847
6cd6cede
PU		 848 /* BCLK divide ratio */
849 if (dac33->fifo_mode)
c8bf93f0 850 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
6cd6cede
PU		 851 else
852 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 853
6cd6cede
PU		 854 switch (dac33->fifo_mode) {
855 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 856 dac33_write16(codec, DAC33_ATHR_MSB,
857 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 858 break;
28e05d98
PU		 859 case DAC33_FIFO_MODE7:
860 /*
861 * Configure the threshold levels, and leave 10 sample space
862 * at the bottom, and also at the top of the FIFO
863 */
864 dac33_write16(codec, DAC33_UTHR_MSB,
865 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10));
866 dac33_write16(codec, DAC33_LTHR_MSB,
867 DAC33_THRREG(10));
868 break;
aec242dc 869 default:
aec242dc 870 break;
c8bf93f0
PU		 871 }
872
873 mutex_unlock(&dac33->mutex);
874
875 return 0;
876}
877
878static void dac33_calculate_times(struct snd_pcm_substream *substream)
879{
880 struct snd_soc_pcm_runtime *rtd = substream->private_data;
881 struct snd_soc_device *socdev = rtd->socdev;
882 struct snd_soc_codec *codec = socdev->card->codec;
883 struct tlv320dac33_priv *dac33 = codec->private_data;
884 unsigned int nsample_limit;
885
886 /* Number of samples (16bit, stereo) in one period */
887 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
888
889 /* Number of samples (16bit, stereo) in ALSA buffer */
890 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
891 /* Subtract one period from the total */
892 dac33->nsample_max -= dac33->nsample_min;
893
894 /* Number of samples for LATENCY_TIME_MS / 2 */
895 dac33->alarm_threshold = substream->runtime->rate /
896 (1000 / (LATENCY_TIME_MS / 2));
897
898 /* Find and fix up the lowest nsmaple limit */
899 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
900
901 if (dac33->nsample_min < nsample_limit)
902 dac33->nsample_min = nsample_limit;
903
904 if (dac33->nsample < dac33->nsample_min)
905 dac33->nsample = dac33->nsample_min;
906
907 /*
908 * Find and fix up the highest nsmaple limit
909 * In order to not overflow the DAC33 buffer substract the
910 * alarm_threshold value from the size of the DAC33 buffer
911 */
912 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
913
914 if (dac33->nsample_max > nsample_limit)
915 dac33->nsample_max = nsample_limit;
916
917 if (dac33->nsample > dac33->nsample_max)
918 dac33->nsample = dac33->nsample_max;
919}
920
921static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
922 struct snd_soc_dai *dai)
923{
924 dac33_calculate_times(substream);
925 dac33_prepare_chip(substream);
926
927 return 0;
928}
929
930static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
931 struct snd_soc_dai *dai)
932{
933 struct snd_soc_pcm_runtime *rtd = substream->private_data;
934 struct snd_soc_device *socdev = rtd->socdev;
935 struct snd_soc_codec *codec = socdev->card->codec;
936 struct tlv320dac33_priv *dac33 = codec->private_data;
937 int ret = 0;
938
939 switch (cmd) {
940 case SNDRV_PCM_TRIGGER_START:
941 case SNDRV_PCM_TRIGGER_RESUME:
942 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 943 if (dac33->fifo_mode) {
c8bf93f0
PU		 944 dac33->state = DAC33_PREFILL;
945 queue_work(dac33->dac33_wq, &dac33->work);
946 }
947 break;
948 case SNDRV_PCM_TRIGGER_STOP:
949 case SNDRV_PCM_TRIGGER_SUSPEND:
950 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 951 if (dac33->fifo_mode) {
c8bf93f0
PU		 952 dac33->state = DAC33_FLUSH;
953 queue_work(dac33->dac33_wq, &dac33->work);
954 }
955 break;
956 default:
957 ret = -EINVAL;
958 }
959
960 return ret;
961}
962
963static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
964 int clk_id, unsigned int freq, int dir)
965{
966 struct snd_soc_codec *codec = codec_dai->codec;
967 struct tlv320dac33_priv *dac33 = codec->private_data;
968 u8 ioc_reg, asrcb_reg;
969
970 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
971 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
972 switch (clk_id) {
973 case TLV320DAC33_MCLK:
974 ioc_reg |= DAC33_REFSEL;
975 asrcb_reg |= DAC33_SRCREFSEL;
976 break;
977 case TLV320DAC33_SLEEPCLK:
978 ioc_reg &= ~DAC33_REFSEL;
979 asrcb_reg &= ~DAC33_SRCREFSEL;
980 break;
981 default:
982 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
983 break;
984 }
985 dac33->refclk = freq;
986
987 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
988 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
989
990 return 0;
991}
992
993static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
994 unsigned int fmt)
995{
996 struct snd_soc_codec *codec = codec_dai->codec;
adcb8bc0 997 struct tlv320dac33_priv *dac33 = codec->private_data;
c8bf93f0
PU		 998 u8 aictrl_a, aictrl_b;
999
1000 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1001 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1002 /* set master/slave audio interface */
1003 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1004 case SND_SOC_DAIFMT_CBM_CFM:
1005 /* Codec Master */
1006 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1007 break;
1008 case SND_SOC_DAIFMT_CBS_CFS:
1009 /* Codec Slave */
adcb8bc0
PU		 1010 if (dac33->fifo_mode) {
1011 dev_err(codec->dev, "FIFO mode requires master mode\n");
1012 return -EINVAL;
1013 } else
1014 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1015 break;
1016 default:
1017 return -EINVAL;
1018 }
1019
1020 aictrl_a &= ~DAC33_AFMT_MASK;
1021 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1022 case SND_SOC_DAIFMT_I2S:
1023 aictrl_a |= DAC33_AFMT_I2S;
1024 break;
1025 case SND_SOC_DAIFMT_DSP_A:
1026 aictrl_a |= DAC33_AFMT_DSP;
1027 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1028 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
1029 break;
1030 case SND_SOC_DAIFMT_DSP_B:
1031 aictrl_a |= DAC33_AFMT_DSP;
1032 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
1033 break;
1034 case SND_SOC_DAIFMT_RIGHT_J:
1035 aictrl_a |= DAC33_AFMT_RIGHT_J;
1036 break;
1037 case SND_SOC_DAIFMT_LEFT_J:
1038 aictrl_a |= DAC33_AFMT_LEFT_J;
1039 break;
1040 default:
1041 dev_err(codec->dev, "Unsupported format (%u)\n",
1042 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1043 return -EINVAL;
1044 }
1045
1046 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1047 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1048
1049 return 0;
1050}
1051
1052static void dac33_init_chip(struct snd_soc_codec *codec)
1053{
1054 /* 44-46: DAC Control Registers */
1055 /* A : DAC sample rate Fsref/1.5 */
1056 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
1057 /* B : DAC src=normal, not muted */
1058 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1059 DAC33_DACSRCL_LEFT);
1060 /* C : (defaults) */
1061 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1062
1063 /* 64-65 : L&R DAC power control
1064 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1065 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1066 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1067
1068 /* 73 : volume soft stepping control,
1069 clock source = internal osc (?) */
1070 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1071
1072 /* 66 : LOP/LOM Modes */
1073 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1074
1075 /* 68 : LOM inverted from LOP */
1076 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1077
1078 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1079}
1080
1081static int dac33_soc_probe(struct platform_device *pdev)
1082{
1083 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1084 struct snd_soc_codec *codec;
1085 struct tlv320dac33_priv *dac33;
1086 int ret = 0;
1087
1088 BUG_ON(!tlv320dac33_codec);
1089
1090 codec = tlv320dac33_codec;
1091 socdev->card->codec = codec;
1092 dac33 = codec->private_data;
1093
1094 /* Power up the codec */
1095 dac33_hard_power(codec, 1);
1096 /* Set default configuration */
1097 dac33_init_chip(codec);
1098
1099 /* register pcms */
1100 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1101 if (ret < 0) {
1102 dev_err(codec->dev, "failed to create pcms\n");
1103 goto pcm_err;
1104 }
1105
1106 snd_soc_add_controls(codec, dac33_snd_controls,
1107 ARRAY_SIZE(dac33_snd_controls));
1108 /* Only add the nSample controls, if we have valid IRQ number */
1109 if (dac33->irq >= 0)
1110 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1111 ARRAY_SIZE(dac33_nsample_snd_controls));
1112
1113 dac33_add_widgets(codec);
1114
1115 /* power on device */
1116 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1117
3a7aaed7
IK		 1118 /* Bias level configuration has enabled regulator an extra time */
1119 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1120
c8bf93f0 1121 return 0;
fe3e78e0 1122
c8bf93f0
PU		 1123pcm_err:
1124 dac33_hard_power(codec, 0);
1125 return ret;
1126}
1127
1128static int dac33_soc_remove(struct platform_device *pdev)
1129{
1130 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1131 struct snd_soc_codec *codec = socdev->card->codec;
1132
1133 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1134
1135 snd_soc_free_pcms(socdev);
1136 snd_soc_dapm_free(socdev);
1137
1138 return 0;
1139}
1140
1141static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1142{
1143 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1144 struct snd_soc_codec *codec = socdev->card->codec;
1145
1146 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1147
1148 return 0;
1149}
1150
1151static int dac33_soc_resume(struct platform_device *pdev)
1152{
1153 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1154 struct snd_soc_codec *codec = socdev->card->codec;
1155
1156 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1157 dac33_set_bias_level(codec, codec->suspend_bias_level);
1158
1159 return 0;
1160}
1161
1162struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1163 .probe = dac33_soc_probe,
1164 .remove = dac33_soc_remove,
1165 .suspend = dac33_soc_suspend,
1166 .resume = dac33_soc_resume,
1167};
1168EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1169
1170#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1171 SNDRV_PCM_RATE_48000)
1172#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1173
1174static struct snd_soc_dai_ops dac33_dai_ops = {
1175 .shutdown = dac33_shutdown,
1176 .hw_params = dac33_hw_params,
1177 .prepare = dac33_pcm_prepare,
1178 .trigger = dac33_pcm_trigger,
1179 .set_sysclk = dac33_set_dai_sysclk,
1180 .set_fmt = dac33_set_dai_fmt,
1181};
1182
1183struct snd_soc_dai dac33_dai = {
1184 .name = "tlv320dac33",
1185 .playback = {
1186 .stream_name = "Playback",
1187 .channels_min = 2,
1188 .channels_max = 2,
1189 .rates = DAC33_RATES,
1190 .formats = DAC33_FORMATS,},
1191 .ops = &dac33_dai_ops,
1192};
1193EXPORT_SYMBOL_GPL(dac33_dai);
1194
735fe4cf
MB		 1195static int __devinit dac33_i2c_probe(struct i2c_client *client,
1196 const struct i2c_device_id *id)
c8bf93f0
PU		 1197{
1198 struct tlv320dac33_platform_data *pdata;
1199 struct tlv320dac33_priv *dac33;
1200 struct snd_soc_codec *codec;
3a7aaed7 1201 int ret, i;
c8bf93f0
PU		 1202
1203 if (client->dev.platform_data == NULL) {
1204 dev_err(&client->dev, "Platform data not set\n");
1205 return -ENODEV;
1206 }
1207 pdata = client->dev.platform_data;
1208
1209 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1210 if (dac33 == NULL)
1211 return -ENOMEM;
1212
1213 codec = &dac33->codec;
1214 codec->private_data = dac33;
1215 codec->control_data = client;
1216
1217 mutex_init(&codec->mutex);
1218 mutex_init(&dac33->mutex);
1219 INIT_LIST_HEAD(&codec->dapm_widgets);
1220 INIT_LIST_HEAD(&codec->dapm_paths);
1221
1222 codec->name = "tlv320dac33";
1223 codec->owner = THIS_MODULE;
1224 codec->read = dac33_read_reg_cache;
1225 codec->write = dac33_write_locked;
1226 codec->hw_write = (hw_write_t) i2c_master_send;
1227 codec->bias_level = SND_SOC_BIAS_OFF;
1228 codec->set_bias_level = dac33_set_bias_level;
1229 codec->dai = &dac33_dai;
1230 codec->num_dai = 1;
1231 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1232 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1233 GFP_KERNEL);
1234 if (codec->reg_cache == NULL) {
1235 ret = -ENOMEM;
1236 goto error_reg;
1237 }
1238
1239 i2c_set_clientdata(client, dac33);
1240
1241 dac33->power_gpio = pdata->power_gpio;
1242 dac33->irq = client->irq;
1243 dac33->nsample = NSAMPLE_MAX;
1244 /* Disable FIFO use by default */
7427b4b9 1245 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1246
1247 tlv320dac33_codec = codec;
1248
1249 codec->dev = &client->dev;
1250 dac33_dai.dev = codec->dev;
1251
1252 /* Check if the reset GPIO number is valid and request it */
1253 if (dac33->power_gpio >= 0) {
1254 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1255 if (ret < 0) {
1256 dev_err(codec->dev,
1257 "Failed to request reset GPIO (%d)\n",
1258 dac33->power_gpio);
1259 snd_soc_unregister_dai(&dac33_dai);
1260 snd_soc_unregister_codec(codec);
1261 goto error_gpio;
1262 }
1263 gpio_direction_output(dac33->power_gpio, 0);
1264 } else {
1265 dac33->chip_power = 1;
1266 }
1267
1268 /* Check if the IRQ number is valid and request it */
1269 if (dac33->irq >= 0) {
1270 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1271 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1272 codec->name, codec);
1273 if (ret < 0) {
1274 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1275 dac33->irq, ret);
1276 dac33->irq = -1;
1277 }
1278 if (dac33->irq != -1) {
1279 /* Setup work queue */
74ea23aa
PU		 1280 dac33->dac33_wq =
1281 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1282 if (dac33->dac33_wq == NULL) {
1283 free_irq(dac33->irq, &dac33->codec);
1284 ret = -ENOMEM;
1285 goto error_wq;
1286 }
1287
1288 INIT_WORK(&dac33->work, dac33_work);
1289 }
1290 }
1291
3a7aaed7
IK		 1292 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1293 dac33->supplies[i].supply = dac33_supply_names[i];
1294
1295 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1296 dac33->supplies);
1297
1298 if (ret != 0) {
1299 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1300 goto err_get;
1301 }
1302
1303 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1304 dac33->supplies);
1305 if (ret != 0) {
1306 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1307 goto err_enable;
1308 }
1309
c8bf93f0
PU		 1310 ret = snd_soc_register_codec(codec);
1311 if (ret != 0) {
1312 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1313 goto error_codec;
1314 }
1315
1316 ret = snd_soc_register_dai(&dac33_dai);
1317 if (ret != 0) {
1318 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1319 snd_soc_unregister_codec(codec);
1320 goto error_codec;
1321 }
1322
1323 /* Shut down the codec for now */
1324 dac33_hard_power(codec, 0);
1325
1326 return ret;
1327
1328error_codec:
3a7aaed7
IK		 1329 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1330err_enable:
1331 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1332err_get:
c8bf93f0
PU		 1333 if (dac33->irq >= 0) {
1334 free_irq(dac33->irq, &dac33->codec);
1335 destroy_workqueue(dac33->dac33_wq);
1336 }
1337error_wq:
1338 if (dac33->power_gpio >= 0)
1339 gpio_free(dac33->power_gpio);
1340error_gpio:
1341 kfree(codec->reg_cache);
1342error_reg:
1343 tlv320dac33_codec = NULL;
1344 kfree(dac33);
1345
1346 return ret;
1347}
1348
735fe4cf 1349static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1350{
1351 struct tlv320dac33_priv *dac33;
1352
1353 dac33 = i2c_get_clientdata(client);
1354 dac33_hard_power(&dac33->codec, 0);
1355
1356 if (dac33->power_gpio >= 0)
1357 gpio_free(dac33->power_gpio);
1358 if (dac33->irq >= 0)
1359 free_irq(dac33->irq, &dac33->codec);
1360
3a7aaed7
IK		 1361 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1362
c8bf93f0
PU		 1363 destroy_workqueue(dac33->dac33_wq);
1364 snd_soc_unregister_dai(&dac33_dai);
1365 snd_soc_unregister_codec(&dac33->codec);
1366 kfree(dac33->codec.reg_cache);
1367 kfree(dac33);
1368 tlv320dac33_codec = NULL;
1369
1370 return 0;
1371}
1372
1373static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1374 {
1375 .name = "tlv320dac33",
1376 .driver_data = 0,
1377 },
1378 { },
1379};
1380
1381static struct i2c_driver tlv320dac33_i2c_driver = {
1382 .driver = {
1383 .name = "tlv320dac33",
1384 .owner = THIS_MODULE,
1385 },
1386 .probe = dac33_i2c_probe,
1387 .remove = __devexit_p(dac33_i2c_remove),
1388 .id_table = tlv320dac33_i2c_id,
1389};
1390
1391static int __init dac33_module_init(void)
1392{
1393 int r;
1394 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1395 if (r < 0) {
1396 printk(KERN_ERR "DAC33: driver registration failed\n");
1397 return r;
1398 }
1399 return 0;
1400}
1401module_init(dac33_module_init);
1402
1403static void __exit dac33_module_exit(void)
1404{
1405 i2c_del_driver(&tlv320dac33_i2c_driver);
1406}
1407module_exit(dac33_module_exit);
1408
1409
1410MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1411MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1412MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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