projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: tlv320dac33: Calculate the interface speed during bursts
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
76f47127
PU		 56#define BURST_BASEFREQ_HZ 49152000
57
c8bf93f0
PU		 58static struct snd_soc_codec *tlv320dac33_codec;
59
60enum dac33_state {
61 DAC33_IDLE = 0,
62 DAC33_PREFILL,
63 DAC33_PLAYBACK,
64 DAC33_FLUSH,
65};
66
7427b4b9
PU		 67enum dac33_fifo_modes {
68 DAC33_FIFO_BYPASS = 0,
69 DAC33_FIFO_MODE1,
28e05d98 70 DAC33_FIFO_MODE7,
7427b4b9
PU		 71 DAC33_FIFO_LAST_MODE,
72};
73
3a7aaed7
IK		 74#define DAC33_NUM_SUPPLIES 3
75static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
76 "AVDD",
77 "DVDD",
78 "IOVDD",
79};
80
c8bf93f0
PU		 81struct tlv320dac33_priv {
82 struct mutex mutex;
83 struct workqueue_struct *dac33_wq;
84 struct work_struct work;
85 struct snd_soc_codec codec;
3a7aaed7 86 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 87 int power_gpio;
88 int chip_power;
89 int irq;
90 unsigned int refclk;
91
92 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
93 unsigned int nsample_min; /* nsample should not be lower than
94 * this */
95 unsigned int nsample_max; /* nsample should not be higher than
96 * this */
7427b4b9 97 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 98 unsigned int nsample; /* burst read amount from host */
6aceabb4 99 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 100 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 101
eeb309a8
PU		 102 int keep_bclk; /* Keep the BCLK continuously running
103 * in FIFO modes */
c8bf93f0
PU		 104 enum dac33_state state;
105};
106
107static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1080x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1090x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1100x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1110x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1120x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1130x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1140x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1150x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1160x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1170x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1180x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1190x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1200x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1210x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1220x00, 0x00, /* 0x38 - 0x39 */
123/* Registers 0x3a - 0x3f are reserved */
124 0x00, 0x00, /* 0x3a - 0x3b */
1250x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
126
1270x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1280x00, 0x80, /* 0x44 - 0x45 */
129/* Registers 0x46 - 0x47 are reserved */
130 0x80, 0x80, /* 0x46 - 0x47 */
131
1320x80, 0x00, 0x00, /* 0x48 - 0x4a */
133/* Registers 0x4b - 0x7c are reserved */
134 0x00, /* 0x4b */
1350x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1360x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1370x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1380x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1390x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1400x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1410x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1420x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1430x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1440x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1450x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1460x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1470x00, /* 0x7c */
148
149 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
150};
151
152/* Register read and write */
153static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
154 unsigned reg)
155{
156 u8 *cache = codec->reg_cache;
157 if (reg >= DAC33_CACHEREGNUM)
158 return 0;
159
160 return cache[reg];
161}
162
163static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
164 u8 reg, u8 value)
165{
166 u8 *cache = codec->reg_cache;
167 if (reg >= DAC33_CACHEREGNUM)
168 return;
169
170 cache[reg] = value;
171}
172
173static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
174 u8 *value)
175{
b2c812e2 176 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 177 int val;
178
179 *value = reg & 0xff;
180
181 /* If powered off, return the cached value */
182 if (dac33->chip_power) {
183 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
184 if (val < 0) {
185 dev_err(codec->dev, "Read failed (%d)\n", val);
186 value[0] = dac33_read_reg_cache(codec, reg);
187 } else {
188 value[0] = val;
189 dac33_write_reg_cache(codec, reg, val);
190 }
191 } else {
192 value[0] = dac33_read_reg_cache(codec, reg);
193 }
194
195 return 0;
196}
197
198static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
199 unsigned int value)
200{
b2c812e2 201 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 202 u8 data[2];
203 int ret = 0;
204
205 /*
206 * data is
207 * D15..D8 dac33 register offset
208 * D7...D0 register data
209 */
210 data[0] = reg & 0xff;
211 data[1] = value & 0xff;
212
213 dac33_write_reg_cache(codec, data[0], data[1]);
214 if (dac33->chip_power) {
215 ret = codec->hw_write(codec->control_data, data, 2);
216 if (ret != 2)
217 dev_err(codec->dev, "Write failed (%d)\n", ret);
218 else
219 ret = 0;
220 }
221
222 return ret;
223}
224
225static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
b2c812e2 228 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 229 int ret;
230
231 mutex_lock(&dac33->mutex);
232 ret = dac33_write(codec, reg, value);
233 mutex_unlock(&dac33->mutex);
234
235 return ret;
236}
237
238#define DAC33_I2C_ADDR_AUTOINC 0x80
239static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
240 unsigned int value)
241{
b2c812e2 242 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 243 u8 data[3];
244 int ret = 0;
245
246 /*
247 * data is
248 * D23..D16 dac33 register offset
249 * D15..D8 register data MSB
250 * D7...D0 register data LSB
251 */
252 data[0] = reg & 0xff;
253 data[1] = (value >> 8) & 0xff;
254 data[2] = value & 0xff;
255
256 dac33_write_reg_cache(codec, data[0], data[1]);
257 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
258
259 if (dac33->chip_power) {
260 /* We need to set autoincrement mode for 16 bit writes */
261 data[0] |= DAC33_I2C_ADDR_AUTOINC;
262 ret = codec->hw_write(codec->control_data, data, 3);
263 if (ret != 3)
264 dev_err(codec->dev, "Write failed (%d)\n", ret);
265 else
266 ret = 0;
267 }
268
269 return ret;
270}
271
272static void dac33_restore_regs(struct snd_soc_codec *codec)
273{
b2c812e2 274 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 275 u8 *cache = codec->reg_cache;
276 u8 data[2];
277 int i, ret;
278
279 if (!dac33->chip_power)
280 return;
281
282 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
283 data[0] = i;
284 data[1] = cache[i];
285 /* Skip the read only registers */
286 if ((i >= DAC33_INT_OSC_STATUS &&
287 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
288 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
289 i == DAC33_DAC_STATUS_FLAGS ||
290 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
291 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
292 continue;
293 ret = codec->hw_write(codec->control_data, data, 2);
294 if (ret != 2)
295 dev_err(codec->dev, "Write failed (%d)\n", ret);
296 }
297 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
298 data[0] = i;
299 data[1] = cache[i];
300 ret = codec->hw_write(codec->control_data, data, 2);
301 if (ret != 2)
302 dev_err(codec->dev, "Write failed (%d)\n", ret);
303 }
304 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
305 data[0] = i;
306 data[1] = cache[i];
307 ret = codec->hw_write(codec->control_data, data, 2);
308 if (ret != 2)
309 dev_err(codec->dev, "Write failed (%d)\n", ret);
310 }
311}
312
313static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
314{
315 u8 reg;
316
317 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
318 if (power)
319 reg |= DAC33_PDNALLB;
320 else
c3746a07
PU		 321 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
322 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 323 dac33_write(codec, DAC33_PWR_CTRL, reg);
324}
325
3a7aaed7 326static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 327{
b2c812e2 328 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 329 int ret;
c8bf93f0
PU		 330
331 mutex_lock(&dac33->mutex);
332 if (power) {
3a7aaed7
IK		 333 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
334 dac33->supplies);
335 if (ret != 0) {
336 dev_err(codec->dev,
337 "Failed to enable supplies: %d\n", ret);
338 goto exit;
c8bf93f0 339 }
3a7aaed7
IK		 340
341 if (dac33->power_gpio >= 0)
342 gpio_set_value(dac33->power_gpio, 1);
343
344 dac33->chip_power = 1;
345
346 /* Restore registers */
347 dac33_restore_regs(codec);
348
c8bf93f0
PU		 349 dac33_soft_power(codec, 1);
350 } else {
351 dac33_soft_power(codec, 0);
3a7aaed7 352 if (dac33->power_gpio >= 0)
c8bf93f0 353 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 354
355 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
356 dac33->supplies);
357 if (ret != 0) {
358 dev_err(codec->dev,
359 "Failed to disable supplies: %d\n", ret);
360 goto exit;
c8bf93f0 361 }
3a7aaed7
IK		 362
363 dac33->chip_power = 0;
c8bf93f0 364 }
c8bf93f0 365
3a7aaed7
IK		 366exit:
367 mutex_unlock(&dac33->mutex);
368 return ret;
c8bf93f0
PU		 369}
370
371static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
372 struct snd_ctl_elem_value *ucontrol)
373{
374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 375 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 376
377 ucontrol->value.integer.value[0] = dac33->nsample;
378
379 return 0;
380}
381
382static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384{
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 386 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 387 int ret = 0;
388
389 if (dac33->nsample == ucontrol->value.integer.value[0])
390 return 0;
391
392 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
393 ucontrol->value.integer.value[0] > dac33->nsample_max)
394 ret = -EINVAL;
395 else
396 dac33->nsample = ucontrol->value.integer.value[0];
397
398 return ret;
399}
400
7427b4b9 401static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 402 struct snd_ctl_elem_value *ucontrol)
403{
404 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 405 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 406
7427b4b9 407 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 408
409 return 0;
410}
411
7427b4b9 412static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 413 struct snd_ctl_elem_value *ucontrol)
414{
415 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 416 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 417 int ret = 0;
418
7427b4b9 419 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 420 return 0;
421 /* Do not allow changes while stream is running*/
422 if (codec->active)
423 return -EPERM;
424
425 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 426 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 427 ret = -EINVAL;
428 else
7427b4b9 429 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 430
431 return ret;
432}
433
7427b4b9
PU		 434/* Codec operation modes */
435static const char *dac33_fifo_mode_texts[] = {
28e05d98 436 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 437};
438
439static const struct soc_enum dac33_fifo_mode_enum =
440 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
441 dac33_fifo_mode_texts);
442
c8bf93f0
PU		 443/*
444 * DACL/R digital volume control:
445 * from 0 dB to -63.5 in 0.5 dB steps
446 * Need to be inverted later on:
447 * 0x00 == 0 dB
448 * 0x7f == -63.5 dB
449 */
450static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
451
452static const struct snd_kcontrol_new dac33_snd_controls[] = {
453 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
454 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
455 0, 0x7f, 1, dac_digivol_tlv),
456 SOC_DOUBLE_R("DAC Digital Playback Switch",
457 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
458 SOC_DOUBLE_R("Line to Line Out Volume",
459 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
460};
461
462static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
463 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
464 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 465 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
466 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 467};
468
469/* Analog bypass */
470static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
471 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
472
473static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
474 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
475
476static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
477 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
478 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
479
480 SND_SOC_DAPM_INPUT("LINEL"),
481 SND_SOC_DAPM_INPUT("LINER"),
482
483 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
484 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
485
486 /* Analog bypass */
487 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
488 &dac33_dapm_abypassl_control),
489 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
490 &dac33_dapm_abypassr_control),
491
492 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
493 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
494 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
495 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
496};
497
498static const struct snd_soc_dapm_route audio_map[] = {
499 /* Analog bypass */
500 {"Analog Left Bypass", "Switch", "LINEL"},
501 {"Analog Right Bypass", "Switch", "LINER"},
502
503 {"Output Left Amp Power", NULL, "DACL"},
504 {"Output Right Amp Power", NULL, "DACR"},
505
506 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
507 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
508
509 /* output */
510 {"LEFT_LO", NULL, "Output Left Amp Power"},
511 {"RIGHT_LO", NULL, "Output Right Amp Power"},
512};
513
514static int dac33_add_widgets(struct snd_soc_codec *codec)
515{
516 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
517 ARRAY_SIZE(dac33_dapm_widgets));
518
519 /* set up audio path interconnects */
520 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 521
522 return 0;
523}
524
525static int dac33_set_bias_level(struct snd_soc_codec *codec,
526 enum snd_soc_bias_level level)
527{
3a7aaed7
IK		 528 int ret;
529
c8bf93f0
PU		 530 switch (level) {
531 case SND_SOC_BIAS_ON:
532 dac33_soft_power(codec, 1);
533 break;
534 case SND_SOC_BIAS_PREPARE:
535 break;
536 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 537 if (codec->bias_level == SND_SOC_BIAS_OFF) {
538 ret = dac33_hard_power(codec, 1);
539 if (ret != 0)
540 return ret;
541 }
542
c8bf93f0
PU		 543 dac33_soft_power(codec, 0);
544 break;
545 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 546 ret = dac33_hard_power(codec, 0);
547 if (ret != 0)
548 return ret;
549
c8bf93f0
PU		 550 break;
551 }
552 codec->bias_level = level;
553
554 return 0;
555}
556
d4f102d4
PU		 557static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
558{
559 struct snd_soc_codec *codec;
560
561 codec = &dac33->codec;
562
563 switch (dac33->fifo_mode) {
564 case DAC33_FIFO_MODE1:
565 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 566 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
d4f102d4
PU		 567 dac33_write16(codec, DAC33_PREFILL_MSB,
568 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 569 /* Enable Alarm Threshold IRQ with a delay */
570 udelay(SAMPLES_TO_US(dac33->burst_rate,
571 dac33->alarm_threshold));
572 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 573 break;
28e05d98
PU		 574 case DAC33_FIFO_MODE7:
575 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 576 DAC33_THRREG(MODE7_LTHR));
28e05d98 577 break;
d4f102d4
PU		 578 default:
579 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
580 dac33->fifo_mode);
581 break;
582 }
583}
584
585static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
586{
587 struct snd_soc_codec *codec;
588
589 codec = &dac33->codec;
590
591 switch (dac33->fifo_mode) {
592 case DAC33_FIFO_MODE1:
593 dac33_write16(codec, DAC33_NSAMPLE_MSB,
594 DAC33_THRREG(dac33->nsample));
595 break;
28e05d98
PU		 596 case DAC33_FIFO_MODE7:
597 /* At the moment we are not using interrupts in mode7 */
598 break;
d4f102d4
PU		 599 default:
600 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
601 dac33->fifo_mode);
602 break;
603 }
604}
605
c8bf93f0
PU		 606static void dac33_work(struct work_struct *work)
607{
608 struct snd_soc_codec *codec;
609 struct tlv320dac33_priv *dac33;
610 u8 reg;
611
612 dac33 = container_of(work, struct tlv320dac33_priv, work);
613 codec = &dac33->codec;
614
615 mutex_lock(&dac33->mutex);
616 switch (dac33->state) {
617 case DAC33_PREFILL:
618 dac33->state = DAC33_PLAYBACK;
d4f102d4 619 dac33_prefill_handler(dac33);
c8bf93f0
PU		 620 break;
621 case DAC33_PLAYBACK:
d4f102d4 622 dac33_playback_handler(dac33);
c8bf93f0
PU		 623 break;
624 case DAC33_IDLE:
625 break;
626 case DAC33_FLUSH:
627 dac33->state = DAC33_IDLE;
628 /* Mask all interrupts from dac33 */
629 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
630
631 /* flush fifo */
632 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
633 reg |= DAC33_FIFOFLUSH;
634 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
635 break;
636 }
637 mutex_unlock(&dac33->mutex);
638}
639
640static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
641{
642 struct snd_soc_codec *codec = dev;
b2c812e2 643 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 644
645 queue_work(dac33->dac33_wq, &dac33->work);
646
647 return IRQ_HANDLED;
648}
649
c8bf93f0
PU		 650static void dac33_oscwait(struct snd_soc_codec *codec)
651{
652 int timeout = 20;
653 u8 reg;
654
655 do {
656 msleep(1);
657 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
658 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
659 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
660 dev_err(codec->dev,
661 "internal oscillator calibration failed\n");
662}
663
664static int dac33_hw_params(struct snd_pcm_substream *substream,
665 struct snd_pcm_hw_params *params,
666 struct snd_soc_dai *dai)
667{
668 struct snd_soc_pcm_runtime *rtd = substream->private_data;
669 struct snd_soc_device *socdev = rtd->socdev;
670 struct snd_soc_codec *codec = socdev->card->codec;
671
672 /* Check parameters for validity */
673 switch (params_rate(params)) {
674 case 44100:
675 case 48000:
676 break;
677 default:
678 dev_err(codec->dev, "unsupported rate %d\n",
679 params_rate(params));
680 return -EINVAL;
681 }
682
683 switch (params_format(params)) {
684 case SNDRV_PCM_FORMAT_S16_LE:
685 break;
686 default:
687 dev_err(codec->dev, "unsupported format %d\n",
688 params_format(params));
689 return -EINVAL;
690 }
691
692 return 0;
693}
694
695#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 696 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 697#define CALC_RATIOSET(rate, refclk) ( \
698 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
699
700/*
701 * tlv320dac33 is strict on the sequence of the register writes, if the register
702 * writes happens in different order, than dac33 might end up in unknown state.
703 * Use the known, working sequence of register writes to initialize the dac33.
704 */
705static int dac33_prepare_chip(struct snd_pcm_substream *substream)
706{
707 struct snd_soc_pcm_runtime *rtd = substream->private_data;
708 struct snd_soc_device *socdev = rtd->socdev;
709 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 710 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 711 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 712 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 713
714 switch (substream->runtime->rate) {
715 case 44100:
716 case 48000:
717 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
718 ratioset = CALC_RATIOSET(substream->runtime->rate,
719 dac33->refclk);
720 break;
721 default:
722 dev_err(codec->dev, "unsupported rate %d\n",
723 substream->runtime->rate);
724 return -EINVAL;
725 }
726
727
728 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
729 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 730 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 731 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 732 fifoctrl_a &= ~DAC33_FIFOFLUSH;
733
c8bf93f0
PU		 734 fifoctrl_a &= ~DAC33_WIDTH;
735 switch (substream->runtime->format) {
736 case SNDRV_PCM_FORMAT_S16_LE:
737 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
738 fifoctrl_a |= DAC33_WIDTH;
739 break;
740 default:
741 dev_err(codec->dev, "unsupported format %d\n",
742 substream->runtime->format);
743 return -EINVAL;
744 }
745
746 mutex_lock(&dac33->mutex);
c3746a07 747 dac33_soft_power(codec, 0);
c8bf93f0
PU		 748 dac33_soft_power(codec, 1);
749
750 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
751 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
752
753 /* Write registers 0x08 and 0x09 (MSB, LSB) */
754 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
755
756 /* calib time: 128 is a nice number ;) */
757 dac33_write(codec, DAC33_CALIB_TIME, 128);
758
759 /* adjustment treshold & step */
760 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
761 DAC33_ADJSTEP(1));
762
763 /* div=4 / gain=1 / div */
764 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
765
766 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
767 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
768 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
769
770 dac33_oscwait(codec);
771
7427b4b9 772 if (dac33->fifo_mode) {
aec242dc 773 /* Generic for all FIFO modes */
c8bf93f0 774 /* 50-51 : ASRC Control registers */
fdb6b1e1 775 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 776 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
777
778 /* Write registers 0x34 and 0x35 (MSB, LSB) */
779 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
780
781 /* Set interrupts to high active */
782 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 783 } else {
aec242dc 784 /* FIFO bypass mode */
c8bf93f0
PU		 785 /* 50-51 : ASRC Control registers */
786 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
787 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
788 }
789
aec242dc
PU		 790 /* Interrupt behaviour configuration */
791 switch (dac33->fifo_mode) {
792 case DAC33_FIFO_MODE1:
793 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
794 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 795 break;
28e05d98
PU		 796 case DAC33_FIFO_MODE7:
797 /* Disable all interrupts */
798 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
799 break;
aec242dc
PU		 800 default:
801 /* in FIFO bypass mode, the interrupts are not used */
802 break;
803 }
804
805 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
806
807 switch (dac33->fifo_mode) {
808 case DAC33_FIFO_MODE1:
809 /*
810 * For mode1:
811 * Disable the FIFO bypass (Enable the use of FIFO)
812 * Select nSample mode
813 * BCLK is only running when data is needed by DAC33
814 */
c8bf93f0 815 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 816 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 817 if (dac33->keep_bclk)
818 aictrl_b |= DAC33_BCLKON;
819 else
820 aictrl_b &= ~DAC33_BCLKON;
aec242dc 821 break;
28e05d98
PU		 822 case DAC33_FIFO_MODE7:
823 /*
824 * For mode1:
825 * Disable the FIFO bypass (Enable the use of FIFO)
826 * Select Threshold mode
827 * BCLK is only running when data is needed by DAC33
828 */
829 fifoctrl_a &= ~DAC33_FBYPAS;
830 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 831 if (dac33->keep_bclk)
832 aictrl_b |= DAC33_BCLKON;
833 else
834 aictrl_b &= ~DAC33_BCLKON;
28e05d98 835 break;
aec242dc
PU		 836 default:
837 /*
838 * For FIFO bypass mode:
839 * Enable the FIFO bypass (Disable the FIFO use)
840 * Set the BCLK as continous
841 */
c8bf93f0 842 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 843 aictrl_b |= DAC33_BCLKON;
844 break;
845 }
c8bf93f0 846
aec242dc 847 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 848 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 849 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 850
6aceabb4
PU		 851 /*
852 * BCLK divide ratio
853 * 0: 1.5
854 * 1: 1
855 * 2: 2
856 * ...
857 * 254: 254
858 * 255: 255
859 */
6cd6cede 860 if (dac33->fifo_mode)
6aceabb4
PU		 861 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
862 dac33->burst_bclkdiv);
6cd6cede
PU		 863 else
864 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 865
6cd6cede
PU		 866 switch (dac33->fifo_mode) {
867 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 868 dac33_write16(codec, DAC33_ATHR_MSB,
869 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 870 break;
28e05d98
PU		 871 case DAC33_FIFO_MODE7:
872 /*
873 * Configure the threshold levels, and leave 10 sample space
874 * at the bottom, and also at the top of the FIFO
875 */
4260393e
PU		 876 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
877 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 878 break;
aec242dc 879 default:
aec242dc 880 break;
c8bf93f0
PU		 881 }
882
883 mutex_unlock(&dac33->mutex);
884
885 return 0;
886}
887
888static void dac33_calculate_times(struct snd_pcm_substream *substream)
889{
890 struct snd_soc_pcm_runtime *rtd = substream->private_data;
891 struct snd_soc_device *socdev = rtd->socdev;
892 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 893 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 894 unsigned int nsample_limit;
895
55abb59c
PU		 896 /* In bypass mode we don't need to calculate */
897 if (!dac33->fifo_mode)
898 return;
899
c8bf93f0
PU		 900 /* Number of samples (16bit, stereo) in one period */
901 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
902
903 /* Number of samples (16bit, stereo) in ALSA buffer */
904 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
905 /* Subtract one period from the total */
906 dac33->nsample_max -= dac33->nsample_min;
907
908 /* Number of samples for LATENCY_TIME_MS / 2 */
909 dac33->alarm_threshold = substream->runtime->rate /
910 (1000 / (LATENCY_TIME_MS / 2));
911
912 /* Find and fix up the lowest nsmaple limit */
913 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
914
915 if (dac33->nsample_min < nsample_limit)
916 dac33->nsample_min = nsample_limit;
917
918 if (dac33->nsample < dac33->nsample_min)
919 dac33->nsample = dac33->nsample_min;
920
921 /*
922 * Find and fix up the highest nsmaple limit
923 * In order to not overflow the DAC33 buffer substract the
924 * alarm_threshold value from the size of the DAC33 buffer
925 */
926 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
927
928 if (dac33->nsample_max > nsample_limit)
929 dac33->nsample_max = nsample_limit;
930
931 if (dac33->nsample > dac33->nsample_max)
932 dac33->nsample = dac33->nsample_max;
933}
934
935static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
936 struct snd_soc_dai *dai)
937{
938 dac33_calculate_times(substream);
939 dac33_prepare_chip(substream);
940
941 return 0;
942}
943
944static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
945 struct snd_soc_dai *dai)
946{
947 struct snd_soc_pcm_runtime *rtd = substream->private_data;
948 struct snd_soc_device *socdev = rtd->socdev;
949 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 950 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 951 int ret = 0;
952
953 switch (cmd) {
954 case SNDRV_PCM_TRIGGER_START:
955 case SNDRV_PCM_TRIGGER_RESUME:
956 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 957 if (dac33->fifo_mode) {
c8bf93f0
PU		 958 dac33->state = DAC33_PREFILL;
959 queue_work(dac33->dac33_wq, &dac33->work);
960 }
961 break;
962 case SNDRV_PCM_TRIGGER_STOP:
963 case SNDRV_PCM_TRIGGER_SUSPEND:
964 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 965 if (dac33->fifo_mode) {
c8bf93f0
PU		 966 dac33->state = DAC33_FLUSH;
967 queue_work(dac33->dac33_wq, &dac33->work);
968 }
969 break;
970 default:
971 ret = -EINVAL;
972 }
973
974 return ret;
975}
976
977static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
978 int clk_id, unsigned int freq, int dir)
979{
980 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 981 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 982 u8 ioc_reg, asrcb_reg;
983
984 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
985 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
986 switch (clk_id) {
987 case TLV320DAC33_MCLK:
988 ioc_reg |= DAC33_REFSEL;
989 asrcb_reg |= DAC33_SRCREFSEL;
990 break;
991 case TLV320DAC33_SLEEPCLK:
992 ioc_reg &= ~DAC33_REFSEL;
993 asrcb_reg &= ~DAC33_SRCREFSEL;
994 break;
995 default:
996 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
997 break;
998 }
999 dac33->refclk = freq;
1000
1001 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1002 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1003
1004 return 0;
1005}
1006
1007static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1008 unsigned int fmt)
1009{
1010 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1011 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1012 u8 aictrl_a, aictrl_b;
1013
1014 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1015 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1016 /* set master/slave audio interface */
1017 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1018 case SND_SOC_DAIFMT_CBM_CFM:
1019 /* Codec Master */
1020 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1021 break;
1022 case SND_SOC_DAIFMT_CBS_CFS:
1023 /* Codec Slave */
adcb8bc0
PU		 1024 if (dac33->fifo_mode) {
1025 dev_err(codec->dev, "FIFO mode requires master mode\n");
1026 return -EINVAL;
1027 } else
1028 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033
1034 aictrl_a &= ~DAC33_AFMT_MASK;
1035 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1036 case SND_SOC_DAIFMT_I2S:
1037 aictrl_a |= DAC33_AFMT_I2S;
1038 break;
1039 case SND_SOC_DAIFMT_DSP_A:
1040 aictrl_a |= DAC33_AFMT_DSP;
1041 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1042 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1043 break;
1044 case SND_SOC_DAIFMT_RIGHT_J:
1045 aictrl_a |= DAC33_AFMT_RIGHT_J;
1046 break;
1047 case SND_SOC_DAIFMT_LEFT_J:
1048 aictrl_a |= DAC33_AFMT_LEFT_J;
1049 break;
1050 default:
1051 dev_err(codec->dev, "Unsupported format (%u)\n",
1052 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1053 return -EINVAL;
1054 }
1055
1056 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1057 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1058
1059 return 0;
1060}
1061
1062static void dac33_init_chip(struct snd_soc_codec *codec)
1063{
1064 /* 44-46: DAC Control Registers */
1065 /* A : DAC sample rate Fsref/1.5 */
fdb6b1e1 1066 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
c8bf93f0
PU		 1067 /* B : DAC src=normal, not muted */
1068 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1069 DAC33_DACSRCL_LEFT);
1070 /* C : (defaults) */
1071 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1072
1073 /* 64-65 : L&R DAC power control
1074 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1075 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1076 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1077
1078 /* 73 : volume soft stepping control,
1079 clock source = internal osc (?) */
1080 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1081
1082 /* 66 : LOP/LOM Modes */
1083 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1084
1085 /* 68 : LOM inverted from LOP */
1086 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1087
1088 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1089}
1090
1091static int dac33_soc_probe(struct platform_device *pdev)
1092{
1093 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1094 struct snd_soc_codec *codec;
1095 struct tlv320dac33_priv *dac33;
1096 int ret = 0;
1097
1098 BUG_ON(!tlv320dac33_codec);
1099
1100 codec = tlv320dac33_codec;
1101 socdev->card->codec = codec;
b2c812e2 1102 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1103
1104 /* Power up the codec */
1105 dac33_hard_power(codec, 1);
1106 /* Set default configuration */
1107 dac33_init_chip(codec);
1108
1109 /* register pcms */
1110 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1111 if (ret < 0) {
1112 dev_err(codec->dev, "failed to create pcms\n");
1113 goto pcm_err;
1114 }
1115
1116 snd_soc_add_controls(codec, dac33_snd_controls,
1117 ARRAY_SIZE(dac33_snd_controls));
1118 /* Only add the nSample controls, if we have valid IRQ number */
1119 if (dac33->irq >= 0)
1120 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1121 ARRAY_SIZE(dac33_nsample_snd_controls));
1122
1123 dac33_add_widgets(codec);
1124
1125 /* power on device */
1126 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1127
3a7aaed7
IK		 1128 /* Bias level configuration has enabled regulator an extra time */
1129 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1130
c8bf93f0 1131 return 0;
fe3e78e0 1132
c8bf93f0
PU		 1133pcm_err:
1134 dac33_hard_power(codec, 0);
1135 return ret;
1136}
1137
1138static int dac33_soc_remove(struct platform_device *pdev)
1139{
1140 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1141 struct snd_soc_codec *codec = socdev->card->codec;
1142
1143 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1144
1145 snd_soc_free_pcms(socdev);
1146 snd_soc_dapm_free(socdev);
1147
1148 return 0;
1149}
1150
1151static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1152{
1153 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1154 struct snd_soc_codec *codec = socdev->card->codec;
1155
1156 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1157
1158 return 0;
1159}
1160
1161static int dac33_soc_resume(struct platform_device *pdev)
1162{
1163 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1164 struct snd_soc_codec *codec = socdev->card->codec;
1165
1166 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1167 dac33_set_bias_level(codec, codec->suspend_bias_level);
1168
1169 return 0;
1170}
1171
1172struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1173 .probe = dac33_soc_probe,
1174 .remove = dac33_soc_remove,
1175 .suspend = dac33_soc_suspend,
1176 .resume = dac33_soc_resume,
1177};
1178EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1179
1180#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1181 SNDRV_PCM_RATE_48000)
1182#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1183
1184static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1185 .hw_params = dac33_hw_params,
1186 .prepare = dac33_pcm_prepare,
1187 .trigger = dac33_pcm_trigger,
1188 .set_sysclk = dac33_set_dai_sysclk,
1189 .set_fmt = dac33_set_dai_fmt,
1190};
1191
1192struct snd_soc_dai dac33_dai = {
1193 .name = "tlv320dac33",
1194 .playback = {
1195 .stream_name = "Playback",
1196 .channels_min = 2,
1197 .channels_max = 2,
1198 .rates = DAC33_RATES,
1199 .formats = DAC33_FORMATS,},
1200 .ops = &dac33_dai_ops,
1201};
1202EXPORT_SYMBOL_GPL(dac33_dai);
1203
735fe4cf
MB		 1204static int __devinit dac33_i2c_probe(struct i2c_client *client,
1205 const struct i2c_device_id *id)
c8bf93f0
PU		 1206{
1207 struct tlv320dac33_platform_data *pdata;
1208 struct tlv320dac33_priv *dac33;
1209 struct snd_soc_codec *codec;
3a7aaed7 1210 int ret, i;
c8bf93f0
PU		 1211
1212 if (client->dev.platform_data == NULL) {
1213 dev_err(&client->dev, "Platform data not set\n");
1214 return -ENODEV;
1215 }
1216 pdata = client->dev.platform_data;
1217
1218 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1219 if (dac33 == NULL)
1220 return -ENOMEM;
1221
1222 codec = &dac33->codec;
b2c812e2 1223 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1224 codec->control_data = client;
1225
1226 mutex_init(&codec->mutex);
1227 mutex_init(&dac33->mutex);
1228 INIT_LIST_HEAD(&codec->dapm_widgets);
1229 INIT_LIST_HEAD(&codec->dapm_paths);
1230
1231 codec->name = "tlv320dac33";
1232 codec->owner = THIS_MODULE;
1233 codec->read = dac33_read_reg_cache;
1234 codec->write = dac33_write_locked;
1235 codec->hw_write = (hw_write_t) i2c_master_send;
1236 codec->bias_level = SND_SOC_BIAS_OFF;
1237 codec->set_bias_level = dac33_set_bias_level;
1238 codec->dai = &dac33_dai;
1239 codec->num_dai = 1;
1240 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1241 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1242 GFP_KERNEL);
1243 if (codec->reg_cache == NULL) {
1244 ret = -ENOMEM;
1245 goto error_reg;
1246 }
1247
1248 i2c_set_clientdata(client, dac33);
1249
1250 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1251 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1252 /* Pre calculate the burst rate */
1253 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1254 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1255 dac33->irq = client->irq;
1256 dac33->nsample = NSAMPLE_MAX;
55abb59c 1257 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1258 /* Disable FIFO use by default */
7427b4b9 1259 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1260
1261 tlv320dac33_codec = codec;
1262
1263 codec->dev = &client->dev;
1264 dac33_dai.dev = codec->dev;
1265
1266 /* Check if the reset GPIO number is valid and request it */
1267 if (dac33->power_gpio >= 0) {
1268 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1269 if (ret < 0) {
1270 dev_err(codec->dev,
1271 "Failed to request reset GPIO (%d)\n",
1272 dac33->power_gpio);
1273 snd_soc_unregister_dai(&dac33_dai);
1274 snd_soc_unregister_codec(codec);
1275 goto error_gpio;
1276 }
1277 gpio_direction_output(dac33->power_gpio, 0);
1278 } else {
1279 dac33->chip_power = 1;
1280 }
1281
1282 /* Check if the IRQ number is valid and request it */
1283 if (dac33->irq >= 0) {
1284 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1285 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1286 codec->name, codec);
1287 if (ret < 0) {
1288 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1289 dac33->irq, ret);
1290 dac33->irq = -1;
1291 }
1292 if (dac33->irq != -1) {
1293 /* Setup work queue */
74ea23aa
PU		 1294 dac33->dac33_wq =
1295 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1296 if (dac33->dac33_wq == NULL) {
1297 free_irq(dac33->irq, &dac33->codec);
1298 ret = -ENOMEM;
1299 goto error_wq;
1300 }
1301
1302 INIT_WORK(&dac33->work, dac33_work);
1303 }
1304 }
1305
3a7aaed7
IK		 1306 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1307 dac33->supplies[i].supply = dac33_supply_names[i];
1308
1309 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1310 dac33->supplies);
1311
1312 if (ret != 0) {
1313 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1314 goto err_get;
1315 }
1316
1317 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1318 dac33->supplies);
1319 if (ret != 0) {
1320 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1321 goto err_enable;
1322 }
1323
c8bf93f0
PU		 1324 ret = snd_soc_register_codec(codec);
1325 if (ret != 0) {
1326 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1327 goto error_codec;
1328 }
1329
1330 ret = snd_soc_register_dai(&dac33_dai);
1331 if (ret != 0) {
1332 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1333 snd_soc_unregister_codec(codec);
1334 goto error_codec;
1335 }
1336
1337 /* Shut down the codec for now */
1338 dac33_hard_power(codec, 0);
1339
1340 return ret;
1341
1342error_codec:
3a7aaed7
IK		 1343 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1344err_enable:
1345 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1346err_get:
c8bf93f0
PU		 1347 if (dac33->irq >= 0) {
1348 free_irq(dac33->irq, &dac33->codec);
1349 destroy_workqueue(dac33->dac33_wq);
1350 }
1351error_wq:
1352 if (dac33->power_gpio >= 0)
1353 gpio_free(dac33->power_gpio);
1354error_gpio:
1355 kfree(codec->reg_cache);
1356error_reg:
1357 tlv320dac33_codec = NULL;
1358 kfree(dac33);
1359
1360 return ret;
1361}
1362
735fe4cf 1363static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1364{
1365 struct tlv320dac33_priv *dac33;
1366
1367 dac33 = i2c_get_clientdata(client);
1368 dac33_hard_power(&dac33->codec, 0);
1369
1370 if (dac33->power_gpio >= 0)
1371 gpio_free(dac33->power_gpio);
1372 if (dac33->irq >= 0)
1373 free_irq(dac33->irq, &dac33->codec);
1374
3a7aaed7
IK		 1375 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1376
c8bf93f0
PU		 1377 destroy_workqueue(dac33->dac33_wq);
1378 snd_soc_unregister_dai(&dac33_dai);
1379 snd_soc_unregister_codec(&dac33->codec);
1380 kfree(dac33->codec.reg_cache);
1381 kfree(dac33);
1382 tlv320dac33_codec = NULL;
1383
1384 return 0;
1385}
1386
1387static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1388 {
1389 .name = "tlv320dac33",
1390 .driver_data = 0,
1391 },
1392 { },
1393};
1394
1395static struct i2c_driver tlv320dac33_i2c_driver = {
1396 .driver = {
1397 .name = "tlv320dac33",
1398 .owner = THIS_MODULE,
1399 },
1400 .probe = dac33_i2c_probe,
1401 .remove = __devexit_p(dac33_i2c_remove),
1402 .id_table = tlv320dac33_i2c_id,
1403};
1404
1405static int __init dac33_module_init(void)
1406{
1407 int r;
1408 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1409 if (r < 0) {
1410 printk(KERN_ERR "DAC33: driver registration failed\n");
1411 return r;
1412 }
1413 return 0;
1414}
1415module_init(dac33_module_init);
1416
1417static void __exit dac33_module_exit(void)
1418{
1419 i2c_del_driver(&tlv320dac33_i2c_driver);
1420}
1421module_exit(dac33_module_exit);
1422
1423
1424MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1425MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1426MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.108963 seconds and 5 git commands to generate.