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ASoC: tlv320dac33: Use dev_dbg in dac33_hard_power function
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
76f47127
PU		 56#define BURST_BASEFREQ_HZ 49152000
57
f57d2cfa
PU		 58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
ad05c03b
PU		 64static void dac33_calculate_times(struct snd_pcm_substream *substream);
65static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 66
c8bf93f0
PU		 67static struct snd_soc_codec *tlv320dac33_codec;
68
69enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74};
75
7427b4b9
PU		 76enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
28e05d98 79 DAC33_FIFO_MODE7,
7427b4b9
PU		 80 DAC33_FIFO_LAST_MODE,
81};
82
3a7aaed7
IK		 83#define DAC33_NUM_SUPPLIES 3
84static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88};
89
c8bf93f0
PU		 90struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec codec;
3a7aaed7 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 96 struct snd_pcm_substream *substream;
c8bf93f0
PU		 97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
104 * this */
105 unsigned int nsample_max; /* nsample should not be higher than
106 * this */
7427b4b9 107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 108 unsigned int nsample; /* burst read amount from host */
6aceabb4 109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 110 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 111
eeb309a8
PU		 112 int keep_bclk; /* Keep the BCLK continuously running
113 * in FIFO modes */
f57d2cfa
PU		 114 spinlock_t lock;
115 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
116 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
117
118 unsigned int mode1_us_burst; /* Time to burst read n number of
119 * samples */
120 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
121
c8bf93f0
PU		 122 enum dac33_state state;
123};
124
125static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1260x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1270x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1280x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1290x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1300x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1310x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1320x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1330x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1340x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1350x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1360x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1370x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1380x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1390x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1400x00, 0x00, /* 0x38 - 0x39 */
141/* Registers 0x3a - 0x3f are reserved */
142 0x00, 0x00, /* 0x3a - 0x3b */
1430x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
144
1450x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1460x00, 0x80, /* 0x44 - 0x45 */
147/* Registers 0x46 - 0x47 are reserved */
148 0x80, 0x80, /* 0x46 - 0x47 */
149
1500x80, 0x00, 0x00, /* 0x48 - 0x4a */
151/* Registers 0x4b - 0x7c are reserved */
152 0x00, /* 0x4b */
1530x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1540x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1550x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1560x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1570x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1580x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1590x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1600x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1610x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1620x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1630x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1640x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1650x00, /* 0x7c */
166
167 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
168};
169
170/* Register read and write */
171static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
172 unsigned reg)
173{
174 u8 *cache = codec->reg_cache;
175 if (reg >= DAC33_CACHEREGNUM)
176 return 0;
177
178 return cache[reg];
179}
180
181static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
182 u8 reg, u8 value)
183{
184 u8 *cache = codec->reg_cache;
185 if (reg >= DAC33_CACHEREGNUM)
186 return;
187
188 cache[reg] = value;
189}
190
191static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
192 u8 *value)
193{
b2c812e2 194 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 195 int val;
196
197 *value = reg & 0xff;
198
199 /* If powered off, return the cached value */
200 if (dac33->chip_power) {
201 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
202 if (val < 0) {
203 dev_err(codec->dev, "Read failed (%d)\n", val);
204 value[0] = dac33_read_reg_cache(codec, reg);
205 } else {
206 value[0] = val;
207 dac33_write_reg_cache(codec, reg, val);
208 }
209 } else {
210 value[0] = dac33_read_reg_cache(codec, reg);
211 }
212
213 return 0;
214}
215
216static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
217 unsigned int value)
218{
b2c812e2 219 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 220 u8 data[2];
221 int ret = 0;
222
223 /*
224 * data is
225 * D15..D8 dac33 register offset
226 * D7...D0 register data
227 */
228 data[0] = reg & 0xff;
229 data[1] = value & 0xff;
230
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 if (dac33->chip_power) {
233 ret = codec->hw_write(codec->control_data, data, 2);
234 if (ret != 2)
235 dev_err(codec->dev, "Write failed (%d)\n", ret);
236 else
237 ret = 0;
238 }
239
240 return ret;
241}
242
243static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
244 unsigned int value)
245{
b2c812e2 246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 247 int ret;
248
249 mutex_lock(&dac33->mutex);
250 ret = dac33_write(codec, reg, value);
251 mutex_unlock(&dac33->mutex);
252
253 return ret;
254}
255
256#define DAC33_I2C_ADDR_AUTOINC 0x80
257static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
258 unsigned int value)
259{
b2c812e2 260 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 261 u8 data[3];
262 int ret = 0;
263
264 /*
265 * data is
266 * D23..D16 dac33 register offset
267 * D15..D8 register data MSB
268 * D7...D0 register data LSB
269 */
270 data[0] = reg & 0xff;
271 data[1] = (value >> 8) & 0xff;
272 data[2] = value & 0xff;
273
274 dac33_write_reg_cache(codec, data[0], data[1]);
275 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
276
277 if (dac33->chip_power) {
278 /* We need to set autoincrement mode for 16 bit writes */
279 data[0] |= DAC33_I2C_ADDR_AUTOINC;
280 ret = codec->hw_write(codec->control_data, data, 3);
281 if (ret != 3)
282 dev_err(codec->dev, "Write failed (%d)\n", ret);
283 else
284 ret = 0;
285 }
286
287 return ret;
288}
289
ef909d67 290static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 291{
b2c812e2 292 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 293
ef909d67 294 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 295 return;
296
ef909d67
PU		 297 /* 44-46: DAC Control Registers */
298 /* A : DAC sample rate Fsref/1.5 */
299 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
300 /* B : DAC src=normal, not muted */
301 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
302 DAC33_DACSRCL_LEFT);
303 /* C : (defaults) */
304 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
305
ef909d67
PU		 306 /* 73 : volume soft stepping control,
307 clock source = internal osc (?) */
308 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
309
ef909d67
PU		 310 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
311
312 /* Restore only selected registers (gains mostly) */
313 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
314 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
315 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
316 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
317
318 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
319 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
320 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
321 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 322}
323
239fe55c
PU		 324static inline void dac33_read_id(struct snd_soc_codec *codec)
325{
326 u8 reg;
327
328 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
329 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
330 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
331}
332
c8bf93f0
PU		 333static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
334{
335 u8 reg;
336
337 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
338 if (power)
339 reg |= DAC33_PDNALLB;
340 else
c3746a07
PU		 341 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
342 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 343 dac33_write(codec, DAC33_PWR_CTRL, reg);
344}
345
3a7aaed7 346static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 347{
b2c812e2 348 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 349 int ret = 0;
c8bf93f0
PU		 350
351 mutex_lock(&dac33->mutex);
ad05c03b
PU		 352
353 /* Safety check */
354 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 355 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 356 power ? "ON" : "OFF");
357 goto exit;
358 }
359
c8bf93f0 360 if (power) {
3a7aaed7
IK		 361 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
362 dac33->supplies);
363 if (ret != 0) {
364 dev_err(codec->dev,
365 "Failed to enable supplies: %d\n", ret);
366 goto exit;
c8bf93f0 367 }
3a7aaed7
IK		 368
369 if (dac33->power_gpio >= 0)
370 gpio_set_value(dac33->power_gpio, 1);
371
372 dac33->chip_power = 1;
c8bf93f0
PU		 373 } else {
374 dac33_soft_power(codec, 0);
3a7aaed7 375 if (dac33->power_gpio >= 0)
c8bf93f0 376 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 377
378 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
379 dac33->supplies);
380 if (ret != 0) {
381 dev_err(codec->dev,
382 "Failed to disable supplies: %d\n", ret);
383 goto exit;
c8bf93f0 384 }
3a7aaed7
IK		 385
386 dac33->chip_power = 0;
c8bf93f0 387 }
c8bf93f0 388
3a7aaed7
IK		 389exit:
390 mutex_unlock(&dac33->mutex);
391 return ret;
c8bf93f0
PU		 392}
393
ad05c03b
PU		 394static int playback_event(struct snd_soc_dapm_widget *w,
395 struct snd_kcontrol *kcontrol, int event)
396{
397 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
398
399 switch (event) {
400 case SND_SOC_DAPM_PRE_PMU:
401 if (likely(dac33->substream)) {
402 dac33_calculate_times(dac33->substream);
403 dac33_prepare_chip(dac33->substream);
404 }
405 break;
406 }
407 return 0;
408}
409
c8bf93f0
PU		 410static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
411 struct snd_ctl_elem_value *ucontrol)
412{
413 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 414 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 415
416 ucontrol->value.integer.value[0] = dac33->nsample;
417
418 return 0;
419}
420
421static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 426 int ret = 0;
427
428 if (dac33->nsample == ucontrol->value.integer.value[0])
429 return 0;
430
431 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 432 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 433 ret = -EINVAL;
f57d2cfa 434 } else {
c8bf93f0 435 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 436 /* Re calculate the burst time */
437 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
438 dac33->nsample);
439 }
c8bf93f0
PU		 440
441 return ret;
442}
443
7427b4b9 444static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 445 struct snd_ctl_elem_value *ucontrol)
446{
447 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 448 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 449
7427b4b9 450 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 451
452 return 0;
453}
454
7427b4b9 455static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 456 struct snd_ctl_elem_value *ucontrol)
457{
458 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 459 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 460 int ret = 0;
461
7427b4b9 462 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 463 return 0;
464 /* Do not allow changes while stream is running*/
465 if (codec->active)
466 return -EPERM;
467
468 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 469 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 470 ret = -EINVAL;
471 else
7427b4b9 472 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 473
474 return ret;
475}
476
7427b4b9
PU		 477/* Codec operation modes */
478static const char *dac33_fifo_mode_texts[] = {
28e05d98 479 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 480};
481
482static const struct soc_enum dac33_fifo_mode_enum =
483 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
484 dac33_fifo_mode_texts);
485
c8bf93f0
PU		 486/*
487 * DACL/R digital volume control:
488 * from 0 dB to -63.5 in 0.5 dB steps
489 * Need to be inverted later on:
490 * 0x00 == 0 dB
491 * 0x7f == -63.5 dB
492 */
493static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
494
495static const struct snd_kcontrol_new dac33_snd_controls[] = {
496 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
497 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
498 0, 0x7f, 1, dac_digivol_tlv),
499 SOC_DOUBLE_R("DAC Digital Playback Switch",
500 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
501 SOC_DOUBLE_R("Line to Line Out Volume",
502 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
503};
504
505static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
506 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
507 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 508 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
509 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 510};
511
512/* Analog bypass */
513static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
514 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
515
516static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
517 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
518
519static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
520 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
521 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
522
523 SND_SOC_DAPM_INPUT("LINEL"),
524 SND_SOC_DAPM_INPUT("LINER"),
525
526 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
527 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
528
529 /* Analog bypass */
530 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
531 &dac33_dapm_abypassl_control),
532 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
533 &dac33_dapm_abypassr_control),
534
535 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
536 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
537 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
538 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b
PU		 539
540 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
c8bf93f0
PU		 541};
542
543static const struct snd_soc_dapm_route audio_map[] = {
544 /* Analog bypass */
545 {"Analog Left Bypass", "Switch", "LINEL"},
546 {"Analog Right Bypass", "Switch", "LINER"},
547
548 {"Output Left Amp Power", NULL, "DACL"},
549 {"Output Right Amp Power", NULL, "DACR"},
550
551 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
552 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
553
554 /* output */
555 {"LEFT_LO", NULL, "Output Left Amp Power"},
556 {"RIGHT_LO", NULL, "Output Right Amp Power"},
557};
558
559static int dac33_add_widgets(struct snd_soc_codec *codec)
560{
561 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
562 ARRAY_SIZE(dac33_dapm_widgets));
563
564 /* set up audio path interconnects */
565 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 566
567 return 0;
568}
569
570static int dac33_set_bias_level(struct snd_soc_codec *codec,
571 enum snd_soc_bias_level level)
572{
3a7aaed7
IK		 573 int ret;
574
c8bf93f0
PU		 575 switch (level) {
576 case SND_SOC_BIAS_ON:
577 dac33_soft_power(codec, 1);
578 break;
579 case SND_SOC_BIAS_PREPARE:
580 break;
581 case SND_SOC_BIAS_STANDBY:
3a7aaed7 582 if (codec->bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 583 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 584 ret = dac33_hard_power(codec, 1);
585 if (ret != 0)
586 return ret;
3a7aaed7 587
ad05c03b
PU		 588 dac33_init_chip(codec);
589 }
c8bf93f0
PU		 590 break;
591 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 592 ret = dac33_hard_power(codec, 0);
593 if (ret != 0)
594 return ret;
c8bf93f0
PU		 595 break;
596 }
597 codec->bias_level = level;
598
599 return 0;
600}
601
d4f102d4
PU		 602static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
603{
604 struct snd_soc_codec *codec;
605
606 codec = &dac33->codec;
607
608 switch (dac33->fifo_mode) {
609 case DAC33_FIFO_MODE1:
610 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 611 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
f57d2cfa
PU		 612
613 /* Take the timestamps */
614 spin_lock_irq(&dac33->lock);
615 dac33->t_stamp2 = ktime_to_us(ktime_get());
616 dac33->t_stamp1 = dac33->t_stamp2;
617 spin_unlock_irq(&dac33->lock);
618
d4f102d4
PU		 619 dac33_write16(codec, DAC33_PREFILL_MSB,
620 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 621 /* Enable Alarm Threshold IRQ with a delay */
622 udelay(SAMPLES_TO_US(dac33->burst_rate,
623 dac33->alarm_threshold));
624 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 625 break;
28e05d98 626 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 627 /* Take the timestamp */
628 spin_lock_irq(&dac33->lock);
629 dac33->t_stamp1 = ktime_to_us(ktime_get());
630 /* Move back the timestamp with drain time */
631 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
632 spin_unlock_irq(&dac33->lock);
633
28e05d98 634 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 635 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 636
637 /* Enable Upper Threshold IRQ */
638 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 639 break;
d4f102d4
PU		 640 default:
641 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
642 dac33->fifo_mode);
643 break;
644 }
645}
646
647static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
648{
649 struct snd_soc_codec *codec;
650
651 codec = &dac33->codec;
652
653 switch (dac33->fifo_mode) {
654 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 655 /* Take the timestamp */
656 spin_lock_irq(&dac33->lock);
657 dac33->t_stamp2 = ktime_to_us(ktime_get());
658 spin_unlock_irq(&dac33->lock);
659
d4f102d4
PU		 660 dac33_write16(codec, DAC33_NSAMPLE_MSB,
661 DAC33_THRREG(dac33->nsample));
662 break;
28e05d98
PU		 663 case DAC33_FIFO_MODE7:
664 /* At the moment we are not using interrupts in mode7 */
665 break;
d4f102d4
PU		 666 default:
667 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
668 dac33->fifo_mode);
669 break;
670 }
671}
672
c8bf93f0
PU		 673static void dac33_work(struct work_struct *work)
674{
675 struct snd_soc_codec *codec;
676 struct tlv320dac33_priv *dac33;
677 u8 reg;
678
679 dac33 = container_of(work, struct tlv320dac33_priv, work);
680 codec = &dac33->codec;
681
682 mutex_lock(&dac33->mutex);
683 switch (dac33->state) {
684 case DAC33_PREFILL:
685 dac33->state = DAC33_PLAYBACK;
d4f102d4 686 dac33_prefill_handler(dac33);
c8bf93f0
PU		 687 break;
688 case DAC33_PLAYBACK:
d4f102d4 689 dac33_playback_handler(dac33);
c8bf93f0
PU		 690 break;
691 case DAC33_IDLE:
692 break;
693 case DAC33_FLUSH:
694 dac33->state = DAC33_IDLE;
695 /* Mask all interrupts from dac33 */
696 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
697
698 /* flush fifo */
699 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
700 reg |= DAC33_FIFOFLUSH;
701 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
702 break;
703 }
704 mutex_unlock(&dac33->mutex);
705}
706
707static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
708{
709 struct snd_soc_codec *codec = dev;
b2c812e2 710 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 711
f57d2cfa
PU		 712 spin_lock(&dac33->lock);
713 dac33->t_stamp1 = ktime_to_us(ktime_get());
714 spin_unlock(&dac33->lock);
715
716 /* Do not schedule the workqueue in Mode7 */
717 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
718 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0
PU		 719
720 return IRQ_HANDLED;
721}
722
c8bf93f0
PU		 723static void dac33_oscwait(struct snd_soc_codec *codec)
724{
725 int timeout = 20;
726 u8 reg;
727
728 do {
729 msleep(1);
730 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
731 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
732 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
733 dev_err(codec->dev,
734 "internal oscillator calibration failed\n");
735}
736
0b61d2b9
PU		 737static int dac33_startup(struct snd_pcm_substream *substream,
738 struct snd_soc_dai *dai)
739{
740 struct snd_soc_pcm_runtime *rtd = substream->private_data;
741 struct snd_soc_device *socdev = rtd->socdev;
742 struct snd_soc_codec *codec = socdev->card->codec;
743 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
744
745 /* Stream started, save the substream pointer */
746 dac33->substream = substream;
747
748 return 0;
749}
750
751static void dac33_shutdown(struct snd_pcm_substream *substream,
752 struct snd_soc_dai *dai)
753{
754 struct snd_soc_pcm_runtime *rtd = substream->private_data;
755 struct snd_soc_device *socdev = rtd->socdev;
756 struct snd_soc_codec *codec = socdev->card->codec;
757 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
758
759 dac33->substream = NULL;
760}
761
c8bf93f0
PU		 762static int dac33_hw_params(struct snd_pcm_substream *substream,
763 struct snd_pcm_hw_params *params,
764 struct snd_soc_dai *dai)
765{
766 struct snd_soc_pcm_runtime *rtd = substream->private_data;
767 struct snd_soc_device *socdev = rtd->socdev;
768 struct snd_soc_codec *codec = socdev->card->codec;
769
770 /* Check parameters for validity */
771 switch (params_rate(params)) {
772 case 44100:
773 case 48000:
774 break;
775 default:
776 dev_err(codec->dev, "unsupported rate %d\n",
777 params_rate(params));
778 return -EINVAL;
779 }
780
781 switch (params_format(params)) {
782 case SNDRV_PCM_FORMAT_S16_LE:
783 break;
784 default:
785 dev_err(codec->dev, "unsupported format %d\n",
786 params_format(params));
787 return -EINVAL;
788 }
789
790 return 0;
791}
792
793#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 794 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 795#define CALC_RATIOSET(rate, refclk) ( \
796 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
797
798/*
799 * tlv320dac33 is strict on the sequence of the register writes, if the register
800 * writes happens in different order, than dac33 might end up in unknown state.
801 * Use the known, working sequence of register writes to initialize the dac33.
802 */
803static int dac33_prepare_chip(struct snd_pcm_substream *substream)
804{
805 struct snd_soc_pcm_runtime *rtd = substream->private_data;
806 struct snd_soc_device *socdev = rtd->socdev;
807 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 808 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 809 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 810 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 811
812 switch (substream->runtime->rate) {
813 case 44100:
814 case 48000:
815 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
816 ratioset = CALC_RATIOSET(substream->runtime->rate,
817 dac33->refclk);
818 break;
819 default:
820 dev_err(codec->dev, "unsupported rate %d\n",
821 substream->runtime->rate);
822 return -EINVAL;
823 }
824
825
826 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
827 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 828 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 829 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 830 fifoctrl_a &= ~DAC33_FIFOFLUSH;
831
c8bf93f0
PU		 832 fifoctrl_a &= ~DAC33_WIDTH;
833 switch (substream->runtime->format) {
834 case SNDRV_PCM_FORMAT_S16_LE:
835 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
836 fifoctrl_a |= DAC33_WIDTH;
837 break;
838 default:
839 dev_err(codec->dev, "unsupported format %d\n",
840 substream->runtime->format);
841 return -EINVAL;
842 }
843
844 mutex_lock(&dac33->mutex);
ad05c03b
PU		 845
846 if (!dac33->chip_power) {
847 /*
848 * Chip is not powered yet.
849 * Do the init in the dac33_set_bias_level later.
850 */
851 mutex_unlock(&dac33->mutex);
852 return 0;
853 }
854
c3746a07 855 dac33_soft_power(codec, 0);
c8bf93f0
PU		 856 dac33_soft_power(codec, 1);
857
858 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
859 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
860
861 /* Write registers 0x08 and 0x09 (MSB, LSB) */
862 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
863
864 /* calib time: 128 is a nice number ;) */
865 dac33_write(codec, DAC33_CALIB_TIME, 128);
866
867 /* adjustment treshold & step */
868 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
869 DAC33_ADJSTEP(1));
870
871 /* div=4 / gain=1 / div */
872 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
873
874 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
875 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
876 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
877
878 dac33_oscwait(codec);
879
7427b4b9 880 if (dac33->fifo_mode) {
aec242dc 881 /* Generic for all FIFO modes */
c8bf93f0 882 /* 50-51 : ASRC Control registers */
fdb6b1e1 883 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 884 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
885
886 /* Write registers 0x34 and 0x35 (MSB, LSB) */
887 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
888
889 /* Set interrupts to high active */
890 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 891 } else {
aec242dc 892 /* FIFO bypass mode */
c8bf93f0
PU		 893 /* 50-51 : ASRC Control registers */
894 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
895 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
896 }
897
aec242dc
PU		 898 /* Interrupt behaviour configuration */
899 switch (dac33->fifo_mode) {
900 case DAC33_FIFO_MODE1:
901 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
902 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 903 break;
28e05d98 904 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 905 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
906 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 907 break;
aec242dc
PU		 908 default:
909 /* in FIFO bypass mode, the interrupts are not used */
910 break;
911 }
912
913 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
914
915 switch (dac33->fifo_mode) {
916 case DAC33_FIFO_MODE1:
917 /*
918 * For mode1:
919 * Disable the FIFO bypass (Enable the use of FIFO)
920 * Select nSample mode
921 * BCLK is only running when data is needed by DAC33
922 */
c8bf93f0 923 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 924 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 925 if (dac33->keep_bclk)
926 aictrl_b |= DAC33_BCLKON;
927 else
928 aictrl_b &= ~DAC33_BCLKON;
aec242dc 929 break;
28e05d98
PU		 930 case DAC33_FIFO_MODE7:
931 /*
932 * For mode1:
933 * Disable the FIFO bypass (Enable the use of FIFO)
934 * Select Threshold mode
935 * BCLK is only running when data is needed by DAC33
936 */
937 fifoctrl_a &= ~DAC33_FBYPAS;
938 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 939 if (dac33->keep_bclk)
940 aictrl_b |= DAC33_BCLKON;
941 else
942 aictrl_b &= ~DAC33_BCLKON;
28e05d98 943 break;
aec242dc
PU		 944 default:
945 /*
946 * For FIFO bypass mode:
947 * Enable the FIFO bypass (Disable the FIFO use)
948 * Set the BCLK as continous
949 */
c8bf93f0 950 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 951 aictrl_b |= DAC33_BCLKON;
952 break;
953 }
c8bf93f0 954
aec242dc 955 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 956 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 957 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 958
6aceabb4
PU		 959 /*
960 * BCLK divide ratio
961 * 0: 1.5
962 * 1: 1
963 * 2: 2
964 * ...
965 * 254: 254
966 * 255: 255
967 */
6cd6cede 968 if (dac33->fifo_mode)
6aceabb4
PU		 969 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
970 dac33->burst_bclkdiv);
6cd6cede
PU		 971 else
972 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 973
6cd6cede
PU		 974 switch (dac33->fifo_mode) {
975 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 976 dac33_write16(codec, DAC33_ATHR_MSB,
977 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 978 break;
28e05d98
PU		 979 case DAC33_FIFO_MODE7:
980 /*
981 * Configure the threshold levels, and leave 10 sample space
982 * at the bottom, and also at the top of the FIFO
983 */
4260393e
PU		 984 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
985 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 986 break;
aec242dc 987 default:
aec242dc 988 break;
c8bf93f0
PU		 989 }
990
991 mutex_unlock(&dac33->mutex);
992
993 return 0;
994}
995
996static void dac33_calculate_times(struct snd_pcm_substream *substream)
997{
998 struct snd_soc_pcm_runtime *rtd = substream->private_data;
999 struct snd_soc_device *socdev = rtd->socdev;
1000 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1001 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1002 unsigned int nsample_limit;
1003
55abb59c
PU		 1004 /* In bypass mode we don't need to calculate */
1005 if (!dac33->fifo_mode)
1006 return;
1007
c8bf93f0
PU		 1008 /* Number of samples (16bit, stereo) in one period */
1009 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1010
1011 /* Number of samples (16bit, stereo) in ALSA buffer */
1012 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1013 /* Subtract one period from the total */
1014 dac33->nsample_max -= dac33->nsample_min;
1015
1016 /* Number of samples for LATENCY_TIME_MS / 2 */
1017 dac33->alarm_threshold = substream->runtime->rate /
1018 (1000 / (LATENCY_TIME_MS / 2));
1019
1020 /* Find and fix up the lowest nsmaple limit */
1021 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1022
1023 if (dac33->nsample_min < nsample_limit)
1024 dac33->nsample_min = nsample_limit;
1025
1026 if (dac33->nsample < dac33->nsample_min)
1027 dac33->nsample = dac33->nsample_min;
1028
1029 /*
1030 * Find and fix up the highest nsmaple limit
1031 * In order to not overflow the DAC33 buffer substract the
1032 * alarm_threshold value from the size of the DAC33 buffer
1033 */
1034 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1035
1036 if (dac33->nsample_max > nsample_limit)
1037 dac33->nsample_max = nsample_limit;
1038
1039 if (dac33->nsample > dac33->nsample_max)
1040 dac33->nsample = dac33->nsample_max;
f57d2cfa
PU		 1041
1042 switch (dac33->fifo_mode) {
1043 case DAC33_FIFO_MODE1:
1044 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1045 dac33->nsample);
1046 dac33->t_stamp1 = 0;
1047 dac33->t_stamp2 = 0;
1048 break;
1049 case DAC33_FIFO_MODE7:
1050 dac33->mode7_us_to_lthr =
1051 SAMPLES_TO_US(substream->runtime->rate,
1052 MODE7_UTHR - MODE7_LTHR + 1);
1053 dac33->t_stamp1 = 0;
1054 break;
1055 default:
1056 break;
1057 }
1058
c8bf93f0
PU		 1059}
1060
c8bf93f0
PU		 1061static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1062 struct snd_soc_dai *dai)
1063{
1064 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1065 struct snd_soc_device *socdev = rtd->socdev;
1066 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1067 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1068 int ret = 0;
1069
1070 switch (cmd) {
1071 case SNDRV_PCM_TRIGGER_START:
1072 case SNDRV_PCM_TRIGGER_RESUME:
1073 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1074 if (dac33->fifo_mode) {
c8bf93f0
PU		 1075 dac33->state = DAC33_PREFILL;
1076 queue_work(dac33->dac33_wq, &dac33->work);
1077 }
1078 break;
1079 case SNDRV_PCM_TRIGGER_STOP:
1080 case SNDRV_PCM_TRIGGER_SUSPEND:
1081 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1082 if (dac33->fifo_mode) {
c8bf93f0
PU		 1083 dac33->state = DAC33_FLUSH;
1084 queue_work(dac33->dac33_wq, &dac33->work);
1085 }
1086 break;
1087 default:
1088 ret = -EINVAL;
1089 }
1090
1091 return ret;
1092}
1093
f57d2cfa
PU		 1094static snd_pcm_sframes_t dac33_dai_delay(
1095 struct snd_pcm_substream *substream,
1096 struct snd_soc_dai *dai)
1097{
1098 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1099 struct snd_soc_device *socdev = rtd->socdev;
1100 struct snd_soc_codec *codec = socdev->card->codec;
1101 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1102 unsigned long long t0, t1, t_now;
1103 unsigned int time_delta;
1104 int samples_out, samples_in, samples;
1105 snd_pcm_sframes_t delay = 0;
1106
1107 switch (dac33->fifo_mode) {
1108 case DAC33_FIFO_BYPASS:
1109 break;
1110 case DAC33_FIFO_MODE1:
1111 spin_lock(&dac33->lock);
1112 t0 = dac33->t_stamp1;
1113 t1 = dac33->t_stamp2;
1114 spin_unlock(&dac33->lock);
1115 t_now = ktime_to_us(ktime_get());
1116
1117 /* We have not started to fill the FIFO yet, delay is 0 */
1118 if (!t1)
1119 goto out;
1120
1121 if (t0 > t1) {
1122 /*
1123 * Phase 1:
1124 * After Alarm threshold, and before nSample write
1125 */
1126 time_delta = t_now - t0;
1127 samples_out = time_delta ? US_TO_SAMPLES(
1128 substream->runtime->rate,
1129 time_delta) : 0;
1130
1131 if (likely(dac33->alarm_threshold > samples_out))
1132 delay = dac33->alarm_threshold - samples_out;
1133 else
1134 delay = 0;
1135 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1136 /*
1137 * Phase 2:
1138 * After nSample write (during burst operation)
1139 */
1140 time_delta = t_now - t0;
1141 samples_out = time_delta ? US_TO_SAMPLES(
1142 substream->runtime->rate,
1143 time_delta) : 0;
1144
1145 time_delta = t_now - t1;
1146 samples_in = time_delta ? US_TO_SAMPLES(
1147 dac33->burst_rate,
1148 time_delta) : 0;
1149
1150 samples = dac33->alarm_threshold;
1151 samples += (samples_in - samples_out);
1152
1153 if (likely(samples > 0))
1154 delay = samples;
1155 else
1156 delay = 0;
1157 } else {
1158 /*
1159 * Phase 3:
1160 * After burst operation, before next alarm threshold
1161 */
1162 time_delta = t_now - t0;
1163 samples_out = time_delta ? US_TO_SAMPLES(
1164 substream->runtime->rate,
1165 time_delta) : 0;
1166
1167 samples_in = dac33->nsample;
1168 samples = dac33->alarm_threshold;
1169 samples += (samples_in - samples_out);
1170
1171 if (likely(samples > 0))
1172 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1173 DAC33_BUFFER_SIZE_SAMPLES : samples;
1174 else
1175 delay = 0;
1176 }
1177 break;
1178 case DAC33_FIFO_MODE7:
1179 spin_lock(&dac33->lock);
1180 t0 = dac33->t_stamp1;
1181 spin_unlock(&dac33->lock);
1182 t_now = ktime_to_us(ktime_get());
1183
1184 /* We have not started to fill the FIFO yet, delay is 0 */
1185 if (!t0)
1186 goto out;
1187
1188 if (t_now <= t0) {
1189 /*
1190 * Either the timestamps are messed or equal. Report
1191 * maximum delay
1192 */
1193 delay = MODE7_UTHR;
1194 goto out;
1195 }
1196
1197 time_delta = t_now - t0;
1198 if (time_delta <= dac33->mode7_us_to_lthr) {
1199 /*
1200 * Phase 1:
1201 * After burst (draining phase)
1202 */
1203 samples_out = US_TO_SAMPLES(
1204 substream->runtime->rate,
1205 time_delta);
1206
1207 if (likely(MODE7_UTHR > samples_out))
1208 delay = MODE7_UTHR - samples_out;
1209 else
1210 delay = 0;
1211 } else {
1212 /*
1213 * Phase 2:
1214 * During burst operation
1215 */
1216 time_delta = time_delta - dac33->mode7_us_to_lthr;
1217
1218 samples_out = US_TO_SAMPLES(
1219 substream->runtime->rate,
1220 time_delta);
1221 samples_in = US_TO_SAMPLES(
1222 dac33->burst_rate,
1223 time_delta);
1224 delay = MODE7_LTHR + samples_in - samples_out;
1225
1226 if (unlikely(delay > MODE7_UTHR))
1227 delay = MODE7_UTHR;
1228 }
1229 break;
1230 default:
1231 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1232 dac33->fifo_mode);
1233 break;
1234 }
1235out:
1236 return delay;
1237}
1238
c8bf93f0
PU		 1239static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1240 int clk_id, unsigned int freq, int dir)
1241{
1242 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1243 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1244 u8 ioc_reg, asrcb_reg;
1245
1246 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1247 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1248 switch (clk_id) {
1249 case TLV320DAC33_MCLK:
1250 ioc_reg |= DAC33_REFSEL;
1251 asrcb_reg |= DAC33_SRCREFSEL;
1252 break;
1253 case TLV320DAC33_SLEEPCLK:
1254 ioc_reg &= ~DAC33_REFSEL;
1255 asrcb_reg &= ~DAC33_SRCREFSEL;
1256 break;
1257 default:
1258 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1259 break;
1260 }
1261 dac33->refclk = freq;
1262
1263 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1264 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1265
1266 return 0;
1267}
1268
1269static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1270 unsigned int fmt)
1271{
1272 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1273 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1274 u8 aictrl_a, aictrl_b;
1275
1276 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1277 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1278 /* set master/slave audio interface */
1279 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1280 case SND_SOC_DAIFMT_CBM_CFM:
1281 /* Codec Master */
1282 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1283 break;
1284 case SND_SOC_DAIFMT_CBS_CFS:
1285 /* Codec Slave */
adcb8bc0
PU		 1286 if (dac33->fifo_mode) {
1287 dev_err(codec->dev, "FIFO mode requires master mode\n");
1288 return -EINVAL;
1289 } else
1290 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1291 break;
1292 default:
1293 return -EINVAL;
1294 }
1295
1296 aictrl_a &= ~DAC33_AFMT_MASK;
1297 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1298 case SND_SOC_DAIFMT_I2S:
1299 aictrl_a |= DAC33_AFMT_I2S;
1300 break;
1301 case SND_SOC_DAIFMT_DSP_A:
1302 aictrl_a |= DAC33_AFMT_DSP;
1303 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1304 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1305 break;
1306 case SND_SOC_DAIFMT_RIGHT_J:
1307 aictrl_a |= DAC33_AFMT_RIGHT_J;
1308 break;
1309 case SND_SOC_DAIFMT_LEFT_J:
1310 aictrl_a |= DAC33_AFMT_LEFT_J;
1311 break;
1312 default:
1313 dev_err(codec->dev, "Unsupported format (%u)\n",
1314 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1315 return -EINVAL;
1316 }
1317
1318 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1319 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1320
1321 return 0;
1322}
1323
c8bf93f0
PU		 1324static int dac33_soc_probe(struct platform_device *pdev)
1325{
1326 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1327 struct snd_soc_codec *codec;
1328 struct tlv320dac33_priv *dac33;
1329 int ret = 0;
1330
1331 BUG_ON(!tlv320dac33_codec);
1332
1333 codec = tlv320dac33_codec;
1334 socdev->card->codec = codec;
b2c812e2 1335 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 1336
c8bf93f0
PU		 1337 /* register pcms */
1338 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1339 if (ret < 0) {
1340 dev_err(codec->dev, "failed to create pcms\n");
1341 goto pcm_err;
1342 }
1343
1344 snd_soc_add_controls(codec, dac33_snd_controls,
1345 ARRAY_SIZE(dac33_snd_controls));
1346 /* Only add the nSample controls, if we have valid IRQ number */
1347 if (dac33->irq >= 0)
1348 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1349 ARRAY_SIZE(dac33_nsample_snd_controls));
1350
1351 dac33_add_widgets(codec);
1352
c8bf93f0 1353 return 0;
fe3e78e0 1354
c8bf93f0
PU		 1355pcm_err:
1356 dac33_hard_power(codec, 0);
1357 return ret;
1358}
1359
1360static int dac33_soc_remove(struct platform_device *pdev)
1361{
1362 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1363 struct snd_soc_codec *codec = socdev->card->codec;
1364
1365 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1366
1367 snd_soc_free_pcms(socdev);
1368 snd_soc_dapm_free(socdev);
1369
1370 return 0;
1371}
1372
1373static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1374{
1375 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1376 struct snd_soc_codec *codec = socdev->card->codec;
1377
1378 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1379
1380 return 0;
1381}
1382
1383static int dac33_soc_resume(struct platform_device *pdev)
1384{
1385 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1386 struct snd_soc_codec *codec = socdev->card->codec;
1387
1388 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1389
1390 return 0;
1391}
1392
1393struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1394 .probe = dac33_soc_probe,
1395 .remove = dac33_soc_remove,
1396 .suspend = dac33_soc_suspend,
1397 .resume = dac33_soc_resume,
1398};
1399EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1400
1401#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1402 SNDRV_PCM_RATE_48000)
1403#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1404
1405static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9
PU		 1406 .startup = dac33_startup,
1407 .shutdown = dac33_shutdown,
c8bf93f0 1408 .hw_params = dac33_hw_params,
c8bf93f0 1409 .trigger = dac33_pcm_trigger,
f57d2cfa 1410 .delay = dac33_dai_delay,
c8bf93f0
PU		 1411 .set_sysclk = dac33_set_dai_sysclk,
1412 .set_fmt = dac33_set_dai_fmt,
1413};
1414
1415struct snd_soc_dai dac33_dai = {
1416 .name = "tlv320dac33",
1417 .playback = {
1418 .stream_name = "Playback",
1419 .channels_min = 2,
1420 .channels_max = 2,
1421 .rates = DAC33_RATES,
1422 .formats = DAC33_FORMATS,},
1423 .ops = &dac33_dai_ops,
1424};
1425EXPORT_SYMBOL_GPL(dac33_dai);
1426
735fe4cf
MB		 1427static int __devinit dac33_i2c_probe(struct i2c_client *client,
1428 const struct i2c_device_id *id)
c8bf93f0
PU		 1429{
1430 struct tlv320dac33_platform_data *pdata;
1431 struct tlv320dac33_priv *dac33;
1432 struct snd_soc_codec *codec;
3a7aaed7 1433 int ret, i;
c8bf93f0
PU		 1434
1435 if (client->dev.platform_data == NULL) {
1436 dev_err(&client->dev, "Platform data not set\n");
1437 return -ENODEV;
1438 }
1439 pdata = client->dev.platform_data;
1440
1441 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1442 if (dac33 == NULL)
1443 return -ENOMEM;
1444
1445 codec = &dac33->codec;
b2c812e2 1446 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1447 codec->control_data = client;
1448
1449 mutex_init(&codec->mutex);
1450 mutex_init(&dac33->mutex);
f57d2cfa 1451 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1452 INIT_LIST_HEAD(&codec->dapm_widgets);
1453 INIT_LIST_HEAD(&codec->dapm_paths);
1454
1455 codec->name = "tlv320dac33";
1456 codec->owner = THIS_MODULE;
1457 codec->read = dac33_read_reg_cache;
1458 codec->write = dac33_write_locked;
1459 codec->hw_write = (hw_write_t) i2c_master_send;
1460 codec->bias_level = SND_SOC_BIAS_OFF;
1461 codec->set_bias_level = dac33_set_bias_level;
ad05c03b 1462 codec->idle_bias_off = 1;
c8bf93f0
PU		 1463 codec->dai = &dac33_dai;
1464 codec->num_dai = 1;
1465 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1466 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1467 GFP_KERNEL);
1468 if (codec->reg_cache == NULL) {
1469 ret = -ENOMEM;
1470 goto error_reg;
1471 }
1472
1473 i2c_set_clientdata(client, dac33);
1474
1475 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1476 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1477 /* Pre calculate the burst rate */
1478 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1479 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1480 dac33->irq = client->irq;
1481 dac33->nsample = NSAMPLE_MAX;
55abb59c 1482 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1483 /* Disable FIFO use by default */
7427b4b9 1484 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1485
1486 tlv320dac33_codec = codec;
1487
1488 codec->dev = &client->dev;
1489 dac33_dai.dev = codec->dev;
1490
1491 /* Check if the reset GPIO number is valid and request it */
1492 if (dac33->power_gpio >= 0) {
1493 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1494 if (ret < 0) {
1495 dev_err(codec->dev,
1496 "Failed to request reset GPIO (%d)\n",
1497 dac33->power_gpio);
1498 snd_soc_unregister_dai(&dac33_dai);
1499 snd_soc_unregister_codec(codec);
1500 goto error_gpio;
1501 }
1502 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1503 }
1504
1505 /* Check if the IRQ number is valid and request it */
1506 if (dac33->irq >= 0) {
1507 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1508 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1509 codec->name, codec);
1510 if (ret < 0) {
1511 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1512 dac33->irq, ret);
1513 dac33->irq = -1;
1514 }
1515 if (dac33->irq != -1) {
1516 /* Setup work queue */
74ea23aa
PU		 1517 dac33->dac33_wq =
1518 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1519 if (dac33->dac33_wq == NULL) {
1520 free_irq(dac33->irq, &dac33->codec);
1521 ret = -ENOMEM;
1522 goto error_wq;
1523 }
1524
1525 INIT_WORK(&dac33->work, dac33_work);
1526 }
1527 }
1528
3a7aaed7
IK		 1529 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1530 dac33->supplies[i].supply = dac33_supply_names[i];
1531
1532 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1533 dac33->supplies);
1534
1535 if (ret != 0) {
1536 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1537 goto err_get;
1538 }
1539
239fe55c
PU		 1540 /* Read the tlv320dac33 ID registers */
1541 ret = dac33_hard_power(codec, 1);
3a7aaed7 1542 if (ret != 0) {
239fe55c
PU		 1543 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1544 goto error_codec;
3a7aaed7 1545 }
239fe55c
PU		 1546 dac33_read_id(codec);
1547 dac33_hard_power(codec, 0);
3a7aaed7 1548
c8bf93f0
PU		 1549 ret = snd_soc_register_codec(codec);
1550 if (ret != 0) {
1551 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1552 goto error_codec;
1553 }
1554
1555 ret = snd_soc_register_dai(&dac33_dai);
1556 if (ret != 0) {
1557 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1558 snd_soc_unregister_codec(codec);
1559 goto error_codec;
1560 }
1561
c8bf93f0
PU		 1562 return ret;
1563
1564error_codec:
3a7aaed7
IK		 1565 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1566err_get:
c8bf93f0
PU		 1567 if (dac33->irq >= 0) {
1568 free_irq(dac33->irq, &dac33->codec);
1569 destroy_workqueue(dac33->dac33_wq);
1570 }
1571error_wq:
1572 if (dac33->power_gpio >= 0)
1573 gpio_free(dac33->power_gpio);
1574error_gpio:
1575 kfree(codec->reg_cache);
1576error_reg:
1577 tlv320dac33_codec = NULL;
1578 kfree(dac33);
1579
1580 return ret;
1581}
1582
735fe4cf 1583static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1584{
1585 struct tlv320dac33_priv *dac33;
1586
1587 dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1588
1589 if (unlikely(dac33->chip_power))
1590 dac33_hard_power(&dac33->codec, 0);
c8bf93f0
PU		 1591
1592 if (dac33->power_gpio >= 0)
1593 gpio_free(dac33->power_gpio);
1594 if (dac33->irq >= 0)
1595 free_irq(dac33->irq, &dac33->codec);
1596
3a7aaed7
IK		 1597 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1598
c8bf93f0
PU		 1599 destroy_workqueue(dac33->dac33_wq);
1600 snd_soc_unregister_dai(&dac33_dai);
1601 snd_soc_unregister_codec(&dac33->codec);
1602 kfree(dac33->codec.reg_cache);
1603 kfree(dac33);
1604 tlv320dac33_codec = NULL;
1605
1606 return 0;
1607}
1608
1609static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1610 {
1611 .name = "tlv320dac33",
1612 .driver_data = 0,
1613 },
1614 { },
1615};
1616
1617static struct i2c_driver tlv320dac33_i2c_driver = {
1618 .driver = {
1619 .name = "tlv320dac33",
1620 .owner = THIS_MODULE,
1621 },
1622 .probe = dac33_i2c_probe,
1623 .remove = __devexit_p(dac33_i2c_remove),
1624 .id_table = tlv320dac33_i2c_id,
1625};
1626
1627static int __init dac33_module_init(void)
1628{
1629 int r;
1630 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1631 if (r < 0) {
1632 printk(KERN_ERR "DAC33: driver registration failed\n");
1633 return r;
1634 }
1635 return 0;
1636}
1637module_init(dac33_module_init);
1638
1639static void __exit dac33_module_exit(void)
1640{
1641 i2c_del_driver(&tlv320dac33_i2c_driver);
1642}
1643module_exit(dac33_module_exit);
1644
1645
1646MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1647MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1648MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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