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ASoC: soc-cache: cleanup training whitespace and coding style
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
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c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
53static struct snd_soc_codec *tlv320dac33_codec;
54
55enum dac33_state {
56 DAC33_IDLE = 0,
57 DAC33_PREFILL,
58 DAC33_PLAYBACK,
59 DAC33_FLUSH,
60};
61
3a7aaed7
IK		 62#define DAC33_NUM_SUPPLIES 3
63static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
64 "AVDD",
65 "DVDD",
66 "IOVDD",
67};
68
c8bf93f0
PU		 69struct tlv320dac33_priv {
70 struct mutex mutex;
71 struct workqueue_struct *dac33_wq;
72 struct work_struct work;
73 struct snd_soc_codec codec;
3a7aaed7 74 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 75 int power_gpio;
76 int chip_power;
77 int irq;
78 unsigned int refclk;
79
80 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
81 unsigned int nsample_min; /* nsample should not be lower than
82 * this */
83 unsigned int nsample_max; /* nsample should not be higher than
84 * this */
85 unsigned int nsample_switch; /* Use FIFO or bypass FIFO switch */
86 unsigned int nsample; /* burst read amount from host */
87
88 enum dac33_state state;
89};
90
91static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
920x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
930x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
940x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
950x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
960x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
970x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
980x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
990x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1000x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1010x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1020x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1030x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1040x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1050x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1060x00, 0x00, /* 0x38 - 0x39 */
107/* Registers 0x3a - 0x3f are reserved */
108 0x00, 0x00, /* 0x3a - 0x3b */
1090x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
110
1110x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1120x00, 0x80, /* 0x44 - 0x45 */
113/* Registers 0x46 - 0x47 are reserved */
114 0x80, 0x80, /* 0x46 - 0x47 */
115
1160x80, 0x00, 0x00, /* 0x48 - 0x4a */
117/* Registers 0x4b - 0x7c are reserved */
118 0x00, /* 0x4b */
1190x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1200x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1210x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1220x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1230x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1240x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1250x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1260x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1270x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1280x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1290x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1300x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1310x00, /* 0x7c */
132
133 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
134};
135
136/* Register read and write */
137static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
138 unsigned reg)
139{
140 u8 *cache = codec->reg_cache;
141 if (reg >= DAC33_CACHEREGNUM)
142 return 0;
143
144 return cache[reg];
145}
146
147static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
148 u8 reg, u8 value)
149{
150 u8 *cache = codec->reg_cache;
151 if (reg >= DAC33_CACHEREGNUM)
152 return;
153
154 cache[reg] = value;
155}
156
157static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
158 u8 *value)
159{
160 struct tlv320dac33_priv *dac33 = codec->private_data;
161 int val;
162
163 *value = reg & 0xff;
164
165 /* If powered off, return the cached value */
166 if (dac33->chip_power) {
167 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
168 if (val < 0) {
169 dev_err(codec->dev, "Read failed (%d)\n", val);
170 value[0] = dac33_read_reg_cache(codec, reg);
171 } else {
172 value[0] = val;
173 dac33_write_reg_cache(codec, reg, val);
174 }
175 } else {
176 value[0] = dac33_read_reg_cache(codec, reg);
177 }
178
179 return 0;
180}
181
182static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
183 unsigned int value)
184{
185 struct tlv320dac33_priv *dac33 = codec->private_data;
186 u8 data[2];
187 int ret = 0;
188
189 /*
190 * data is
191 * D15..D8 dac33 register offset
192 * D7...D0 register data
193 */
194 data[0] = reg & 0xff;
195 data[1] = value & 0xff;
196
197 dac33_write_reg_cache(codec, data[0], data[1]);
198 if (dac33->chip_power) {
199 ret = codec->hw_write(codec->control_data, data, 2);
200 if (ret != 2)
201 dev_err(codec->dev, "Write failed (%d)\n", ret);
202 else
203 ret = 0;
204 }
205
206 return ret;
207}
208
209static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
210 unsigned int value)
211{
212 struct tlv320dac33_priv *dac33 = codec->private_data;
213 int ret;
214
215 mutex_lock(&dac33->mutex);
216 ret = dac33_write(codec, reg, value);
217 mutex_unlock(&dac33->mutex);
218
219 return ret;
220}
221
222#define DAC33_I2C_ADDR_AUTOINC 0x80
223static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
224 unsigned int value)
225{
226 struct tlv320dac33_priv *dac33 = codec->private_data;
227 u8 data[3];
228 int ret = 0;
229
230 /*
231 * data is
232 * D23..D16 dac33 register offset
233 * D15..D8 register data MSB
234 * D7...D0 register data LSB
235 */
236 data[0] = reg & 0xff;
237 data[1] = (value >> 8) & 0xff;
238 data[2] = value & 0xff;
239
240 dac33_write_reg_cache(codec, data[0], data[1]);
241 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
242
243 if (dac33->chip_power) {
244 /* We need to set autoincrement mode for 16 bit writes */
245 data[0] |= DAC33_I2C_ADDR_AUTOINC;
246 ret = codec->hw_write(codec->control_data, data, 3);
247 if (ret != 3)
248 dev_err(codec->dev, "Write failed (%d)\n", ret);
249 else
250 ret = 0;
251 }
252
253 return ret;
254}
255
256static void dac33_restore_regs(struct snd_soc_codec *codec)
257{
258 struct tlv320dac33_priv *dac33 = codec->private_data;
259 u8 *cache = codec->reg_cache;
260 u8 data[2];
261 int i, ret;
262
263 if (!dac33->chip_power)
264 return;
265
266 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
267 data[0] = i;
268 data[1] = cache[i];
269 /* Skip the read only registers */
270 if ((i >= DAC33_INT_OSC_STATUS &&
271 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
272 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
273 i == DAC33_DAC_STATUS_FLAGS ||
274 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
275 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
276 continue;
277 ret = codec->hw_write(codec->control_data, data, 2);
278 if (ret != 2)
279 dev_err(codec->dev, "Write failed (%d)\n", ret);
280 }
281 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
282 data[0] = i;
283 data[1] = cache[i];
284 ret = codec->hw_write(codec->control_data, data, 2);
285 if (ret != 2)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 }
288 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
289 data[0] = i;
290 data[1] = cache[i];
291 ret = codec->hw_write(codec->control_data, data, 2);
292 if (ret != 2)
293 dev_err(codec->dev, "Write failed (%d)\n", ret);
294 }
295}
296
297static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
298{
299 u8 reg;
300
301 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
302 if (power)
303 reg |= DAC33_PDNALLB;
304 else
305 reg &= ~DAC33_PDNALLB;
306 dac33_write(codec, DAC33_PWR_CTRL, reg);
307}
308
3a7aaed7 309static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0
PU		 310{
311 struct tlv320dac33_priv *dac33 = codec->private_data;
3a7aaed7 312 int ret;
c8bf93f0
PU		 313
314 mutex_lock(&dac33->mutex);
315 if (power) {
3a7aaed7
IK		 316 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
317 dac33->supplies);
318 if (ret != 0) {
319 dev_err(codec->dev,
320 "Failed to enable supplies: %d\n", ret);
321 goto exit;
c8bf93f0 322 }
3a7aaed7
IK		 323
324 if (dac33->power_gpio >= 0)
325 gpio_set_value(dac33->power_gpio, 1);
326
327 dac33->chip_power = 1;
328
329 /* Restore registers */
330 dac33_restore_regs(codec);
331
c8bf93f0
PU		 332 dac33_soft_power(codec, 1);
333 } else {
334 dac33_soft_power(codec, 0);
3a7aaed7 335 if (dac33->power_gpio >= 0)
c8bf93f0 336 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 337
338 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
339 dac33->supplies);
340 if (ret != 0) {
341 dev_err(codec->dev,
342 "Failed to disable supplies: %d\n", ret);
343 goto exit;
c8bf93f0 344 }
3a7aaed7
IK		 345
346 dac33->chip_power = 0;
c8bf93f0 347 }
c8bf93f0 348
3a7aaed7
IK		 349exit:
350 mutex_unlock(&dac33->mutex);
351 return ret;
c8bf93f0
PU		 352}
353
354static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356{
357 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct tlv320dac33_priv *dac33 = codec->private_data;
359
360 ucontrol->value.integer.value[0] = dac33->nsample;
361
362 return 0;
363}
364
365static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_value *ucontrol)
367{
368 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
369 struct tlv320dac33_priv *dac33 = codec->private_data;
370 int ret = 0;
371
372 if (dac33->nsample == ucontrol->value.integer.value[0])
373 return 0;
374
375 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
376 ucontrol->value.integer.value[0] > dac33->nsample_max)
377 ret = -EINVAL;
378 else
379 dac33->nsample = ucontrol->value.integer.value[0];
380
381 return ret;
382}
383
384static int dac33_get_nsample_switch(struct snd_kcontrol *kcontrol,
385 struct snd_ctl_elem_value *ucontrol)
386{
387 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
388 struct tlv320dac33_priv *dac33 = codec->private_data;
389
390 ucontrol->value.integer.value[0] = dac33->nsample_switch;
391
392 return 0;
393}
394
395static int dac33_set_nsample_switch(struct snd_kcontrol *kcontrol,
396 struct snd_ctl_elem_value *ucontrol)
397{
398 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
399 struct tlv320dac33_priv *dac33 = codec->private_data;
400 int ret = 0;
401
402 if (dac33->nsample_switch == ucontrol->value.integer.value[0])
403 return 0;
404 /* Do not allow changes while stream is running*/
405 if (codec->active)
406 return -EPERM;
407
408 if (ucontrol->value.integer.value[0] < 0 ||
409 ucontrol->value.integer.value[0] > 1)
410 ret = -EINVAL;
411 else
412 dac33->nsample_switch = ucontrol->value.integer.value[0];
413
414 return ret;
415}
416
417/*
418 * DACL/R digital volume control:
419 * from 0 dB to -63.5 in 0.5 dB steps
420 * Need to be inverted later on:
421 * 0x00 == 0 dB
422 * 0x7f == -63.5 dB
423 */
424static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
425
426static const struct snd_kcontrol_new dac33_snd_controls[] = {
427 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
428 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
429 0, 0x7f, 1, dac_digivol_tlv),
430 SOC_DOUBLE_R("DAC Digital Playback Switch",
431 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
432 SOC_DOUBLE_R("Line to Line Out Volume",
433 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
434};
435
436static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
437 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
438 dac33_get_nsample, dac33_set_nsample),
439 SOC_SINGLE_EXT("nSample Switch", 0, 0, 1, 0,
440 dac33_get_nsample_switch, dac33_set_nsample_switch),
441};
442
443/* Analog bypass */
444static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
445 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
446
447static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
448 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
449
450static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
451 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
452 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
453
454 SND_SOC_DAPM_INPUT("LINEL"),
455 SND_SOC_DAPM_INPUT("LINER"),
456
457 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
458 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
459
460 /* Analog bypass */
461 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
462 &dac33_dapm_abypassl_control),
463 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
464 &dac33_dapm_abypassr_control),
465
466 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
467 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
468 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
469 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
470};
471
472static const struct snd_soc_dapm_route audio_map[] = {
473 /* Analog bypass */
474 {"Analog Left Bypass", "Switch", "LINEL"},
475 {"Analog Right Bypass", "Switch", "LINER"},
476
477 {"Output Left Amp Power", NULL, "DACL"},
478 {"Output Right Amp Power", NULL, "DACR"},
479
480 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
481 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
482
483 /* output */
484 {"LEFT_LO", NULL, "Output Left Amp Power"},
485 {"RIGHT_LO", NULL, "Output Right Amp Power"},
486};
487
488static int dac33_add_widgets(struct snd_soc_codec *codec)
489{
490 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
491 ARRAY_SIZE(dac33_dapm_widgets));
492
493 /* set up audio path interconnects */
494 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 495
496 return 0;
497}
498
499static int dac33_set_bias_level(struct snd_soc_codec *codec,
500 enum snd_soc_bias_level level)
501{
3a7aaed7
IK		 502 int ret;
503
c8bf93f0
PU		 504 switch (level) {
505 case SND_SOC_BIAS_ON:
506 dac33_soft_power(codec, 1);
507 break;
508 case SND_SOC_BIAS_PREPARE:
509 break;
510 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 511 if (codec->bias_level == SND_SOC_BIAS_OFF) {
512 ret = dac33_hard_power(codec, 1);
513 if (ret != 0)
514 return ret;
515 }
516
c8bf93f0
PU		 517 dac33_soft_power(codec, 0);
518 break;
519 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 520 ret = dac33_hard_power(codec, 0);
521 if (ret != 0)
522 return ret;
523
c8bf93f0
PU		 524 break;
525 }
526 codec->bias_level = level;
527
528 return 0;
529}
530
531static void dac33_work(struct work_struct *work)
532{
533 struct snd_soc_codec *codec;
534 struct tlv320dac33_priv *dac33;
535 u8 reg;
536
537 dac33 = container_of(work, struct tlv320dac33_priv, work);
538 codec = &dac33->codec;
539
540 mutex_lock(&dac33->mutex);
541 switch (dac33->state) {
542 case DAC33_PREFILL:
543 dac33->state = DAC33_PLAYBACK;
544 dac33_write16(codec, DAC33_NSAMPLE_MSB,
545 DAC33_THRREG(dac33->nsample));
546 dac33_write16(codec, DAC33_PREFILL_MSB,
547 DAC33_THRREG(dac33->alarm_threshold));
548 break;
549 case DAC33_PLAYBACK:
550 dac33_write16(codec, DAC33_NSAMPLE_MSB,
551 DAC33_THRREG(dac33->nsample));
552 break;
553 case DAC33_IDLE:
554 break;
555 case DAC33_FLUSH:
556 dac33->state = DAC33_IDLE;
557 /* Mask all interrupts from dac33 */
558 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
559
560 /* flush fifo */
561 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
562 reg |= DAC33_FIFOFLUSH;
563 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
564 break;
565 }
566 mutex_unlock(&dac33->mutex);
567}
568
569static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
570{
571 struct snd_soc_codec *codec = dev;
572 struct tlv320dac33_priv *dac33 = codec->private_data;
573
574 queue_work(dac33->dac33_wq, &dac33->work);
575
576 return IRQ_HANDLED;
577}
578
579static void dac33_shutdown(struct snd_pcm_substream *substream,
580 struct snd_soc_dai *dai)
581{
582 struct snd_soc_pcm_runtime *rtd = substream->private_data;
583 struct snd_soc_device *socdev = rtd->socdev;
584 struct snd_soc_codec *codec = socdev->card->codec;
585 struct tlv320dac33_priv *dac33 = codec->private_data;
586 unsigned int pwr_ctrl;
587
588 /* Stop pending workqueue */
589 if (dac33->nsample_switch)
590 cancel_work_sync(&dac33->work);
591
592 mutex_lock(&dac33->mutex);
593 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
594 pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
595 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
596 mutex_unlock(&dac33->mutex);
597}
598
599static void dac33_oscwait(struct snd_soc_codec *codec)
600{
601 int timeout = 20;
602 u8 reg;
603
604 do {
605 msleep(1);
606 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
607 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
608 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
609 dev_err(codec->dev,
610 "internal oscillator calibration failed\n");
611}
612
613static int dac33_hw_params(struct snd_pcm_substream *substream,
614 struct snd_pcm_hw_params *params,
615 struct snd_soc_dai *dai)
616{
617 struct snd_soc_pcm_runtime *rtd = substream->private_data;
618 struct snd_soc_device *socdev = rtd->socdev;
619 struct snd_soc_codec *codec = socdev->card->codec;
620
621 /* Check parameters for validity */
622 switch (params_rate(params)) {
623 case 44100:
624 case 48000:
625 break;
626 default:
627 dev_err(codec->dev, "unsupported rate %d\n",
628 params_rate(params));
629 return -EINVAL;
630 }
631
632 switch (params_format(params)) {
633 case SNDRV_PCM_FORMAT_S16_LE:
634 break;
635 default:
636 dev_err(codec->dev, "unsupported format %d\n",
637 params_format(params));
638 return -EINVAL;
639 }
640
641 return 0;
642}
643
644#define CALC_OSCSET(rate, refclk) ( \
645 ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
646#define CALC_RATIOSET(rate, refclk) ( \
647 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
648
649/*
650 * tlv320dac33 is strict on the sequence of the register writes, if the register
651 * writes happens in different order, than dac33 might end up in unknown state.
652 * Use the known, working sequence of register writes to initialize the dac33.
653 */
654static int dac33_prepare_chip(struct snd_pcm_substream *substream)
655{
656 struct snd_soc_pcm_runtime *rtd = substream->private_data;
657 struct snd_soc_device *socdev = rtd->socdev;
658 struct snd_soc_codec *codec = socdev->card->codec;
659 struct tlv320dac33_priv *dac33 = codec->private_data;
660 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
661 u8 aictrl_a, fifoctrl_a;
662
663 switch (substream->runtime->rate) {
664 case 44100:
665 case 48000:
666 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
667 ratioset = CALC_RATIOSET(substream->runtime->rate,
668 dac33->refclk);
669 break;
670 default:
671 dev_err(codec->dev, "unsupported rate %d\n",
672 substream->runtime->rate);
673 return -EINVAL;
674 }
675
676
677 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
678 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
679 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
680 fifoctrl_a &= ~DAC33_WIDTH;
681 switch (substream->runtime->format) {
682 case SNDRV_PCM_FORMAT_S16_LE:
683 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
684 fifoctrl_a |= DAC33_WIDTH;
685 break;
686 default:
687 dev_err(codec->dev, "unsupported format %d\n",
688 substream->runtime->format);
689 return -EINVAL;
690 }
691
692 mutex_lock(&dac33->mutex);
693 dac33_soft_power(codec, 1);
694
695 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
696 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
697
698 /* Write registers 0x08 and 0x09 (MSB, LSB) */
699 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
700
701 /* calib time: 128 is a nice number ;) */
702 dac33_write(codec, DAC33_CALIB_TIME, 128);
703
704 /* adjustment treshold & step */
705 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
706 DAC33_ADJSTEP(1));
707
708 /* div=4 / gain=1 / div */
709 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
710
711 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
712 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
713 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
714
715 dac33_oscwait(codec);
716
717 if (dac33->nsample_switch) {
718 /* 50-51 : ASRC Control registers */
719 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
720 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
721
722 /* Write registers 0x34 and 0x35 (MSB, LSB) */
723 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
724
725 /* Set interrupts to high active */
726 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
727
728 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
729 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
730 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
731 } else {
732 /* 50-51 : ASRC Control registers */
733 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
734 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
735 }
736
737 if (dac33->nsample_switch)
738 fifoctrl_a &= ~DAC33_FBYPAS;
739 else
740 fifoctrl_a |= DAC33_FBYPAS;
741 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
742
743 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
744 reg_tmp = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
745 if (dac33->nsample_switch)
746 reg_tmp &= ~DAC33_BCLKON;
747 else
748 reg_tmp |= DAC33_BCLKON;
749 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg_tmp);
750
751 if (dac33->nsample_switch) {
752 /* 20: BCLK divide ratio */
753 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
754
755 dac33_write16(codec, DAC33_ATHR_MSB,
756 DAC33_THRREG(dac33->alarm_threshold));
757 } else {
758 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
759 }
760
761 mutex_unlock(&dac33->mutex);
762
763 return 0;
764}
765
766static void dac33_calculate_times(struct snd_pcm_substream *substream)
767{
768 struct snd_soc_pcm_runtime *rtd = substream->private_data;
769 struct snd_soc_device *socdev = rtd->socdev;
770 struct snd_soc_codec *codec = socdev->card->codec;
771 struct tlv320dac33_priv *dac33 = codec->private_data;
772 unsigned int nsample_limit;
773
774 /* Number of samples (16bit, stereo) in one period */
775 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
776
777 /* Number of samples (16bit, stereo) in ALSA buffer */
778 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
779 /* Subtract one period from the total */
780 dac33->nsample_max -= dac33->nsample_min;
781
782 /* Number of samples for LATENCY_TIME_MS / 2 */
783 dac33->alarm_threshold = substream->runtime->rate /
784 (1000 / (LATENCY_TIME_MS / 2));
785
786 /* Find and fix up the lowest nsmaple limit */
787 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
788
789 if (dac33->nsample_min < nsample_limit)
790 dac33->nsample_min = nsample_limit;
791
792 if (dac33->nsample < dac33->nsample_min)
793 dac33->nsample = dac33->nsample_min;
794
795 /*
796 * Find and fix up the highest nsmaple limit
797 * In order to not overflow the DAC33 buffer substract the
798 * alarm_threshold value from the size of the DAC33 buffer
799 */
800 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
801
802 if (dac33->nsample_max > nsample_limit)
803 dac33->nsample_max = nsample_limit;
804
805 if (dac33->nsample > dac33->nsample_max)
806 dac33->nsample = dac33->nsample_max;
807}
808
809static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
810 struct snd_soc_dai *dai)
811{
812 dac33_calculate_times(substream);
813 dac33_prepare_chip(substream);
814
815 return 0;
816}
817
818static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
819 struct snd_soc_dai *dai)
820{
821 struct snd_soc_pcm_runtime *rtd = substream->private_data;
822 struct snd_soc_device *socdev = rtd->socdev;
823 struct snd_soc_codec *codec = socdev->card->codec;
824 struct tlv320dac33_priv *dac33 = codec->private_data;
825 int ret = 0;
826
827 switch (cmd) {
828 case SNDRV_PCM_TRIGGER_START:
829 case SNDRV_PCM_TRIGGER_RESUME:
830 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
831 if (dac33->nsample_switch) {
832 dac33->state = DAC33_PREFILL;
833 queue_work(dac33->dac33_wq, &dac33->work);
834 }
835 break;
836 case SNDRV_PCM_TRIGGER_STOP:
837 case SNDRV_PCM_TRIGGER_SUSPEND:
838 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
839 if (dac33->nsample_switch) {
840 dac33->state = DAC33_FLUSH;
841 queue_work(dac33->dac33_wq, &dac33->work);
842 }
843 break;
844 default:
845 ret = -EINVAL;
846 }
847
848 return ret;
849}
850
851static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
852 int clk_id, unsigned int freq, int dir)
853{
854 struct snd_soc_codec *codec = codec_dai->codec;
855 struct tlv320dac33_priv *dac33 = codec->private_data;
856 u8 ioc_reg, asrcb_reg;
857
858 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
859 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
860 switch (clk_id) {
861 case TLV320DAC33_MCLK:
862 ioc_reg |= DAC33_REFSEL;
863 asrcb_reg |= DAC33_SRCREFSEL;
864 break;
865 case TLV320DAC33_SLEEPCLK:
866 ioc_reg &= ~DAC33_REFSEL;
867 asrcb_reg &= ~DAC33_SRCREFSEL;
868 break;
869 default:
870 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
871 break;
872 }
873 dac33->refclk = freq;
874
875 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
876 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
877
878 return 0;
879}
880
881static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
882 unsigned int fmt)
883{
884 struct snd_soc_codec *codec = codec_dai->codec;
885 u8 aictrl_a, aictrl_b;
886
887 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
888 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
889 /* set master/slave audio interface */
890 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
891 case SND_SOC_DAIFMT_CBM_CFM:
892 /* Codec Master */
893 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
894 break;
895 case SND_SOC_DAIFMT_CBS_CFS:
896 /* Codec Slave */
897 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
898 break;
899 default:
900 return -EINVAL;
901 }
902
903 aictrl_a &= ~DAC33_AFMT_MASK;
904 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
905 case SND_SOC_DAIFMT_I2S:
906 aictrl_a |= DAC33_AFMT_I2S;
907 break;
908 case SND_SOC_DAIFMT_DSP_A:
909 aictrl_a |= DAC33_AFMT_DSP;
910 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
911 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
912 break;
913 case SND_SOC_DAIFMT_DSP_B:
914 aictrl_a |= DAC33_AFMT_DSP;
915 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
916 break;
917 case SND_SOC_DAIFMT_RIGHT_J:
918 aictrl_a |= DAC33_AFMT_RIGHT_J;
919 break;
920 case SND_SOC_DAIFMT_LEFT_J:
921 aictrl_a |= DAC33_AFMT_LEFT_J;
922 break;
923 default:
924 dev_err(codec->dev, "Unsupported format (%u)\n",
925 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
926 return -EINVAL;
927 }
928
929 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
930 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
931
932 return 0;
933}
934
935static void dac33_init_chip(struct snd_soc_codec *codec)
936{
937 /* 44-46: DAC Control Registers */
938 /* A : DAC sample rate Fsref/1.5 */
939 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
940 /* B : DAC src=normal, not muted */
941 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
942 DAC33_DACSRCL_LEFT);
943 /* C : (defaults) */
944 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
945
946 /* 64-65 : L&R DAC power control
947 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
948 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
949 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
950
951 /* 73 : volume soft stepping control,
952 clock source = internal osc (?) */
953 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
954
955 /* 66 : LOP/LOM Modes */
956 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
957
958 /* 68 : LOM inverted from LOP */
959 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
960
961 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
962}
963
964static int dac33_soc_probe(struct platform_device *pdev)
965{
966 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
967 struct snd_soc_codec *codec;
968 struct tlv320dac33_priv *dac33;
969 int ret = 0;
970
971 BUG_ON(!tlv320dac33_codec);
972
973 codec = tlv320dac33_codec;
974 socdev->card->codec = codec;
975 dac33 = codec->private_data;
976
977 /* Power up the codec */
978 dac33_hard_power(codec, 1);
979 /* Set default configuration */
980 dac33_init_chip(codec);
981
982 /* register pcms */
983 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
984 if (ret < 0) {
985 dev_err(codec->dev, "failed to create pcms\n");
986 goto pcm_err;
987 }
988
989 snd_soc_add_controls(codec, dac33_snd_controls,
990 ARRAY_SIZE(dac33_snd_controls));
991 /* Only add the nSample controls, if we have valid IRQ number */
992 if (dac33->irq >= 0)
993 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
994 ARRAY_SIZE(dac33_nsample_snd_controls));
995
996 dac33_add_widgets(codec);
997
998 /* power on device */
999 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1000
3a7aaed7
IK		 1001 /* Bias level configuration has enabled regulator an extra time */
1002 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1003
c8bf93f0 1004 return 0;
fe3e78e0 1005
c8bf93f0
PU		 1006pcm_err:
1007 dac33_hard_power(codec, 0);
1008 return ret;
1009}
1010
1011static int dac33_soc_remove(struct platform_device *pdev)
1012{
1013 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1014 struct snd_soc_codec *codec = socdev->card->codec;
1015
1016 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1017
1018 snd_soc_free_pcms(socdev);
1019 snd_soc_dapm_free(socdev);
1020
1021 return 0;
1022}
1023
1024static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1025{
1026 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1027 struct snd_soc_codec *codec = socdev->card->codec;
1028
1029 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1030
1031 return 0;
1032}
1033
1034static int dac33_soc_resume(struct platform_device *pdev)
1035{
1036 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1037 struct snd_soc_codec *codec = socdev->card->codec;
1038
1039 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1040 dac33_set_bias_level(codec, codec->suspend_bias_level);
1041
1042 return 0;
1043}
1044
1045struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1046 .probe = dac33_soc_probe,
1047 .remove = dac33_soc_remove,
1048 .suspend = dac33_soc_suspend,
1049 .resume = dac33_soc_resume,
1050};
1051EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1052
1053#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1054 SNDRV_PCM_RATE_48000)
1055#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1056
1057static struct snd_soc_dai_ops dac33_dai_ops = {
1058 .shutdown = dac33_shutdown,
1059 .hw_params = dac33_hw_params,
1060 .prepare = dac33_pcm_prepare,
1061 .trigger = dac33_pcm_trigger,
1062 .set_sysclk = dac33_set_dai_sysclk,
1063 .set_fmt = dac33_set_dai_fmt,
1064};
1065
1066struct snd_soc_dai dac33_dai = {
1067 .name = "tlv320dac33",
1068 .playback = {
1069 .stream_name = "Playback",
1070 .channels_min = 2,
1071 .channels_max = 2,
1072 .rates = DAC33_RATES,
1073 .formats = DAC33_FORMATS,},
1074 .ops = &dac33_dai_ops,
1075};
1076EXPORT_SYMBOL_GPL(dac33_dai);
1077
1078static int dac33_i2c_probe(struct i2c_client *client,
1079 const struct i2c_device_id *id)
1080{
1081 struct tlv320dac33_platform_data *pdata;
1082 struct tlv320dac33_priv *dac33;
1083 struct snd_soc_codec *codec;
3a7aaed7 1084 int ret, i;
c8bf93f0
PU		 1085
1086 if (client->dev.platform_data == NULL) {
1087 dev_err(&client->dev, "Platform data not set\n");
1088 return -ENODEV;
1089 }
1090 pdata = client->dev.platform_data;
1091
1092 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1093 if (dac33 == NULL)
1094 return -ENOMEM;
1095
1096 codec = &dac33->codec;
1097 codec->private_data = dac33;
1098 codec->control_data = client;
1099
1100 mutex_init(&codec->mutex);
1101 mutex_init(&dac33->mutex);
1102 INIT_LIST_HEAD(&codec->dapm_widgets);
1103 INIT_LIST_HEAD(&codec->dapm_paths);
1104
1105 codec->name = "tlv320dac33";
1106 codec->owner = THIS_MODULE;
1107 codec->read = dac33_read_reg_cache;
1108 codec->write = dac33_write_locked;
1109 codec->hw_write = (hw_write_t) i2c_master_send;
1110 codec->bias_level = SND_SOC_BIAS_OFF;
1111 codec->set_bias_level = dac33_set_bias_level;
1112 codec->dai = &dac33_dai;
1113 codec->num_dai = 1;
1114 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1115 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1116 GFP_KERNEL);
1117 if (codec->reg_cache == NULL) {
1118 ret = -ENOMEM;
1119 goto error_reg;
1120 }
1121
1122 i2c_set_clientdata(client, dac33);
1123
1124 dac33->power_gpio = pdata->power_gpio;
1125 dac33->irq = client->irq;
1126 dac33->nsample = NSAMPLE_MAX;
1127 /* Disable FIFO use by default */
1128 dac33->nsample_switch = 0;
1129
1130 tlv320dac33_codec = codec;
1131
1132 codec->dev = &client->dev;
1133 dac33_dai.dev = codec->dev;
1134
1135 /* Check if the reset GPIO number is valid and request it */
1136 if (dac33->power_gpio >= 0) {
1137 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1138 if (ret < 0) {
1139 dev_err(codec->dev,
1140 "Failed to request reset GPIO (%d)\n",
1141 dac33->power_gpio);
1142 snd_soc_unregister_dai(&dac33_dai);
1143 snd_soc_unregister_codec(codec);
1144 goto error_gpio;
1145 }
1146 gpio_direction_output(dac33->power_gpio, 0);
1147 } else {
1148 dac33->chip_power = 1;
1149 }
1150
1151 /* Check if the IRQ number is valid and request it */
1152 if (dac33->irq >= 0) {
1153 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1154 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1155 codec->name, codec);
1156 if (ret < 0) {
1157 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1158 dac33->irq, ret);
1159 dac33->irq = -1;
1160 }
1161 if (dac33->irq != -1) {
1162 /* Setup work queue */
74ea23aa
PU		 1163 dac33->dac33_wq =
1164 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1165 if (dac33->dac33_wq == NULL) {
1166 free_irq(dac33->irq, &dac33->codec);
1167 ret = -ENOMEM;
1168 goto error_wq;
1169 }
1170
1171 INIT_WORK(&dac33->work, dac33_work);
1172 }
1173 }
1174
3a7aaed7
IK		 1175 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1176 dac33->supplies[i].supply = dac33_supply_names[i];
1177
1178 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1179 dac33->supplies);
1180
1181 if (ret != 0) {
1182 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1183 goto err_get;
1184 }
1185
1186 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1187 dac33->supplies);
1188 if (ret != 0) {
1189 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1190 goto err_enable;
1191 }
1192
c8bf93f0
PU		 1193 ret = snd_soc_register_codec(codec);
1194 if (ret != 0) {
1195 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1196 goto error_codec;
1197 }
1198
1199 ret = snd_soc_register_dai(&dac33_dai);
1200 if (ret != 0) {
1201 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1202 snd_soc_unregister_codec(codec);
1203 goto error_codec;
1204 }
1205
1206 /* Shut down the codec for now */
1207 dac33_hard_power(codec, 0);
1208
1209 return ret;
1210
1211error_codec:
3a7aaed7
IK		 1212 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1213err_enable:
1214 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1215err_get:
c8bf93f0
PU		 1216 if (dac33->irq >= 0) {
1217 free_irq(dac33->irq, &dac33->codec);
1218 destroy_workqueue(dac33->dac33_wq);
1219 }
1220error_wq:
1221 if (dac33->power_gpio >= 0)
1222 gpio_free(dac33->power_gpio);
1223error_gpio:
1224 kfree(codec->reg_cache);
1225error_reg:
1226 tlv320dac33_codec = NULL;
1227 kfree(dac33);
1228
1229 return ret;
1230}
1231
1232static int dac33_i2c_remove(struct i2c_client *client)
1233{
1234 struct tlv320dac33_priv *dac33;
1235
1236 dac33 = i2c_get_clientdata(client);
1237 dac33_hard_power(&dac33->codec, 0);
1238
1239 if (dac33->power_gpio >= 0)
1240 gpio_free(dac33->power_gpio);
1241 if (dac33->irq >= 0)
1242 free_irq(dac33->irq, &dac33->codec);
1243
3a7aaed7
IK		 1244 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1245
c8bf93f0
PU		 1246 destroy_workqueue(dac33->dac33_wq);
1247 snd_soc_unregister_dai(&dac33_dai);
1248 snd_soc_unregister_codec(&dac33->codec);
1249 kfree(dac33->codec.reg_cache);
1250 kfree(dac33);
1251 tlv320dac33_codec = NULL;
1252
1253 return 0;
1254}
1255
1256static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1257 {
1258 .name = "tlv320dac33",
1259 .driver_data = 0,
1260 },
1261 { },
1262};
1263
1264static struct i2c_driver tlv320dac33_i2c_driver = {
1265 .driver = {
1266 .name = "tlv320dac33",
1267 .owner = THIS_MODULE,
1268 },
1269 .probe = dac33_i2c_probe,
1270 .remove = __devexit_p(dac33_i2c_remove),
1271 .id_table = tlv320dac33_i2c_id,
1272};
1273
1274static int __init dac33_module_init(void)
1275{
1276 int r;
1277 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1278 if (r < 0) {
1279 printk(KERN_ERR "DAC33: driver registration failed\n");
1280 return r;
1281 }
1282 return 0;
1283}
1284module_init(dac33_module_init);
1285
1286static void __exit dac33_module_exit(void)
1287{
1288 i2c_del_driver(&tlv320dac33_i2c_driver);
1289}
1290module_exit(dac33_module_exit);
1291
1292
1293MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1294MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1295MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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