Commit | Line | Data |
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c8bf93f0 PU |
1 | /* |
2 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver | |
3 | * | |
4 | * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com> | |
5 | * | |
6 | * Copyright: (C) 2009 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/moduleparam.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/pm.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/gpio.h> | |
3a7aaed7 | 33 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
c8bf93f0 PU |
35 | #include <sound/core.h> |
36 | #include <sound/pcm.h> | |
37 | #include <sound/pcm_params.h> | |
38 | #include <sound/soc.h> | |
c8bf93f0 PU |
39 | #include <sound/initval.h> |
40 | #include <sound/tlv.h> | |
41 | ||
42 | #include <sound/tlv320dac33-plat.h> | |
43 | #include "tlv320dac33.h" | |
44 | ||
45 | #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words, | |
46 | * 6144 stereo */ | |
47 | #define DAC33_BUFFER_SIZE_SAMPLES 6144 | |
48 | ||
49 | #define NSAMPLE_MAX 5700 | |
50 | ||
4260393e PU |
51 | #define MODE7_LTHR 10 |
52 | #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10) | |
53 | ||
76f47127 PU |
54 | #define BURST_BASEFREQ_HZ 49152000 |
55 | ||
f57d2cfa PU |
56 | #define SAMPLES_TO_US(rate, samples) \ |
57 | (1000000000 / ((rate * 1000) / samples)) | |
58 | ||
59 | #define US_TO_SAMPLES(rate, us) \ | |
d54e1f4f | 60 | (rate / (1000000 / (us < 1000000 ? us : 1000000))) |
f57d2cfa | 61 | |
a577b318 PU |
62 | #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ |
63 | ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate))) | |
64 | ||
ad05c03b PU |
65 | static void dac33_calculate_times(struct snd_pcm_substream *substream); |
66 | static int dac33_prepare_chip(struct snd_pcm_substream *substream); | |
f57d2cfa | 67 | |
c8bf93f0 PU |
68 | enum dac33_state { |
69 | DAC33_IDLE = 0, | |
70 | DAC33_PREFILL, | |
71 | DAC33_PLAYBACK, | |
72 | DAC33_FLUSH, | |
73 | }; | |
74 | ||
7427b4b9 PU |
75 | enum dac33_fifo_modes { |
76 | DAC33_FIFO_BYPASS = 0, | |
77 | DAC33_FIFO_MODE1, | |
28e05d98 | 78 | DAC33_FIFO_MODE7, |
7427b4b9 PU |
79 | DAC33_FIFO_LAST_MODE, |
80 | }; | |
81 | ||
3a7aaed7 IK |
82 | #define DAC33_NUM_SUPPLIES 3 |
83 | static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { | |
84 | "AVDD", | |
85 | "DVDD", | |
86 | "IOVDD", | |
87 | }; | |
88 | ||
c8bf93f0 PU |
89 | struct tlv320dac33_priv { |
90 | struct mutex mutex; | |
91 | struct workqueue_struct *dac33_wq; | |
92 | struct work_struct work; | |
f0fba2ad | 93 | struct snd_soc_codec *codec; |
3a7aaed7 | 94 | struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; |
0b61d2b9 | 95 | struct snd_pcm_substream *substream; |
c8bf93f0 PU |
96 | int power_gpio; |
97 | int chip_power; | |
98 | int irq; | |
99 | unsigned int refclk; | |
100 | ||
101 | unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ | |
102 | unsigned int nsample_min; /* nsample should not be lower than | |
103 | * this */ | |
104 | unsigned int nsample_max; /* nsample should not be higher than | |
105 | * this */ | |
7427b4b9 | 106 | enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ |
c8bf93f0 | 107 | unsigned int nsample; /* burst read amount from host */ |
f430a27f PU |
108 | int mode1_latency; /* latency caused by the i2c writes in |
109 | * us */ | |
a577b318 PU |
110 | int auto_fifo_config; /* Configure the FIFO based on the |
111 | * period size */ | |
6aceabb4 | 112 | u8 burst_bclkdiv; /* BCLK divider value in burst mode */ |
76f47127 | 113 | unsigned int burst_rate; /* Interface speed in Burst modes */ |
c8bf93f0 | 114 | |
eeb309a8 PU |
115 | int keep_bclk; /* Keep the BCLK continuously running |
116 | * in FIFO modes */ | |
f57d2cfa PU |
117 | spinlock_t lock; |
118 | unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ | |
119 | unsigned long long t_stamp2; /* calculate the FIFO caused delay */ | |
120 | ||
121 | unsigned int mode1_us_burst; /* Time to burst read n number of | |
122 | * samples */ | |
123 | unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ | |
c8bf93f0 | 124 | |
9d7db2b2 PU |
125 | unsigned int uthr; |
126 | ||
c8bf93f0 | 127 | enum dac33_state state; |
f0fba2ad LG |
128 | enum snd_soc_control_type control_type; |
129 | void *control_data; | |
c8bf93f0 PU |
130 | }; |
131 | ||
132 | static const u8 dac33_reg[DAC33_CACHEREGNUM] = { | |
133 | 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ | |
134 | 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ | |
135 | 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ | |
136 | 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ | |
137 | 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ | |
138 | 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ | |
139 | 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ | |
140 | 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ | |
141 | 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ | |
142 | 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ | |
143 | 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ | |
144 | 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ | |
145 | 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ | |
146 | 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ | |
147 | 0x00, 0x00, /* 0x38 - 0x39 */ | |
148 | /* Registers 0x3a - 0x3f are reserved */ | |
149 | 0x00, 0x00, /* 0x3a - 0x3b */ | |
150 | 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ | |
151 | ||
152 | 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ | |
153 | 0x00, 0x80, /* 0x44 - 0x45 */ | |
154 | /* Registers 0x46 - 0x47 are reserved */ | |
155 | 0x80, 0x80, /* 0x46 - 0x47 */ | |
156 | ||
157 | 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ | |
158 | /* Registers 0x4b - 0x7c are reserved */ | |
159 | 0x00, /* 0x4b */ | |
160 | 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ | |
161 | 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ | |
162 | 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ | |
163 | 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ | |
164 | 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ | |
165 | 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ | |
166 | 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ | |
167 | 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ | |
168 | 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ | |
169 | 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ | |
170 | 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ | |
171 | 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ | |
172 | 0x00, /* 0x7c */ | |
173 | ||
174 | 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ | |
175 | }; | |
176 | ||
177 | /* Register read and write */ | |
178 | static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, | |
179 | unsigned reg) | |
180 | { | |
181 | u8 *cache = codec->reg_cache; | |
182 | if (reg >= DAC33_CACHEREGNUM) | |
183 | return 0; | |
184 | ||
185 | return cache[reg]; | |
186 | } | |
187 | ||
188 | static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, | |
189 | u8 reg, u8 value) | |
190 | { | |
191 | u8 *cache = codec->reg_cache; | |
192 | if (reg >= DAC33_CACHEREGNUM) | |
193 | return; | |
194 | ||
195 | cache[reg] = value; | |
196 | } | |
197 | ||
198 | static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, | |
199 | u8 *value) | |
200 | { | |
b2c812e2 | 201 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
911a0f0b | 202 | int val, ret = 0; |
c8bf93f0 PU |
203 | |
204 | *value = reg & 0xff; | |
205 | ||
206 | /* If powered off, return the cached value */ | |
207 | if (dac33->chip_power) { | |
208 | val = i2c_smbus_read_byte_data(codec->control_data, value[0]); | |
209 | if (val < 0) { | |
210 | dev_err(codec->dev, "Read failed (%d)\n", val); | |
211 | value[0] = dac33_read_reg_cache(codec, reg); | |
911a0f0b | 212 | ret = val; |
c8bf93f0 PU |
213 | } else { |
214 | value[0] = val; | |
215 | dac33_write_reg_cache(codec, reg, val); | |
216 | } | |
217 | } else { | |
218 | value[0] = dac33_read_reg_cache(codec, reg); | |
219 | } | |
220 | ||
911a0f0b | 221 | return ret; |
c8bf93f0 PU |
222 | } |
223 | ||
224 | static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, | |
225 | unsigned int value) | |
226 | { | |
b2c812e2 | 227 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
228 | u8 data[2]; |
229 | int ret = 0; | |
230 | ||
231 | /* | |
232 | * data is | |
233 | * D15..D8 dac33 register offset | |
234 | * D7...D0 register data | |
235 | */ | |
236 | data[0] = reg & 0xff; | |
237 | data[1] = value & 0xff; | |
238 | ||
239 | dac33_write_reg_cache(codec, data[0], data[1]); | |
240 | if (dac33->chip_power) { | |
241 | ret = codec->hw_write(codec->control_data, data, 2); | |
242 | if (ret != 2) | |
243 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
244 | else | |
245 | ret = 0; | |
246 | } | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
251 | static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, | |
252 | unsigned int value) | |
253 | { | |
b2c812e2 | 254 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
255 | int ret; |
256 | ||
257 | mutex_lock(&dac33->mutex); | |
258 | ret = dac33_write(codec, reg, value); | |
259 | mutex_unlock(&dac33->mutex); | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
264 | #define DAC33_I2C_ADDR_AUTOINC 0x80 | |
265 | static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, | |
266 | unsigned int value) | |
267 | { | |
b2c812e2 | 268 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
269 | u8 data[3]; |
270 | int ret = 0; | |
271 | ||
272 | /* | |
273 | * data is | |
274 | * D23..D16 dac33 register offset | |
275 | * D15..D8 register data MSB | |
276 | * D7...D0 register data LSB | |
277 | */ | |
278 | data[0] = reg & 0xff; | |
279 | data[1] = (value >> 8) & 0xff; | |
280 | data[2] = value & 0xff; | |
281 | ||
282 | dac33_write_reg_cache(codec, data[0], data[1]); | |
283 | dac33_write_reg_cache(codec, data[0] + 1, data[2]); | |
284 | ||
285 | if (dac33->chip_power) { | |
286 | /* We need to set autoincrement mode for 16 bit writes */ | |
287 | data[0] |= DAC33_I2C_ADDR_AUTOINC; | |
288 | ret = codec->hw_write(codec->control_data, data, 3); | |
289 | if (ret != 3) | |
290 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
291 | else | |
292 | ret = 0; | |
293 | } | |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
ef909d67 | 298 | static void dac33_init_chip(struct snd_soc_codec *codec) |
c8bf93f0 | 299 | { |
b2c812e2 | 300 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 301 | |
ef909d67 | 302 | if (unlikely(!dac33->chip_power)) |
c8bf93f0 PU |
303 | return; |
304 | ||
ef909d67 PU |
305 | /* 44-46: DAC Control Registers */ |
306 | /* A : DAC sample rate Fsref/1.5 */ | |
307 | dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); | |
308 | /* B : DAC src=normal, not muted */ | |
309 | dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | | |
310 | DAC33_DACSRCL_LEFT); | |
311 | /* C : (defaults) */ | |
312 | dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); | |
313 | ||
ef909d67 PU |
314 | /* 73 : volume soft stepping control, |
315 | clock source = internal osc (?) */ | |
316 | dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); | |
317 | ||
ef909d67 PU |
318 | /* Restore only selected registers (gains mostly) */ |
319 | dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, | |
320 | dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); | |
321 | dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, | |
322 | dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); | |
323 | ||
324 | dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, | |
325 | dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); | |
326 | dac33_write(codec, DAC33_LINER_TO_RLO_VOL, | |
327 | dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); | |
c8bf93f0 PU |
328 | } |
329 | ||
911a0f0b | 330 | static inline int dac33_read_id(struct snd_soc_codec *codec) |
239fe55c | 331 | { |
911a0f0b | 332 | int i, ret = 0; |
239fe55c PU |
333 | u8 reg; |
334 | ||
911a0f0b PU |
335 | for (i = 0; i < 3; i++) { |
336 | ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); | |
337 | if (ret < 0) | |
338 | break; | |
339 | } | |
340 | ||
341 | return ret; | |
c8bf93f0 PU |
342 | } |
343 | ||
344 | static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) | |
345 | { | |
346 | u8 reg; | |
347 | ||
348 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
349 | if (power) | |
350 | reg |= DAC33_PDNALLB; | |
351 | else | |
c3746a07 PU |
352 | reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | |
353 | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
c8bf93f0 PU |
354 | dac33_write(codec, DAC33_PWR_CTRL, reg); |
355 | } | |
356 | ||
3a7aaed7 | 357 | static int dac33_hard_power(struct snd_soc_codec *codec, int power) |
c8bf93f0 | 358 | { |
b2c812e2 | 359 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
ad05c03b | 360 | int ret = 0; |
c8bf93f0 PU |
361 | |
362 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
363 | |
364 | /* Safety check */ | |
365 | if (unlikely(power == dac33->chip_power)) { | |
7fd1d74b | 366 | dev_dbg(codec->dev, "Trying to set the same power state: %s\n", |
ad05c03b PU |
367 | power ? "ON" : "OFF"); |
368 | goto exit; | |
369 | } | |
370 | ||
c8bf93f0 | 371 | if (power) { |
3a7aaed7 IK |
372 | ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), |
373 | dac33->supplies); | |
374 | if (ret != 0) { | |
375 | dev_err(codec->dev, | |
376 | "Failed to enable supplies: %d\n", ret); | |
377 | goto exit; | |
c8bf93f0 | 378 | } |
3a7aaed7 IK |
379 | |
380 | if (dac33->power_gpio >= 0) | |
381 | gpio_set_value(dac33->power_gpio, 1); | |
382 | ||
383 | dac33->chip_power = 1; | |
c8bf93f0 PU |
384 | } else { |
385 | dac33_soft_power(codec, 0); | |
3a7aaed7 | 386 | if (dac33->power_gpio >= 0) |
c8bf93f0 | 387 | gpio_set_value(dac33->power_gpio, 0); |
3a7aaed7 IK |
388 | |
389 | ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), | |
390 | dac33->supplies); | |
391 | if (ret != 0) { | |
392 | dev_err(codec->dev, | |
393 | "Failed to disable supplies: %d\n", ret); | |
394 | goto exit; | |
c8bf93f0 | 395 | } |
3a7aaed7 IK |
396 | |
397 | dac33->chip_power = 0; | |
c8bf93f0 | 398 | } |
c8bf93f0 | 399 | |
3a7aaed7 IK |
400 | exit: |
401 | mutex_unlock(&dac33->mutex); | |
402 | return ret; | |
c8bf93f0 PU |
403 | } |
404 | ||
ad05c03b PU |
405 | static int playback_event(struct snd_soc_dapm_widget *w, |
406 | struct snd_kcontrol *kcontrol, int event) | |
407 | { | |
408 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); | |
409 | ||
410 | switch (event) { | |
411 | case SND_SOC_DAPM_PRE_PMU: | |
412 | if (likely(dac33->substream)) { | |
413 | dac33_calculate_times(dac33->substream); | |
414 | dac33_prepare_chip(dac33->substream); | |
415 | } | |
416 | break; | |
417 | } | |
418 | return 0; | |
419 | } | |
420 | ||
c8bf93f0 PU |
421 | static int dac33_get_nsample(struct snd_kcontrol *kcontrol, |
422 | struct snd_ctl_elem_value *ucontrol) | |
423 | { | |
424 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 425 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
426 | |
427 | ucontrol->value.integer.value[0] = dac33->nsample; | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | static int dac33_set_nsample(struct snd_kcontrol *kcontrol, | |
433 | struct snd_ctl_elem_value *ucontrol) | |
434 | { | |
435 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 436 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
437 | int ret = 0; |
438 | ||
439 | if (dac33->nsample == ucontrol->value.integer.value[0]) | |
440 | return 0; | |
441 | ||
442 | if (ucontrol->value.integer.value[0] < dac33->nsample_min || | |
f57d2cfa | 443 | ucontrol->value.integer.value[0] > dac33->nsample_max) { |
c8bf93f0 | 444 | ret = -EINVAL; |
f57d2cfa | 445 | } else { |
c8bf93f0 | 446 | dac33->nsample = ucontrol->value.integer.value[0]; |
f57d2cfa PU |
447 | /* Re calculate the burst time */ |
448 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, | |
449 | dac33->nsample); | |
450 | } | |
c8bf93f0 PU |
451 | |
452 | return ret; | |
453 | } | |
454 | ||
9d7db2b2 PU |
455 | static int dac33_get_uthr(struct snd_kcontrol *kcontrol, |
456 | struct snd_ctl_elem_value *ucontrol) | |
457 | { | |
458 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
459 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
460 | ||
461 | ucontrol->value.integer.value[0] = dac33->uthr; | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int dac33_set_uthr(struct snd_kcontrol *kcontrol, | |
467 | struct snd_ctl_elem_value *ucontrol) | |
468 | { | |
469 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
470 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
471 | int ret = 0; | |
472 | ||
473 | if (dac33->substream) | |
474 | return -EBUSY; | |
475 | ||
476 | if (dac33->uthr == ucontrol->value.integer.value[0]) | |
477 | return 0; | |
478 | ||
479 | if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) || | |
480 | ucontrol->value.integer.value[0] > MODE7_UTHR) | |
481 | ret = -EINVAL; | |
482 | else | |
483 | dac33->uthr = ucontrol->value.integer.value[0]; | |
484 | ||
485 | return ret; | |
486 | } | |
487 | ||
7427b4b9 | 488 | static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
489 | struct snd_ctl_elem_value *ucontrol) |
490 | { | |
491 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 492 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 493 | |
7427b4b9 | 494 | ucontrol->value.integer.value[0] = dac33->fifo_mode; |
c8bf93f0 PU |
495 | |
496 | return 0; | |
497 | } | |
498 | ||
7427b4b9 | 499 | static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
500 | struct snd_ctl_elem_value *ucontrol) |
501 | { | |
502 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 503 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
504 | int ret = 0; |
505 | ||
7427b4b9 | 506 | if (dac33->fifo_mode == ucontrol->value.integer.value[0]) |
c8bf93f0 PU |
507 | return 0; |
508 | /* Do not allow changes while stream is running*/ | |
509 | if (codec->active) | |
510 | return -EPERM; | |
511 | ||
512 | if (ucontrol->value.integer.value[0] < 0 || | |
7427b4b9 | 513 | ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) |
c8bf93f0 PU |
514 | ret = -EINVAL; |
515 | else | |
7427b4b9 | 516 | dac33->fifo_mode = ucontrol->value.integer.value[0]; |
c8bf93f0 PU |
517 | |
518 | return ret; | |
519 | } | |
520 | ||
7427b4b9 PU |
521 | /* Codec operation modes */ |
522 | static const char *dac33_fifo_mode_texts[] = { | |
28e05d98 | 523 | "Bypass", "Mode 1", "Mode 7" |
7427b4b9 PU |
524 | }; |
525 | ||
526 | static const struct soc_enum dac33_fifo_mode_enum = | |
527 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), | |
528 | dac33_fifo_mode_texts); | |
529 | ||
cf4bb698 PU |
530 | /* L/R Line Output Gain */ |
531 | static const char *lr_lineout_gain_texts[] = { | |
532 | "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", | |
533 | "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", | |
534 | }; | |
535 | ||
536 | static const struct soc_enum l_lineout_gain_enum = | |
537 | SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0, | |
538 | ARRAY_SIZE(lr_lineout_gain_texts), | |
539 | lr_lineout_gain_texts); | |
540 | ||
541 | static const struct soc_enum r_lineout_gain_enum = | |
542 | SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0, | |
543 | ARRAY_SIZE(lr_lineout_gain_texts), | |
544 | lr_lineout_gain_texts); | |
545 | ||
c8bf93f0 PU |
546 | /* |
547 | * DACL/R digital volume control: | |
548 | * from 0 dB to -63.5 in 0.5 dB steps | |
549 | * Need to be inverted later on: | |
550 | * 0x00 == 0 dB | |
551 | * 0x7f == -63.5 dB | |
552 | */ | |
553 | static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); | |
554 | ||
555 | static const struct snd_kcontrol_new dac33_snd_controls[] = { | |
556 | SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", | |
557 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, | |
558 | 0, 0x7f, 1, dac_digivol_tlv), | |
559 | SOC_DOUBLE_R("DAC Digital Playback Switch", | |
560 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), | |
561 | SOC_DOUBLE_R("Line to Line Out Volume", | |
562 | DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), | |
cf4bb698 PU |
563 | SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), |
564 | SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), | |
c8bf93f0 PU |
565 | }; |
566 | ||
a577b318 PU |
567 | static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { |
568 | SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, | |
569 | dac33_get_fifo_mode, dac33_set_fifo_mode), | |
570 | }; | |
571 | ||
572 | static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = { | |
c8bf93f0 | 573 | SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0, |
a577b318 | 574 | dac33_get_nsample, dac33_set_nsample), |
9d7db2b2 PU |
575 | SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0, |
576 | dac33_get_uthr, dac33_set_uthr), | |
c8bf93f0 PU |
577 | }; |
578 | ||
579 | /* Analog bypass */ | |
580 | static const struct snd_kcontrol_new dac33_dapm_abypassl_control = | |
581 | SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); | |
582 | ||
583 | static const struct snd_kcontrol_new dac33_dapm_abypassr_control = | |
584 | SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); | |
585 | ||
586 | static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { | |
587 | SND_SOC_DAPM_OUTPUT("LEFT_LO"), | |
588 | SND_SOC_DAPM_OUTPUT("RIGHT_LO"), | |
589 | ||
590 | SND_SOC_DAPM_INPUT("LINEL"), | |
591 | SND_SOC_DAPM_INPUT("LINER"), | |
592 | ||
593 | SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0), | |
594 | SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0), | |
595 | ||
596 | /* Analog bypass */ | |
597 | SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, | |
598 | &dac33_dapm_abypassl_control), | |
599 | SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, | |
600 | &dac33_dapm_abypassr_control), | |
601 | ||
9e87186f | 602 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", |
c8bf93f0 | 603 | DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), |
9e87186f | 604 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", |
c8bf93f0 | 605 | DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), |
ad05c03b PU |
606 | |
607 | SND_SOC_DAPM_PRE("Prepare Playback", playback_event), | |
c8bf93f0 PU |
608 | }; |
609 | ||
610 | static const struct snd_soc_dapm_route audio_map[] = { | |
611 | /* Analog bypass */ | |
612 | {"Analog Left Bypass", "Switch", "LINEL"}, | |
613 | {"Analog Right Bypass", "Switch", "LINER"}, | |
614 | ||
9e87186f PU |
615 | {"Output Left Amplifier", NULL, "DACL"}, |
616 | {"Output Right Amplifier", NULL, "DACR"}, | |
c8bf93f0 | 617 | |
9e87186f PU |
618 | {"Output Left Amplifier", NULL, "Analog Left Bypass"}, |
619 | {"Output Right Amplifier", NULL, "Analog Right Bypass"}, | |
c8bf93f0 PU |
620 | |
621 | /* output */ | |
9e87186f PU |
622 | {"LEFT_LO", NULL, "Output Left Amplifier"}, |
623 | {"RIGHT_LO", NULL, "Output Right Amplifier"}, | |
c8bf93f0 PU |
624 | }; |
625 | ||
626 | static int dac33_add_widgets(struct snd_soc_codec *codec) | |
627 | { | |
ce6120cc | 628 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
c8bf93f0 | 629 | |
ce6120cc LG |
630 | snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets, |
631 | ARRAY_SIZE(dac33_dapm_widgets)); | |
c8bf93f0 | 632 | /* set up audio path interconnects */ |
ce6120cc | 633 | snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); |
c8bf93f0 PU |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
638 | static int dac33_set_bias_level(struct snd_soc_codec *codec, | |
639 | enum snd_soc_bias_level level) | |
640 | { | |
3a7aaed7 IK |
641 | int ret; |
642 | ||
c8bf93f0 PU |
643 | switch (level) { |
644 | case SND_SOC_BIAS_ON: | |
3e202345 PU |
645 | if (!dac33->substream) |
646 | dac33_soft_power(codec, 1); | |
c8bf93f0 PU |
647 | break; |
648 | case SND_SOC_BIAS_PREPARE: | |
649 | break; | |
650 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 651 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
ad05c03b | 652 | /* Coming from OFF, switch on the codec */ |
3a7aaed7 IK |
653 | ret = dac33_hard_power(codec, 1); |
654 | if (ret != 0) | |
655 | return ret; | |
3a7aaed7 | 656 | |
ad05c03b PU |
657 | dac33_init_chip(codec); |
658 | } | |
c8bf93f0 PU |
659 | break; |
660 | case SND_SOC_BIAS_OFF: | |
2d4cdd6f | 661 | /* Do not power off, when the codec is already off */ |
ce6120cc | 662 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
2d4cdd6f | 663 | return 0; |
3a7aaed7 IK |
664 | ret = dac33_hard_power(codec, 0); |
665 | if (ret != 0) | |
666 | return ret; | |
c8bf93f0 PU |
667 | break; |
668 | } | |
ce6120cc | 669 | codec->dapm.bias_level = level; |
c8bf93f0 PU |
670 | |
671 | return 0; | |
672 | } | |
673 | ||
d4f102d4 PU |
674 | static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) |
675 | { | |
f0fba2ad | 676 | struct snd_soc_codec *codec = dac33->codec; |
84eae18c | 677 | unsigned int delay; |
d4f102d4 PU |
678 | |
679 | switch (dac33->fifo_mode) { | |
680 | case DAC33_FIFO_MODE1: | |
681 | dac33_write16(codec, DAC33_NSAMPLE_MSB, | |
f430a27f | 682 | DAC33_THRREG(dac33->nsample)); |
f57d2cfa PU |
683 | |
684 | /* Take the timestamps */ | |
685 | spin_lock_irq(&dac33->lock); | |
686 | dac33->t_stamp2 = ktime_to_us(ktime_get()); | |
687 | dac33->t_stamp1 = dac33->t_stamp2; | |
688 | spin_unlock_irq(&dac33->lock); | |
689 | ||
d4f102d4 PU |
690 | dac33_write16(codec, DAC33_PREFILL_MSB, |
691 | DAC33_THRREG(dac33->alarm_threshold)); | |
f4d59328 | 692 | /* Enable Alarm Threshold IRQ with a delay */ |
84eae18c PU |
693 | delay = SAMPLES_TO_US(dac33->burst_rate, |
694 | dac33->alarm_threshold) + 1000; | |
695 | usleep_range(delay, delay + 500); | |
f4d59328 | 696 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); |
d4f102d4 | 697 | break; |
28e05d98 | 698 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
699 | /* Take the timestamp */ |
700 | spin_lock_irq(&dac33->lock); | |
701 | dac33->t_stamp1 = ktime_to_us(ktime_get()); | |
702 | /* Move back the timestamp with drain time */ | |
703 | dac33->t_stamp1 -= dac33->mode7_us_to_lthr; | |
704 | spin_unlock_irq(&dac33->lock); | |
705 | ||
28e05d98 | 706 | dac33_write16(codec, DAC33_PREFILL_MSB, |
4260393e | 707 | DAC33_THRREG(MODE7_LTHR)); |
f57d2cfa PU |
708 | |
709 | /* Enable Upper Threshold IRQ */ | |
710 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); | |
28e05d98 | 711 | break; |
d4f102d4 PU |
712 | default: |
713 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
714 | dac33->fifo_mode); | |
715 | break; | |
716 | } | |
717 | } | |
718 | ||
719 | static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) | |
720 | { | |
f0fba2ad | 721 | struct snd_soc_codec *codec = dac33->codec; |
d4f102d4 PU |
722 | |
723 | switch (dac33->fifo_mode) { | |
724 | case DAC33_FIFO_MODE1: | |
f57d2cfa PU |
725 | /* Take the timestamp */ |
726 | spin_lock_irq(&dac33->lock); | |
727 | dac33->t_stamp2 = ktime_to_us(ktime_get()); | |
728 | spin_unlock_irq(&dac33->lock); | |
729 | ||
d4f102d4 PU |
730 | dac33_write16(codec, DAC33_NSAMPLE_MSB, |
731 | DAC33_THRREG(dac33->nsample)); | |
732 | break; | |
28e05d98 PU |
733 | case DAC33_FIFO_MODE7: |
734 | /* At the moment we are not using interrupts in mode7 */ | |
735 | break; | |
d4f102d4 PU |
736 | default: |
737 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
738 | dac33->fifo_mode); | |
739 | break; | |
740 | } | |
741 | } | |
742 | ||
c8bf93f0 PU |
743 | static void dac33_work(struct work_struct *work) |
744 | { | |
745 | struct snd_soc_codec *codec; | |
746 | struct tlv320dac33_priv *dac33; | |
747 | u8 reg; | |
748 | ||
749 | dac33 = container_of(work, struct tlv320dac33_priv, work); | |
f0fba2ad | 750 | codec = dac33->codec; |
c8bf93f0 PU |
751 | |
752 | mutex_lock(&dac33->mutex); | |
753 | switch (dac33->state) { | |
754 | case DAC33_PREFILL: | |
755 | dac33->state = DAC33_PLAYBACK; | |
d4f102d4 | 756 | dac33_prefill_handler(dac33); |
c8bf93f0 PU |
757 | break; |
758 | case DAC33_PLAYBACK: | |
d4f102d4 | 759 | dac33_playback_handler(dac33); |
c8bf93f0 PU |
760 | break; |
761 | case DAC33_IDLE: | |
762 | break; | |
763 | case DAC33_FLUSH: | |
764 | dac33->state = DAC33_IDLE; | |
765 | /* Mask all interrupts from dac33 */ | |
766 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); | |
767 | ||
768 | /* flush fifo */ | |
769 | reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); | |
770 | reg |= DAC33_FIFOFLUSH; | |
771 | dac33_write(codec, DAC33_FIFO_CTRL_A, reg); | |
772 | break; | |
773 | } | |
774 | mutex_unlock(&dac33->mutex); | |
775 | } | |
776 | ||
777 | static irqreturn_t dac33_interrupt_handler(int irq, void *dev) | |
778 | { | |
779 | struct snd_soc_codec *codec = dev; | |
b2c812e2 | 780 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 781 | |
f57d2cfa PU |
782 | spin_lock(&dac33->lock); |
783 | dac33->t_stamp1 = ktime_to_us(ktime_get()); | |
784 | spin_unlock(&dac33->lock); | |
c8bf93f0 | 785 | |
f57d2cfa PU |
786 | /* Do not schedule the workqueue in Mode7 */ |
787 | if (dac33->fifo_mode != DAC33_FIFO_MODE7) | |
788 | queue_work(dac33->dac33_wq, &dac33->work); | |
c8bf93f0 | 789 | |
c8bf93f0 | 790 | return IRQ_HANDLED; |
c8bf93f0 PU |
791 | } |
792 | ||
793 | static void dac33_oscwait(struct snd_soc_codec *codec) | |
794 | { | |
84eae18c | 795 | int timeout = 60; |
c8bf93f0 PU |
796 | u8 reg; |
797 | ||
798 | do { | |
84eae18c | 799 | usleep_range(1000, 2000); |
c8bf93f0 PU |
800 | dac33_read(codec, DAC33_INT_OSC_STATUS, ®); |
801 | } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); | |
802 | if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) | |
803 | dev_err(codec->dev, | |
804 | "internal oscillator calibration failed\n"); | |
805 | } | |
806 | ||
0b61d2b9 PU |
807 | static int dac33_startup(struct snd_pcm_substream *substream, |
808 | struct snd_soc_dai *dai) | |
809 | { | |
810 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 811 | struct snd_soc_codec *codec = rtd->codec; |
0b61d2b9 PU |
812 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
813 | ||
814 | /* Stream started, save the substream pointer */ | |
815 | dac33->substream = substream; | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | static void dac33_shutdown(struct snd_pcm_substream *substream, | |
821 | struct snd_soc_dai *dai) | |
822 | { | |
823 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 824 | struct snd_soc_codec *codec = rtd->codec; |
0b61d2b9 PU |
825 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
826 | ||
827 | dac33->substream = NULL; | |
f430a27f PU |
828 | |
829 | /* Reset the nSample restrictions */ | |
830 | dac33->nsample_min = 0; | |
831 | dac33->nsample_max = NSAMPLE_MAX; | |
0b61d2b9 PU |
832 | } |
833 | ||
c8bf93f0 PU |
834 | static int dac33_hw_params(struct snd_pcm_substream *substream, |
835 | struct snd_pcm_hw_params *params, | |
836 | struct snd_soc_dai *dai) | |
837 | { | |
838 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 839 | struct snd_soc_codec *codec = rtd->codec; |
c8bf93f0 PU |
840 | |
841 | /* Check parameters for validity */ | |
842 | switch (params_rate(params)) { | |
843 | case 44100: | |
844 | case 48000: | |
845 | break; | |
846 | default: | |
847 | dev_err(codec->dev, "unsupported rate %d\n", | |
848 | params_rate(params)); | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
852 | switch (params_format(params)) { | |
853 | case SNDRV_PCM_FORMAT_S16_LE: | |
854 | break; | |
855 | default: | |
856 | dev_err(codec->dev, "unsupported format %d\n", | |
857 | params_format(params)); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
864 | #define CALC_OSCSET(rate, refclk) ( \ | |
7833ae0e | 865 | ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) |
c8bf93f0 PU |
866 | #define CALC_RATIOSET(rate, refclk) ( \ |
867 | ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) | |
868 | ||
869 | /* | |
870 | * tlv320dac33 is strict on the sequence of the register writes, if the register | |
871 | * writes happens in different order, than dac33 might end up in unknown state. | |
872 | * Use the known, working sequence of register writes to initialize the dac33. | |
873 | */ | |
874 | static int dac33_prepare_chip(struct snd_pcm_substream *substream) | |
875 | { | |
876 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 877 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 878 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 879 | unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; |
aec242dc | 880 | u8 aictrl_a, aictrl_b, fifoctrl_a; |
c8bf93f0 PU |
881 | |
882 | switch (substream->runtime->rate) { | |
883 | case 44100: | |
884 | case 48000: | |
885 | oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); | |
886 | ratioset = CALC_RATIOSET(substream->runtime->rate, | |
887 | dac33->refclk); | |
888 | break; | |
889 | default: | |
890 | dev_err(codec->dev, "unsupported rate %d\n", | |
891 | substream->runtime->rate); | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
895 | ||
896 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
897 | aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); | |
e5e878c1 | 898 | /* Read FIFO control A, and clear FIFO flush bit */ |
c8bf93f0 | 899 | fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); |
e5e878c1 PU |
900 | fifoctrl_a &= ~DAC33_FIFOFLUSH; |
901 | ||
c8bf93f0 PU |
902 | fifoctrl_a &= ~DAC33_WIDTH; |
903 | switch (substream->runtime->format) { | |
904 | case SNDRV_PCM_FORMAT_S16_LE: | |
905 | aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); | |
906 | fifoctrl_a |= DAC33_WIDTH; | |
907 | break; | |
908 | default: | |
909 | dev_err(codec->dev, "unsupported format %d\n", | |
910 | substream->runtime->format); | |
911 | return -EINVAL; | |
912 | } | |
913 | ||
914 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
915 | |
916 | if (!dac33->chip_power) { | |
917 | /* | |
918 | * Chip is not powered yet. | |
919 | * Do the init in the dac33_set_bias_level later. | |
920 | */ | |
921 | mutex_unlock(&dac33->mutex); | |
922 | return 0; | |
923 | } | |
924 | ||
c3746a07 | 925 | dac33_soft_power(codec, 0); |
c8bf93f0 PU |
926 | dac33_soft_power(codec, 1); |
927 | ||
928 | reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
929 | dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); | |
930 | ||
931 | /* Write registers 0x08 and 0x09 (MSB, LSB) */ | |
932 | dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); | |
933 | ||
934 | /* calib time: 128 is a nice number ;) */ | |
935 | dac33_write(codec, DAC33_CALIB_TIME, 128); | |
936 | ||
937 | /* adjustment treshold & step */ | |
938 | dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | | |
939 | DAC33_ADJSTEP(1)); | |
940 | ||
941 | /* div=4 / gain=1 / div */ | |
942 | dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); | |
943 | ||
944 | pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
945 | pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; | |
946 | dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); | |
947 | ||
948 | dac33_oscwait(codec); | |
949 | ||
7427b4b9 | 950 | if (dac33->fifo_mode) { |
aec242dc | 951 | /* Generic for all FIFO modes */ |
c8bf93f0 | 952 | /* 50-51 : ASRC Control registers */ |
fdb6b1e1 | 953 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); |
c8bf93f0 PU |
954 | dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ |
955 | ||
956 | /* Write registers 0x34 and 0x35 (MSB, LSB) */ | |
957 | dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); | |
958 | ||
959 | /* Set interrupts to high active */ | |
960 | dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); | |
c8bf93f0 | 961 | } else { |
aec242dc | 962 | /* FIFO bypass mode */ |
c8bf93f0 PU |
963 | /* 50-51 : ASRC Control registers */ |
964 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); | |
965 | dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ | |
966 | } | |
967 | ||
aec242dc PU |
968 | /* Interrupt behaviour configuration */ |
969 | switch (dac33->fifo_mode) { | |
970 | case DAC33_FIFO_MODE1: | |
971 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, | |
972 | DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
aec242dc | 973 | break; |
28e05d98 | 974 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
975 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, |
976 | DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
28e05d98 | 977 | break; |
aec242dc PU |
978 | default: |
979 | /* in FIFO bypass mode, the interrupts are not used */ | |
980 | break; | |
981 | } | |
982 | ||
983 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
984 | ||
985 | switch (dac33->fifo_mode) { | |
986 | case DAC33_FIFO_MODE1: | |
987 | /* | |
988 | * For mode1: | |
989 | * Disable the FIFO bypass (Enable the use of FIFO) | |
990 | * Select nSample mode | |
991 | * BCLK is only running when data is needed by DAC33 | |
992 | */ | |
c8bf93f0 | 993 | fifoctrl_a &= ~DAC33_FBYPAS; |
aec242dc | 994 | fifoctrl_a &= ~DAC33_FAUTO; |
eeb309a8 PU |
995 | if (dac33->keep_bclk) |
996 | aictrl_b |= DAC33_BCLKON; | |
997 | else | |
998 | aictrl_b &= ~DAC33_BCLKON; | |
aec242dc | 999 | break; |
28e05d98 PU |
1000 | case DAC33_FIFO_MODE7: |
1001 | /* | |
1002 | * For mode1: | |
1003 | * Disable the FIFO bypass (Enable the use of FIFO) | |
1004 | * Select Threshold mode | |
1005 | * BCLK is only running when data is needed by DAC33 | |
1006 | */ | |
1007 | fifoctrl_a &= ~DAC33_FBYPAS; | |
1008 | fifoctrl_a |= DAC33_FAUTO; | |
eeb309a8 PU |
1009 | if (dac33->keep_bclk) |
1010 | aictrl_b |= DAC33_BCLKON; | |
1011 | else | |
1012 | aictrl_b &= ~DAC33_BCLKON; | |
28e05d98 | 1013 | break; |
aec242dc PU |
1014 | default: |
1015 | /* | |
1016 | * For FIFO bypass mode: | |
1017 | * Enable the FIFO bypass (Disable the FIFO use) | |
1018 | * Set the BCLK as continous | |
1019 | */ | |
c8bf93f0 | 1020 | fifoctrl_a |= DAC33_FBYPAS; |
aec242dc PU |
1021 | aictrl_b |= DAC33_BCLKON; |
1022 | break; | |
1023 | } | |
c8bf93f0 | 1024 | |
aec242dc | 1025 | dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); |
c8bf93f0 | 1026 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); |
aec242dc | 1027 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); |
c8bf93f0 | 1028 | |
6aceabb4 PU |
1029 | /* |
1030 | * BCLK divide ratio | |
1031 | * 0: 1.5 | |
1032 | * 1: 1 | |
1033 | * 2: 2 | |
1034 | * ... | |
1035 | * 254: 254 | |
1036 | * 255: 255 | |
1037 | */ | |
6cd6cede | 1038 | if (dac33->fifo_mode) |
6aceabb4 PU |
1039 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, |
1040 | dac33->burst_bclkdiv); | |
6cd6cede PU |
1041 | else |
1042 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); | |
c8bf93f0 | 1043 | |
6cd6cede PU |
1044 | switch (dac33->fifo_mode) { |
1045 | case DAC33_FIFO_MODE1: | |
c8bf93f0 PU |
1046 | dac33_write16(codec, DAC33_ATHR_MSB, |
1047 | DAC33_THRREG(dac33->alarm_threshold)); | |
aec242dc | 1048 | break; |
28e05d98 PU |
1049 | case DAC33_FIFO_MODE7: |
1050 | /* | |
1051 | * Configure the threshold levels, and leave 10 sample space | |
1052 | * at the bottom, and also at the top of the FIFO | |
1053 | */ | |
9d7db2b2 | 1054 | dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); |
4260393e | 1055 | dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR)); |
28e05d98 | 1056 | break; |
aec242dc | 1057 | default: |
aec242dc | 1058 | break; |
c8bf93f0 PU |
1059 | } |
1060 | ||
1061 | mutex_unlock(&dac33->mutex); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static void dac33_calculate_times(struct snd_pcm_substream *substream) | |
1067 | { | |
1068 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1069 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 1070 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
f430a27f PU |
1071 | unsigned int period_size = substream->runtime->period_size; |
1072 | unsigned int rate = substream->runtime->rate; | |
c8bf93f0 PU |
1073 | unsigned int nsample_limit; |
1074 | ||
55abb59c PU |
1075 | /* In bypass mode we don't need to calculate */ |
1076 | if (!dac33->fifo_mode) | |
1077 | return; | |
1078 | ||
f57d2cfa PU |
1079 | switch (dac33->fifo_mode) { |
1080 | case DAC33_FIFO_MODE1: | |
f430a27f PU |
1081 | /* Number of samples under i2c latency */ |
1082 | dac33->alarm_threshold = US_TO_SAMPLES(rate, | |
1083 | dac33->mode1_latency); | |
1bc13b2e PU |
1084 | nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - |
1085 | dac33->alarm_threshold; | |
1086 | ||
a577b318 PU |
1087 | if (dac33->auto_fifo_config) { |
1088 | if (period_size <= dac33->alarm_threshold) | |
1089 | /* | |
1090 | * Configure nSamaple to number of periods, | |
1091 | * which covers the latency requironment. | |
1092 | */ | |
1093 | dac33->nsample = period_size * | |
1094 | ((dac33->alarm_threshold / period_size) + | |
1095 | (dac33->alarm_threshold % period_size ? | |
1096 | 1 : 0)); | |
1bc13b2e PU |
1097 | else if (period_size > nsample_limit) |
1098 | dac33->nsample = nsample_limit; | |
a577b318 PU |
1099 | else |
1100 | dac33->nsample = period_size; | |
1101 | } else { | |
1102 | /* nSample time shall not be shorter than i2c latency */ | |
1103 | dac33->nsample_min = dac33->alarm_threshold; | |
1104 | /* | |
1105 | * nSample should not be bigger than alsa buffer minus | |
1106 | * size of one period to avoid overruns | |
1107 | */ | |
1108 | dac33->nsample_max = substream->runtime->buffer_size - | |
1109 | period_size; | |
1bc13b2e | 1110 | |
a577b318 PU |
1111 | if (dac33->nsample_max > nsample_limit) |
1112 | dac33->nsample_max = nsample_limit; | |
1113 | ||
1114 | /* Correct the nSample if it is outside of the ranges */ | |
1115 | if (dac33->nsample < dac33->nsample_min) | |
1116 | dac33->nsample = dac33->nsample_min; | |
1117 | if (dac33->nsample > dac33->nsample_max) | |
1118 | dac33->nsample = dac33->nsample_max; | |
1119 | } | |
f430a27f | 1120 | |
f57d2cfa PU |
1121 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, |
1122 | dac33->nsample); | |
1123 | dac33->t_stamp1 = 0; | |
1124 | dac33->t_stamp2 = 0; | |
1125 | break; | |
1126 | case DAC33_FIFO_MODE7: | |
a577b318 PU |
1127 | if (dac33->auto_fifo_config) { |
1128 | dac33->uthr = UTHR_FROM_PERIOD_SIZE( | |
1129 | period_size, | |
1130 | rate, | |
1131 | dac33->burst_rate) + 9; | |
1132 | if (dac33->uthr > MODE7_UTHR) | |
1133 | dac33->uthr = MODE7_UTHR; | |
1134 | if (dac33->uthr < (MODE7_LTHR + 10)) | |
1135 | dac33->uthr = (MODE7_LTHR + 10); | |
1136 | } | |
f57d2cfa | 1137 | dac33->mode7_us_to_lthr = |
9d7db2b2 PU |
1138 | SAMPLES_TO_US(substream->runtime->rate, |
1139 | dac33->uthr - MODE7_LTHR + 1); | |
f57d2cfa PU |
1140 | dac33->t_stamp1 = 0; |
1141 | break; | |
1142 | default: | |
1143 | break; | |
1144 | } | |
c8bf93f0 | 1145 | |
c8bf93f0 PU |
1146 | } |
1147 | ||
1148 | static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, | |
1149 | struct snd_soc_dai *dai) | |
1150 | { | |
1151 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1152 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 1153 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1154 | int ret = 0; |
1155 | ||
1156 | switch (cmd) { | |
1157 | case SNDRV_PCM_TRIGGER_START: | |
1158 | case SNDRV_PCM_TRIGGER_RESUME: | |
1159 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
7427b4b9 | 1160 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1161 | dac33->state = DAC33_PREFILL; |
1162 | queue_work(dac33->dac33_wq, &dac33->work); | |
1163 | } | |
1164 | break; | |
1165 | case SNDRV_PCM_TRIGGER_STOP: | |
1166 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1167 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
7427b4b9 | 1168 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1169 | dac33->state = DAC33_FLUSH; |
1170 | queue_work(dac33->dac33_wq, &dac33->work); | |
1171 | } | |
1172 | break; | |
1173 | default: | |
1174 | ret = -EINVAL; | |
1175 | } | |
1176 | ||
1177 | return ret; | |
1178 | } | |
1179 | ||
f57d2cfa PU |
1180 | static snd_pcm_sframes_t dac33_dai_delay( |
1181 | struct snd_pcm_substream *substream, | |
1182 | struct snd_soc_dai *dai) | |
1183 | { | |
1184 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1185 | struct snd_soc_codec *codec = rtd->codec; |
f57d2cfa PU |
1186 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
1187 | unsigned long long t0, t1, t_now; | |
9d7db2b2 | 1188 | unsigned int time_delta, uthr; |
f57d2cfa PU |
1189 | int samples_out, samples_in, samples; |
1190 | snd_pcm_sframes_t delay = 0; | |
1191 | ||
1192 | switch (dac33->fifo_mode) { | |
1193 | case DAC33_FIFO_BYPASS: | |
1194 | break; | |
1195 | case DAC33_FIFO_MODE1: | |
1196 | spin_lock(&dac33->lock); | |
1197 | t0 = dac33->t_stamp1; | |
1198 | t1 = dac33->t_stamp2; | |
1199 | spin_unlock(&dac33->lock); | |
1200 | t_now = ktime_to_us(ktime_get()); | |
1201 | ||
1202 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1203 | if (!t1) | |
1204 | goto out; | |
1205 | ||
1206 | if (t0 > t1) { | |
1207 | /* | |
1208 | * Phase 1: | |
1209 | * After Alarm threshold, and before nSample write | |
1210 | */ | |
1211 | time_delta = t_now - t0; | |
1212 | samples_out = time_delta ? US_TO_SAMPLES( | |
1213 | substream->runtime->rate, | |
1214 | time_delta) : 0; | |
1215 | ||
1216 | if (likely(dac33->alarm_threshold > samples_out)) | |
1217 | delay = dac33->alarm_threshold - samples_out; | |
1218 | else | |
1219 | delay = 0; | |
1220 | } else if ((t_now - t1) <= dac33->mode1_us_burst) { | |
1221 | /* | |
1222 | * Phase 2: | |
1223 | * After nSample write (during burst operation) | |
1224 | */ | |
1225 | time_delta = t_now - t0; | |
1226 | samples_out = time_delta ? US_TO_SAMPLES( | |
1227 | substream->runtime->rate, | |
1228 | time_delta) : 0; | |
1229 | ||
1230 | time_delta = t_now - t1; | |
1231 | samples_in = time_delta ? US_TO_SAMPLES( | |
1232 | dac33->burst_rate, | |
1233 | time_delta) : 0; | |
1234 | ||
1235 | samples = dac33->alarm_threshold; | |
1236 | samples += (samples_in - samples_out); | |
1237 | ||
1238 | if (likely(samples > 0)) | |
1239 | delay = samples; | |
1240 | else | |
1241 | delay = 0; | |
1242 | } else { | |
1243 | /* | |
1244 | * Phase 3: | |
1245 | * After burst operation, before next alarm threshold | |
1246 | */ | |
1247 | time_delta = t_now - t0; | |
1248 | samples_out = time_delta ? US_TO_SAMPLES( | |
1249 | substream->runtime->rate, | |
1250 | time_delta) : 0; | |
1251 | ||
1252 | samples_in = dac33->nsample; | |
1253 | samples = dac33->alarm_threshold; | |
1254 | samples += (samples_in - samples_out); | |
1255 | ||
1256 | if (likely(samples > 0)) | |
1257 | delay = samples > DAC33_BUFFER_SIZE_SAMPLES ? | |
1258 | DAC33_BUFFER_SIZE_SAMPLES : samples; | |
1259 | else | |
1260 | delay = 0; | |
1261 | } | |
1262 | break; | |
1263 | case DAC33_FIFO_MODE7: | |
1264 | spin_lock(&dac33->lock); | |
1265 | t0 = dac33->t_stamp1; | |
9d7db2b2 | 1266 | uthr = dac33->uthr; |
f57d2cfa PU |
1267 | spin_unlock(&dac33->lock); |
1268 | t_now = ktime_to_us(ktime_get()); | |
1269 | ||
1270 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1271 | if (!t0) | |
1272 | goto out; | |
1273 | ||
1274 | if (t_now <= t0) { | |
1275 | /* | |
1276 | * Either the timestamps are messed or equal. Report | |
1277 | * maximum delay | |
1278 | */ | |
9d7db2b2 | 1279 | delay = uthr; |
f57d2cfa PU |
1280 | goto out; |
1281 | } | |
1282 | ||
1283 | time_delta = t_now - t0; | |
1284 | if (time_delta <= dac33->mode7_us_to_lthr) { | |
1285 | /* | |
1286 | * Phase 1: | |
1287 | * After burst (draining phase) | |
1288 | */ | |
1289 | samples_out = US_TO_SAMPLES( | |
1290 | substream->runtime->rate, | |
1291 | time_delta); | |
1292 | ||
9d7db2b2 PU |
1293 | if (likely(uthr > samples_out)) |
1294 | delay = uthr - samples_out; | |
f57d2cfa PU |
1295 | else |
1296 | delay = 0; | |
1297 | } else { | |
1298 | /* | |
1299 | * Phase 2: | |
1300 | * During burst operation | |
1301 | */ | |
1302 | time_delta = time_delta - dac33->mode7_us_to_lthr; | |
1303 | ||
1304 | samples_out = US_TO_SAMPLES( | |
1305 | substream->runtime->rate, | |
1306 | time_delta); | |
1307 | samples_in = US_TO_SAMPLES( | |
1308 | dac33->burst_rate, | |
1309 | time_delta); | |
1310 | delay = MODE7_LTHR + samples_in - samples_out; | |
1311 | ||
9d7db2b2 PU |
1312 | if (unlikely(delay > uthr)) |
1313 | delay = uthr; | |
f57d2cfa PU |
1314 | } |
1315 | break; | |
1316 | default: | |
1317 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
1318 | dac33->fifo_mode); | |
1319 | break; | |
1320 | } | |
1321 | out: | |
1322 | return delay; | |
1323 | } | |
1324 | ||
c8bf93f0 PU |
1325 | static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1326 | int clk_id, unsigned int freq, int dir) | |
1327 | { | |
1328 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1329 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1330 | u8 ioc_reg, asrcb_reg; |
1331 | ||
1332 | ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
1333 | asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); | |
1334 | switch (clk_id) { | |
1335 | case TLV320DAC33_MCLK: | |
1336 | ioc_reg |= DAC33_REFSEL; | |
1337 | asrcb_reg |= DAC33_SRCREFSEL; | |
1338 | break; | |
1339 | case TLV320DAC33_SLEEPCLK: | |
1340 | ioc_reg &= ~DAC33_REFSEL; | |
1341 | asrcb_reg &= ~DAC33_SRCREFSEL; | |
1342 | break; | |
1343 | default: | |
1344 | dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); | |
1345 | break; | |
1346 | } | |
1347 | dac33->refclk = freq; | |
1348 | ||
1349 | dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); | |
1350 | dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1356 | unsigned int fmt) | |
1357 | { | |
1358 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1359 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1360 | u8 aictrl_a, aictrl_b; |
1361 | ||
1362 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
1363 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
1364 | /* set master/slave audio interface */ | |
1365 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1366 | case SND_SOC_DAIFMT_CBM_CFM: | |
1367 | /* Codec Master */ | |
1368 | aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); | |
1369 | break; | |
1370 | case SND_SOC_DAIFMT_CBS_CFS: | |
1371 | /* Codec Slave */ | |
adcb8bc0 PU |
1372 | if (dac33->fifo_mode) { |
1373 | dev_err(codec->dev, "FIFO mode requires master mode\n"); | |
1374 | return -EINVAL; | |
1375 | } else | |
1376 | aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); | |
c8bf93f0 PU |
1377 | break; |
1378 | default: | |
1379 | return -EINVAL; | |
1380 | } | |
1381 | ||
1382 | aictrl_a &= ~DAC33_AFMT_MASK; | |
1383 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1384 | case SND_SOC_DAIFMT_I2S: | |
1385 | aictrl_a |= DAC33_AFMT_I2S; | |
1386 | break; | |
1387 | case SND_SOC_DAIFMT_DSP_A: | |
1388 | aictrl_a |= DAC33_AFMT_DSP; | |
1389 | aictrl_b &= ~DAC33_DATA_DELAY_MASK; | |
44f497b4 | 1390 | aictrl_b |= DAC33_DATA_DELAY(0); |
c8bf93f0 PU |
1391 | break; |
1392 | case SND_SOC_DAIFMT_RIGHT_J: | |
1393 | aictrl_a |= DAC33_AFMT_RIGHT_J; | |
1394 | break; | |
1395 | case SND_SOC_DAIFMT_LEFT_J: | |
1396 | aictrl_a |= DAC33_AFMT_LEFT_J; | |
1397 | break; | |
1398 | default: | |
1399 | dev_err(codec->dev, "Unsupported format (%u)\n", | |
1400 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
1404 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); | |
1405 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
f0fba2ad | 1410 | static int dac33_soc_probe(struct snd_soc_codec *codec) |
c8bf93f0 | 1411 | { |
f0fba2ad | 1412 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1413 | int ret = 0; |
1414 | ||
f0fba2ad LG |
1415 | codec->control_data = dac33->control_data; |
1416 | codec->hw_write = (hw_write_t) i2c_master_send; | |
ce6120cc | 1417 | codec->dapm.idle_bias_off = 1; |
f0fba2ad | 1418 | dac33->codec = codec; |
c8bf93f0 | 1419 | |
f0fba2ad LG |
1420 | /* Read the tlv320dac33 ID registers */ |
1421 | ret = dac33_hard_power(codec, 1); | |
1422 | if (ret != 0) { | |
1423 | dev_err(codec->dev, "Failed to power up codec: %d\n", ret); | |
1424 | goto err_power; | |
1425 | } | |
911a0f0b | 1426 | ret = dac33_read_id(codec); |
f0fba2ad | 1427 | dac33_hard_power(codec, 0); |
c8bf93f0 | 1428 | |
911a0f0b PU |
1429 | if (ret < 0) { |
1430 | dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); | |
1431 | ret = -ENODEV; | |
1432 | goto err_power; | |
1433 | } | |
1434 | ||
f0fba2ad LG |
1435 | /* Check if the IRQ number is valid and request it */ |
1436 | if (dac33->irq >= 0) { | |
1437 | ret = request_irq(dac33->irq, dac33_interrupt_handler, | |
1438 | IRQF_TRIGGER_RISING | IRQF_DISABLED, | |
1439 | codec->name, codec); | |
1440 | if (ret < 0) { | |
1441 | dev_err(codec->dev, "Could not request IRQ%d (%d)\n", | |
1442 | dac33->irq, ret); | |
1443 | dac33->irq = -1; | |
1444 | } | |
1445 | if (dac33->irq != -1) { | |
1446 | /* Setup work queue */ | |
1447 | dac33->dac33_wq = | |
1448 | create_singlethread_workqueue("tlv320dac33"); | |
1449 | if (dac33->dac33_wq == NULL) { | |
1450 | free_irq(dac33->irq, codec); | |
1451 | return -ENOMEM; | |
1452 | } | |
1453 | ||
1454 | INIT_WORK(&dac33->work, dac33_work); | |
1455 | } | |
c8bf93f0 PU |
1456 | } |
1457 | ||
1458 | snd_soc_add_controls(codec, dac33_snd_controls, | |
1459 | ARRAY_SIZE(dac33_snd_controls)); | |
a577b318 PU |
1460 | /* Only add the FIFO controls, if we have valid IRQ number */ |
1461 | if (dac33->irq >= 0) { | |
1462 | snd_soc_add_controls(codec, dac33_mode_snd_controls, | |
1463 | ARRAY_SIZE(dac33_mode_snd_controls)); | |
1464 | /* FIFO usage controls only, if autoio config is not selected */ | |
1465 | if (!dac33->auto_fifo_config) | |
1466 | snd_soc_add_controls(codec, dac33_fifo_snd_controls, | |
1467 | ARRAY_SIZE(dac33_fifo_snd_controls)); | |
1468 | } | |
c8bf93f0 PU |
1469 | dac33_add_widgets(codec); |
1470 | ||
f0fba2ad | 1471 | err_power: |
c8bf93f0 PU |
1472 | return ret; |
1473 | } | |
1474 | ||
f0fba2ad | 1475 | static int dac33_soc_remove(struct snd_soc_codec *codec) |
c8bf93f0 | 1476 | { |
f0fba2ad | 1477 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1478 | |
1479 | dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1480 | ||
f0fba2ad LG |
1481 | if (dac33->irq >= 0) { |
1482 | free_irq(dac33->irq, dac33->codec); | |
1483 | destroy_workqueue(dac33->dac33_wq); | |
1484 | } | |
c8bf93f0 PU |
1485 | return 0; |
1486 | } | |
1487 | ||
f0fba2ad | 1488 | static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state) |
c8bf93f0 | 1489 | { |
c8bf93f0 PU |
1490 | dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
f0fba2ad | 1495 | static int dac33_soc_resume(struct snd_soc_codec *codec) |
c8bf93f0 | 1496 | { |
c8bf93f0 | 1497 | dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
c8bf93f0 PU |
1498 | |
1499 | return 0; | |
1500 | } | |
1501 | ||
f0fba2ad LG |
1502 | static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { |
1503 | .read = dac33_read_reg_cache, | |
1504 | .write = dac33_write_locked, | |
1505 | .set_bias_level = dac33_set_bias_level, | |
1506 | .reg_cache_size = ARRAY_SIZE(dac33_reg), | |
1507 | .reg_word_size = sizeof(u8), | |
1508 | .reg_cache_default = dac33_reg, | |
c8bf93f0 PU |
1509 | .probe = dac33_soc_probe, |
1510 | .remove = dac33_soc_remove, | |
1511 | .suspend = dac33_soc_suspend, | |
1512 | .resume = dac33_soc_resume, | |
1513 | }; | |
c8bf93f0 PU |
1514 | |
1515 | #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ | |
1516 | SNDRV_PCM_RATE_48000) | |
1517 | #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
1518 | ||
1519 | static struct snd_soc_dai_ops dac33_dai_ops = { | |
0b61d2b9 | 1520 | .startup = dac33_startup, |
c8bf93f0 PU |
1521 | .shutdown = dac33_shutdown, |
1522 | .hw_params = dac33_hw_params, | |
c8bf93f0 | 1523 | .trigger = dac33_pcm_trigger, |
f57d2cfa | 1524 | .delay = dac33_dai_delay, |
c8bf93f0 PU |
1525 | .set_sysclk = dac33_set_dai_sysclk, |
1526 | .set_fmt = dac33_set_dai_fmt, | |
1527 | }; | |
1528 | ||
f0fba2ad LG |
1529 | static struct snd_soc_dai_driver dac33_dai = { |
1530 | .name = "tlv320dac33-hifi", | |
c8bf93f0 PU |
1531 | .playback = { |
1532 | .stream_name = "Playback", | |
1533 | .channels_min = 2, | |
1534 | .channels_max = 2, | |
1535 | .rates = DAC33_RATES, | |
1536 | .formats = DAC33_FORMATS,}, | |
1537 | .ops = &dac33_dai_ops, | |
1538 | }; | |
c8bf93f0 | 1539 | |
735fe4cf MB |
1540 | static int __devinit dac33_i2c_probe(struct i2c_client *client, |
1541 | const struct i2c_device_id *id) | |
c8bf93f0 PU |
1542 | { |
1543 | struct tlv320dac33_platform_data *pdata; | |
1544 | struct tlv320dac33_priv *dac33; | |
3a7aaed7 | 1545 | int ret, i; |
c8bf93f0 PU |
1546 | |
1547 | if (client->dev.platform_data == NULL) { | |
1548 | dev_err(&client->dev, "Platform data not set\n"); | |
1549 | return -ENODEV; | |
1550 | } | |
1551 | pdata = client->dev.platform_data; | |
1552 | ||
1553 | dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL); | |
1554 | if (dac33 == NULL) | |
1555 | return -ENOMEM; | |
1556 | ||
f0fba2ad | 1557 | dac33->control_data = client; |
c8bf93f0 | 1558 | mutex_init(&dac33->mutex); |
f57d2cfa | 1559 | spin_lock_init(&dac33->lock); |
c8bf93f0 PU |
1560 | |
1561 | i2c_set_clientdata(client, dac33); | |
1562 | ||
1563 | dac33->power_gpio = pdata->power_gpio; | |
6aceabb4 | 1564 | dac33->burst_bclkdiv = pdata->burst_bclkdiv; |
76f47127 PU |
1565 | /* Pre calculate the burst rate */ |
1566 | dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32; | |
eeb309a8 | 1567 | dac33->keep_bclk = pdata->keep_bclk; |
a577b318 | 1568 | dac33->auto_fifo_config = pdata->auto_fifo_config; |
f430a27f PU |
1569 | dac33->mode1_latency = pdata->mode1_latency; |
1570 | if (!dac33->mode1_latency) | |
1571 | dac33->mode1_latency = 10000; /* 10ms */ | |
c8bf93f0 PU |
1572 | dac33->irq = client->irq; |
1573 | dac33->nsample = NSAMPLE_MAX; | |
55abb59c | 1574 | dac33->nsample_max = NSAMPLE_MAX; |
9d7db2b2 | 1575 | dac33->uthr = MODE7_UTHR; |
c8bf93f0 | 1576 | /* Disable FIFO use by default */ |
7427b4b9 | 1577 | dac33->fifo_mode = DAC33_FIFO_BYPASS; |
c8bf93f0 | 1578 | |
c8bf93f0 PU |
1579 | /* Check if the reset GPIO number is valid and request it */ |
1580 | if (dac33->power_gpio >= 0) { | |
1581 | ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); | |
1582 | if (ret < 0) { | |
f0fba2ad | 1583 | dev_err(&client->dev, |
c8bf93f0 PU |
1584 | "Failed to request reset GPIO (%d)\n", |
1585 | dac33->power_gpio); | |
f0fba2ad | 1586 | goto err_gpio; |
c8bf93f0 PU |
1587 | } |
1588 | gpio_direction_output(dac33->power_gpio, 0); | |
c8bf93f0 PU |
1589 | } |
1590 | ||
3a7aaed7 IK |
1591 | for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) |
1592 | dac33->supplies[i].supply = dac33_supply_names[i]; | |
1593 | ||
f0fba2ad | 1594 | ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), |
3a7aaed7 IK |
1595 | dac33->supplies); |
1596 | ||
1597 | if (ret != 0) { | |
f0fba2ad | 1598 | dev_err(&client->dev, "Failed to request supplies: %d\n", ret); |
3a7aaed7 IK |
1599 | goto err_get; |
1600 | } | |
1601 | ||
f0fba2ad LG |
1602 | ret = snd_soc_register_codec(&client->dev, |
1603 | &soc_codec_dev_tlv320dac33, &dac33_dai, 1); | |
1604 | if (ret < 0) | |
1605 | goto err_register; | |
c8bf93f0 | 1606 | |
c8bf93f0 | 1607 | return ret; |
f0fba2ad | 1608 | err_register: |
3a7aaed7 IK |
1609 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1610 | err_get: | |
c8bf93f0 PU |
1611 | if (dac33->power_gpio >= 0) |
1612 | gpio_free(dac33->power_gpio); | |
f0fba2ad | 1613 | err_gpio: |
c8bf93f0 | 1614 | kfree(dac33); |
c8bf93f0 PU |
1615 | return ret; |
1616 | } | |
1617 | ||
735fe4cf | 1618 | static int __devexit dac33_i2c_remove(struct i2c_client *client) |
c8bf93f0 | 1619 | { |
f0fba2ad | 1620 | struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); |
239fe55c PU |
1621 | |
1622 | if (unlikely(dac33->chip_power)) | |
f0fba2ad | 1623 | dac33_hard_power(dac33->codec, 0); |
c8bf93f0 PU |
1624 | |
1625 | if (dac33->power_gpio >= 0) | |
1626 | gpio_free(dac33->power_gpio); | |
c8bf93f0 | 1627 | |
3a7aaed7 IK |
1628 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1629 | ||
f0fba2ad | 1630 | snd_soc_unregister_codec(&client->dev); |
c8bf93f0 | 1631 | kfree(dac33); |
c8bf93f0 PU |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static const struct i2c_device_id tlv320dac33_i2c_id[] = { | |
1637 | { | |
1638 | .name = "tlv320dac33", | |
1639 | .driver_data = 0, | |
1640 | }, | |
1641 | { }, | |
1642 | }; | |
1643 | ||
1644 | static struct i2c_driver tlv320dac33_i2c_driver = { | |
1645 | .driver = { | |
f0fba2ad | 1646 | .name = "tlv320dac33-codec", |
c8bf93f0 PU |
1647 | .owner = THIS_MODULE, |
1648 | }, | |
1649 | .probe = dac33_i2c_probe, | |
1650 | .remove = __devexit_p(dac33_i2c_remove), | |
1651 | .id_table = tlv320dac33_i2c_id, | |
1652 | }; | |
1653 | ||
1654 | static int __init dac33_module_init(void) | |
1655 | { | |
1656 | int r; | |
1657 | r = i2c_add_driver(&tlv320dac33_i2c_driver); | |
1658 | if (r < 0) { | |
1659 | printk(KERN_ERR "DAC33: driver registration failed\n"); | |
1660 | return r; | |
1661 | } | |
1662 | return 0; | |
1663 | } | |
1664 | module_init(dac33_module_init); | |
1665 | ||
1666 | static void __exit dac33_module_exit(void) | |
1667 | { | |
1668 | i2c_del_driver(&tlv320dac33_i2c_driver); | |
1669 | } | |
1670 | module_exit(dac33_module_exit); | |
1671 | ||
1672 | ||
1673 | MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); | |
1674 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>"); | |
1675 | MODULE_LICENSE("GPL"); |