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ASoC: tlv320dac33: Fix inconsistent spinlock usage
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
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c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
c8bf93f0
PU		 39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
549675ed
PU		 45/*
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
50 */
51#define DAC33_FIFO_SIZE_16BIT 6144
52#define DAC33_FIFO_SIZE_24BIT 4096
53#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
4260393e 54
76f47127
PU		 55#define BURST_BASEFREQ_HZ 49152000
56
f57d2cfa
PU		 57#define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60#define US_TO_SAMPLES(rate, us) \
d54e1f4f 61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
f57d2cfa 62
a577b318
PU		 63#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65
ad05c03b
PU		 66static void dac33_calculate_times(struct snd_pcm_substream *substream);
67static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 68
c8bf93f0
PU		 69enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74};
75
7427b4b9
PU		 76enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
28e05d98 79 DAC33_FIFO_MODE7,
7427b4b9
PU		 80 DAC33_FIFO_LAST_MODE,
81};
82
3a7aaed7
IK		 83#define DAC33_NUM_SUPPLIES 3
84static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88};
89
c8bf93f0
PU		 90struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
f0fba2ad 94 struct snd_soc_codec *codec;
3a7aaed7 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 96 struct snd_pcm_substream *substream;
c8bf93f0
PU		 97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
7427b4b9 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
549675ed 104 unsigned int fifo_size; /* Size of the FIFO in samples */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 106 int mode1_latency; /* latency caused by the i2c writes in
107 * us */
6aceabb4 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 109 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 110
eeb309a8
PU		 111 int keep_bclk; /* Keep the BCLK continuously running
112 * in FIFO modes */
f57d2cfa
PU		 113 spinlock_t lock;
114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
116
117 unsigned int mode1_us_burst; /* Time to burst read n number of
118 * samples */
119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 120
9d7db2b2
PU		 121 unsigned int uthr;
122
c8bf93f0 123 enum dac33_state state;
f0fba2ad
LG		 124 enum snd_soc_control_type control_type;
125 void *control_data;
c8bf93f0
PU		 126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 198 int val, ret = 0;
c8bf93f0
PU		 199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 208 ret = val;
c8bf93f0
PU		 209 } else {
210 value[0] = val;
211 dac33_write_reg_cache(codec, reg, val);
212 }
213 } else {
214 value[0] = dac33_read_reg_cache(codec, reg);
215 }
216
911a0f0b 217 return ret;
c8bf93f0
PU		 218}
219
220static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
221 unsigned int value)
222{
b2c812e2 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 224 u8 data[2];
225 int ret = 0;
226
227 /*
228 * data is
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
231 */
232 data[0] = reg & 0xff;
233 data[1] = value & 0xff;
234
235 dac33_write_reg_cache(codec, data[0], data[1]);
236 if (dac33->chip_power) {
237 ret = codec->hw_write(codec->control_data, data, 2);
238 if (ret != 2)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245}
246
247static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
248 unsigned int value)
249{
b2c812e2 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 251 int ret;
252
253 mutex_lock(&dac33->mutex);
254 ret = dac33_write(codec, reg, value);
255 mutex_unlock(&dac33->mutex);
256
257 return ret;
258}
259
260#define DAC33_I2C_ADDR_AUTOINC 0x80
261static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
262 unsigned int value)
263{
b2c812e2 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 265 u8 data[3];
266 int ret = 0;
267
268 /*
269 * data is
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
273 */
274 data[0] = reg & 0xff;
275 data[1] = (value >> 8) & 0xff;
276 data[2] = value & 0xff;
277
278 dac33_write_reg_cache(codec, data[0], data[1]);
279 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
280
281 if (dac33->chip_power) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data[0] |= DAC33_I2C_ADDR_AUTOINC;
284 ret = codec->hw_write(codec->control_data, data, 3);
285 if (ret != 3)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 else
288 ret = 0;
289 }
290
291 return ret;
292}
293
ef909d67 294static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 295{
b2c812e2 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 297
ef909d67 298 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 299 return;
300
ef909d67
PU		 301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
ef909d67
PU		 309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
ef909d67
PU		 313 /* Restore only selected registers (gains mostly) */
314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
318
319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
399b82e4
PU		 323
324 dac33_write(codec, DAC33_OUT_AMP_CTRL,
325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
326
c8bf93f0
PU		 327}
328
911a0f0b 329static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 330{
911a0f0b 331 int i, ret = 0;
239fe55c
PU		 332 u8 reg;
333
911a0f0b
PU		 334 for (i = 0; i < 3; i++) {
335 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
336 if (ret < 0)
337 break;
338 }
339
340 return ret;
c8bf93f0
PU		 341}
342
343static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
344{
345 u8 reg;
346
347 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
348 if (power)
349 reg |= DAC33_PDNALLB;
350 else
c3746a07
PU		 351 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
352 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 353 dac33_write(codec, DAC33_PWR_CTRL, reg);
354}
355
a6cea965
PU		 356static inline void dac33_disable_digital(struct snd_soc_codec *codec)
357{
358 u8 reg;
359
360 /* Stop the DAI clock */
361 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
362 reg &= ~DAC33_BCLKON;
363 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
364
365 /* Power down the Oscillator, and DACs */
366 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
367 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
368 dac33_write(codec, DAC33_PWR_CTRL, reg);
369}
370
3a7aaed7 371static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 372{
b2c812e2 373 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 374 int ret = 0;
c8bf93f0
PU		 375
376 mutex_lock(&dac33->mutex);
ad05c03b
PU		 377
378 /* Safety check */
379 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 380 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 381 power ? "ON" : "OFF");
382 goto exit;
383 }
384
c8bf93f0 385 if (power) {
3a7aaed7
IK		 386 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
387 dac33->supplies);
388 if (ret != 0) {
389 dev_err(codec->dev,
390 "Failed to enable supplies: %d\n", ret);
391 goto exit;
c8bf93f0 392 }
3a7aaed7
IK		 393
394 if (dac33->power_gpio >= 0)
395 gpio_set_value(dac33->power_gpio, 1);
396
397 dac33->chip_power = 1;
c8bf93f0
PU		 398 } else {
399 dac33_soft_power(codec, 0);
3a7aaed7 400 if (dac33->power_gpio >= 0)
c8bf93f0 401 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 402
403 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
404 dac33->supplies);
405 if (ret != 0) {
406 dev_err(codec->dev,
407 "Failed to disable supplies: %d\n", ret);
408 goto exit;
c8bf93f0 409 }
3a7aaed7
IK		 410
411 dac33->chip_power = 0;
c8bf93f0 412 }
c8bf93f0 413
3a7aaed7
IK		 414exit:
415 mutex_unlock(&dac33->mutex);
416 return ret;
c8bf93f0
PU		 417}
418
a6cea965 419static int dac33_playback_event(struct snd_soc_dapm_widget *w,
ad05c03b
PU		 420 struct snd_kcontrol *kcontrol, int event)
421{
422 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
423
424 switch (event) {
425 case SND_SOC_DAPM_PRE_PMU:
426 if (likely(dac33->substream)) {
427 dac33_calculate_times(dac33->substream);
428 dac33_prepare_chip(dac33->substream);
429 }
430 break;
a6cea965
PU		 431 case SND_SOC_DAPM_POST_PMD:
432 dac33_disable_digital(w->codec);
433 break;
ad05c03b
PU		 434 }
435 return 0;
436}
437
7427b4b9 438static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 439 struct snd_ctl_elem_value *ucontrol)
440{
441 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 442 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 443
7427b4b9 444 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 445
446 return 0;
447}
448
7427b4b9 449static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 450 struct snd_ctl_elem_value *ucontrol)
451{
452 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 453 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 454 int ret = 0;
455
7427b4b9 456 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 457 return 0;
458 /* Do not allow changes while stream is running*/
459 if (codec->active)
460 return -EPERM;
461
462 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 463 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 464 ret = -EINVAL;
465 else
7427b4b9 466 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 467
468 return ret;
469}
470
7427b4b9
PU		 471/* Codec operation modes */
472static const char *dac33_fifo_mode_texts[] = {
28e05d98 473 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 474};
475
476static const struct soc_enum dac33_fifo_mode_enum =
477 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
478 dac33_fifo_mode_texts);
479
cf4bb698
PU		 480/* L/R Line Output Gain */
481static const char *lr_lineout_gain_texts[] = {
482 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
483 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
484};
485
486static const struct soc_enum l_lineout_gain_enum =
487 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
488 ARRAY_SIZE(lr_lineout_gain_texts),
489 lr_lineout_gain_texts);
490
491static const struct soc_enum r_lineout_gain_enum =
492 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
493 ARRAY_SIZE(lr_lineout_gain_texts),
494 lr_lineout_gain_texts);
495
c8bf93f0
PU		 496/*
497 * DACL/R digital volume control:
498 * from 0 dB to -63.5 in 0.5 dB steps
499 * Need to be inverted later on:
500 * 0x00 == 0 dB
501 * 0x7f == -63.5 dB
502 */
503static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
504
505static const struct snd_kcontrol_new dac33_snd_controls[] = {
506 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
507 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
508 0, 0x7f, 1, dac_digivol_tlv),
509 SOC_DOUBLE_R("DAC Digital Playback Switch",
510 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
511 SOC_DOUBLE_R("Line to Line Out Volume",
512 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 513 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
514 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 515};
516
a577b318
PU		 517static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
518 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
519 dac33_get_fifo_mode, dac33_set_fifo_mode),
520};
521
c8bf93f0
PU		 522/* Analog bypass */
523static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
524 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
525
526static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
527 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
528
399b82e4
PU		 529/* LOP L/R invert selection */
530static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
531
532static const struct soc_enum dac33_left_lom_enum =
533 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
534 ARRAY_SIZE(dac33_lr_lom_texts),
535 dac33_lr_lom_texts);
536
537static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
538SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
539
540static const struct soc_enum dac33_right_lom_enum =
541 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
542 ARRAY_SIZE(dac33_lr_lom_texts),
543 dac33_lr_lom_texts);
544
545static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
546SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
547
c8bf93f0
PU		 548static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
549 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
550 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
551
552 SND_SOC_DAPM_INPUT("LINEL"),
553 SND_SOC_DAPM_INPUT("LINER"),
554
76eac39c
PU		 555 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
556 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 557
558 /* Analog bypass */
559 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
560 &dac33_dapm_abypassl_control),
561 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
562 &dac33_dapm_abypassr_control),
563
399b82e4
PU		 564 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
565 &dac33_dapm_left_lom_control),
566 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
567 &dac33_dapm_right_lom_control),
568 /*
569 * For DAPM path, when only the anlog bypass path is enabled, and the
570 * LOP inverted from the corresponding DAC side.
571 * This is needed, so we can attach the DAC power supply in this case.
572 */
573 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
574 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
575
9e87186f 576 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 577 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 578 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 579 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 580
76eac39c
PU		 581 SND_SOC_DAPM_SUPPLY("Left DAC Power",
582 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
583 SND_SOC_DAPM_SUPPLY("Right DAC Power",
584 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
585
a6cea965
PU		 586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
c8bf93f0
PU		 588};
589
590static const struct snd_soc_dapm_route audio_map[] = {
591 /* Analog bypass */
592 {"Analog Left Bypass", "Switch", "LINEL"},
593 {"Analog Right Bypass", "Switch", "LINER"},
594
9e87186f
PU		 595 {"Output Left Amplifier", NULL, "DACL"},
596 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 597
399b82e4
PU		 598 {"Left Bypass PGA", NULL, "Analog Left Bypass"},
599 {"Right Bypass PGA", NULL, "Analog Right Bypass"},
600
601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
605
606 {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
607 {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
608
609 {"DACL", NULL, "Left DAC Power"},
610 {"DACR", NULL, "Right DAC Power"},
c8bf93f0 611
399b82e4
PU		 612 {"Left Bypass PGA", NULL, "Left DAC Power"},
613 {"Right Bypass PGA", NULL, "Right DAC Power"},
76eac39c 614
c8bf93f0 615 /* output */
9e87186f
PU		 616 {"LEFT_LO", NULL, "Output Left Amplifier"},
617 {"RIGHT_LO", NULL, "Output Right Amplifier"},
c8bf93f0
PU		 618};
619
620static int dac33_add_widgets(struct snd_soc_codec *codec)
621{
ce6120cc 622 struct snd_soc_dapm_context *dapm = &codec->dapm;
c8bf93f0 623
ce6120cc
LG		 624 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
625 ARRAY_SIZE(dac33_dapm_widgets));
c8bf93f0 626 /* set up audio path interconnects */
ce6120cc 627 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 628
629 return 0;
630}
631
632static int dac33_set_bias_level(struct snd_soc_codec *codec,
633 enum snd_soc_bias_level level)
634{
3ee4fe15 635 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7
IK		 636 int ret;
637
c8bf93f0
PU		 638 switch (level) {
639 case SND_SOC_BIAS_ON:
3e202345
PU		 640 if (!dac33->substream)
641 dac33_soft_power(codec, 1);
c8bf93f0
PU		 642 break;
643 case SND_SOC_BIAS_PREPARE:
644 break;
645 case SND_SOC_BIAS_STANDBY:
ce6120cc 646 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 647 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 648 ret = dac33_hard_power(codec, 1);
649 if (ret != 0)
650 return ret;
3a7aaed7 651
ad05c03b
PU		 652 dac33_init_chip(codec);
653 }
c8bf93f0
PU		 654 break;
655 case SND_SOC_BIAS_OFF:
2d4cdd6f 656 /* Do not power off, when the codec is already off */
ce6120cc 657 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2d4cdd6f 658 return 0;
3a7aaed7
IK		 659 ret = dac33_hard_power(codec, 0);
660 if (ret != 0)
661 return ret;
c8bf93f0
PU		 662 break;
663 }
ce6120cc 664 codec->dapm.bias_level = level;
c8bf93f0
PU		 665
666 return 0;
667}
668
d4f102d4
PU		 669static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
670{
f0fba2ad 671 struct snd_soc_codec *codec = dac33->codec;
84eae18c 672 unsigned int delay;
a3b55791 673 unsigned long flags;
d4f102d4
PU		 674
675 switch (dac33->fifo_mode) {
676 case DAC33_FIFO_MODE1:
677 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 678 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 679
680 /* Take the timestamps */
a3b55791 681 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 682 dac33->t_stamp2 = ktime_to_us(ktime_get());
683 dac33->t_stamp1 = dac33->t_stamp2;
a3b55791 684 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 685
d4f102d4
PU		 686 dac33_write16(codec, DAC33_PREFILL_MSB,
687 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 688 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 689 delay = SAMPLES_TO_US(dac33->burst_rate,
690 dac33->alarm_threshold) + 1000;
691 usleep_range(delay, delay + 500);
f4d59328 692 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 693 break;
28e05d98 694 case DAC33_FIFO_MODE7:
f57d2cfa 695 /* Take the timestamp */
a3b55791 696 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 697 dac33->t_stamp1 = ktime_to_us(ktime_get());
698 /* Move back the timestamp with drain time */
699 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
a3b55791 700 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 701
28e05d98 702 dac33_write16(codec, DAC33_PREFILL_MSB,
549675ed 703 DAC33_THRREG(DAC33_MODE7_MARGIN));
f57d2cfa
PU		 704
705 /* Enable Upper Threshold IRQ */
706 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 707 break;
d4f102d4
PU		 708 default:
709 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
710 dac33->fifo_mode);
711 break;
712 }
713}
714
715static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
716{
f0fba2ad 717 struct snd_soc_codec *codec = dac33->codec;
a3b55791 718 unsigned long flags;
d4f102d4
PU		 719
720 switch (dac33->fifo_mode) {
721 case DAC33_FIFO_MODE1:
f57d2cfa 722 /* Take the timestamp */
a3b55791 723 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 724 dac33->t_stamp2 = ktime_to_us(ktime_get());
a3b55791 725 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 726
d4f102d4
PU		 727 dac33_write16(codec, DAC33_NSAMPLE_MSB,
728 DAC33_THRREG(dac33->nsample));
729 break;
28e05d98
PU		 730 case DAC33_FIFO_MODE7:
731 /* At the moment we are not using interrupts in mode7 */
732 break;
d4f102d4
PU		 733 default:
734 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
735 dac33->fifo_mode);
736 break;
737 }
738}
739
c8bf93f0
PU		 740static void dac33_work(struct work_struct *work)
741{
742 struct snd_soc_codec *codec;
743 struct tlv320dac33_priv *dac33;
744 u8 reg;
745
746 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 747 codec = dac33->codec;
c8bf93f0
PU		 748
749 mutex_lock(&dac33->mutex);
750 switch (dac33->state) {
751 case DAC33_PREFILL:
752 dac33->state = DAC33_PLAYBACK;
d4f102d4 753 dac33_prefill_handler(dac33);
c8bf93f0
PU		 754 break;
755 case DAC33_PLAYBACK:
d4f102d4 756 dac33_playback_handler(dac33);
c8bf93f0
PU		 757 break;
758 case DAC33_IDLE:
759 break;
760 case DAC33_FLUSH:
761 dac33->state = DAC33_IDLE;
762 /* Mask all interrupts from dac33 */
763 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
764
765 /* flush fifo */
766 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
767 reg |= DAC33_FIFOFLUSH;
768 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
769 break;
770 }
771 mutex_unlock(&dac33->mutex);
772}
773
774static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
775{
776 struct snd_soc_codec *codec = dev;
b2c812e2 777 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
a3b55791 778 unsigned long flags;
c8bf93f0 779
a3b55791 780 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 781 dac33->t_stamp1 = ktime_to_us(ktime_get());
a3b55791 782 spin_unlock_irqrestore(&dac33->lock, flags);
c8bf93f0 783
f57d2cfa
PU		 784 /* Do not schedule the workqueue in Mode7 */
785 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
786 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 787
c8bf93f0 788 return IRQ_HANDLED;
c8bf93f0
PU		 789}
790
791static void dac33_oscwait(struct snd_soc_codec *codec)
792{
84eae18c 793 int timeout = 60;
c8bf93f0
PU		 794 u8 reg;
795
796 do {
84eae18c 797 usleep_range(1000, 2000);
c8bf93f0
PU		 798 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
799 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
800 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
801 dev_err(codec->dev,
802 "internal oscillator calibration failed\n");
803}
804
0b61d2b9
PU		 805static int dac33_startup(struct snd_pcm_substream *substream,
806 struct snd_soc_dai *dai)
807{
808 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 809 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 810 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
811
812 /* Stream started, save the substream pointer */
813 dac33->substream = substream;
814
0d99d2b0
PU		 815 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
816
0b61d2b9
PU		 817 return 0;
818}
819
820static void dac33_shutdown(struct snd_pcm_substream *substream,
821 struct snd_soc_dai *dai)
822{
823 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 824 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 825 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
826
827 dac33->substream = NULL;
828}
829
549675ed
PU		 830#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
831 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
c8bf93f0
PU		 832static int dac33_hw_params(struct snd_pcm_substream *substream,
833 struct snd_pcm_hw_params *params,
834 struct snd_soc_dai *dai)
835{
836 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 837 struct snd_soc_codec *codec = rtd->codec;
549675ed 838 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 839
840 /* Check parameters for validity */
841 switch (params_rate(params)) {
842 case 44100:
843 case 48000:
844 break;
845 default:
846 dev_err(codec->dev, "unsupported rate %d\n",
847 params_rate(params));
848 return -EINVAL;
849 }
850
851 switch (params_format(params)) {
852 case SNDRV_PCM_FORMAT_S16_LE:
549675ed
PU		 853 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
854 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
c8bf93f0 855 break;
0d99d2b0
PU		 856 case SNDRV_PCM_FORMAT_S32_LE:
857 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
858 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
859 break;
c8bf93f0
PU		 860 default:
861 dev_err(codec->dev, "unsupported format %d\n",
862 params_format(params));
863 return -EINVAL;
864 }
865
866 return 0;
867}
868
869#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 870 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 871#define CALC_RATIOSET(rate, refclk) ( \
872 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
873
874/*
875 * tlv320dac33 is strict on the sequence of the register writes, if the register
876 * writes happens in different order, than dac33 might end up in unknown state.
877 * Use the known, working sequence of register writes to initialize the dac33.
878 */
879static int dac33_prepare_chip(struct snd_pcm_substream *substream)
880{
881 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 882 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 883 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 884 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 885 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 886
887 switch (substream->runtime->rate) {
888 case 44100:
889 case 48000:
890 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
891 ratioset = CALC_RATIOSET(substream->runtime->rate,
892 dac33->refclk);
893 break;
894 default:
895 dev_err(codec->dev, "unsupported rate %d\n",
896 substream->runtime->rate);
897 return -EINVAL;
898 }
899
900
901 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
902 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 903 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 904 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 905 fifoctrl_a &= ~DAC33_FIFOFLUSH;
906
c8bf93f0
PU		 907 fifoctrl_a &= ~DAC33_WIDTH;
908 switch (substream->runtime->format) {
909 case SNDRV_PCM_FORMAT_S16_LE:
910 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
911 fifoctrl_a |= DAC33_WIDTH;
912 break;
0d99d2b0
PU		 913 case SNDRV_PCM_FORMAT_S32_LE:
914 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
915 break;
c8bf93f0
PU		 916 default:
917 dev_err(codec->dev, "unsupported format %d\n",
918 substream->runtime->format);
919 return -EINVAL;
920 }
921
922 mutex_lock(&dac33->mutex);
ad05c03b
PU		 923
924 if (!dac33->chip_power) {
925 /*
926 * Chip is not powered yet.
927 * Do the init in the dac33_set_bias_level later.
928 */
929 mutex_unlock(&dac33->mutex);
930 return 0;
931 }
932
c3746a07 933 dac33_soft_power(codec, 0);
c8bf93f0
PU		 934 dac33_soft_power(codec, 1);
935
936 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
937 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
938
939 /* Write registers 0x08 and 0x09 (MSB, LSB) */
940 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
941
942 /* calib time: 128 is a nice number ;) */
943 dac33_write(codec, DAC33_CALIB_TIME, 128);
944
945 /* adjustment treshold & step */
946 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
947 DAC33_ADJSTEP(1));
948
949 /* div=4 / gain=1 / div */
950 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
951
952 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
953 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
954 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
955
956 dac33_oscwait(codec);
957
7427b4b9 958 if (dac33->fifo_mode) {
aec242dc 959 /* Generic for all FIFO modes */
c8bf93f0 960 /* 50-51 : ASRC Control registers */
fdb6b1e1 961 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 962 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
963
964 /* Write registers 0x34 and 0x35 (MSB, LSB) */
965 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
966
967 /* Set interrupts to high active */
968 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 969 } else {
aec242dc 970 /* FIFO bypass mode */
c8bf93f0
PU		 971 /* 50-51 : ASRC Control registers */
972 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
973 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
974 }
975
aec242dc
PU		 976 /* Interrupt behaviour configuration */
977 switch (dac33->fifo_mode) {
978 case DAC33_FIFO_MODE1:
979 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
980 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 981 break;
28e05d98 982 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 983 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
984 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 985 break;
aec242dc
PU		 986 default:
987 /* in FIFO bypass mode, the interrupts are not used */
988 break;
989 }
990
991 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
992
993 switch (dac33->fifo_mode) {
994 case DAC33_FIFO_MODE1:
995 /*
996 * For mode1:
997 * Disable the FIFO bypass (Enable the use of FIFO)
998 * Select nSample mode
999 * BCLK is only running when data is needed by DAC33
1000 */
c8bf93f0 1001 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 1002 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 1003 if (dac33->keep_bclk)
1004 aictrl_b |= DAC33_BCLKON;
1005 else
1006 aictrl_b &= ~DAC33_BCLKON;
aec242dc 1007 break;
28e05d98
PU		 1008 case DAC33_FIFO_MODE7:
1009 /*
1010 * For mode1:
1011 * Disable the FIFO bypass (Enable the use of FIFO)
1012 * Select Threshold mode
1013 * BCLK is only running when data is needed by DAC33
1014 */
1015 fifoctrl_a &= ~DAC33_FBYPAS;
1016 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 1017 if (dac33->keep_bclk)
1018 aictrl_b |= DAC33_BCLKON;
1019 else
1020 aictrl_b &= ~DAC33_BCLKON;
28e05d98 1021 break;
aec242dc
PU		 1022 default:
1023 /*
1024 * For FIFO bypass mode:
1025 * Enable the FIFO bypass (Disable the FIFO use)
1026 * Set the BCLK as continous
1027 */
c8bf93f0 1028 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 1029 aictrl_b |= DAC33_BCLKON;
1030 break;
1031 }
c8bf93f0 1032
aec242dc 1033 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 1034 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 1035 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 1036
6aceabb4
PU		 1037 /*
1038 * BCLK divide ratio
1039 * 0: 1.5
1040 * 1: 1
1041 * 2: 2
1042 * ...
1043 * 254: 254
1044 * 255: 255
1045 */
6cd6cede 1046 if (dac33->fifo_mode)
6aceabb4
PU		 1047 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1048 dac33->burst_bclkdiv);
6cd6cede 1049 else
0d99d2b0
PU		 1050 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1051 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1052 else
1053 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
c8bf93f0 1054
6cd6cede
PU		 1055 switch (dac33->fifo_mode) {
1056 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1057 dac33_write16(codec, DAC33_ATHR_MSB,
1058 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1059 break;
28e05d98
PU		 1060 case DAC33_FIFO_MODE7:
1061 /*
1062 * Configure the threshold levels, and leave 10 sample space
1063 * at the bottom, and also at the top of the FIFO
1064 */
9d7db2b2 1065 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
549675ed
PU		 1066 dac33_write16(codec, DAC33_LTHR_MSB,
1067 DAC33_THRREG(DAC33_MODE7_MARGIN));
28e05d98 1068 break;
aec242dc 1069 default:
aec242dc 1070 break;
c8bf93f0
PU		 1071 }
1072
1073 mutex_unlock(&dac33->mutex);
1074
1075 return 0;
1076}
1077
1078static void dac33_calculate_times(struct snd_pcm_substream *substream)
1079{
1080 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1081 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1082 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1083 unsigned int period_size = substream->runtime->period_size;
1084 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1085 unsigned int nsample_limit;
1086
55abb59c
PU		 1087 /* In bypass mode we don't need to calculate */
1088 if (!dac33->fifo_mode)
1089 return;
1090
f57d2cfa
PU		 1091 switch (dac33->fifo_mode) {
1092 case DAC33_FIFO_MODE1:
f430a27f
PU		 1093 /* Number of samples under i2c latency */
1094 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1095 dac33->mode1_latency);
549675ed 1096 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1bc13b2e 1097
3591f4cd 1098 if (period_size <= dac33->alarm_threshold)
a577b318 1099 /*
3591f4cd
PU		 1100 * Configure nSamaple to number of periods,
1101 * which covers the latency requironment.
a577b318 1102 */
3591f4cd
PU		 1103 dac33->nsample = period_size *
1104 ((dac33->alarm_threshold / period_size) +
1105 (dac33->alarm_threshold % period_size ?
1106 1 : 0));
1107 else if (period_size > nsample_limit)
1108 dac33->nsample = nsample_limit;
1109 else
1110 dac33->nsample = period_size;
f430a27f 1111
f57d2cfa
PU		 1112 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1113 dac33->nsample);
1114 dac33->t_stamp1 = 0;
1115 dac33->t_stamp2 = 0;
1116 break;
1117 case DAC33_FIFO_MODE7:
3591f4cd
PU		 1118 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1119 dac33->burst_rate) + 9;
549675ed
PU		 1120 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1121 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1122 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1123 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
3591f4cd 1124
f57d2cfa 1125 dac33->mode7_us_to_lthr =
9d7db2b2 1126 SAMPLES_TO_US(substream->runtime->rate,
549675ed 1127 dac33->uthr - DAC33_MODE7_MARGIN + 1);
f57d2cfa
PU		 1128 dac33->t_stamp1 = 0;
1129 break;
1130 default:
1131 break;
1132 }
c8bf93f0 1133
c8bf93f0
PU		 1134}
1135
1136static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1137 struct snd_soc_dai *dai)
1138{
1139 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1140 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1141 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1142 int ret = 0;
1143
1144 switch (cmd) {
1145 case SNDRV_PCM_TRIGGER_START:
1146 case SNDRV_PCM_TRIGGER_RESUME:
1147 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1148 if (dac33->fifo_mode) {
c8bf93f0
PU		 1149 dac33->state = DAC33_PREFILL;
1150 queue_work(dac33->dac33_wq, &dac33->work);
1151 }
1152 break;
1153 case SNDRV_PCM_TRIGGER_STOP:
1154 case SNDRV_PCM_TRIGGER_SUSPEND:
1155 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1156 if (dac33->fifo_mode) {
c8bf93f0
PU		 1157 dac33->state = DAC33_FLUSH;
1158 queue_work(dac33->dac33_wq, &dac33->work);
1159 }
1160 break;
1161 default:
1162 ret = -EINVAL;
1163 }
1164
1165 return ret;
1166}
1167
f57d2cfa
PU		 1168static snd_pcm_sframes_t dac33_dai_delay(
1169 struct snd_pcm_substream *substream,
1170 struct snd_soc_dai *dai)
1171{
1172 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1173 struct snd_soc_codec *codec = rtd->codec;
f57d2cfa
PU		 1174 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1175 unsigned long long t0, t1, t_now;
9d7db2b2 1176 unsigned int time_delta, uthr;
f57d2cfa
PU		 1177 int samples_out, samples_in, samples;
1178 snd_pcm_sframes_t delay = 0;
a3b55791 1179 unsigned long flags;
f57d2cfa
PU		 1180
1181 switch (dac33->fifo_mode) {
1182 case DAC33_FIFO_BYPASS:
1183 break;
1184 case DAC33_FIFO_MODE1:
a3b55791 1185 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 1186 t0 = dac33->t_stamp1;
1187 t1 = dac33->t_stamp2;
a3b55791 1188 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1189 t_now = ktime_to_us(ktime_get());
1190
1191 /* We have not started to fill the FIFO yet, delay is 0 */
1192 if (!t1)
1193 goto out;
1194
1195 if (t0 > t1) {
1196 /*
1197 * Phase 1:
1198 * After Alarm threshold, and before nSample write
1199 */
1200 time_delta = t_now - t0;
1201 samples_out = time_delta ? US_TO_SAMPLES(
1202 substream->runtime->rate,
1203 time_delta) : 0;
1204
1205 if (likely(dac33->alarm_threshold > samples_out))
1206 delay = dac33->alarm_threshold - samples_out;
1207 else
1208 delay = 0;
1209 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1210 /*
1211 * Phase 2:
1212 * After nSample write (during burst operation)
1213 */
1214 time_delta = t_now - t0;
1215 samples_out = time_delta ? US_TO_SAMPLES(
1216 substream->runtime->rate,
1217 time_delta) : 0;
1218
1219 time_delta = t_now - t1;
1220 samples_in = time_delta ? US_TO_SAMPLES(
1221 dac33->burst_rate,
1222 time_delta) : 0;
1223
1224 samples = dac33->alarm_threshold;
1225 samples += (samples_in - samples_out);
1226
1227 if (likely(samples > 0))
1228 delay = samples;
1229 else
1230 delay = 0;
1231 } else {
1232 /*
1233 * Phase 3:
1234 * After burst operation, before next alarm threshold
1235 */
1236 time_delta = t_now - t0;
1237 samples_out = time_delta ? US_TO_SAMPLES(
1238 substream->runtime->rate,
1239 time_delta) : 0;
1240
1241 samples_in = dac33->nsample;
1242 samples = dac33->alarm_threshold;
1243 samples += (samples_in - samples_out);
1244
1245 if (likely(samples > 0))
549675ed
PU		 1246 delay = samples > dac33->fifo_size ?
1247 dac33->fifo_size : samples;
f57d2cfa
PU		 1248 else
1249 delay = 0;
1250 }
1251 break;
1252 case DAC33_FIFO_MODE7:
a3b55791 1253 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 1254 t0 = dac33->t_stamp1;
9d7db2b2 1255 uthr = dac33->uthr;
a3b55791 1256 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1257 t_now = ktime_to_us(ktime_get());
1258
1259 /* We have not started to fill the FIFO yet, delay is 0 */
1260 if (!t0)
1261 goto out;
1262
1263 if (t_now <= t0) {
1264 /*
1265 * Either the timestamps are messed or equal. Report
1266 * maximum delay
1267 */
9d7db2b2 1268 delay = uthr;
f57d2cfa
PU		 1269 goto out;
1270 }
1271
1272 time_delta = t_now - t0;
1273 if (time_delta <= dac33->mode7_us_to_lthr) {
1274 /*
1275 * Phase 1:
1276 * After burst (draining phase)
1277 */
1278 samples_out = US_TO_SAMPLES(
1279 substream->runtime->rate,
1280 time_delta);
1281
9d7db2b2
PU		 1282 if (likely(uthr > samples_out))
1283 delay = uthr - samples_out;
f57d2cfa
PU		 1284 else
1285 delay = 0;
1286 } else {
1287 /*
1288 * Phase 2:
1289 * During burst operation
1290 */
1291 time_delta = time_delta - dac33->mode7_us_to_lthr;
1292
1293 samples_out = US_TO_SAMPLES(
1294 substream->runtime->rate,
1295 time_delta);
1296 samples_in = US_TO_SAMPLES(
1297 dac33->burst_rate,
1298 time_delta);
549675ed 1299 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
f57d2cfa 1300
9d7db2b2
PU		 1301 if (unlikely(delay > uthr))
1302 delay = uthr;
f57d2cfa
PU		 1303 }
1304 break;
1305 default:
1306 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1307 dac33->fifo_mode);
1308 break;
1309 }
1310out:
1311 return delay;
1312}
1313
c8bf93f0
PU		 1314static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1315 int clk_id, unsigned int freq, int dir)
1316{
1317 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1318 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1319 u8 ioc_reg, asrcb_reg;
1320
1321 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1322 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1323 switch (clk_id) {
1324 case TLV320DAC33_MCLK:
1325 ioc_reg |= DAC33_REFSEL;
1326 asrcb_reg |= DAC33_SRCREFSEL;
1327 break;
1328 case TLV320DAC33_SLEEPCLK:
1329 ioc_reg &= ~DAC33_REFSEL;
1330 asrcb_reg &= ~DAC33_SRCREFSEL;
1331 break;
1332 default:
1333 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1334 break;
1335 }
1336 dac33->refclk = freq;
1337
1338 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1339 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1340
1341 return 0;
1342}
1343
1344static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1345 unsigned int fmt)
1346{
1347 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1348 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1349 u8 aictrl_a, aictrl_b;
1350
1351 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1352 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1353 /* set master/slave audio interface */
1354 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1355 case SND_SOC_DAIFMT_CBM_CFM:
1356 /* Codec Master */
1357 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1358 break;
1359 case SND_SOC_DAIFMT_CBS_CFS:
1360 /* Codec Slave */
adcb8bc0
PU		 1361 if (dac33->fifo_mode) {
1362 dev_err(codec->dev, "FIFO mode requires master mode\n");
1363 return -EINVAL;
1364 } else
1365 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1366 break;
1367 default:
1368 return -EINVAL;
1369 }
1370
1371 aictrl_a &= ~DAC33_AFMT_MASK;
1372 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1373 case SND_SOC_DAIFMT_I2S:
1374 aictrl_a |= DAC33_AFMT_I2S;
1375 break;
1376 case SND_SOC_DAIFMT_DSP_A:
1377 aictrl_a |= DAC33_AFMT_DSP;
1378 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1379 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1380 break;
1381 case SND_SOC_DAIFMT_RIGHT_J:
1382 aictrl_a |= DAC33_AFMT_RIGHT_J;
1383 break;
1384 case SND_SOC_DAIFMT_LEFT_J:
1385 aictrl_a |= DAC33_AFMT_LEFT_J;
1386 break;
1387 default:
1388 dev_err(codec->dev, "Unsupported format (%u)\n",
1389 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1390 return -EINVAL;
1391 }
1392
1393 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1394 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1395
1396 return 0;
1397}
1398
f0fba2ad 1399static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1400{
f0fba2ad 1401 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1402 int ret = 0;
1403
f0fba2ad
LG		 1404 codec->control_data = dac33->control_data;
1405 codec->hw_write = (hw_write_t) i2c_master_send;
ce6120cc 1406 codec->dapm.idle_bias_off = 1;
f0fba2ad 1407 dac33->codec = codec;
c8bf93f0 1408
f0fba2ad
LG		 1409 /* Read the tlv320dac33 ID registers */
1410 ret = dac33_hard_power(codec, 1);
1411 if (ret != 0) {
1412 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1413 goto err_power;
1414 }
911a0f0b 1415 ret = dac33_read_id(codec);
f0fba2ad 1416 dac33_hard_power(codec, 0);
c8bf93f0 1417
911a0f0b
PU		 1418 if (ret < 0) {
1419 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1420 ret = -ENODEV;
1421 goto err_power;
1422 }
1423
f0fba2ad
LG		 1424 /* Check if the IRQ number is valid and request it */
1425 if (dac33->irq >= 0) {
1426 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1427 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1428 codec->name, codec);
1429 if (ret < 0) {
1430 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1431 dac33->irq, ret);
1432 dac33->irq = -1;
1433 }
1434 if (dac33->irq != -1) {
1435 /* Setup work queue */
1436 dac33->dac33_wq =
1437 create_singlethread_workqueue("tlv320dac33");
1438 if (dac33->dac33_wq == NULL) {
1439 free_irq(dac33->irq, codec);
1440 return -ENOMEM;
1441 }
1442
1443 INIT_WORK(&dac33->work, dac33_work);
1444 }
c8bf93f0
PU		 1445 }
1446
1447 snd_soc_add_controls(codec, dac33_snd_controls,
1448 ARRAY_SIZE(dac33_snd_controls));
a577b318 1449 /* Only add the FIFO controls, if we have valid IRQ number */
3591f4cd 1450 if (dac33->irq >= 0)
a577b318
PU		 1451 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1452 ARRAY_SIZE(dac33_mode_snd_controls));
3591f4cd 1453
c8bf93f0
PU		 1454 dac33_add_widgets(codec);
1455
f0fba2ad 1456err_power:
c8bf93f0
PU		 1457 return ret;
1458}
1459
f0fba2ad 1460static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1461{
f0fba2ad 1462 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1463
1464 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1465
f0fba2ad
LG		 1466 if (dac33->irq >= 0) {
1467 free_irq(dac33->irq, dac33->codec);
1468 destroy_workqueue(dac33->dac33_wq);
1469 }
c8bf93f0
PU		 1470 return 0;
1471}
1472
f0fba2ad 1473static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
c8bf93f0 1474{
c8bf93f0
PU		 1475 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1476
1477 return 0;
1478}
1479
f0fba2ad 1480static int dac33_soc_resume(struct snd_soc_codec *codec)
c8bf93f0 1481{
c8bf93f0 1482 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1483
1484 return 0;
1485}
1486
f0fba2ad
LG		 1487static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1488 .read = dac33_read_reg_cache,
1489 .write = dac33_write_locked,
1490 .set_bias_level = dac33_set_bias_level,
1491 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1492 .reg_word_size = sizeof(u8),
1493 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1494 .probe = dac33_soc_probe,
1495 .remove = dac33_soc_remove,
1496 .suspend = dac33_soc_suspend,
1497 .resume = dac33_soc_resume,
1498};
c8bf93f0
PU		 1499
1500#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1501 SNDRV_PCM_RATE_48000)
0d99d2b0 1502#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
c8bf93f0
PU		 1503
1504static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1505 .startup = dac33_startup,
c8bf93f0
PU		 1506 .shutdown = dac33_shutdown,
1507 .hw_params = dac33_hw_params,
c8bf93f0 1508 .trigger = dac33_pcm_trigger,
f57d2cfa 1509 .delay = dac33_dai_delay,
c8bf93f0
PU		 1510 .set_sysclk = dac33_set_dai_sysclk,
1511 .set_fmt = dac33_set_dai_fmt,
1512};
1513
f0fba2ad
LG		 1514static struct snd_soc_dai_driver dac33_dai = {
1515 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1516 .playback = {
1517 .stream_name = "Playback",
1518 .channels_min = 2,
1519 .channels_max = 2,
1520 .rates = DAC33_RATES,
1521 .formats = DAC33_FORMATS,},
1522 .ops = &dac33_dai_ops,
1523};
c8bf93f0 1524
735fe4cf
MB		 1525static int __devinit dac33_i2c_probe(struct i2c_client *client,
1526 const struct i2c_device_id *id)
c8bf93f0
PU		 1527{
1528 struct tlv320dac33_platform_data *pdata;
1529 struct tlv320dac33_priv *dac33;
3a7aaed7 1530 int ret, i;
c8bf93f0
PU		 1531
1532 if (client->dev.platform_data == NULL) {
1533 dev_err(&client->dev, "Platform data not set\n");
1534 return -ENODEV;
1535 }
1536 pdata = client->dev.platform_data;
1537
1538 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1539 if (dac33 == NULL)
1540 return -ENOMEM;
1541
f0fba2ad 1542 dac33->control_data = client;
c8bf93f0 1543 mutex_init(&dac33->mutex);
f57d2cfa 1544 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1545
1546 i2c_set_clientdata(client, dac33);
1547
1548 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1549 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1550 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1551 dac33->mode1_latency = pdata->mode1_latency;
1552 if (!dac33->mode1_latency)
1553 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0 1554 dac33->irq = client->irq;
c8bf93f0 1555 /* Disable FIFO use by default */
7427b4b9 1556 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1557
c8bf93f0
PU		 1558 /* Check if the reset GPIO number is valid and request it */
1559 if (dac33->power_gpio >= 0) {
1560 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1561 if (ret < 0) {
f0fba2ad 1562 dev_err(&client->dev,
c8bf93f0
PU		 1563 "Failed to request reset GPIO (%d)\n",
1564 dac33->power_gpio);
f0fba2ad 1565 goto err_gpio;
c8bf93f0
PU		 1566 }
1567 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1568 }
1569
3a7aaed7
IK		 1570 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1571 dac33->supplies[i].supply = dac33_supply_names[i];
1572
f0fba2ad 1573 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1574 dac33->supplies);
1575
1576 if (ret != 0) {
f0fba2ad 1577 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1578 goto err_get;
1579 }
1580
f0fba2ad
LG		 1581 ret = snd_soc_register_codec(&client->dev,
1582 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1583 if (ret < 0)
1584 goto err_register;
c8bf93f0 1585
c8bf93f0 1586 return ret;
f0fba2ad 1587err_register:
3a7aaed7
IK		 1588 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1589err_get:
c8bf93f0
PU		 1590 if (dac33->power_gpio >= 0)
1591 gpio_free(dac33->power_gpio);
f0fba2ad 1592err_gpio:
c8bf93f0 1593 kfree(dac33);
c8bf93f0
PU		 1594 return ret;
1595}
1596
735fe4cf 1597static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1598{
f0fba2ad 1599 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1600
1601 if (unlikely(dac33->chip_power))
f0fba2ad 1602 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1603
1604 if (dac33->power_gpio >= 0)
1605 gpio_free(dac33->power_gpio);
c8bf93f0 1606
3a7aaed7
IK		 1607 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1608
f0fba2ad 1609 snd_soc_unregister_codec(&client->dev);
c8bf93f0 1610 kfree(dac33);
c8bf93f0
PU		 1611
1612 return 0;
1613}
1614
1615static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1616 {
1617 .name = "tlv320dac33",
1618 .driver_data = 0,
1619 },
1620 { },
1621};
1622
1623static struct i2c_driver tlv320dac33_i2c_driver = {
1624 .driver = {
f0fba2ad 1625 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1626 .owner = THIS_MODULE,
1627 },
1628 .probe = dac33_i2c_probe,
1629 .remove = __devexit_p(dac33_i2c_remove),
1630 .id_table = tlv320dac33_i2c_id,
1631};
1632
1633static int __init dac33_module_init(void)
1634{
1635 int r;
1636 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1637 if (r < 0) {
1638 printk(KERN_ERR "DAC33: driver registration failed\n");
1639 return r;
1640 }
1641 return 0;
1642}
1643module_init(dac33_module_init);
1644
1645static void __exit dac33_module_exit(void)
1646{
1647 i2c_del_driver(&tlv320dac33_i2c_driver);
1648}
1649module_exit(dac33_module_exit);
1650
1651
1652MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1653MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1654MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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