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ASoC: DMIC codec: Adding a generic DMIC codec
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
c8bf93f0
PU		 39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
549675ed
PU		 45/*
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
50 */
51#define DAC33_FIFO_SIZE_16BIT 6144
52#define DAC33_FIFO_SIZE_24BIT 4096
53#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
4260393e 54
76f47127
PU		 55#define BURST_BASEFREQ_HZ 49152000
56
f57d2cfa
PU		 57#define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60#define US_TO_SAMPLES(rate, us) \
d54e1f4f 61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
f57d2cfa 62
a577b318
PU		 63#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65
ad05c03b
PU		 66static void dac33_calculate_times(struct snd_pcm_substream *substream);
67static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 68
c8bf93f0
PU		 69enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74};
75
7427b4b9
PU		 76enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
28e05d98 79 DAC33_FIFO_MODE7,
7427b4b9
PU		 80 DAC33_FIFO_LAST_MODE,
81};
82
3a7aaed7
IK		 83#define DAC33_NUM_SUPPLIES 3
84static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88};
89
c8bf93f0
PU		 90struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
f0fba2ad 94 struct snd_soc_codec *codec;
3a7aaed7 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 96 struct snd_pcm_substream *substream;
c8bf93f0
PU		 97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
7427b4b9 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
549675ed 104 unsigned int fifo_size; /* Size of the FIFO in samples */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 106 int mode1_latency; /* latency caused by the i2c writes in
107 * us */
6aceabb4 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 109 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 110
eeb309a8
PU		 111 int keep_bclk; /* Keep the BCLK continuously running
112 * in FIFO modes */
f57d2cfa
PU		 113 spinlock_t lock;
114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
116
117 unsigned int mode1_us_burst; /* Time to burst read n number of
118 * samples */
119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 120
9d7db2b2
PU		 121 unsigned int uthr;
122
c8bf93f0 123 enum dac33_state state;
f0fba2ad
LG		 124 enum snd_soc_control_type control_type;
125 void *control_data;
c8bf93f0
PU		 126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 198 int val, ret = 0;
c8bf93f0
PU		 199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 208 ret = val;
c8bf93f0
PU		 209 } else {
210 value[0] = val;
211 dac33_write_reg_cache(codec, reg, val);
212 }
213 } else {
214 value[0] = dac33_read_reg_cache(codec, reg);
215 }
216
911a0f0b 217 return ret;
c8bf93f0
PU		 218}
219
220static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
221 unsigned int value)
222{
b2c812e2 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 224 u8 data[2];
225 int ret = 0;
226
227 /*
228 * data is
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
231 */
232 data[0] = reg & 0xff;
233 data[1] = value & 0xff;
234
235 dac33_write_reg_cache(codec, data[0], data[1]);
236 if (dac33->chip_power) {
237 ret = codec->hw_write(codec->control_data, data, 2);
238 if (ret != 2)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245}
246
247static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
248 unsigned int value)
249{
b2c812e2 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 251 int ret;
252
253 mutex_lock(&dac33->mutex);
254 ret = dac33_write(codec, reg, value);
255 mutex_unlock(&dac33->mutex);
256
257 return ret;
258}
259
260#define DAC33_I2C_ADDR_AUTOINC 0x80
261static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
262 unsigned int value)
263{
b2c812e2 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 265 u8 data[3];
266 int ret = 0;
267
268 /*
269 * data is
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
273 */
274 data[0] = reg & 0xff;
275 data[1] = (value >> 8) & 0xff;
276 data[2] = value & 0xff;
277
278 dac33_write_reg_cache(codec, data[0], data[1]);
279 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
280
281 if (dac33->chip_power) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data[0] |= DAC33_I2C_ADDR_AUTOINC;
284 ret = codec->hw_write(codec->control_data, data, 3);
285 if (ret != 3)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 else
288 ret = 0;
289 }
290
291 return ret;
292}
293
ef909d67 294static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 295{
b2c812e2 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 297
ef909d67 298 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 299 return;
300
ef909d67
PU		 301 /* 44-46: DAC Control Registers */
302 /* A : DAC sample rate Fsref/1.5 */
303 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
304 /* B : DAC src=normal, not muted */
305 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
306 DAC33_DACSRCL_LEFT);
307 /* C : (defaults) */
308 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
309
ef909d67
PU		 310 /* 73 : volume soft stepping control,
311 clock source = internal osc (?) */
312 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
313
ef909d67
PU		 314 /* Restore only selected registers (gains mostly) */
315 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
316 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
317 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
318 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
319
320 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
321 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
322 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
323 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 324}
325
911a0f0b 326static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 327{
911a0f0b 328 int i, ret = 0;
239fe55c
PU		 329 u8 reg;
330
911a0f0b
PU		 331 for (i = 0; i < 3; i++) {
332 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
333 if (ret < 0)
334 break;
335 }
336
337 return ret;
c8bf93f0
PU		 338}
339
340static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
341{
342 u8 reg;
343
344 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
345 if (power)
346 reg |= DAC33_PDNALLB;
347 else
c3746a07
PU		 348 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
349 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 350 dac33_write(codec, DAC33_PWR_CTRL, reg);
351}
352
a6cea965
PU		 353static inline void dac33_disable_digital(struct snd_soc_codec *codec)
354{
355 u8 reg;
356
357 /* Stop the DAI clock */
358 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
359 reg &= ~DAC33_BCLKON;
360 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
361
362 /* Power down the Oscillator, and DACs */
363 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
364 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
365 dac33_write(codec, DAC33_PWR_CTRL, reg);
366}
367
3a7aaed7 368static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 369{
b2c812e2 370 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 371 int ret = 0;
c8bf93f0
PU		 372
373 mutex_lock(&dac33->mutex);
ad05c03b
PU		 374
375 /* Safety check */
376 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 377 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 378 power ? "ON" : "OFF");
379 goto exit;
380 }
381
c8bf93f0 382 if (power) {
3a7aaed7
IK		 383 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
384 dac33->supplies);
385 if (ret != 0) {
386 dev_err(codec->dev,
387 "Failed to enable supplies: %d\n", ret);
388 goto exit;
c8bf93f0 389 }
3a7aaed7
IK		 390
391 if (dac33->power_gpio >= 0)
392 gpio_set_value(dac33->power_gpio, 1);
393
394 dac33->chip_power = 1;
c8bf93f0
PU		 395 } else {
396 dac33_soft_power(codec, 0);
3a7aaed7 397 if (dac33->power_gpio >= 0)
c8bf93f0 398 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 399
400 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
401 dac33->supplies);
402 if (ret != 0) {
403 dev_err(codec->dev,
404 "Failed to disable supplies: %d\n", ret);
405 goto exit;
c8bf93f0 406 }
3a7aaed7
IK		 407
408 dac33->chip_power = 0;
c8bf93f0 409 }
c8bf93f0 410
3a7aaed7
IK		 411exit:
412 mutex_unlock(&dac33->mutex);
413 return ret;
c8bf93f0
PU		 414}
415
a6cea965 416static int dac33_playback_event(struct snd_soc_dapm_widget *w,
ad05c03b
PU		 417 struct snd_kcontrol *kcontrol, int event)
418{
419 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
420
421 switch (event) {
422 case SND_SOC_DAPM_PRE_PMU:
423 if (likely(dac33->substream)) {
424 dac33_calculate_times(dac33->substream);
425 dac33_prepare_chip(dac33->substream);
426 }
427 break;
a6cea965
PU		 428 case SND_SOC_DAPM_POST_PMD:
429 dac33_disable_digital(w->codec);
430 break;
ad05c03b
PU		 431 }
432 return 0;
433}
434
7427b4b9 435static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 436 struct snd_ctl_elem_value *ucontrol)
437{
438 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 439 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 440
7427b4b9 441 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 442
443 return 0;
444}
445
7427b4b9 446static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 447 struct snd_ctl_elem_value *ucontrol)
448{
449 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 450 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 451 int ret = 0;
452
7427b4b9 453 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 454 return 0;
455 /* Do not allow changes while stream is running*/
456 if (codec->active)
457 return -EPERM;
458
459 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 460 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 461 ret = -EINVAL;
462 else
7427b4b9 463 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 464
465 return ret;
466}
467
7427b4b9
PU		 468/* Codec operation modes */
469static const char *dac33_fifo_mode_texts[] = {
28e05d98 470 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 471};
472
473static const struct soc_enum dac33_fifo_mode_enum =
474 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
475 dac33_fifo_mode_texts);
476
cf4bb698
PU		 477/* L/R Line Output Gain */
478static const char *lr_lineout_gain_texts[] = {
479 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
480 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
481};
482
483static const struct soc_enum l_lineout_gain_enum =
484 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
485 ARRAY_SIZE(lr_lineout_gain_texts),
486 lr_lineout_gain_texts);
487
488static const struct soc_enum r_lineout_gain_enum =
489 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
490 ARRAY_SIZE(lr_lineout_gain_texts),
491 lr_lineout_gain_texts);
492
c8bf93f0
PU		 493/*
494 * DACL/R digital volume control:
495 * from 0 dB to -63.5 in 0.5 dB steps
496 * Need to be inverted later on:
497 * 0x00 == 0 dB
498 * 0x7f == -63.5 dB
499 */
500static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
501
502static const struct snd_kcontrol_new dac33_snd_controls[] = {
503 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
504 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
505 0, 0x7f, 1, dac_digivol_tlv),
506 SOC_DOUBLE_R("DAC Digital Playback Switch",
507 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
508 SOC_DOUBLE_R("Line to Line Out Volume",
509 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 510 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
511 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 512};
513
a577b318
PU		 514static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
515 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
516 dac33_get_fifo_mode, dac33_set_fifo_mode),
517};
518
c8bf93f0
PU		 519/* Analog bypass */
520static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
521 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
522
523static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
524 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
525
526static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
527 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
528 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
529
530 SND_SOC_DAPM_INPUT("LINEL"),
531 SND_SOC_DAPM_INPUT("LINER"),
532
76eac39c
PU		 533 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
534 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 535
536 /* Analog bypass */
537 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
538 &dac33_dapm_abypassl_control),
539 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
540 &dac33_dapm_abypassr_control),
541
9e87186f 542 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 543 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 544 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 545 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 546
76eac39c
PU		 547 SND_SOC_DAPM_SUPPLY("Left DAC Power",
548 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
549 SND_SOC_DAPM_SUPPLY("Right DAC Power",
550 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
551
a6cea965
PU		 552 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
553 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
c8bf93f0
PU		 554};
555
556static const struct snd_soc_dapm_route audio_map[] = {
557 /* Analog bypass */
558 {"Analog Left Bypass", "Switch", "LINEL"},
559 {"Analog Right Bypass", "Switch", "LINER"},
560
9e87186f
PU		 561 {"Output Left Amplifier", NULL, "DACL"},
562 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 563
9e87186f
PU		 564 {"Output Left Amplifier", NULL, "Analog Left Bypass"},
565 {"Output Right Amplifier", NULL, "Analog Right Bypass"},
c8bf93f0 566
76eac39c
PU		 567 {"Output Left Amplifier", NULL, "Left DAC Power"},
568 {"Output Right Amplifier", NULL, "Right DAC Power"},
569
c8bf93f0 570 /* output */
9e87186f
PU		 571 {"LEFT_LO", NULL, "Output Left Amplifier"},
572 {"RIGHT_LO", NULL, "Output Right Amplifier"},
c8bf93f0
PU		 573};
574
575static int dac33_add_widgets(struct snd_soc_codec *codec)
576{
ce6120cc 577 struct snd_soc_dapm_context *dapm = &codec->dapm;
c8bf93f0 578
ce6120cc
LG		 579 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
580 ARRAY_SIZE(dac33_dapm_widgets));
c8bf93f0 581 /* set up audio path interconnects */
ce6120cc 582 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 583
584 return 0;
585}
586
587static int dac33_set_bias_level(struct snd_soc_codec *codec,
588 enum snd_soc_bias_level level)
589{
3ee4fe15 590 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7
IK		 591 int ret;
592
c8bf93f0
PU		 593 switch (level) {
594 case SND_SOC_BIAS_ON:
3e202345
PU		 595 if (!dac33->substream)
596 dac33_soft_power(codec, 1);
c8bf93f0
PU		 597 break;
598 case SND_SOC_BIAS_PREPARE:
599 break;
600 case SND_SOC_BIAS_STANDBY:
ce6120cc 601 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 602 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 603 ret = dac33_hard_power(codec, 1);
604 if (ret != 0)
605 return ret;
3a7aaed7 606
ad05c03b
PU		 607 dac33_init_chip(codec);
608 }
c8bf93f0
PU		 609 break;
610 case SND_SOC_BIAS_OFF:
2d4cdd6f 611 /* Do not power off, when the codec is already off */
ce6120cc 612 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2d4cdd6f 613 return 0;
3a7aaed7
IK		 614 ret = dac33_hard_power(codec, 0);
615 if (ret != 0)
616 return ret;
c8bf93f0
PU		 617 break;
618 }
ce6120cc 619 codec->dapm.bias_level = level;
c8bf93f0
PU		 620
621 return 0;
622}
623
d4f102d4
PU		 624static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
625{
f0fba2ad 626 struct snd_soc_codec *codec = dac33->codec;
84eae18c 627 unsigned int delay;
d4f102d4
PU		 628
629 switch (dac33->fifo_mode) {
630 case DAC33_FIFO_MODE1:
631 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 632 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 633
634 /* Take the timestamps */
635 spin_lock_irq(&dac33->lock);
636 dac33->t_stamp2 = ktime_to_us(ktime_get());
637 dac33->t_stamp1 = dac33->t_stamp2;
638 spin_unlock_irq(&dac33->lock);
639
d4f102d4
PU		 640 dac33_write16(codec, DAC33_PREFILL_MSB,
641 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 642 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 643 delay = SAMPLES_TO_US(dac33->burst_rate,
644 dac33->alarm_threshold) + 1000;
645 usleep_range(delay, delay + 500);
f4d59328 646 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 647 break;
28e05d98 648 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 649 /* Take the timestamp */
650 spin_lock_irq(&dac33->lock);
651 dac33->t_stamp1 = ktime_to_us(ktime_get());
652 /* Move back the timestamp with drain time */
653 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
654 spin_unlock_irq(&dac33->lock);
655
28e05d98 656 dac33_write16(codec, DAC33_PREFILL_MSB,
549675ed 657 DAC33_THRREG(DAC33_MODE7_MARGIN));
f57d2cfa
PU		 658
659 /* Enable Upper Threshold IRQ */
660 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 661 break;
d4f102d4
PU		 662 default:
663 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
664 dac33->fifo_mode);
665 break;
666 }
667}
668
669static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
670{
f0fba2ad 671 struct snd_soc_codec *codec = dac33->codec;
d4f102d4
PU		 672
673 switch (dac33->fifo_mode) {
674 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 675 /* Take the timestamp */
676 spin_lock_irq(&dac33->lock);
677 dac33->t_stamp2 = ktime_to_us(ktime_get());
678 spin_unlock_irq(&dac33->lock);
679
d4f102d4
PU		 680 dac33_write16(codec, DAC33_NSAMPLE_MSB,
681 DAC33_THRREG(dac33->nsample));
682 break;
28e05d98
PU		 683 case DAC33_FIFO_MODE7:
684 /* At the moment we are not using interrupts in mode7 */
685 break;
d4f102d4
PU		 686 default:
687 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
688 dac33->fifo_mode);
689 break;
690 }
691}
692
c8bf93f0
PU		 693static void dac33_work(struct work_struct *work)
694{
695 struct snd_soc_codec *codec;
696 struct tlv320dac33_priv *dac33;
697 u8 reg;
698
699 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 700 codec = dac33->codec;
c8bf93f0
PU		 701
702 mutex_lock(&dac33->mutex);
703 switch (dac33->state) {
704 case DAC33_PREFILL:
705 dac33->state = DAC33_PLAYBACK;
d4f102d4 706 dac33_prefill_handler(dac33);
c8bf93f0
PU		 707 break;
708 case DAC33_PLAYBACK:
d4f102d4 709 dac33_playback_handler(dac33);
c8bf93f0
PU		 710 break;
711 case DAC33_IDLE:
712 break;
713 case DAC33_FLUSH:
714 dac33->state = DAC33_IDLE;
715 /* Mask all interrupts from dac33 */
716 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
717
718 /* flush fifo */
719 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
720 reg |= DAC33_FIFOFLUSH;
721 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
722 break;
723 }
724 mutex_unlock(&dac33->mutex);
725}
726
727static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
728{
729 struct snd_soc_codec *codec = dev;
b2c812e2 730 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 731
f57d2cfa
PU		 732 spin_lock(&dac33->lock);
733 dac33->t_stamp1 = ktime_to_us(ktime_get());
734 spin_unlock(&dac33->lock);
c8bf93f0 735
f57d2cfa
PU		 736 /* Do not schedule the workqueue in Mode7 */
737 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
738 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 739
c8bf93f0 740 return IRQ_HANDLED;
c8bf93f0
PU		 741}
742
743static void dac33_oscwait(struct snd_soc_codec *codec)
744{
84eae18c 745 int timeout = 60;
c8bf93f0
PU		 746 u8 reg;
747
748 do {
84eae18c 749 usleep_range(1000, 2000);
c8bf93f0
PU		 750 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
751 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
752 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
753 dev_err(codec->dev,
754 "internal oscillator calibration failed\n");
755}
756
0b61d2b9
PU		 757static int dac33_startup(struct snd_pcm_substream *substream,
758 struct snd_soc_dai *dai)
759{
760 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 761 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 762 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
763
764 /* Stream started, save the substream pointer */
765 dac33->substream = substream;
766
0d99d2b0
PU		 767 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
768
0b61d2b9
PU		 769 return 0;
770}
771
772static void dac33_shutdown(struct snd_pcm_substream *substream,
773 struct snd_soc_dai *dai)
774{
775 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 776 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 777 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
778
779 dac33->substream = NULL;
780}
781
549675ed
PU		 782#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
783 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
c8bf93f0
PU		 784static int dac33_hw_params(struct snd_pcm_substream *substream,
785 struct snd_pcm_hw_params *params,
786 struct snd_soc_dai *dai)
787{
788 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 789 struct snd_soc_codec *codec = rtd->codec;
549675ed 790 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 791
792 /* Check parameters for validity */
793 switch (params_rate(params)) {
794 case 44100:
795 case 48000:
796 break;
797 default:
798 dev_err(codec->dev, "unsupported rate %d\n",
799 params_rate(params));
800 return -EINVAL;
801 }
802
803 switch (params_format(params)) {
804 case SNDRV_PCM_FORMAT_S16_LE:
549675ed
PU		 805 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
806 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
c8bf93f0 807 break;
0d99d2b0
PU		 808 case SNDRV_PCM_FORMAT_S32_LE:
809 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
810 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
811 break;
c8bf93f0
PU		 812 default:
813 dev_err(codec->dev, "unsupported format %d\n",
814 params_format(params));
815 return -EINVAL;
816 }
817
818 return 0;
819}
820
821#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 822 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 823#define CALC_RATIOSET(rate, refclk) ( \
824 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
825
826/*
827 * tlv320dac33 is strict on the sequence of the register writes, if the register
828 * writes happens in different order, than dac33 might end up in unknown state.
829 * Use the known, working sequence of register writes to initialize the dac33.
830 */
831static int dac33_prepare_chip(struct snd_pcm_substream *substream)
832{
833 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 834 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 835 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 836 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 837 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 838
839 switch (substream->runtime->rate) {
840 case 44100:
841 case 48000:
842 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
843 ratioset = CALC_RATIOSET(substream->runtime->rate,
844 dac33->refclk);
845 break;
846 default:
847 dev_err(codec->dev, "unsupported rate %d\n",
848 substream->runtime->rate);
849 return -EINVAL;
850 }
851
852
853 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
854 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 855 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 856 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 857 fifoctrl_a &= ~DAC33_FIFOFLUSH;
858
c8bf93f0
PU		 859 fifoctrl_a &= ~DAC33_WIDTH;
860 switch (substream->runtime->format) {
861 case SNDRV_PCM_FORMAT_S16_LE:
862 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
863 fifoctrl_a |= DAC33_WIDTH;
864 break;
0d99d2b0
PU		 865 case SNDRV_PCM_FORMAT_S32_LE:
866 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
867 break;
c8bf93f0
PU		 868 default:
869 dev_err(codec->dev, "unsupported format %d\n",
870 substream->runtime->format);
871 return -EINVAL;
872 }
873
874 mutex_lock(&dac33->mutex);
ad05c03b
PU		 875
876 if (!dac33->chip_power) {
877 /*
878 * Chip is not powered yet.
879 * Do the init in the dac33_set_bias_level later.
880 */
881 mutex_unlock(&dac33->mutex);
882 return 0;
883 }
884
c3746a07 885 dac33_soft_power(codec, 0);
c8bf93f0
PU		 886 dac33_soft_power(codec, 1);
887
888 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
889 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
890
891 /* Write registers 0x08 and 0x09 (MSB, LSB) */
892 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
893
894 /* calib time: 128 is a nice number ;) */
895 dac33_write(codec, DAC33_CALIB_TIME, 128);
896
897 /* adjustment treshold & step */
898 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
899 DAC33_ADJSTEP(1));
900
901 /* div=4 / gain=1 / div */
902 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
903
904 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
905 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
906 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
907
908 dac33_oscwait(codec);
909
7427b4b9 910 if (dac33->fifo_mode) {
aec242dc 911 /* Generic for all FIFO modes */
c8bf93f0 912 /* 50-51 : ASRC Control registers */
fdb6b1e1 913 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 914 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
915
916 /* Write registers 0x34 and 0x35 (MSB, LSB) */
917 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
918
919 /* Set interrupts to high active */
920 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 921 } else {
aec242dc 922 /* FIFO bypass mode */
c8bf93f0
PU		 923 /* 50-51 : ASRC Control registers */
924 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
925 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
926 }
927
aec242dc
PU		 928 /* Interrupt behaviour configuration */
929 switch (dac33->fifo_mode) {
930 case DAC33_FIFO_MODE1:
931 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
932 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 933 break;
28e05d98 934 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 935 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
936 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 937 break;
aec242dc
PU		 938 default:
939 /* in FIFO bypass mode, the interrupts are not used */
940 break;
941 }
942
943 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
944
945 switch (dac33->fifo_mode) {
946 case DAC33_FIFO_MODE1:
947 /*
948 * For mode1:
949 * Disable the FIFO bypass (Enable the use of FIFO)
950 * Select nSample mode
951 * BCLK is only running when data is needed by DAC33
952 */
c8bf93f0 953 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 954 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 955 if (dac33->keep_bclk)
956 aictrl_b |= DAC33_BCLKON;
957 else
958 aictrl_b &= ~DAC33_BCLKON;
aec242dc 959 break;
28e05d98
PU		 960 case DAC33_FIFO_MODE7:
961 /*
962 * For mode1:
963 * Disable the FIFO bypass (Enable the use of FIFO)
964 * Select Threshold mode
965 * BCLK is only running when data is needed by DAC33
966 */
967 fifoctrl_a &= ~DAC33_FBYPAS;
968 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 969 if (dac33->keep_bclk)
970 aictrl_b |= DAC33_BCLKON;
971 else
972 aictrl_b &= ~DAC33_BCLKON;
28e05d98 973 break;
aec242dc
PU		 974 default:
975 /*
976 * For FIFO bypass mode:
977 * Enable the FIFO bypass (Disable the FIFO use)
978 * Set the BCLK as continous
979 */
c8bf93f0 980 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 981 aictrl_b |= DAC33_BCLKON;
982 break;
983 }
c8bf93f0 984
aec242dc 985 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 986 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 987 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 988
6aceabb4
PU		 989 /*
990 * BCLK divide ratio
991 * 0: 1.5
992 * 1: 1
993 * 2: 2
994 * ...
995 * 254: 254
996 * 255: 255
997 */
6cd6cede 998 if (dac33->fifo_mode)
6aceabb4
PU		 999 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1000 dac33->burst_bclkdiv);
6cd6cede 1001 else
0d99d2b0
PU		 1002 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1003 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1004 else
1005 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
c8bf93f0 1006
6cd6cede
PU		 1007 switch (dac33->fifo_mode) {
1008 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1009 dac33_write16(codec, DAC33_ATHR_MSB,
1010 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1011 break;
28e05d98
PU		 1012 case DAC33_FIFO_MODE7:
1013 /*
1014 * Configure the threshold levels, and leave 10 sample space
1015 * at the bottom, and also at the top of the FIFO
1016 */
9d7db2b2 1017 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
549675ed
PU		 1018 dac33_write16(codec, DAC33_LTHR_MSB,
1019 DAC33_THRREG(DAC33_MODE7_MARGIN));
28e05d98 1020 break;
aec242dc 1021 default:
aec242dc 1022 break;
c8bf93f0
PU		 1023 }
1024
1025 mutex_unlock(&dac33->mutex);
1026
1027 return 0;
1028}
1029
1030static void dac33_calculate_times(struct snd_pcm_substream *substream)
1031{
1032 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1033 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1034 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1035 unsigned int period_size = substream->runtime->period_size;
1036 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1037 unsigned int nsample_limit;
1038
55abb59c
PU		 1039 /* In bypass mode we don't need to calculate */
1040 if (!dac33->fifo_mode)
1041 return;
1042
f57d2cfa
PU		 1043 switch (dac33->fifo_mode) {
1044 case DAC33_FIFO_MODE1:
f430a27f
PU		 1045 /* Number of samples under i2c latency */
1046 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1047 dac33->mode1_latency);
549675ed 1048 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1bc13b2e 1049
3591f4cd 1050 if (period_size <= dac33->alarm_threshold)
a577b318 1051 /*
3591f4cd
PU		 1052 * Configure nSamaple to number of periods,
1053 * which covers the latency requironment.
a577b318 1054 */
3591f4cd
PU		 1055 dac33->nsample = period_size *
1056 ((dac33->alarm_threshold / period_size) +
1057 (dac33->alarm_threshold % period_size ?
1058 1 : 0));
1059 else if (period_size > nsample_limit)
1060 dac33->nsample = nsample_limit;
1061 else
1062 dac33->nsample = period_size;
f430a27f 1063
f57d2cfa
PU		 1064 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1065 dac33->nsample);
1066 dac33->t_stamp1 = 0;
1067 dac33->t_stamp2 = 0;
1068 break;
1069 case DAC33_FIFO_MODE7:
3591f4cd
PU		 1070 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1071 dac33->burst_rate) + 9;
549675ed
PU		 1072 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1073 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1074 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1075 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
3591f4cd 1076
f57d2cfa 1077 dac33->mode7_us_to_lthr =
9d7db2b2 1078 SAMPLES_TO_US(substream->runtime->rate,
549675ed 1079 dac33->uthr - DAC33_MODE7_MARGIN + 1);
f57d2cfa
PU		 1080 dac33->t_stamp1 = 0;
1081 break;
1082 default:
1083 break;
1084 }
c8bf93f0 1085
c8bf93f0
PU		 1086}
1087
1088static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1089 struct snd_soc_dai *dai)
1090{
1091 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1092 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1093 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1094 int ret = 0;
1095
1096 switch (cmd) {
1097 case SNDRV_PCM_TRIGGER_START:
1098 case SNDRV_PCM_TRIGGER_RESUME:
1099 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1100 if (dac33->fifo_mode) {
c8bf93f0
PU		 1101 dac33->state = DAC33_PREFILL;
1102 queue_work(dac33->dac33_wq, &dac33->work);
1103 }
1104 break;
1105 case SNDRV_PCM_TRIGGER_STOP:
1106 case SNDRV_PCM_TRIGGER_SUSPEND:
1107 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1108 if (dac33->fifo_mode) {
c8bf93f0
PU		 1109 dac33->state = DAC33_FLUSH;
1110 queue_work(dac33->dac33_wq, &dac33->work);
1111 }
1112 break;
1113 default:
1114 ret = -EINVAL;
1115 }
1116
1117 return ret;
1118}
1119
f57d2cfa
PU		 1120static snd_pcm_sframes_t dac33_dai_delay(
1121 struct snd_pcm_substream *substream,
1122 struct snd_soc_dai *dai)
1123{
1124 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1125 struct snd_soc_codec *codec = rtd->codec;
f57d2cfa
PU		 1126 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1127 unsigned long long t0, t1, t_now;
9d7db2b2 1128 unsigned int time_delta, uthr;
f57d2cfa
PU		 1129 int samples_out, samples_in, samples;
1130 snd_pcm_sframes_t delay = 0;
1131
1132 switch (dac33->fifo_mode) {
1133 case DAC33_FIFO_BYPASS:
1134 break;
1135 case DAC33_FIFO_MODE1:
1136 spin_lock(&dac33->lock);
1137 t0 = dac33->t_stamp1;
1138 t1 = dac33->t_stamp2;
1139 spin_unlock(&dac33->lock);
1140 t_now = ktime_to_us(ktime_get());
1141
1142 /* We have not started to fill the FIFO yet, delay is 0 */
1143 if (!t1)
1144 goto out;
1145
1146 if (t0 > t1) {
1147 /*
1148 * Phase 1:
1149 * After Alarm threshold, and before nSample write
1150 */
1151 time_delta = t_now - t0;
1152 samples_out = time_delta ? US_TO_SAMPLES(
1153 substream->runtime->rate,
1154 time_delta) : 0;
1155
1156 if (likely(dac33->alarm_threshold > samples_out))
1157 delay = dac33->alarm_threshold - samples_out;
1158 else
1159 delay = 0;
1160 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1161 /*
1162 * Phase 2:
1163 * After nSample write (during burst operation)
1164 */
1165 time_delta = t_now - t0;
1166 samples_out = time_delta ? US_TO_SAMPLES(
1167 substream->runtime->rate,
1168 time_delta) : 0;
1169
1170 time_delta = t_now - t1;
1171 samples_in = time_delta ? US_TO_SAMPLES(
1172 dac33->burst_rate,
1173 time_delta) : 0;
1174
1175 samples = dac33->alarm_threshold;
1176 samples += (samples_in - samples_out);
1177
1178 if (likely(samples > 0))
1179 delay = samples;
1180 else
1181 delay = 0;
1182 } else {
1183 /*
1184 * Phase 3:
1185 * After burst operation, before next alarm threshold
1186 */
1187 time_delta = t_now - t0;
1188 samples_out = time_delta ? US_TO_SAMPLES(
1189 substream->runtime->rate,
1190 time_delta) : 0;
1191
1192 samples_in = dac33->nsample;
1193 samples = dac33->alarm_threshold;
1194 samples += (samples_in - samples_out);
1195
1196 if (likely(samples > 0))
549675ed
PU		 1197 delay = samples > dac33->fifo_size ?
1198 dac33->fifo_size : samples;
f57d2cfa
PU		 1199 else
1200 delay = 0;
1201 }
1202 break;
1203 case DAC33_FIFO_MODE7:
1204 spin_lock(&dac33->lock);
1205 t0 = dac33->t_stamp1;
9d7db2b2 1206 uthr = dac33->uthr;
f57d2cfa
PU		 1207 spin_unlock(&dac33->lock);
1208 t_now = ktime_to_us(ktime_get());
1209
1210 /* We have not started to fill the FIFO yet, delay is 0 */
1211 if (!t0)
1212 goto out;
1213
1214 if (t_now <= t0) {
1215 /*
1216 * Either the timestamps are messed or equal. Report
1217 * maximum delay
1218 */
9d7db2b2 1219 delay = uthr;
f57d2cfa
PU		 1220 goto out;
1221 }
1222
1223 time_delta = t_now - t0;
1224 if (time_delta <= dac33->mode7_us_to_lthr) {
1225 /*
1226 * Phase 1:
1227 * After burst (draining phase)
1228 */
1229 samples_out = US_TO_SAMPLES(
1230 substream->runtime->rate,
1231 time_delta);
1232
9d7db2b2
PU		 1233 if (likely(uthr > samples_out))
1234 delay = uthr - samples_out;
f57d2cfa
PU		 1235 else
1236 delay = 0;
1237 } else {
1238 /*
1239 * Phase 2:
1240 * During burst operation
1241 */
1242 time_delta = time_delta - dac33->mode7_us_to_lthr;
1243
1244 samples_out = US_TO_SAMPLES(
1245 substream->runtime->rate,
1246 time_delta);
1247 samples_in = US_TO_SAMPLES(
1248 dac33->burst_rate,
1249 time_delta);
549675ed 1250 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
f57d2cfa 1251
9d7db2b2
PU		 1252 if (unlikely(delay > uthr))
1253 delay = uthr;
f57d2cfa
PU		 1254 }
1255 break;
1256 default:
1257 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1258 dac33->fifo_mode);
1259 break;
1260 }
1261out:
1262 return delay;
1263}
1264
c8bf93f0
PU		 1265static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1266 int clk_id, unsigned int freq, int dir)
1267{
1268 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1269 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1270 u8 ioc_reg, asrcb_reg;
1271
1272 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1273 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1274 switch (clk_id) {
1275 case TLV320DAC33_MCLK:
1276 ioc_reg |= DAC33_REFSEL;
1277 asrcb_reg |= DAC33_SRCREFSEL;
1278 break;
1279 case TLV320DAC33_SLEEPCLK:
1280 ioc_reg &= ~DAC33_REFSEL;
1281 asrcb_reg &= ~DAC33_SRCREFSEL;
1282 break;
1283 default:
1284 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1285 break;
1286 }
1287 dac33->refclk = freq;
1288
1289 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1290 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1291
1292 return 0;
1293}
1294
1295static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1296 unsigned int fmt)
1297{
1298 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1299 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1300 u8 aictrl_a, aictrl_b;
1301
1302 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1303 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1304 /* set master/slave audio interface */
1305 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1306 case SND_SOC_DAIFMT_CBM_CFM:
1307 /* Codec Master */
1308 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1309 break;
1310 case SND_SOC_DAIFMT_CBS_CFS:
1311 /* Codec Slave */
adcb8bc0
PU		 1312 if (dac33->fifo_mode) {
1313 dev_err(codec->dev, "FIFO mode requires master mode\n");
1314 return -EINVAL;
1315 } else
1316 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1317 break;
1318 default:
1319 return -EINVAL;
1320 }
1321
1322 aictrl_a &= ~DAC33_AFMT_MASK;
1323 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1324 case SND_SOC_DAIFMT_I2S:
1325 aictrl_a |= DAC33_AFMT_I2S;
1326 break;
1327 case SND_SOC_DAIFMT_DSP_A:
1328 aictrl_a |= DAC33_AFMT_DSP;
1329 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1330 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1331 break;
1332 case SND_SOC_DAIFMT_RIGHT_J:
1333 aictrl_a |= DAC33_AFMT_RIGHT_J;
1334 break;
1335 case SND_SOC_DAIFMT_LEFT_J:
1336 aictrl_a |= DAC33_AFMT_LEFT_J;
1337 break;
1338 default:
1339 dev_err(codec->dev, "Unsupported format (%u)\n",
1340 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1341 return -EINVAL;
1342 }
1343
1344 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1345 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1346
1347 return 0;
1348}
1349
f0fba2ad 1350static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1351{
f0fba2ad 1352 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1353 int ret = 0;
1354
f0fba2ad
LG		 1355 codec->control_data = dac33->control_data;
1356 codec->hw_write = (hw_write_t) i2c_master_send;
ce6120cc 1357 codec->dapm.idle_bias_off = 1;
f0fba2ad 1358 dac33->codec = codec;
c8bf93f0 1359
f0fba2ad
LG		 1360 /* Read the tlv320dac33 ID registers */
1361 ret = dac33_hard_power(codec, 1);
1362 if (ret != 0) {
1363 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1364 goto err_power;
1365 }
911a0f0b 1366 ret = dac33_read_id(codec);
f0fba2ad 1367 dac33_hard_power(codec, 0);
c8bf93f0 1368
911a0f0b
PU		 1369 if (ret < 0) {
1370 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1371 ret = -ENODEV;
1372 goto err_power;
1373 }
1374
f0fba2ad
LG		 1375 /* Check if the IRQ number is valid and request it */
1376 if (dac33->irq >= 0) {
1377 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1378 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1379 codec->name, codec);
1380 if (ret < 0) {
1381 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1382 dac33->irq, ret);
1383 dac33->irq = -1;
1384 }
1385 if (dac33->irq != -1) {
1386 /* Setup work queue */
1387 dac33->dac33_wq =
1388 create_singlethread_workqueue("tlv320dac33");
1389 if (dac33->dac33_wq == NULL) {
1390 free_irq(dac33->irq, codec);
1391 return -ENOMEM;
1392 }
1393
1394 INIT_WORK(&dac33->work, dac33_work);
1395 }
c8bf93f0
PU		 1396 }
1397
1398 snd_soc_add_controls(codec, dac33_snd_controls,
1399 ARRAY_SIZE(dac33_snd_controls));
a577b318 1400 /* Only add the FIFO controls, if we have valid IRQ number */
3591f4cd 1401 if (dac33->irq >= 0)
a577b318
PU		 1402 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1403 ARRAY_SIZE(dac33_mode_snd_controls));
3591f4cd 1404
c8bf93f0
PU		 1405 dac33_add_widgets(codec);
1406
f0fba2ad 1407err_power:
c8bf93f0
PU		 1408 return ret;
1409}
1410
f0fba2ad 1411static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1412{
f0fba2ad 1413 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1414
1415 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1416
f0fba2ad
LG		 1417 if (dac33->irq >= 0) {
1418 free_irq(dac33->irq, dac33->codec);
1419 destroy_workqueue(dac33->dac33_wq);
1420 }
c8bf93f0
PU		 1421 return 0;
1422}
1423
f0fba2ad 1424static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
c8bf93f0 1425{
c8bf93f0
PU		 1426 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1427
1428 return 0;
1429}
1430
f0fba2ad 1431static int dac33_soc_resume(struct snd_soc_codec *codec)
c8bf93f0 1432{
c8bf93f0 1433 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1434
1435 return 0;
1436}
1437
f0fba2ad
LG		 1438static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1439 .read = dac33_read_reg_cache,
1440 .write = dac33_write_locked,
1441 .set_bias_level = dac33_set_bias_level,
1442 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1443 .reg_word_size = sizeof(u8),
1444 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1445 .probe = dac33_soc_probe,
1446 .remove = dac33_soc_remove,
1447 .suspend = dac33_soc_suspend,
1448 .resume = dac33_soc_resume,
1449};
c8bf93f0
PU		 1450
1451#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1452 SNDRV_PCM_RATE_48000)
0d99d2b0 1453#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
c8bf93f0
PU		 1454
1455static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1456 .startup = dac33_startup,
c8bf93f0
PU		 1457 .shutdown = dac33_shutdown,
1458 .hw_params = dac33_hw_params,
c8bf93f0 1459 .trigger = dac33_pcm_trigger,
f57d2cfa 1460 .delay = dac33_dai_delay,
c8bf93f0
PU		 1461 .set_sysclk = dac33_set_dai_sysclk,
1462 .set_fmt = dac33_set_dai_fmt,
1463};
1464
f0fba2ad
LG		 1465static struct snd_soc_dai_driver dac33_dai = {
1466 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1467 .playback = {
1468 .stream_name = "Playback",
1469 .channels_min = 2,
1470 .channels_max = 2,
1471 .rates = DAC33_RATES,
1472 .formats = DAC33_FORMATS,},
1473 .ops = &dac33_dai_ops,
1474};
c8bf93f0 1475
735fe4cf
MB		 1476static int __devinit dac33_i2c_probe(struct i2c_client *client,
1477 const struct i2c_device_id *id)
c8bf93f0
PU		 1478{
1479 struct tlv320dac33_platform_data *pdata;
1480 struct tlv320dac33_priv *dac33;
3a7aaed7 1481 int ret, i;
c8bf93f0
PU		 1482
1483 if (client->dev.platform_data == NULL) {
1484 dev_err(&client->dev, "Platform data not set\n");
1485 return -ENODEV;
1486 }
1487 pdata = client->dev.platform_data;
1488
1489 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1490 if (dac33 == NULL)
1491 return -ENOMEM;
1492
f0fba2ad 1493 dac33->control_data = client;
c8bf93f0 1494 mutex_init(&dac33->mutex);
f57d2cfa 1495 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1496
1497 i2c_set_clientdata(client, dac33);
1498
1499 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1500 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1501 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1502 dac33->mode1_latency = pdata->mode1_latency;
1503 if (!dac33->mode1_latency)
1504 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0 1505 dac33->irq = client->irq;
c8bf93f0 1506 /* Disable FIFO use by default */
7427b4b9 1507 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1508
c8bf93f0
PU		 1509 /* Check if the reset GPIO number is valid and request it */
1510 if (dac33->power_gpio >= 0) {
1511 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1512 if (ret < 0) {
f0fba2ad 1513 dev_err(&client->dev,
c8bf93f0
PU		 1514 "Failed to request reset GPIO (%d)\n",
1515 dac33->power_gpio);
f0fba2ad 1516 goto err_gpio;
c8bf93f0
PU		 1517 }
1518 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1519 }
1520
3a7aaed7
IK		 1521 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1522 dac33->supplies[i].supply = dac33_supply_names[i];
1523
f0fba2ad 1524 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1525 dac33->supplies);
1526
1527 if (ret != 0) {
f0fba2ad 1528 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1529 goto err_get;
1530 }
1531
f0fba2ad
LG		 1532 ret = snd_soc_register_codec(&client->dev,
1533 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1534 if (ret < 0)
1535 goto err_register;
c8bf93f0 1536
c8bf93f0 1537 return ret;
f0fba2ad 1538err_register:
3a7aaed7
IK		 1539 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1540err_get:
c8bf93f0
PU		 1541 if (dac33->power_gpio >= 0)
1542 gpio_free(dac33->power_gpio);
f0fba2ad 1543err_gpio:
c8bf93f0 1544 kfree(dac33);
c8bf93f0
PU		 1545 return ret;
1546}
1547
735fe4cf 1548static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1549{
f0fba2ad 1550 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1551
1552 if (unlikely(dac33->chip_power))
f0fba2ad 1553 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1554
1555 if (dac33->power_gpio >= 0)
1556 gpio_free(dac33->power_gpio);
c8bf93f0 1557
3a7aaed7
IK		 1558 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1559
f0fba2ad 1560 snd_soc_unregister_codec(&client->dev);
c8bf93f0 1561 kfree(dac33);
c8bf93f0
PU		 1562
1563 return 0;
1564}
1565
1566static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1567 {
1568 .name = "tlv320dac33",
1569 .driver_data = 0,
1570 },
1571 { },
1572};
1573
1574static struct i2c_driver tlv320dac33_i2c_driver = {
1575 .driver = {
f0fba2ad 1576 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1577 .owner = THIS_MODULE,
1578 },
1579 .probe = dac33_i2c_probe,
1580 .remove = __devexit_p(dac33_i2c_remove),
1581 .id_table = tlv320dac33_i2c_id,
1582};
1583
1584static int __init dac33_module_init(void)
1585{
1586 int r;
1587 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1588 if (r < 0) {
1589 printk(KERN_ERR "DAC33: driver registration failed\n");
1590 return r;
1591 }
1592 return 0;
1593}
1594module_init(dac33_module_init);
1595
1596static void __exit dac33_module_exit(void)
1597{
1598 i2c_del_driver(&tlv320dac33_i2c_driver);
1599}
1600module_exit(dac33_module_exit);
1601
1602
1603MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1604MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1605MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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