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ASoC: tlv320dac33: Optimize power up, and restore
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
76f47127
PU		 56#define BURST_BASEFREQ_HZ 49152000
57
f57d2cfa
PU		 58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64
c8bf93f0
PU		 65static struct snd_soc_codec *tlv320dac33_codec;
66
67enum dac33_state {
68 DAC33_IDLE = 0,
69 DAC33_PREFILL,
70 DAC33_PLAYBACK,
71 DAC33_FLUSH,
72};
73
7427b4b9
PU		 74enum dac33_fifo_modes {
75 DAC33_FIFO_BYPASS = 0,
76 DAC33_FIFO_MODE1,
28e05d98 77 DAC33_FIFO_MODE7,
7427b4b9
PU		 78 DAC33_FIFO_LAST_MODE,
79};
80
3a7aaed7
IK		 81#define DAC33_NUM_SUPPLIES 3
82static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
83 "AVDD",
84 "DVDD",
85 "IOVDD",
86};
87
c8bf93f0
PU		 88struct tlv320dac33_priv {
89 struct mutex mutex;
90 struct workqueue_struct *dac33_wq;
91 struct work_struct work;
92 struct snd_soc_codec codec;
3a7aaed7 93 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 94 int power_gpio;
95 int chip_power;
96 int irq;
97 unsigned int refclk;
98
99 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
100 unsigned int nsample_min; /* nsample should not be lower than
101 * this */
102 unsigned int nsample_max; /* nsample should not be higher than
103 * this */
7427b4b9 104 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
6aceabb4 106 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 107 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 108
eeb309a8
PU		 109 int keep_bclk; /* Keep the BCLK continuously running
110 * in FIFO modes */
f57d2cfa
PU		 111 spinlock_t lock;
112 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
113 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
114
115 unsigned int mode1_us_burst; /* Time to burst read n number of
116 * samples */
117 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
118
c8bf93f0
PU		 119 enum dac33_state state;
120};
121
122static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1230x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1240x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1250x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1260x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1270x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1280x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1290x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1300x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1310x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1320x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1330x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1340x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1350x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1360x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1370x00, 0x00, /* 0x38 - 0x39 */
138/* Registers 0x3a - 0x3f are reserved */
139 0x00, 0x00, /* 0x3a - 0x3b */
1400x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
141
1420x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1430x00, 0x80, /* 0x44 - 0x45 */
144/* Registers 0x46 - 0x47 are reserved */
145 0x80, 0x80, /* 0x46 - 0x47 */
146
1470x80, 0x00, 0x00, /* 0x48 - 0x4a */
148/* Registers 0x4b - 0x7c are reserved */
149 0x00, /* 0x4b */
1500x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1510x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1520x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1530x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1540x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1550x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1560x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1570x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1580x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1590x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1600x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1610x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1620x00, /* 0x7c */
163
164 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
165};
166
167/* Register read and write */
168static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
169 unsigned reg)
170{
171 u8 *cache = codec->reg_cache;
172 if (reg >= DAC33_CACHEREGNUM)
173 return 0;
174
175 return cache[reg];
176}
177
178static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
179 u8 reg, u8 value)
180{
181 u8 *cache = codec->reg_cache;
182 if (reg >= DAC33_CACHEREGNUM)
183 return;
184
185 cache[reg] = value;
186}
187
188static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
189 u8 *value)
190{
b2c812e2 191 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 192 int val;
193
194 *value = reg & 0xff;
195
196 /* If powered off, return the cached value */
197 if (dac33->chip_power) {
198 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
199 if (val < 0) {
200 dev_err(codec->dev, "Read failed (%d)\n", val);
201 value[0] = dac33_read_reg_cache(codec, reg);
202 } else {
203 value[0] = val;
204 dac33_write_reg_cache(codec, reg, val);
205 }
206 } else {
207 value[0] = dac33_read_reg_cache(codec, reg);
208 }
209
210 return 0;
211}
212
213static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
214 unsigned int value)
215{
b2c812e2 216 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 217 u8 data[2];
218 int ret = 0;
219
220 /*
221 * data is
222 * D15..D8 dac33 register offset
223 * D7...D0 register data
224 */
225 data[0] = reg & 0xff;
226 data[1] = value & 0xff;
227
228 dac33_write_reg_cache(codec, data[0], data[1]);
229 if (dac33->chip_power) {
230 ret = codec->hw_write(codec->control_data, data, 2);
231 if (ret != 2)
232 dev_err(codec->dev, "Write failed (%d)\n", ret);
233 else
234 ret = 0;
235 }
236
237 return ret;
238}
239
240static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
241 unsigned int value)
242{
b2c812e2 243 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 244 int ret;
245
246 mutex_lock(&dac33->mutex);
247 ret = dac33_write(codec, reg, value);
248 mutex_unlock(&dac33->mutex);
249
250 return ret;
251}
252
253#define DAC33_I2C_ADDR_AUTOINC 0x80
254static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
255 unsigned int value)
256{
b2c812e2 257 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 258 u8 data[3];
259 int ret = 0;
260
261 /*
262 * data is
263 * D23..D16 dac33 register offset
264 * D15..D8 register data MSB
265 * D7...D0 register data LSB
266 */
267 data[0] = reg & 0xff;
268 data[1] = (value >> 8) & 0xff;
269 data[2] = value & 0xff;
270
271 dac33_write_reg_cache(codec, data[0], data[1]);
272 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
273
274 if (dac33->chip_power) {
275 /* We need to set autoincrement mode for 16 bit writes */
276 data[0] |= DAC33_I2C_ADDR_AUTOINC;
277 ret = codec->hw_write(codec->control_data, data, 3);
278 if (ret != 3)
279 dev_err(codec->dev, "Write failed (%d)\n", ret);
280 else
281 ret = 0;
282 }
283
284 return ret;
285}
286
ef909d67 287static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 288{
b2c812e2 289 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 290
ef909d67 291 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 292 return;
293
ef909d67
PU		 294 /* 44-46: DAC Control Registers */
295 /* A : DAC sample rate Fsref/1.5 */
296 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
297 /* B : DAC src=normal, not muted */
298 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
299 DAC33_DACSRCL_LEFT);
300 /* C : (defaults) */
301 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
302
303 /* 64-65 : L&R DAC power control
304 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
305 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
306 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
307
308 /* 73 : volume soft stepping control,
309 clock source = internal osc (?) */
310 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
311
312 /* 66 : LOP/LOM Modes */
313 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
314
315 /* 68 : LOM inverted from LOP */
316 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
317
318 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
319
320 /* Restore only selected registers (gains mostly) */
321 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
322 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
323 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
324 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
325
326 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
327 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
328 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
329 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 330}
331
332static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
333{
334 u8 reg;
335
336 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
337 if (power)
338 reg |= DAC33_PDNALLB;
339 else
c3746a07
PU		 340 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
341 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 342 dac33_write(codec, DAC33_PWR_CTRL, reg);
343}
344
3a7aaed7 345static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 346{
b2c812e2 347 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 348 int ret;
c8bf93f0
PU		 349
350 mutex_lock(&dac33->mutex);
351 if (power) {
3a7aaed7
IK		 352 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
353 dac33->supplies);
354 if (ret != 0) {
355 dev_err(codec->dev,
356 "Failed to enable supplies: %d\n", ret);
357 goto exit;
c8bf93f0 358 }
3a7aaed7
IK		 359
360 if (dac33->power_gpio >= 0)
361 gpio_set_value(dac33->power_gpio, 1);
362
363 dac33->chip_power = 1;
364
ef909d67 365 dac33_init_chip(codec);
3a7aaed7 366
c8bf93f0
PU		 367 dac33_soft_power(codec, 1);
368 } else {
369 dac33_soft_power(codec, 0);
3a7aaed7 370 if (dac33->power_gpio >= 0)
c8bf93f0 371 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 372
373 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
374 dac33->supplies);
375 if (ret != 0) {
376 dev_err(codec->dev,
377 "Failed to disable supplies: %d\n", ret);
378 goto exit;
c8bf93f0 379 }
3a7aaed7
IK		 380
381 dac33->chip_power = 0;
c8bf93f0 382 }
c8bf93f0 383
3a7aaed7
IK		 384exit:
385 mutex_unlock(&dac33->mutex);
386 return ret;
c8bf93f0
PU		 387}
388
389static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol)
391{
392 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 393 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 394
395 ucontrol->value.integer.value[0] = dac33->nsample;
396
397 return 0;
398}
399
400static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_value *ucontrol)
402{
403 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 404 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 405 int ret = 0;
406
407 if (dac33->nsample == ucontrol->value.integer.value[0])
408 return 0;
409
410 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 411 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 412 ret = -EINVAL;
f57d2cfa 413 } else {
c8bf93f0 414 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 415 /* Re calculate the burst time */
416 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
417 dac33->nsample);
418 }
c8bf93f0
PU		 419
420 return ret;
421}
422
7427b4b9 423static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 424 struct snd_ctl_elem_value *ucontrol)
425{
426 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 427 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 428
7427b4b9 429 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 430
431 return 0;
432}
433
7427b4b9 434static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 435 struct snd_ctl_elem_value *ucontrol)
436{
437 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 438 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 439 int ret = 0;
440
7427b4b9 441 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 442 return 0;
443 /* Do not allow changes while stream is running*/
444 if (codec->active)
445 return -EPERM;
446
447 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 448 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 449 ret = -EINVAL;
450 else
7427b4b9 451 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 452
453 return ret;
454}
455
7427b4b9
PU		 456/* Codec operation modes */
457static const char *dac33_fifo_mode_texts[] = {
28e05d98 458 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 459};
460
461static const struct soc_enum dac33_fifo_mode_enum =
462 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
463 dac33_fifo_mode_texts);
464
c8bf93f0
PU		 465/*
466 * DACL/R digital volume control:
467 * from 0 dB to -63.5 in 0.5 dB steps
468 * Need to be inverted later on:
469 * 0x00 == 0 dB
470 * 0x7f == -63.5 dB
471 */
472static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
473
474static const struct snd_kcontrol_new dac33_snd_controls[] = {
475 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
476 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
477 0, 0x7f, 1, dac_digivol_tlv),
478 SOC_DOUBLE_R("DAC Digital Playback Switch",
479 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
480 SOC_DOUBLE_R("Line to Line Out Volume",
481 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
482};
483
484static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
485 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
486 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 487 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
488 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 489};
490
491/* Analog bypass */
492static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
493 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
494
495static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
496 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
497
498static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
499 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
500 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
501
502 SND_SOC_DAPM_INPUT("LINEL"),
503 SND_SOC_DAPM_INPUT("LINER"),
504
505 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
506 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
507
508 /* Analog bypass */
509 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
510 &dac33_dapm_abypassl_control),
511 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
512 &dac33_dapm_abypassr_control),
513
514 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
515 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
516 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
517 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
518};
519
520static const struct snd_soc_dapm_route audio_map[] = {
521 /* Analog bypass */
522 {"Analog Left Bypass", "Switch", "LINEL"},
523 {"Analog Right Bypass", "Switch", "LINER"},
524
525 {"Output Left Amp Power", NULL, "DACL"},
526 {"Output Right Amp Power", NULL, "DACR"},
527
528 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
529 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
530
531 /* output */
532 {"LEFT_LO", NULL, "Output Left Amp Power"},
533 {"RIGHT_LO", NULL, "Output Right Amp Power"},
534};
535
536static int dac33_add_widgets(struct snd_soc_codec *codec)
537{
538 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
539 ARRAY_SIZE(dac33_dapm_widgets));
540
541 /* set up audio path interconnects */
542 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 543
544 return 0;
545}
546
547static int dac33_set_bias_level(struct snd_soc_codec *codec,
548 enum snd_soc_bias_level level)
549{
3a7aaed7
IK		 550 int ret;
551
c8bf93f0
PU		 552 switch (level) {
553 case SND_SOC_BIAS_ON:
554 dac33_soft_power(codec, 1);
555 break;
556 case SND_SOC_BIAS_PREPARE:
557 break;
558 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 559 if (codec->bias_level == SND_SOC_BIAS_OFF) {
560 ret = dac33_hard_power(codec, 1);
561 if (ret != 0)
562 return ret;
563 }
564
c8bf93f0
PU		 565 dac33_soft_power(codec, 0);
566 break;
567 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 568 ret = dac33_hard_power(codec, 0);
569 if (ret != 0)
570 return ret;
571
c8bf93f0
PU		 572 break;
573 }
574 codec->bias_level = level;
575
576 return 0;
577}
578
d4f102d4
PU		 579static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
580{
581 struct snd_soc_codec *codec;
582
583 codec = &dac33->codec;
584
585 switch (dac33->fifo_mode) {
586 case DAC33_FIFO_MODE1:
587 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 588 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
f57d2cfa
PU		 589
590 /* Take the timestamps */
591 spin_lock_irq(&dac33->lock);
592 dac33->t_stamp2 = ktime_to_us(ktime_get());
593 dac33->t_stamp1 = dac33->t_stamp2;
594 spin_unlock_irq(&dac33->lock);
595
d4f102d4
PU		 596 dac33_write16(codec, DAC33_PREFILL_MSB,
597 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 598 /* Enable Alarm Threshold IRQ with a delay */
599 udelay(SAMPLES_TO_US(dac33->burst_rate,
600 dac33->alarm_threshold));
601 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 602 break;
28e05d98 603 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 604 /* Take the timestamp */
605 spin_lock_irq(&dac33->lock);
606 dac33->t_stamp1 = ktime_to_us(ktime_get());
607 /* Move back the timestamp with drain time */
608 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
609 spin_unlock_irq(&dac33->lock);
610
28e05d98 611 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 612 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 613
614 /* Enable Upper Threshold IRQ */
615 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 616 break;
d4f102d4
PU		 617 default:
618 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
619 dac33->fifo_mode);
620 break;
621 }
622}
623
624static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
625{
626 struct snd_soc_codec *codec;
627
628 codec = &dac33->codec;
629
630 switch (dac33->fifo_mode) {
631 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 632 /* Take the timestamp */
633 spin_lock_irq(&dac33->lock);
634 dac33->t_stamp2 = ktime_to_us(ktime_get());
635 spin_unlock_irq(&dac33->lock);
636
d4f102d4
PU		 637 dac33_write16(codec, DAC33_NSAMPLE_MSB,
638 DAC33_THRREG(dac33->nsample));
639 break;
28e05d98
PU		 640 case DAC33_FIFO_MODE7:
641 /* At the moment we are not using interrupts in mode7 */
642 break;
d4f102d4
PU		 643 default:
644 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
645 dac33->fifo_mode);
646 break;
647 }
648}
649
c8bf93f0
PU		 650static void dac33_work(struct work_struct *work)
651{
652 struct snd_soc_codec *codec;
653 struct tlv320dac33_priv *dac33;
654 u8 reg;
655
656 dac33 = container_of(work, struct tlv320dac33_priv, work);
657 codec = &dac33->codec;
658
659 mutex_lock(&dac33->mutex);
660 switch (dac33->state) {
661 case DAC33_PREFILL:
662 dac33->state = DAC33_PLAYBACK;
d4f102d4 663 dac33_prefill_handler(dac33);
c8bf93f0
PU		 664 break;
665 case DAC33_PLAYBACK:
d4f102d4 666 dac33_playback_handler(dac33);
c8bf93f0
PU		 667 break;
668 case DAC33_IDLE:
669 break;
670 case DAC33_FLUSH:
671 dac33->state = DAC33_IDLE;
672 /* Mask all interrupts from dac33 */
673 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
674
675 /* flush fifo */
676 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
677 reg |= DAC33_FIFOFLUSH;
678 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
679 break;
680 }
681 mutex_unlock(&dac33->mutex);
682}
683
684static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
685{
686 struct snd_soc_codec *codec = dev;
b2c812e2 687 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 688
f57d2cfa
PU		 689 spin_lock(&dac33->lock);
690 dac33->t_stamp1 = ktime_to_us(ktime_get());
691 spin_unlock(&dac33->lock);
692
693 /* Do not schedule the workqueue in Mode7 */
694 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
695 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0
PU		 696
697 return IRQ_HANDLED;
698}
699
c8bf93f0
PU		 700static void dac33_oscwait(struct snd_soc_codec *codec)
701{
702 int timeout = 20;
703 u8 reg;
704
705 do {
706 msleep(1);
707 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
708 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
709 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
710 dev_err(codec->dev,
711 "internal oscillator calibration failed\n");
712}
713
714static int dac33_hw_params(struct snd_pcm_substream *substream,
715 struct snd_pcm_hw_params *params,
716 struct snd_soc_dai *dai)
717{
718 struct snd_soc_pcm_runtime *rtd = substream->private_data;
719 struct snd_soc_device *socdev = rtd->socdev;
720 struct snd_soc_codec *codec = socdev->card->codec;
721
722 /* Check parameters for validity */
723 switch (params_rate(params)) {
724 case 44100:
725 case 48000:
726 break;
727 default:
728 dev_err(codec->dev, "unsupported rate %d\n",
729 params_rate(params));
730 return -EINVAL;
731 }
732
733 switch (params_format(params)) {
734 case SNDRV_PCM_FORMAT_S16_LE:
735 break;
736 default:
737 dev_err(codec->dev, "unsupported format %d\n",
738 params_format(params));
739 return -EINVAL;
740 }
741
742 return 0;
743}
744
745#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 746 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 747#define CALC_RATIOSET(rate, refclk) ( \
748 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
749
750/*
751 * tlv320dac33 is strict on the sequence of the register writes, if the register
752 * writes happens in different order, than dac33 might end up in unknown state.
753 * Use the known, working sequence of register writes to initialize the dac33.
754 */
755static int dac33_prepare_chip(struct snd_pcm_substream *substream)
756{
757 struct snd_soc_pcm_runtime *rtd = substream->private_data;
758 struct snd_soc_device *socdev = rtd->socdev;
759 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 760 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 761 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 762 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 763
764 switch (substream->runtime->rate) {
765 case 44100:
766 case 48000:
767 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
768 ratioset = CALC_RATIOSET(substream->runtime->rate,
769 dac33->refclk);
770 break;
771 default:
772 dev_err(codec->dev, "unsupported rate %d\n",
773 substream->runtime->rate);
774 return -EINVAL;
775 }
776
777
778 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
779 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 780 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 781 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 782 fifoctrl_a &= ~DAC33_FIFOFLUSH;
783
c8bf93f0
PU		 784 fifoctrl_a &= ~DAC33_WIDTH;
785 switch (substream->runtime->format) {
786 case SNDRV_PCM_FORMAT_S16_LE:
787 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
788 fifoctrl_a |= DAC33_WIDTH;
789 break;
790 default:
791 dev_err(codec->dev, "unsupported format %d\n",
792 substream->runtime->format);
793 return -EINVAL;
794 }
795
796 mutex_lock(&dac33->mutex);
c3746a07 797 dac33_soft_power(codec, 0);
c8bf93f0
PU		 798 dac33_soft_power(codec, 1);
799
800 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
801 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
802
803 /* Write registers 0x08 and 0x09 (MSB, LSB) */
804 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
805
806 /* calib time: 128 is a nice number ;) */
807 dac33_write(codec, DAC33_CALIB_TIME, 128);
808
809 /* adjustment treshold & step */
810 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
811 DAC33_ADJSTEP(1));
812
813 /* div=4 / gain=1 / div */
814 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
815
816 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
817 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
818 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
819
820 dac33_oscwait(codec);
821
7427b4b9 822 if (dac33->fifo_mode) {
aec242dc 823 /* Generic for all FIFO modes */
c8bf93f0 824 /* 50-51 : ASRC Control registers */
fdb6b1e1 825 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 826 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
827
828 /* Write registers 0x34 and 0x35 (MSB, LSB) */
829 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
830
831 /* Set interrupts to high active */
832 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 833 } else {
aec242dc 834 /* FIFO bypass mode */
c8bf93f0
PU		 835 /* 50-51 : ASRC Control registers */
836 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
837 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
838 }
839
aec242dc
PU		 840 /* Interrupt behaviour configuration */
841 switch (dac33->fifo_mode) {
842 case DAC33_FIFO_MODE1:
843 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
844 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 845 break;
28e05d98 846 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 847 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
848 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 849 break;
aec242dc
PU		 850 default:
851 /* in FIFO bypass mode, the interrupts are not used */
852 break;
853 }
854
855 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
856
857 switch (dac33->fifo_mode) {
858 case DAC33_FIFO_MODE1:
859 /*
860 * For mode1:
861 * Disable the FIFO bypass (Enable the use of FIFO)
862 * Select nSample mode
863 * BCLK is only running when data is needed by DAC33
864 */
c8bf93f0 865 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 866 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 867 if (dac33->keep_bclk)
868 aictrl_b |= DAC33_BCLKON;
869 else
870 aictrl_b &= ~DAC33_BCLKON;
aec242dc 871 break;
28e05d98
PU		 872 case DAC33_FIFO_MODE7:
873 /*
874 * For mode1:
875 * Disable the FIFO bypass (Enable the use of FIFO)
876 * Select Threshold mode
877 * BCLK is only running when data is needed by DAC33
878 */
879 fifoctrl_a &= ~DAC33_FBYPAS;
880 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 881 if (dac33->keep_bclk)
882 aictrl_b |= DAC33_BCLKON;
883 else
884 aictrl_b &= ~DAC33_BCLKON;
28e05d98 885 break;
aec242dc
PU		 886 default:
887 /*
888 * For FIFO bypass mode:
889 * Enable the FIFO bypass (Disable the FIFO use)
890 * Set the BCLK as continous
891 */
c8bf93f0 892 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 893 aictrl_b |= DAC33_BCLKON;
894 break;
895 }
c8bf93f0 896
aec242dc 897 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 898 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 899 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 900
6aceabb4
PU		 901 /*
902 * BCLK divide ratio
903 * 0: 1.5
904 * 1: 1
905 * 2: 2
906 * ...
907 * 254: 254
908 * 255: 255
909 */
6cd6cede 910 if (dac33->fifo_mode)
6aceabb4
PU		 911 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
912 dac33->burst_bclkdiv);
6cd6cede
PU		 913 else
914 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 915
6cd6cede
PU		 916 switch (dac33->fifo_mode) {
917 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 918 dac33_write16(codec, DAC33_ATHR_MSB,
919 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 920 break;
28e05d98
PU		 921 case DAC33_FIFO_MODE7:
922 /*
923 * Configure the threshold levels, and leave 10 sample space
924 * at the bottom, and also at the top of the FIFO
925 */
4260393e
PU		 926 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
927 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 928 break;
aec242dc 929 default:
aec242dc 930 break;
c8bf93f0
PU		 931 }
932
933 mutex_unlock(&dac33->mutex);
934
935 return 0;
936}
937
938static void dac33_calculate_times(struct snd_pcm_substream *substream)
939{
940 struct snd_soc_pcm_runtime *rtd = substream->private_data;
941 struct snd_soc_device *socdev = rtd->socdev;
942 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 943 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 944 unsigned int nsample_limit;
945
55abb59c
PU		 946 /* In bypass mode we don't need to calculate */
947 if (!dac33->fifo_mode)
948 return;
949
c8bf93f0
PU		 950 /* Number of samples (16bit, stereo) in one period */
951 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
952
953 /* Number of samples (16bit, stereo) in ALSA buffer */
954 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
955 /* Subtract one period from the total */
956 dac33->nsample_max -= dac33->nsample_min;
957
958 /* Number of samples for LATENCY_TIME_MS / 2 */
959 dac33->alarm_threshold = substream->runtime->rate /
960 (1000 / (LATENCY_TIME_MS / 2));
961
962 /* Find and fix up the lowest nsmaple limit */
963 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
964
965 if (dac33->nsample_min < nsample_limit)
966 dac33->nsample_min = nsample_limit;
967
968 if (dac33->nsample < dac33->nsample_min)
969 dac33->nsample = dac33->nsample_min;
970
971 /*
972 * Find and fix up the highest nsmaple limit
973 * In order to not overflow the DAC33 buffer substract the
974 * alarm_threshold value from the size of the DAC33 buffer
975 */
976 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
977
978 if (dac33->nsample_max > nsample_limit)
979 dac33->nsample_max = nsample_limit;
980
981 if (dac33->nsample > dac33->nsample_max)
982 dac33->nsample = dac33->nsample_max;
f57d2cfa
PU		 983
984 switch (dac33->fifo_mode) {
985 case DAC33_FIFO_MODE1:
986 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
987 dac33->nsample);
988 dac33->t_stamp1 = 0;
989 dac33->t_stamp2 = 0;
990 break;
991 case DAC33_FIFO_MODE7:
992 dac33->mode7_us_to_lthr =
993 SAMPLES_TO_US(substream->runtime->rate,
994 MODE7_UTHR - MODE7_LTHR + 1);
995 dac33->t_stamp1 = 0;
996 break;
997 default:
998 break;
999 }
1000
c8bf93f0
PU		 1001}
1002
1003static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
1004 struct snd_soc_dai *dai)
1005{
1006 dac33_calculate_times(substream);
1007 dac33_prepare_chip(substream);
1008
1009 return 0;
1010}
1011
1012static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1013 struct snd_soc_dai *dai)
1014{
1015 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1016 struct snd_soc_device *socdev = rtd->socdev;
1017 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1018 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1019 int ret = 0;
1020
1021 switch (cmd) {
1022 case SNDRV_PCM_TRIGGER_START:
1023 case SNDRV_PCM_TRIGGER_RESUME:
1024 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1025 if (dac33->fifo_mode) {
c8bf93f0
PU		 1026 dac33->state = DAC33_PREFILL;
1027 queue_work(dac33->dac33_wq, &dac33->work);
1028 }
1029 break;
1030 case SNDRV_PCM_TRIGGER_STOP:
1031 case SNDRV_PCM_TRIGGER_SUSPEND:
1032 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1033 if (dac33->fifo_mode) {
c8bf93f0
PU		 1034 dac33->state = DAC33_FLUSH;
1035 queue_work(dac33->dac33_wq, &dac33->work);
1036 }
1037 break;
1038 default:
1039 ret = -EINVAL;
1040 }
1041
1042 return ret;
1043}
1044
f57d2cfa
PU		 1045static snd_pcm_sframes_t dac33_dai_delay(
1046 struct snd_pcm_substream *substream,
1047 struct snd_soc_dai *dai)
1048{
1049 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1050 struct snd_soc_device *socdev = rtd->socdev;
1051 struct snd_soc_codec *codec = socdev->card->codec;
1052 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1053 unsigned long long t0, t1, t_now;
1054 unsigned int time_delta;
1055 int samples_out, samples_in, samples;
1056 snd_pcm_sframes_t delay = 0;
1057
1058 switch (dac33->fifo_mode) {
1059 case DAC33_FIFO_BYPASS:
1060 break;
1061 case DAC33_FIFO_MODE1:
1062 spin_lock(&dac33->lock);
1063 t0 = dac33->t_stamp1;
1064 t1 = dac33->t_stamp2;
1065 spin_unlock(&dac33->lock);
1066 t_now = ktime_to_us(ktime_get());
1067
1068 /* We have not started to fill the FIFO yet, delay is 0 */
1069 if (!t1)
1070 goto out;
1071
1072 if (t0 > t1) {
1073 /*
1074 * Phase 1:
1075 * After Alarm threshold, and before nSample write
1076 */
1077 time_delta = t_now - t0;
1078 samples_out = time_delta ? US_TO_SAMPLES(
1079 substream->runtime->rate,
1080 time_delta) : 0;
1081
1082 if (likely(dac33->alarm_threshold > samples_out))
1083 delay = dac33->alarm_threshold - samples_out;
1084 else
1085 delay = 0;
1086 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1087 /*
1088 * Phase 2:
1089 * After nSample write (during burst operation)
1090 */
1091 time_delta = t_now - t0;
1092 samples_out = time_delta ? US_TO_SAMPLES(
1093 substream->runtime->rate,
1094 time_delta) : 0;
1095
1096 time_delta = t_now - t1;
1097 samples_in = time_delta ? US_TO_SAMPLES(
1098 dac33->burst_rate,
1099 time_delta) : 0;
1100
1101 samples = dac33->alarm_threshold;
1102 samples += (samples_in - samples_out);
1103
1104 if (likely(samples > 0))
1105 delay = samples;
1106 else
1107 delay = 0;
1108 } else {
1109 /*
1110 * Phase 3:
1111 * After burst operation, before next alarm threshold
1112 */
1113 time_delta = t_now - t0;
1114 samples_out = time_delta ? US_TO_SAMPLES(
1115 substream->runtime->rate,
1116 time_delta) : 0;
1117
1118 samples_in = dac33->nsample;
1119 samples = dac33->alarm_threshold;
1120 samples += (samples_in - samples_out);
1121
1122 if (likely(samples > 0))
1123 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1124 DAC33_BUFFER_SIZE_SAMPLES : samples;
1125 else
1126 delay = 0;
1127 }
1128 break;
1129 case DAC33_FIFO_MODE7:
1130 spin_lock(&dac33->lock);
1131 t0 = dac33->t_stamp1;
1132 spin_unlock(&dac33->lock);
1133 t_now = ktime_to_us(ktime_get());
1134
1135 /* We have not started to fill the FIFO yet, delay is 0 */
1136 if (!t0)
1137 goto out;
1138
1139 if (t_now <= t0) {
1140 /*
1141 * Either the timestamps are messed or equal. Report
1142 * maximum delay
1143 */
1144 delay = MODE7_UTHR;
1145 goto out;
1146 }
1147
1148 time_delta = t_now - t0;
1149 if (time_delta <= dac33->mode7_us_to_lthr) {
1150 /*
1151 * Phase 1:
1152 * After burst (draining phase)
1153 */
1154 samples_out = US_TO_SAMPLES(
1155 substream->runtime->rate,
1156 time_delta);
1157
1158 if (likely(MODE7_UTHR > samples_out))
1159 delay = MODE7_UTHR - samples_out;
1160 else
1161 delay = 0;
1162 } else {
1163 /*
1164 * Phase 2:
1165 * During burst operation
1166 */
1167 time_delta = time_delta - dac33->mode7_us_to_lthr;
1168
1169 samples_out = US_TO_SAMPLES(
1170 substream->runtime->rate,
1171 time_delta);
1172 samples_in = US_TO_SAMPLES(
1173 dac33->burst_rate,
1174 time_delta);
1175 delay = MODE7_LTHR + samples_in - samples_out;
1176
1177 if (unlikely(delay > MODE7_UTHR))
1178 delay = MODE7_UTHR;
1179 }
1180 break;
1181 default:
1182 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1183 dac33->fifo_mode);
1184 break;
1185 }
1186out:
1187 return delay;
1188}
1189
c8bf93f0
PU		 1190static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1191 int clk_id, unsigned int freq, int dir)
1192{
1193 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1194 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1195 u8 ioc_reg, asrcb_reg;
1196
1197 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1198 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1199 switch (clk_id) {
1200 case TLV320DAC33_MCLK:
1201 ioc_reg |= DAC33_REFSEL;
1202 asrcb_reg |= DAC33_SRCREFSEL;
1203 break;
1204 case TLV320DAC33_SLEEPCLK:
1205 ioc_reg &= ~DAC33_REFSEL;
1206 asrcb_reg &= ~DAC33_SRCREFSEL;
1207 break;
1208 default:
1209 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1210 break;
1211 }
1212 dac33->refclk = freq;
1213
1214 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1215 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1216
1217 return 0;
1218}
1219
1220static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1221 unsigned int fmt)
1222{
1223 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1224 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1225 u8 aictrl_a, aictrl_b;
1226
1227 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1228 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1229 /* set master/slave audio interface */
1230 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1231 case SND_SOC_DAIFMT_CBM_CFM:
1232 /* Codec Master */
1233 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1234 break;
1235 case SND_SOC_DAIFMT_CBS_CFS:
1236 /* Codec Slave */
adcb8bc0
PU		 1237 if (dac33->fifo_mode) {
1238 dev_err(codec->dev, "FIFO mode requires master mode\n");
1239 return -EINVAL;
1240 } else
1241 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1242 break;
1243 default:
1244 return -EINVAL;
1245 }
1246
1247 aictrl_a &= ~DAC33_AFMT_MASK;
1248 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1249 case SND_SOC_DAIFMT_I2S:
1250 aictrl_a |= DAC33_AFMT_I2S;
1251 break;
1252 case SND_SOC_DAIFMT_DSP_A:
1253 aictrl_a |= DAC33_AFMT_DSP;
1254 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1255 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1256 break;
1257 case SND_SOC_DAIFMT_RIGHT_J:
1258 aictrl_a |= DAC33_AFMT_RIGHT_J;
1259 break;
1260 case SND_SOC_DAIFMT_LEFT_J:
1261 aictrl_a |= DAC33_AFMT_LEFT_J;
1262 break;
1263 default:
1264 dev_err(codec->dev, "Unsupported format (%u)\n",
1265 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1266 return -EINVAL;
1267 }
1268
1269 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1270 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1271
1272 return 0;
1273}
1274
c8bf93f0
PU		 1275static int dac33_soc_probe(struct platform_device *pdev)
1276{
1277 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1278 struct snd_soc_codec *codec;
1279 struct tlv320dac33_priv *dac33;
1280 int ret = 0;
1281
1282 BUG_ON(!tlv320dac33_codec);
1283
1284 codec = tlv320dac33_codec;
1285 socdev->card->codec = codec;
b2c812e2 1286 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1287
1288 /* Power up the codec */
1289 dac33_hard_power(codec, 1);
c8bf93f0
PU		 1290
1291 /* register pcms */
1292 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1293 if (ret < 0) {
1294 dev_err(codec->dev, "failed to create pcms\n");
1295 goto pcm_err;
1296 }
1297
1298 snd_soc_add_controls(codec, dac33_snd_controls,
1299 ARRAY_SIZE(dac33_snd_controls));
1300 /* Only add the nSample controls, if we have valid IRQ number */
1301 if (dac33->irq >= 0)
1302 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1303 ARRAY_SIZE(dac33_nsample_snd_controls));
1304
1305 dac33_add_widgets(codec);
1306
1307 /* power on device */
1308 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1309
3a7aaed7
IK		 1310 /* Bias level configuration has enabled regulator an extra time */
1311 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1312
c8bf93f0 1313 return 0;
fe3e78e0 1314
c8bf93f0
PU		 1315pcm_err:
1316 dac33_hard_power(codec, 0);
1317 return ret;
1318}
1319
1320static int dac33_soc_remove(struct platform_device *pdev)
1321{
1322 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1323 struct snd_soc_codec *codec = socdev->card->codec;
1324
1325 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1326
1327 snd_soc_free_pcms(socdev);
1328 snd_soc_dapm_free(socdev);
1329
1330 return 0;
1331}
1332
1333static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1334{
1335 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1336 struct snd_soc_codec *codec = socdev->card->codec;
1337
1338 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1339
1340 return 0;
1341}
1342
1343static int dac33_soc_resume(struct platform_device *pdev)
1344{
1345 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1346 struct snd_soc_codec *codec = socdev->card->codec;
1347
1348 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1349 dac33_set_bias_level(codec, codec->suspend_bias_level);
1350
1351 return 0;
1352}
1353
1354struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1355 .probe = dac33_soc_probe,
1356 .remove = dac33_soc_remove,
1357 .suspend = dac33_soc_suspend,
1358 .resume = dac33_soc_resume,
1359};
1360EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1361
1362#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1363 SNDRV_PCM_RATE_48000)
1364#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1365
1366static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1367 .hw_params = dac33_hw_params,
1368 .prepare = dac33_pcm_prepare,
1369 .trigger = dac33_pcm_trigger,
f57d2cfa 1370 .delay = dac33_dai_delay,
c8bf93f0
PU		 1371 .set_sysclk = dac33_set_dai_sysclk,
1372 .set_fmt = dac33_set_dai_fmt,
1373};
1374
1375struct snd_soc_dai dac33_dai = {
1376 .name = "tlv320dac33",
1377 .playback = {
1378 .stream_name = "Playback",
1379 .channels_min = 2,
1380 .channels_max = 2,
1381 .rates = DAC33_RATES,
1382 .formats = DAC33_FORMATS,},
1383 .ops = &dac33_dai_ops,
1384};
1385EXPORT_SYMBOL_GPL(dac33_dai);
1386
735fe4cf
MB		 1387static int __devinit dac33_i2c_probe(struct i2c_client *client,
1388 const struct i2c_device_id *id)
c8bf93f0
PU		 1389{
1390 struct tlv320dac33_platform_data *pdata;
1391 struct tlv320dac33_priv *dac33;
1392 struct snd_soc_codec *codec;
3a7aaed7 1393 int ret, i;
c8bf93f0
PU		 1394
1395 if (client->dev.platform_data == NULL) {
1396 dev_err(&client->dev, "Platform data not set\n");
1397 return -ENODEV;
1398 }
1399 pdata = client->dev.platform_data;
1400
1401 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1402 if (dac33 == NULL)
1403 return -ENOMEM;
1404
1405 codec = &dac33->codec;
b2c812e2 1406 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1407 codec->control_data = client;
1408
1409 mutex_init(&codec->mutex);
1410 mutex_init(&dac33->mutex);
f57d2cfa 1411 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1412 INIT_LIST_HEAD(&codec->dapm_widgets);
1413 INIT_LIST_HEAD(&codec->dapm_paths);
1414
1415 codec->name = "tlv320dac33";
1416 codec->owner = THIS_MODULE;
1417 codec->read = dac33_read_reg_cache;
1418 codec->write = dac33_write_locked;
1419 codec->hw_write = (hw_write_t) i2c_master_send;
1420 codec->bias_level = SND_SOC_BIAS_OFF;
1421 codec->set_bias_level = dac33_set_bias_level;
1422 codec->dai = &dac33_dai;
1423 codec->num_dai = 1;
1424 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1425 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1426 GFP_KERNEL);
1427 if (codec->reg_cache == NULL) {
1428 ret = -ENOMEM;
1429 goto error_reg;
1430 }
1431
1432 i2c_set_clientdata(client, dac33);
1433
1434 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1435 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1436 /* Pre calculate the burst rate */
1437 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1438 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1439 dac33->irq = client->irq;
1440 dac33->nsample = NSAMPLE_MAX;
55abb59c 1441 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1442 /* Disable FIFO use by default */
7427b4b9 1443 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1444
1445 tlv320dac33_codec = codec;
1446
1447 codec->dev = &client->dev;
1448 dac33_dai.dev = codec->dev;
1449
1450 /* Check if the reset GPIO number is valid and request it */
1451 if (dac33->power_gpio >= 0) {
1452 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1453 if (ret < 0) {
1454 dev_err(codec->dev,
1455 "Failed to request reset GPIO (%d)\n",
1456 dac33->power_gpio);
1457 snd_soc_unregister_dai(&dac33_dai);
1458 snd_soc_unregister_codec(codec);
1459 goto error_gpio;
1460 }
1461 gpio_direction_output(dac33->power_gpio, 0);
1462 } else {
1463 dac33->chip_power = 1;
1464 }
1465
1466 /* Check if the IRQ number is valid and request it */
1467 if (dac33->irq >= 0) {
1468 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1469 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1470 codec->name, codec);
1471 if (ret < 0) {
1472 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1473 dac33->irq, ret);
1474 dac33->irq = -1;
1475 }
1476 if (dac33->irq != -1) {
1477 /* Setup work queue */
74ea23aa
PU		 1478 dac33->dac33_wq =
1479 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1480 if (dac33->dac33_wq == NULL) {
1481 free_irq(dac33->irq, &dac33->codec);
1482 ret = -ENOMEM;
1483 goto error_wq;
1484 }
1485
1486 INIT_WORK(&dac33->work, dac33_work);
1487 }
1488 }
1489
3a7aaed7
IK		 1490 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1491 dac33->supplies[i].supply = dac33_supply_names[i];
1492
1493 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1494 dac33->supplies);
1495
1496 if (ret != 0) {
1497 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1498 goto err_get;
1499 }
1500
1501 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1502 dac33->supplies);
1503 if (ret != 0) {
1504 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1505 goto err_enable;
1506 }
1507
c8bf93f0
PU		 1508 ret = snd_soc_register_codec(codec);
1509 if (ret != 0) {
1510 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1511 goto error_codec;
1512 }
1513
1514 ret = snd_soc_register_dai(&dac33_dai);
1515 if (ret != 0) {
1516 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1517 snd_soc_unregister_codec(codec);
1518 goto error_codec;
1519 }
1520
1521 /* Shut down the codec for now */
1522 dac33_hard_power(codec, 0);
1523
1524 return ret;
1525
1526error_codec:
3a7aaed7
IK		 1527 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1528err_enable:
1529 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1530err_get:
c8bf93f0
PU		 1531 if (dac33->irq >= 0) {
1532 free_irq(dac33->irq, &dac33->codec);
1533 destroy_workqueue(dac33->dac33_wq);
1534 }
1535error_wq:
1536 if (dac33->power_gpio >= 0)
1537 gpio_free(dac33->power_gpio);
1538error_gpio:
1539 kfree(codec->reg_cache);
1540error_reg:
1541 tlv320dac33_codec = NULL;
1542 kfree(dac33);
1543
1544 return ret;
1545}
1546
735fe4cf 1547static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1548{
1549 struct tlv320dac33_priv *dac33;
1550
1551 dac33 = i2c_get_clientdata(client);
1552 dac33_hard_power(&dac33->codec, 0);
1553
1554 if (dac33->power_gpio >= 0)
1555 gpio_free(dac33->power_gpio);
1556 if (dac33->irq >= 0)
1557 free_irq(dac33->irq, &dac33->codec);
1558
cf134d5b 1559 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
3a7aaed7
IK		 1560 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1561
c8bf93f0
PU		 1562 destroy_workqueue(dac33->dac33_wq);
1563 snd_soc_unregister_dai(&dac33_dai);
1564 snd_soc_unregister_codec(&dac33->codec);
1565 kfree(dac33->codec.reg_cache);
1566 kfree(dac33);
1567 tlv320dac33_codec = NULL;
1568
1569 return 0;
1570}
1571
1572static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1573 {
1574 .name = "tlv320dac33",
1575 .driver_data = 0,
1576 },
1577 { },
1578};
1579
1580static struct i2c_driver tlv320dac33_i2c_driver = {
1581 .driver = {
1582 .name = "tlv320dac33",
1583 .owner = THIS_MODULE,
1584 },
1585 .probe = dac33_i2c_probe,
1586 .remove = __devexit_p(dac33_i2c_remove),
1587 .id_table = tlv320dac33_i2c_id,
1588};
1589
1590static int __init dac33_module_init(void)
1591{
1592 int r;
1593 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1594 if (r < 0) {
1595 printk(KERN_ERR "DAC33: driver registration failed\n");
1596 return r;
1597 }
1598 return 0;
1599}
1600module_init(dac33_module_init);
1601
1602static void __exit dac33_module_exit(void)
1603{
1604 i2c_del_driver(&tlv320dac33_i2c_driver);
1605}
1606module_exit(dac33_module_exit);
1607
1608
1609MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1610MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1611MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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