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ASoC: tlv320dac33: Revisit the FIFO Mode1 handling
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h>
41#include <sound/tlv.h>
42
43#include <sound/tlv320dac33-plat.h>
44#include "tlv320dac33.h"
45
46#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 * 6144 stereo */
48#define DAC33_BUFFER_SIZE_SAMPLES 6144
49
50#define NSAMPLE_MAX 5700
51
4260393e
PU		 52#define MODE7_LTHR 10
53#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
54
76f47127
PU		 55#define BURST_BASEFREQ_HZ 49152000
56
f57d2cfa
PU		 57#define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60#define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / us))
62
ad05c03b
PU		 63static void dac33_calculate_times(struct snd_pcm_substream *substream);
64static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 65
c8bf93f0
PU		 66static struct snd_soc_codec *tlv320dac33_codec;
67
68enum dac33_state {
69 DAC33_IDLE = 0,
70 DAC33_PREFILL,
71 DAC33_PLAYBACK,
72 DAC33_FLUSH,
73};
74
7427b4b9
PU		 75enum dac33_fifo_modes {
76 DAC33_FIFO_BYPASS = 0,
77 DAC33_FIFO_MODE1,
28e05d98 78 DAC33_FIFO_MODE7,
7427b4b9
PU		 79 DAC33_FIFO_LAST_MODE,
80};
81
3a7aaed7
IK		 82#define DAC33_NUM_SUPPLIES 3
83static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
84 "AVDD",
85 "DVDD",
86 "IOVDD",
87};
88
c8bf93f0
PU		 89struct tlv320dac33_priv {
90 struct mutex mutex;
91 struct workqueue_struct *dac33_wq;
92 struct work_struct work;
93 struct snd_soc_codec codec;
3a7aaed7 94 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 95 struct snd_pcm_substream *substream;
c8bf93f0
PU		 96 int power_gpio;
97 int chip_power;
98 int irq;
99 unsigned int refclk;
100
101 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
102 unsigned int nsample_min; /* nsample should not be lower than
103 * this */
104 unsigned int nsample_max; /* nsample should not be higher than
105 * this */
7427b4b9 106 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 107 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 108 int mode1_latency; /* latency caused by the i2c writes in
109 * us */
6aceabb4 110 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 111 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 112
eeb309a8
PU		 113 int keep_bclk; /* Keep the BCLK continuously running
114 * in FIFO modes */
f57d2cfa
PU		 115 spinlock_t lock;
116 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
117 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
118
119 unsigned int mode1_us_burst; /* Time to burst read n number of
120 * samples */
121 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 122
9d7db2b2
PU		 123 unsigned int uthr;
124
c8bf93f0
PU		 125 enum dac33_state state;
126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 198 int val;
199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
208 } else {
209 value[0] = val;
210 dac33_write_reg_cache(codec, reg, val);
211 }
212 } else {
213 value[0] = dac33_read_reg_cache(codec, reg);
214 }
215
216 return 0;
217}
218
219static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
220 unsigned int value)
221{
b2c812e2 222 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 223 u8 data[2];
224 int ret = 0;
225
226 /*
227 * data is
228 * D15..D8 dac33 register offset
229 * D7...D0 register data
230 */
231 data[0] = reg & 0xff;
232 data[1] = value & 0xff;
233
234 dac33_write_reg_cache(codec, data[0], data[1]);
235 if (dac33->chip_power) {
236 ret = codec->hw_write(codec->control_data, data, 2);
237 if (ret != 2)
238 dev_err(codec->dev, "Write failed (%d)\n", ret);
239 else
240 ret = 0;
241 }
242
243 return ret;
244}
245
246static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
247 unsigned int value)
248{
b2c812e2 249 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 250 int ret;
251
252 mutex_lock(&dac33->mutex);
253 ret = dac33_write(codec, reg, value);
254 mutex_unlock(&dac33->mutex);
255
256 return ret;
257}
258
259#define DAC33_I2C_ADDR_AUTOINC 0x80
260static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
261 unsigned int value)
262{
b2c812e2 263 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 264 u8 data[3];
265 int ret = 0;
266
267 /*
268 * data is
269 * D23..D16 dac33 register offset
270 * D15..D8 register data MSB
271 * D7...D0 register data LSB
272 */
273 data[0] = reg & 0xff;
274 data[1] = (value >> 8) & 0xff;
275 data[2] = value & 0xff;
276
277 dac33_write_reg_cache(codec, data[0], data[1]);
278 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
279
280 if (dac33->chip_power) {
281 /* We need to set autoincrement mode for 16 bit writes */
282 data[0] |= DAC33_I2C_ADDR_AUTOINC;
283 ret = codec->hw_write(codec->control_data, data, 3);
284 if (ret != 3)
285 dev_err(codec->dev, "Write failed (%d)\n", ret);
286 else
287 ret = 0;
288 }
289
290 return ret;
291}
292
ef909d67 293static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 294{
b2c812e2 295 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 296
ef909d67 297 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 298 return;
299
ef909d67
PU		 300 /* 44-46: DAC Control Registers */
301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
ef909d67
PU		 309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
ef909d67
PU		 313 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
314
315 /* Restore only selected registers (gains mostly) */
316 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
318 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
319 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
320
321 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
323 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
324 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 325}
326
239fe55c
PU		 327static inline void dac33_read_id(struct snd_soc_codec *codec)
328{
329 u8 reg;
330
331 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
332 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
333 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
c8bf93f0
PU		 334}
335
336static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
337{
338 u8 reg;
339
340 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
341 if (power)
342 reg |= DAC33_PDNALLB;
343 else
c3746a07
PU		 344 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
345 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 346 dac33_write(codec, DAC33_PWR_CTRL, reg);
347}
348
3a7aaed7 349static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 350{
b2c812e2 351 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 352 int ret = 0;
c8bf93f0
PU		 353
354 mutex_lock(&dac33->mutex);
ad05c03b
PU		 355
356 /* Safety check */
357 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 358 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 359 power ? "ON" : "OFF");
360 goto exit;
361 }
362
c8bf93f0 363 if (power) {
3a7aaed7
IK		 364 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
365 dac33->supplies);
366 if (ret != 0) {
367 dev_err(codec->dev,
368 "Failed to enable supplies: %d\n", ret);
369 goto exit;
c8bf93f0 370 }
3a7aaed7
IK		 371
372 if (dac33->power_gpio >= 0)
373 gpio_set_value(dac33->power_gpio, 1);
374
375 dac33->chip_power = 1;
c8bf93f0
PU		 376 } else {
377 dac33_soft_power(codec, 0);
3a7aaed7 378 if (dac33->power_gpio >= 0)
c8bf93f0 379 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 380
381 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
382 dac33->supplies);
383 if (ret != 0) {
384 dev_err(codec->dev,
385 "Failed to disable supplies: %d\n", ret);
386 goto exit;
c8bf93f0 387 }
3a7aaed7
IK		 388
389 dac33->chip_power = 0;
c8bf93f0 390 }
c8bf93f0 391
3a7aaed7
IK		 392exit:
393 mutex_unlock(&dac33->mutex);
394 return ret;
c8bf93f0
PU		 395}
396
ad05c03b
PU		 397static int playback_event(struct snd_soc_dapm_widget *w,
398 struct snd_kcontrol *kcontrol, int event)
399{
400 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
401
402 switch (event) {
403 case SND_SOC_DAPM_PRE_PMU:
404 if (likely(dac33->substream)) {
405 dac33_calculate_times(dac33->substream);
406 dac33_prepare_chip(dac33->substream);
407 }
408 break;
409 }
410 return 0;
411}
412
c8bf93f0
PU		 413static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415{
416 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 417 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 418
419 ucontrol->value.integer.value[0] = dac33->nsample;
420
421 return 0;
422}
423
424static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426{
427 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 428 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 429 int ret = 0;
430
431 if (dac33->nsample == ucontrol->value.integer.value[0])
432 return 0;
433
434 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 435 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 436 ret = -EINVAL;
f57d2cfa 437 } else {
c8bf93f0 438 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 439 /* Re calculate the burst time */
440 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
441 dac33->nsample);
442 }
c8bf93f0
PU		 443
444 return ret;
445}
446
9d7db2b2
PU		 447static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
452
453 ucontrol->value.integer.value[0] = dac33->uthr;
454
455 return 0;
456}
457
458static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
463 int ret = 0;
464
465 if (dac33->substream)
466 return -EBUSY;
467
468 if (dac33->uthr == ucontrol->value.integer.value[0])
469 return 0;
470
471 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
472 ucontrol->value.integer.value[0] > MODE7_UTHR)
473 ret = -EINVAL;
474 else
475 dac33->uthr = ucontrol->value.integer.value[0];
476
477 return ret;
478}
479
7427b4b9 480static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 481 struct snd_ctl_elem_value *ucontrol)
482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 484 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 485
7427b4b9 486 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 487
488 return 0;
489}
490
7427b4b9 491static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 492 struct snd_ctl_elem_value *ucontrol)
493{
494 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 495 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 496 int ret = 0;
497
7427b4b9 498 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 499 return 0;
500 /* Do not allow changes while stream is running*/
501 if (codec->active)
502 return -EPERM;
503
504 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 505 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 506 ret = -EINVAL;
507 else
7427b4b9 508 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 509
510 return ret;
511}
512
7427b4b9
PU		 513/* Codec operation modes */
514static const char *dac33_fifo_mode_texts[] = {
28e05d98 515 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 516};
517
518static const struct soc_enum dac33_fifo_mode_enum =
519 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
520 dac33_fifo_mode_texts);
521
c8bf93f0
PU		 522/*
523 * DACL/R digital volume control:
524 * from 0 dB to -63.5 in 0.5 dB steps
525 * Need to be inverted later on:
526 * 0x00 == 0 dB
527 * 0x7f == -63.5 dB
528 */
529static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
530
531static const struct snd_kcontrol_new dac33_snd_controls[] = {
532 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
533 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
534 0, 0x7f, 1, dac_digivol_tlv),
535 SOC_DOUBLE_R("DAC Digital Playback Switch",
536 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
537 SOC_DOUBLE_R("Line to Line Out Volume",
538 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
539};
540
541static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
542 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
543 dac33_get_nsample, dac33_set_nsample),
9d7db2b2
PU		 544 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
545 dac33_get_uthr, dac33_set_uthr),
7427b4b9
PU		 546 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
547 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 548};
549
550/* Analog bypass */
551static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
552 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
553
554static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
555 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
556
557static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
558 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
559 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
560
561 SND_SOC_DAPM_INPUT("LINEL"),
562 SND_SOC_DAPM_INPUT("LINER"),
563
564 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
565 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
566
567 /* Analog bypass */
568 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
569 &dac33_dapm_abypassl_control),
570 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
571 &dac33_dapm_abypassr_control),
572
573 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
574 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
575 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
576 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b
PU		 577
578 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
c8bf93f0
PU		 579};
580
581static const struct snd_soc_dapm_route audio_map[] = {
582 /* Analog bypass */
583 {"Analog Left Bypass", "Switch", "LINEL"},
584 {"Analog Right Bypass", "Switch", "LINER"},
585
586 {"Output Left Amp Power", NULL, "DACL"},
587 {"Output Right Amp Power", NULL, "DACR"},
588
589 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
590 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
591
592 /* output */
593 {"LEFT_LO", NULL, "Output Left Amp Power"},
594 {"RIGHT_LO", NULL, "Output Right Amp Power"},
595};
596
597static int dac33_add_widgets(struct snd_soc_codec *codec)
598{
599 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
600 ARRAY_SIZE(dac33_dapm_widgets));
601
602 /* set up audio path interconnects */
603 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 604
605 return 0;
606}
607
608static int dac33_set_bias_level(struct snd_soc_codec *codec,
609 enum snd_soc_bias_level level)
610{
3a7aaed7
IK		 611 int ret;
612
c8bf93f0
PU		 613 switch (level) {
614 case SND_SOC_BIAS_ON:
615 dac33_soft_power(codec, 1);
616 break;
617 case SND_SOC_BIAS_PREPARE:
618 break;
619 case SND_SOC_BIAS_STANDBY:
3a7aaed7 620 if (codec->bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 621 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 622 ret = dac33_hard_power(codec, 1);
623 if (ret != 0)
624 return ret;
3a7aaed7 625
ad05c03b
PU		 626 dac33_init_chip(codec);
627 }
c8bf93f0
PU		 628 break;
629 case SND_SOC_BIAS_OFF:
2d4cdd6f
PU		 630 /* Do not power off, when the codec is already off */
631 if (codec->bias_level == SND_SOC_BIAS_OFF)
632 return 0;
3a7aaed7
IK		 633 ret = dac33_hard_power(codec, 0);
634 if (ret != 0)
635 return ret;
c8bf93f0
PU		 636 break;
637 }
638 codec->bias_level = level;
639
640 return 0;
641}
642
d4f102d4
PU		 643static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
644{
645 struct snd_soc_codec *codec;
646
647 codec = &dac33->codec;
648
649 switch (dac33->fifo_mode) {
650 case DAC33_FIFO_MODE1:
651 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 652 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 653
654 /* Take the timestamps */
655 spin_lock_irq(&dac33->lock);
656 dac33->t_stamp2 = ktime_to_us(ktime_get());
657 dac33->t_stamp1 = dac33->t_stamp2;
658 spin_unlock_irq(&dac33->lock);
659
d4f102d4
PU		 660 dac33_write16(codec, DAC33_PREFILL_MSB,
661 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 662 /* Enable Alarm Threshold IRQ with a delay */
663 udelay(SAMPLES_TO_US(dac33->burst_rate,
664 dac33->alarm_threshold));
665 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 666 break;
28e05d98 667 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 668 /* Take the timestamp */
669 spin_lock_irq(&dac33->lock);
670 dac33->t_stamp1 = ktime_to_us(ktime_get());
671 /* Move back the timestamp with drain time */
672 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
673 spin_unlock_irq(&dac33->lock);
674
28e05d98 675 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 676 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 677
678 /* Enable Upper Threshold IRQ */
679 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 680 break;
d4f102d4
PU		 681 default:
682 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
683 dac33->fifo_mode);
684 break;
685 }
686}
687
688static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
689{
690 struct snd_soc_codec *codec;
691
692 codec = &dac33->codec;
693
694 switch (dac33->fifo_mode) {
695 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 696 /* Take the timestamp */
697 spin_lock_irq(&dac33->lock);
698 dac33->t_stamp2 = ktime_to_us(ktime_get());
699 spin_unlock_irq(&dac33->lock);
700
d4f102d4
PU		 701 dac33_write16(codec, DAC33_NSAMPLE_MSB,
702 DAC33_THRREG(dac33->nsample));
703 break;
28e05d98
PU		 704 case DAC33_FIFO_MODE7:
705 /* At the moment we are not using interrupts in mode7 */
706 break;
d4f102d4
PU		 707 default:
708 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
709 dac33->fifo_mode);
710 break;
711 }
712}
713
c8bf93f0
PU		 714static void dac33_work(struct work_struct *work)
715{
716 struct snd_soc_codec *codec;
717 struct tlv320dac33_priv *dac33;
718 u8 reg;
719
720 dac33 = container_of(work, struct tlv320dac33_priv, work);
721 codec = &dac33->codec;
722
723 mutex_lock(&dac33->mutex);
724 switch (dac33->state) {
725 case DAC33_PREFILL:
726 dac33->state = DAC33_PLAYBACK;
d4f102d4 727 dac33_prefill_handler(dac33);
c8bf93f0
PU		 728 break;
729 case DAC33_PLAYBACK:
d4f102d4 730 dac33_playback_handler(dac33);
c8bf93f0
PU		 731 break;
732 case DAC33_IDLE:
733 break;
734 case DAC33_FLUSH:
735 dac33->state = DAC33_IDLE;
736 /* Mask all interrupts from dac33 */
737 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
738
739 /* flush fifo */
740 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
741 reg |= DAC33_FIFOFLUSH;
742 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
743 break;
744 }
745 mutex_unlock(&dac33->mutex);
746}
747
748static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
749{
750 struct snd_soc_codec *codec = dev;
b2c812e2 751 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 752
f57d2cfa
PU		 753 spin_lock(&dac33->lock);
754 dac33->t_stamp1 = ktime_to_us(ktime_get());
755 spin_unlock(&dac33->lock);
c8bf93f0 756
f57d2cfa
PU		 757 /* Do not schedule the workqueue in Mode7 */
758 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
759 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 760
c8bf93f0 761 return IRQ_HANDLED;
c8bf93f0
PU		 762}
763
764static void dac33_oscwait(struct snd_soc_codec *codec)
765{
766 int timeout = 20;
767 u8 reg;
768
769 do {
770 msleep(1);
771 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
772 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
773 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
774 dev_err(codec->dev,
775 "internal oscillator calibration failed\n");
776}
777
0b61d2b9
PU		 778static int dac33_startup(struct snd_pcm_substream *substream,
779 struct snd_soc_dai *dai)
780{
781 struct snd_soc_pcm_runtime *rtd = substream->private_data;
782 struct snd_soc_device *socdev = rtd->socdev;
783 struct snd_soc_codec *codec = socdev->card->codec;
784 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
785
786 /* Stream started, save the substream pointer */
787 dac33->substream = substream;
788
789 return 0;
790}
791
792static void dac33_shutdown(struct snd_pcm_substream *substream,
793 struct snd_soc_dai *dai)
794{
795 struct snd_soc_pcm_runtime *rtd = substream->private_data;
796 struct snd_soc_device *socdev = rtd->socdev;
797 struct snd_soc_codec *codec = socdev->card->codec;
798 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
799
800 dac33->substream = NULL;
f430a27f
PU		 801
802 /* Reset the nSample restrictions */
803 dac33->nsample_min = 0;
804 dac33->nsample_max = NSAMPLE_MAX;
0b61d2b9
PU		 805}
806
c8bf93f0
PU		 807static int dac33_hw_params(struct snd_pcm_substream *substream,
808 struct snd_pcm_hw_params *params,
809 struct snd_soc_dai *dai)
810{
811 struct snd_soc_pcm_runtime *rtd = substream->private_data;
812 struct snd_soc_device *socdev = rtd->socdev;
813 struct snd_soc_codec *codec = socdev->card->codec;
814
815 /* Check parameters for validity */
816 switch (params_rate(params)) {
817 case 44100:
818 case 48000:
819 break;
820 default:
821 dev_err(codec->dev, "unsupported rate %d\n",
822 params_rate(params));
823 return -EINVAL;
824 }
825
826 switch (params_format(params)) {
827 case SNDRV_PCM_FORMAT_S16_LE:
828 break;
829 default:
830 dev_err(codec->dev, "unsupported format %d\n",
831 params_format(params));
832 return -EINVAL;
833 }
834
835 return 0;
836}
837
838#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 839 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 840#define CALC_RATIOSET(rate, refclk) ( \
841 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
842
843/*
844 * tlv320dac33 is strict on the sequence of the register writes, if the register
845 * writes happens in different order, than dac33 might end up in unknown state.
846 * Use the known, working sequence of register writes to initialize the dac33.
847 */
848static int dac33_prepare_chip(struct snd_pcm_substream *substream)
849{
850 struct snd_soc_pcm_runtime *rtd = substream->private_data;
851 struct snd_soc_device *socdev = rtd->socdev;
852 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 853 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 854 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 855 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 856
857 switch (substream->runtime->rate) {
858 case 44100:
859 case 48000:
860 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
861 ratioset = CALC_RATIOSET(substream->runtime->rate,
862 dac33->refclk);
863 break;
864 default:
865 dev_err(codec->dev, "unsupported rate %d\n",
866 substream->runtime->rate);
867 return -EINVAL;
868 }
869
870
871 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
872 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 873 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 874 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 875 fifoctrl_a &= ~DAC33_FIFOFLUSH;
876
c8bf93f0
PU		 877 fifoctrl_a &= ~DAC33_WIDTH;
878 switch (substream->runtime->format) {
879 case SNDRV_PCM_FORMAT_S16_LE:
880 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
881 fifoctrl_a |= DAC33_WIDTH;
882 break;
883 default:
884 dev_err(codec->dev, "unsupported format %d\n",
885 substream->runtime->format);
886 return -EINVAL;
887 }
888
889 mutex_lock(&dac33->mutex);
ad05c03b
PU		 890
891 if (!dac33->chip_power) {
892 /*
893 * Chip is not powered yet.
894 * Do the init in the dac33_set_bias_level later.
895 */
896 mutex_unlock(&dac33->mutex);
897 return 0;
898 }
899
c3746a07 900 dac33_soft_power(codec, 0);
c8bf93f0
PU		 901 dac33_soft_power(codec, 1);
902
903 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
904 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
905
906 /* Write registers 0x08 and 0x09 (MSB, LSB) */
907 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
908
909 /* calib time: 128 is a nice number ;) */
910 dac33_write(codec, DAC33_CALIB_TIME, 128);
911
912 /* adjustment treshold & step */
913 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
914 DAC33_ADJSTEP(1));
915
916 /* div=4 / gain=1 / div */
917 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
918
919 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
920 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
921 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
922
923 dac33_oscwait(codec);
924
7427b4b9 925 if (dac33->fifo_mode) {
aec242dc 926 /* Generic for all FIFO modes */
c8bf93f0 927 /* 50-51 : ASRC Control registers */
fdb6b1e1 928 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 929 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
930
931 /* Write registers 0x34 and 0x35 (MSB, LSB) */
932 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
933
934 /* Set interrupts to high active */
935 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 936 } else {
aec242dc 937 /* FIFO bypass mode */
c8bf93f0
PU		 938 /* 50-51 : ASRC Control registers */
939 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
940 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
941 }
942
aec242dc
PU		 943 /* Interrupt behaviour configuration */
944 switch (dac33->fifo_mode) {
945 case DAC33_FIFO_MODE1:
946 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
947 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 948 break;
28e05d98 949 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 950 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
951 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 952 break;
aec242dc
PU		 953 default:
954 /* in FIFO bypass mode, the interrupts are not used */
955 break;
956 }
957
958 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
959
960 switch (dac33->fifo_mode) {
961 case DAC33_FIFO_MODE1:
962 /*
963 * For mode1:
964 * Disable the FIFO bypass (Enable the use of FIFO)
965 * Select nSample mode
966 * BCLK is only running when data is needed by DAC33
967 */
c8bf93f0 968 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 969 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 970 if (dac33->keep_bclk)
971 aictrl_b |= DAC33_BCLKON;
972 else
973 aictrl_b &= ~DAC33_BCLKON;
aec242dc 974 break;
28e05d98
PU		 975 case DAC33_FIFO_MODE7:
976 /*
977 * For mode1:
978 * Disable the FIFO bypass (Enable the use of FIFO)
979 * Select Threshold mode
980 * BCLK is only running when data is needed by DAC33
981 */
982 fifoctrl_a &= ~DAC33_FBYPAS;
983 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 984 if (dac33->keep_bclk)
985 aictrl_b |= DAC33_BCLKON;
986 else
987 aictrl_b &= ~DAC33_BCLKON;
28e05d98 988 break;
aec242dc
PU		 989 default:
990 /*
991 * For FIFO bypass mode:
992 * Enable the FIFO bypass (Disable the FIFO use)
993 * Set the BCLK as continous
994 */
c8bf93f0 995 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 996 aictrl_b |= DAC33_BCLKON;
997 break;
998 }
c8bf93f0 999
aec242dc 1000 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 1001 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 1002 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 1003
6aceabb4
PU		 1004 /*
1005 * BCLK divide ratio
1006 * 0: 1.5
1007 * 1: 1
1008 * 2: 2
1009 * ...
1010 * 254: 254
1011 * 255: 255
1012 */
6cd6cede 1013 if (dac33->fifo_mode)
6aceabb4
PU		 1014 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1015 dac33->burst_bclkdiv);
6cd6cede
PU		 1016 else
1017 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 1018
6cd6cede
PU		 1019 switch (dac33->fifo_mode) {
1020 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1021 dac33_write16(codec, DAC33_ATHR_MSB,
1022 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1023 break;
28e05d98
PU		 1024 case DAC33_FIFO_MODE7:
1025 /*
1026 * Configure the threshold levels, and leave 10 sample space
1027 * at the bottom, and also at the top of the FIFO
1028 */
9d7db2b2 1029 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
4260393e 1030 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 1031 break;
aec242dc 1032 default:
aec242dc 1033 break;
c8bf93f0
PU		 1034 }
1035
1036 mutex_unlock(&dac33->mutex);
1037
1038 return 0;
1039}
1040
1041static void dac33_calculate_times(struct snd_pcm_substream *substream)
1042{
1043 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1044 struct snd_soc_device *socdev = rtd->socdev;
1045 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1046 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1047 unsigned int period_size = substream->runtime->period_size;
1048 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1049 unsigned int nsample_limit;
1050
55abb59c
PU		 1051 /* In bypass mode we don't need to calculate */
1052 if (!dac33->fifo_mode)
1053 return;
1054
f57d2cfa
PU		 1055 switch (dac33->fifo_mode) {
1056 case DAC33_FIFO_MODE1:
f430a27f
PU		 1057 /* Number of samples under i2c latency */
1058 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1059 dac33->mode1_latency);
1060 /* nSample time shall not be shorter than i2c latency */
1061 dac33->nsample_min = dac33->alarm_threshold;
1062 /*
1063 * nSample should not be bigger than alsa buffer minus
1064 * size of one period to avoid overruns
1065 */
1066 dac33->nsample_max = substream->runtime->buffer_size -
1067 period_size;
1068 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1069 dac33->alarm_threshold;
1070 if (dac33->nsample_max > nsample_limit)
1071 dac33->nsample_max = nsample_limit;
1072
1073 /* Correct the nSample if it is outside of the ranges */
1074 if (dac33->nsample < dac33->nsample_min)
1075 dac33->nsample = dac33->nsample_min;
1076 if (dac33->nsample > dac33->nsample_max)
1077 dac33->nsample = dac33->nsample_max;
1078
f57d2cfa
PU		 1079 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1080 dac33->nsample);
1081 dac33->t_stamp1 = 0;
1082 dac33->t_stamp2 = 0;
1083 break;
1084 case DAC33_FIFO_MODE7:
1085 dac33->mode7_us_to_lthr =
9d7db2b2
PU		 1086 SAMPLES_TO_US(substream->runtime->rate,
1087 dac33->uthr - MODE7_LTHR + 1);
f57d2cfa
PU		 1088 dac33->t_stamp1 = 0;
1089 break;
1090 default:
1091 break;
1092 }
c8bf93f0 1093
c8bf93f0
PU		 1094}
1095
1096static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1097 struct snd_soc_dai *dai)
1098{
1099 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1100 struct snd_soc_device *socdev = rtd->socdev;
1101 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1102 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1103 int ret = 0;
1104
1105 switch (cmd) {
1106 case SNDRV_PCM_TRIGGER_START:
1107 case SNDRV_PCM_TRIGGER_RESUME:
1108 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1109 if (dac33->fifo_mode) {
c8bf93f0
PU		 1110 dac33->state = DAC33_PREFILL;
1111 queue_work(dac33->dac33_wq, &dac33->work);
1112 }
1113 break;
1114 case SNDRV_PCM_TRIGGER_STOP:
1115 case SNDRV_PCM_TRIGGER_SUSPEND:
1116 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1117 if (dac33->fifo_mode) {
c8bf93f0
PU		 1118 dac33->state = DAC33_FLUSH;
1119 queue_work(dac33->dac33_wq, &dac33->work);
1120 }
1121 break;
1122 default:
1123 ret = -EINVAL;
1124 }
1125
1126 return ret;
1127}
1128
f57d2cfa
PU		 1129static snd_pcm_sframes_t dac33_dai_delay(
1130 struct snd_pcm_substream *substream,
1131 struct snd_soc_dai *dai)
1132{
1133 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1134 struct snd_soc_device *socdev = rtd->socdev;
1135 struct snd_soc_codec *codec = socdev->card->codec;
1136 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1137 unsigned long long t0, t1, t_now;
9d7db2b2 1138 unsigned int time_delta, uthr;
f57d2cfa
PU		 1139 int samples_out, samples_in, samples;
1140 snd_pcm_sframes_t delay = 0;
1141
1142 switch (dac33->fifo_mode) {
1143 case DAC33_FIFO_BYPASS:
1144 break;
1145 case DAC33_FIFO_MODE1:
1146 spin_lock(&dac33->lock);
1147 t0 = dac33->t_stamp1;
1148 t1 = dac33->t_stamp2;
1149 spin_unlock(&dac33->lock);
1150 t_now = ktime_to_us(ktime_get());
1151
1152 /* We have not started to fill the FIFO yet, delay is 0 */
1153 if (!t1)
1154 goto out;
1155
1156 if (t0 > t1) {
1157 /*
1158 * Phase 1:
1159 * After Alarm threshold, and before nSample write
1160 */
1161 time_delta = t_now - t0;
1162 samples_out = time_delta ? US_TO_SAMPLES(
1163 substream->runtime->rate,
1164 time_delta) : 0;
1165
1166 if (likely(dac33->alarm_threshold > samples_out))
1167 delay = dac33->alarm_threshold - samples_out;
1168 else
1169 delay = 0;
1170 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1171 /*
1172 * Phase 2:
1173 * After nSample write (during burst operation)
1174 */
1175 time_delta = t_now - t0;
1176 samples_out = time_delta ? US_TO_SAMPLES(
1177 substream->runtime->rate,
1178 time_delta) : 0;
1179
1180 time_delta = t_now - t1;
1181 samples_in = time_delta ? US_TO_SAMPLES(
1182 dac33->burst_rate,
1183 time_delta) : 0;
1184
1185 samples = dac33->alarm_threshold;
1186 samples += (samples_in - samples_out);
1187
1188 if (likely(samples > 0))
1189 delay = samples;
1190 else
1191 delay = 0;
1192 } else {
1193 /*
1194 * Phase 3:
1195 * After burst operation, before next alarm threshold
1196 */
1197 time_delta = t_now - t0;
1198 samples_out = time_delta ? US_TO_SAMPLES(
1199 substream->runtime->rate,
1200 time_delta) : 0;
1201
1202 samples_in = dac33->nsample;
1203 samples = dac33->alarm_threshold;
1204 samples += (samples_in - samples_out);
1205
1206 if (likely(samples > 0))
1207 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1208 DAC33_BUFFER_SIZE_SAMPLES : samples;
1209 else
1210 delay = 0;
1211 }
1212 break;
1213 case DAC33_FIFO_MODE7:
1214 spin_lock(&dac33->lock);
1215 t0 = dac33->t_stamp1;
9d7db2b2 1216 uthr = dac33->uthr;
f57d2cfa
PU		 1217 spin_unlock(&dac33->lock);
1218 t_now = ktime_to_us(ktime_get());
1219
1220 /* We have not started to fill the FIFO yet, delay is 0 */
1221 if (!t0)
1222 goto out;
1223
1224 if (t_now <= t0) {
1225 /*
1226 * Either the timestamps are messed or equal. Report
1227 * maximum delay
1228 */
9d7db2b2 1229 delay = uthr;
f57d2cfa
PU		 1230 goto out;
1231 }
1232
1233 time_delta = t_now - t0;
1234 if (time_delta <= dac33->mode7_us_to_lthr) {
1235 /*
1236 * Phase 1:
1237 * After burst (draining phase)
1238 */
1239 samples_out = US_TO_SAMPLES(
1240 substream->runtime->rate,
1241 time_delta);
1242
9d7db2b2
PU		 1243 if (likely(uthr > samples_out))
1244 delay = uthr - samples_out;
f57d2cfa
PU		 1245 else
1246 delay = 0;
1247 } else {
1248 /*
1249 * Phase 2:
1250 * During burst operation
1251 */
1252 time_delta = time_delta - dac33->mode7_us_to_lthr;
1253
1254 samples_out = US_TO_SAMPLES(
1255 substream->runtime->rate,
1256 time_delta);
1257 samples_in = US_TO_SAMPLES(
1258 dac33->burst_rate,
1259 time_delta);
1260 delay = MODE7_LTHR + samples_in - samples_out;
1261
9d7db2b2
PU		 1262 if (unlikely(delay > uthr))
1263 delay = uthr;
f57d2cfa
PU		 1264 }
1265 break;
1266 default:
1267 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1268 dac33->fifo_mode);
1269 break;
1270 }
1271out:
1272 return delay;
1273}
1274
c8bf93f0
PU		 1275static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1276 int clk_id, unsigned int freq, int dir)
1277{
1278 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1279 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1280 u8 ioc_reg, asrcb_reg;
1281
1282 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1283 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1284 switch (clk_id) {
1285 case TLV320DAC33_MCLK:
1286 ioc_reg |= DAC33_REFSEL;
1287 asrcb_reg |= DAC33_SRCREFSEL;
1288 break;
1289 case TLV320DAC33_SLEEPCLK:
1290 ioc_reg &= ~DAC33_REFSEL;
1291 asrcb_reg &= ~DAC33_SRCREFSEL;
1292 break;
1293 default:
1294 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1295 break;
1296 }
1297 dac33->refclk = freq;
1298
1299 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1300 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1301
1302 return 0;
1303}
1304
1305static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1306 unsigned int fmt)
1307{
1308 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1309 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1310 u8 aictrl_a, aictrl_b;
1311
1312 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1313 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1314 /* set master/slave audio interface */
1315 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1316 case SND_SOC_DAIFMT_CBM_CFM:
1317 /* Codec Master */
1318 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1319 break;
1320 case SND_SOC_DAIFMT_CBS_CFS:
1321 /* Codec Slave */
adcb8bc0
PU		 1322 if (dac33->fifo_mode) {
1323 dev_err(codec->dev, "FIFO mode requires master mode\n");
1324 return -EINVAL;
1325 } else
1326 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331
1332 aictrl_a &= ~DAC33_AFMT_MASK;
1333 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1334 case SND_SOC_DAIFMT_I2S:
1335 aictrl_a |= DAC33_AFMT_I2S;
1336 break;
1337 case SND_SOC_DAIFMT_DSP_A:
1338 aictrl_a |= DAC33_AFMT_DSP;
1339 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1340 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1341 break;
1342 case SND_SOC_DAIFMT_RIGHT_J:
1343 aictrl_a |= DAC33_AFMT_RIGHT_J;
1344 break;
1345 case SND_SOC_DAIFMT_LEFT_J:
1346 aictrl_a |= DAC33_AFMT_LEFT_J;
1347 break;
1348 default:
1349 dev_err(codec->dev, "Unsupported format (%u)\n",
1350 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1351 return -EINVAL;
1352 }
1353
1354 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1355 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1356
1357 return 0;
1358}
1359
c8bf93f0
PU		 1360static int dac33_soc_probe(struct platform_device *pdev)
1361{
1362 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1363 struct snd_soc_codec *codec;
1364 struct tlv320dac33_priv *dac33;
1365 int ret = 0;
1366
1367 BUG_ON(!tlv320dac33_codec);
1368
1369 codec = tlv320dac33_codec;
1370 socdev->card->codec = codec;
b2c812e2 1371 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1372
1373 /* register pcms */
1374 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1375 if (ret < 0) {
1376 dev_err(codec->dev, "failed to create pcms\n");
1377 goto pcm_err;
1378 }
1379
1380 snd_soc_add_controls(codec, dac33_snd_controls,
1381 ARRAY_SIZE(dac33_snd_controls));
1382 /* Only add the nSample controls, if we have valid IRQ number */
1383 if (dac33->irq >= 0)
1384 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1385 ARRAY_SIZE(dac33_nsample_snd_controls));
1386
1387 dac33_add_widgets(codec);
1388
c8bf93f0 1389 return 0;
fe3e78e0 1390
c8bf93f0
PU		 1391pcm_err:
1392 dac33_hard_power(codec, 0);
1393 return ret;
1394}
1395
1396static int dac33_soc_remove(struct platform_device *pdev)
1397{
1398 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1399 struct snd_soc_codec *codec = socdev->card->codec;
1400
1401 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1402
1403 snd_soc_free_pcms(socdev);
1404 snd_soc_dapm_free(socdev);
1405
1406 return 0;
1407}
1408
1409static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1410{
1411 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1412 struct snd_soc_codec *codec = socdev->card->codec;
1413
1414 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1415
1416 return 0;
1417}
1418
1419static int dac33_soc_resume(struct platform_device *pdev)
1420{
1421 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1422 struct snd_soc_codec *codec = socdev->card->codec;
1423
1424 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1425
1426 return 0;
1427}
1428
1429struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1430 .probe = dac33_soc_probe,
1431 .remove = dac33_soc_remove,
1432 .suspend = dac33_soc_suspend,
1433 .resume = dac33_soc_resume,
1434};
1435EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1436
1437#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1438 SNDRV_PCM_RATE_48000)
1439#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1440
1441static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1442 .startup = dac33_startup,
c8bf93f0
PU		 1443 .shutdown = dac33_shutdown,
1444 .hw_params = dac33_hw_params,
c8bf93f0 1445 .trigger = dac33_pcm_trigger,
f57d2cfa 1446 .delay = dac33_dai_delay,
c8bf93f0
PU		 1447 .set_sysclk = dac33_set_dai_sysclk,
1448 .set_fmt = dac33_set_dai_fmt,
1449};
1450
1451struct snd_soc_dai dac33_dai = {
1452 .name = "tlv320dac33",
1453 .playback = {
1454 .stream_name = "Playback",
1455 .channels_min = 2,
1456 .channels_max = 2,
1457 .rates = DAC33_RATES,
1458 .formats = DAC33_FORMATS,},
1459 .ops = &dac33_dai_ops,
1460};
1461EXPORT_SYMBOL_GPL(dac33_dai);
1462
735fe4cf
MB		 1463static int __devinit dac33_i2c_probe(struct i2c_client *client,
1464 const struct i2c_device_id *id)
c8bf93f0
PU		 1465{
1466 struct tlv320dac33_platform_data *pdata;
1467 struct tlv320dac33_priv *dac33;
1468 struct snd_soc_codec *codec;
3a7aaed7 1469 int ret, i;
c8bf93f0
PU		 1470
1471 if (client->dev.platform_data == NULL) {
1472 dev_err(&client->dev, "Platform data not set\n");
1473 return -ENODEV;
1474 }
1475 pdata = client->dev.platform_data;
1476
1477 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1478 if (dac33 == NULL)
1479 return -ENOMEM;
1480
1481 codec = &dac33->codec;
b2c812e2 1482 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1483 codec->control_data = client;
1484
1485 mutex_init(&codec->mutex);
1486 mutex_init(&dac33->mutex);
f57d2cfa 1487 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1488 INIT_LIST_HEAD(&codec->dapm_widgets);
1489 INIT_LIST_HEAD(&codec->dapm_paths);
1490
1491 codec->name = "tlv320dac33";
1492 codec->owner = THIS_MODULE;
1493 codec->read = dac33_read_reg_cache;
1494 codec->write = dac33_write_locked;
1495 codec->hw_write = (hw_write_t) i2c_master_send;
1496 codec->bias_level = SND_SOC_BIAS_OFF;
1497 codec->set_bias_level = dac33_set_bias_level;
ad05c03b 1498 codec->idle_bias_off = 1;
c8bf93f0
PU		 1499 codec->dai = &dac33_dai;
1500 codec->num_dai = 1;
1501 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1502 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1503 GFP_KERNEL);
1504 if (codec->reg_cache == NULL) {
1505 ret = -ENOMEM;
1506 goto error_reg;
1507 }
1508
1509 i2c_set_clientdata(client, dac33);
1510
1511 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1512 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1513 /* Pre calculate the burst rate */
1514 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1515 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1516 dac33->mode1_latency = pdata->mode1_latency;
1517 if (!dac33->mode1_latency)
1518 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0
PU		 1519 dac33->irq = client->irq;
1520 dac33->nsample = NSAMPLE_MAX;
55abb59c 1521 dac33->nsample_max = NSAMPLE_MAX;
9d7db2b2 1522 dac33->uthr = MODE7_UTHR;
c8bf93f0 1523 /* Disable FIFO use by default */
7427b4b9 1524 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1525
1526 tlv320dac33_codec = codec;
1527
1528 codec->dev = &client->dev;
1529 dac33_dai.dev = codec->dev;
1530
1531 /* Check if the reset GPIO number is valid and request it */
1532 if (dac33->power_gpio >= 0) {
1533 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1534 if (ret < 0) {
1535 dev_err(codec->dev,
1536 "Failed to request reset GPIO (%d)\n",
1537 dac33->power_gpio);
1538 snd_soc_unregister_dai(&dac33_dai);
1539 snd_soc_unregister_codec(codec);
1540 goto error_gpio;
1541 }
1542 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1543 }
1544
1545 /* Check if the IRQ number is valid and request it */
1546 if (dac33->irq >= 0) {
1547 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1548 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1549 codec->name, codec);
1550 if (ret < 0) {
1551 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1552 dac33->irq, ret);
1553 dac33->irq = -1;
1554 }
1555 if (dac33->irq != -1) {
1556 /* Setup work queue */
74ea23aa
PU		 1557 dac33->dac33_wq =
1558 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1559 if (dac33->dac33_wq == NULL) {
1560 free_irq(dac33->irq, &dac33->codec);
1561 ret = -ENOMEM;
1562 goto error_wq;
1563 }
1564
1565 INIT_WORK(&dac33->work, dac33_work);
1566 }
1567 }
1568
3a7aaed7
IK		 1569 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1570 dac33->supplies[i].supply = dac33_supply_names[i];
1571
1572 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1573 dac33->supplies);
1574
1575 if (ret != 0) {
1576 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1577 goto err_get;
1578 }
1579
239fe55c
PU		 1580 /* Read the tlv320dac33 ID registers */
1581 ret = dac33_hard_power(codec, 1);
3a7aaed7 1582 if (ret != 0) {
239fe55c
PU		 1583 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1584 goto error_codec;
3a7aaed7 1585 }
239fe55c
PU		 1586 dac33_read_id(codec);
1587 dac33_hard_power(codec, 0);
3a7aaed7 1588
c8bf93f0
PU		 1589 ret = snd_soc_register_codec(codec);
1590 if (ret != 0) {
1591 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1592 goto error_codec;
1593 }
1594
1595 ret = snd_soc_register_dai(&dac33_dai);
1596 if (ret != 0) {
1597 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1598 snd_soc_unregister_codec(codec);
1599 goto error_codec;
1600 }
1601
c8bf93f0
PU		 1602 return ret;
1603
1604error_codec:
3a7aaed7
IK		 1605 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1606err_get:
c8bf93f0
PU		 1607 if (dac33->irq >= 0) {
1608 free_irq(dac33->irq, &dac33->codec);
1609 destroy_workqueue(dac33->dac33_wq);
1610 }
1611error_wq:
1612 if (dac33->power_gpio >= 0)
1613 gpio_free(dac33->power_gpio);
1614error_gpio:
1615 kfree(codec->reg_cache);
1616error_reg:
1617 tlv320dac33_codec = NULL;
1618 kfree(dac33);
1619
1620 return ret;
1621}
1622
735fe4cf 1623static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1624{
1625 struct tlv320dac33_priv *dac33;
1626
1627 dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1628
1629 if (unlikely(dac33->chip_power))
1630 dac33_hard_power(&dac33->codec, 0);
c8bf93f0
PU		 1631
1632 if (dac33->power_gpio >= 0)
1633 gpio_free(dac33->power_gpio);
1634 if (dac33->irq >= 0)
1635 free_irq(dac33->irq, &dac33->codec);
1636
3a7aaed7
IK		 1637 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1638
c8bf93f0
PU		 1639 destroy_workqueue(dac33->dac33_wq);
1640 snd_soc_unregister_dai(&dac33_dai);
1641 snd_soc_unregister_codec(&dac33->codec);
1642 kfree(dac33->codec.reg_cache);
1643 kfree(dac33);
1644 tlv320dac33_codec = NULL;
1645
1646 return 0;
1647}
1648
1649static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1650 {
1651 .name = "tlv320dac33",
1652 .driver_data = 0,
1653 },
1654 { },
1655};
1656
1657static struct i2c_driver tlv320dac33_i2c_driver = {
1658 .driver = {
1659 .name = "tlv320dac33",
1660 .owner = THIS_MODULE,
1661 },
1662 .probe = dac33_i2c_probe,
1663 .remove = __devexit_p(dac33_i2c_remove),
1664 .id_table = tlv320dac33_i2c_id,
1665};
1666
1667static int __init dac33_module_init(void)
1668{
1669 int r;
1670 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1671 if (r < 0) {
1672 printk(KERN_ERR "DAC33: driver registration failed\n");
1673 return r;
1674 }
1675 return 0;
1676}
1677module_init(dac33_module_init);
1678
1679static void __exit dac33_module_exit(void)
1680{
1681 i2c_del_driver(&tlv320dac33_i2c_driver);
1682}
1683module_exit(dac33_module_exit);
1684
1685
1686MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1687MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1688MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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