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ASoC: tlv320dac33: Fix for early interrupt in FIFO Mode1
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
53static struct snd_soc_codec *tlv320dac33_codec;
54
55enum dac33_state {
56 DAC33_IDLE = 0,
57 DAC33_PREFILL,
58 DAC33_PLAYBACK,
59 DAC33_FLUSH,
60};
61
7427b4b9
PU		 62enum dac33_fifo_modes {
63 DAC33_FIFO_BYPASS = 0,
64 DAC33_FIFO_MODE1,
28e05d98 65 DAC33_FIFO_MODE7,
7427b4b9
PU		 66 DAC33_FIFO_LAST_MODE,
67};
68
3a7aaed7
IK		 69#define DAC33_NUM_SUPPLIES 3
70static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
71 "AVDD",
72 "DVDD",
73 "IOVDD",
74};
75
c8bf93f0
PU		 76struct tlv320dac33_priv {
77 struct mutex mutex;
78 struct workqueue_struct *dac33_wq;
79 struct work_struct work;
80 struct snd_soc_codec codec;
3a7aaed7 81 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 82 int power_gpio;
83 int chip_power;
84 int irq;
85 unsigned int refclk;
86
87 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
88 unsigned int nsample_min; /* nsample should not be lower than
89 * this */
90 unsigned int nsample_max; /* nsample should not be higher than
91 * this */
7427b4b9 92 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 93 unsigned int nsample; /* burst read amount from host */
6aceabb4 94 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
c8bf93f0 95
eeb309a8
PU		 96 int keep_bclk; /* Keep the BCLK continuously running
97 * in FIFO modes */
c8bf93f0
PU		 98 enum dac33_state state;
99};
100
101static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1020x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1030x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1040x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1050x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1060x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1070x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1080x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1090x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1100x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1110x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1120x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1130x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1140x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1150x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1160x00, 0x00, /* 0x38 - 0x39 */
117/* Registers 0x3a - 0x3f are reserved */
118 0x00, 0x00, /* 0x3a - 0x3b */
1190x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
120
1210x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1220x00, 0x80, /* 0x44 - 0x45 */
123/* Registers 0x46 - 0x47 are reserved */
124 0x80, 0x80, /* 0x46 - 0x47 */
125
1260x80, 0x00, 0x00, /* 0x48 - 0x4a */
127/* Registers 0x4b - 0x7c are reserved */
128 0x00, /* 0x4b */
1290x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1300x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1310x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1320x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1330x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1340x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1350x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1360x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1370x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1380x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1390x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1400x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1410x00, /* 0x7c */
142
143 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
144};
145
146/* Register read and write */
147static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
148 unsigned reg)
149{
150 u8 *cache = codec->reg_cache;
151 if (reg >= DAC33_CACHEREGNUM)
152 return 0;
153
154 return cache[reg];
155}
156
157static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
158 u8 reg, u8 value)
159{
160 u8 *cache = codec->reg_cache;
161 if (reg >= DAC33_CACHEREGNUM)
162 return;
163
164 cache[reg] = value;
165}
166
167static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
168 u8 *value)
169{
b2c812e2 170 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 171 int val;
172
173 *value = reg & 0xff;
174
175 /* If powered off, return the cached value */
176 if (dac33->chip_power) {
177 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
178 if (val < 0) {
179 dev_err(codec->dev, "Read failed (%d)\n", val);
180 value[0] = dac33_read_reg_cache(codec, reg);
181 } else {
182 value[0] = val;
183 dac33_write_reg_cache(codec, reg, val);
184 }
185 } else {
186 value[0] = dac33_read_reg_cache(codec, reg);
187 }
188
189 return 0;
190}
191
192static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
193 unsigned int value)
194{
b2c812e2 195 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 196 u8 data[2];
197 int ret = 0;
198
199 /*
200 * data is
201 * D15..D8 dac33 register offset
202 * D7...D0 register data
203 */
204 data[0] = reg & 0xff;
205 data[1] = value & 0xff;
206
207 dac33_write_reg_cache(codec, data[0], data[1]);
208 if (dac33->chip_power) {
209 ret = codec->hw_write(codec->control_data, data, 2);
210 if (ret != 2)
211 dev_err(codec->dev, "Write failed (%d)\n", ret);
212 else
213 ret = 0;
214 }
215
216 return ret;
217}
218
219static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
220 unsigned int value)
221{
b2c812e2 222 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 223 int ret;
224
225 mutex_lock(&dac33->mutex);
226 ret = dac33_write(codec, reg, value);
227 mutex_unlock(&dac33->mutex);
228
229 return ret;
230}
231
232#define DAC33_I2C_ADDR_AUTOINC 0x80
233static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
234 unsigned int value)
235{
b2c812e2 236 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 237 u8 data[3];
238 int ret = 0;
239
240 /*
241 * data is
242 * D23..D16 dac33 register offset
243 * D15..D8 register data MSB
244 * D7...D0 register data LSB
245 */
246 data[0] = reg & 0xff;
247 data[1] = (value >> 8) & 0xff;
248 data[2] = value & 0xff;
249
250 dac33_write_reg_cache(codec, data[0], data[1]);
251 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
252
253 if (dac33->chip_power) {
254 /* We need to set autoincrement mode for 16 bit writes */
255 data[0] |= DAC33_I2C_ADDR_AUTOINC;
256 ret = codec->hw_write(codec->control_data, data, 3);
257 if (ret != 3)
258 dev_err(codec->dev, "Write failed (%d)\n", ret);
259 else
260 ret = 0;
261 }
262
263 return ret;
264}
265
266static void dac33_restore_regs(struct snd_soc_codec *codec)
267{
b2c812e2 268 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 269 u8 *cache = codec->reg_cache;
270 u8 data[2];
271 int i, ret;
272
273 if (!dac33->chip_power)
274 return;
275
276 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
277 data[0] = i;
278 data[1] = cache[i];
279 /* Skip the read only registers */
280 if ((i >= DAC33_INT_OSC_STATUS &&
281 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
282 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
283 i == DAC33_DAC_STATUS_FLAGS ||
284 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
285 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
286 continue;
287 ret = codec->hw_write(codec->control_data, data, 2);
288 if (ret != 2)
289 dev_err(codec->dev, "Write failed (%d)\n", ret);
290 }
291 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
292 data[0] = i;
293 data[1] = cache[i];
294 ret = codec->hw_write(codec->control_data, data, 2);
295 if (ret != 2)
296 dev_err(codec->dev, "Write failed (%d)\n", ret);
297 }
298 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
299 data[0] = i;
300 data[1] = cache[i];
301 ret = codec->hw_write(codec->control_data, data, 2);
302 if (ret != 2)
303 dev_err(codec->dev, "Write failed (%d)\n", ret);
304 }
305}
306
307static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
308{
309 u8 reg;
310
311 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
312 if (power)
313 reg |= DAC33_PDNALLB;
314 else
c3746a07
PU		 315 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
316 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 317 dac33_write(codec, DAC33_PWR_CTRL, reg);
318}
319
3a7aaed7 320static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 321{
b2c812e2 322 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 323 int ret;
c8bf93f0
PU		 324
325 mutex_lock(&dac33->mutex);
326 if (power) {
3a7aaed7
IK		 327 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
328 dac33->supplies);
329 if (ret != 0) {
330 dev_err(codec->dev,
331 "Failed to enable supplies: %d\n", ret);
332 goto exit;
c8bf93f0 333 }
3a7aaed7
IK		 334
335 if (dac33->power_gpio >= 0)
336 gpio_set_value(dac33->power_gpio, 1);
337
338 dac33->chip_power = 1;
339
340 /* Restore registers */
341 dac33_restore_regs(codec);
342
c8bf93f0
PU		 343 dac33_soft_power(codec, 1);
344 } else {
345 dac33_soft_power(codec, 0);
3a7aaed7 346 if (dac33->power_gpio >= 0)
c8bf93f0 347 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 348
349 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
350 dac33->supplies);
351 if (ret != 0) {
352 dev_err(codec->dev,
353 "Failed to disable supplies: %d\n", ret);
354 goto exit;
c8bf93f0 355 }
3a7aaed7
IK		 356
357 dac33->chip_power = 0;
c8bf93f0 358 }
c8bf93f0 359
3a7aaed7
IK		 360exit:
361 mutex_unlock(&dac33->mutex);
362 return ret;
c8bf93f0
PU		 363}
364
365static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_value *ucontrol)
367{
368 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 369 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 370
371 ucontrol->value.integer.value[0] = dac33->nsample;
372
373 return 0;
374}
375
376static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
377 struct snd_ctl_elem_value *ucontrol)
378{
379 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 380 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 381 int ret = 0;
382
383 if (dac33->nsample == ucontrol->value.integer.value[0])
384 return 0;
385
386 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
387 ucontrol->value.integer.value[0] > dac33->nsample_max)
388 ret = -EINVAL;
389 else
390 dac33->nsample = ucontrol->value.integer.value[0];
391
392 return ret;
393}
394
7427b4b9 395static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 396 struct snd_ctl_elem_value *ucontrol)
397{
398 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 399 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 400
7427b4b9 401 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 402
403 return 0;
404}
405
7427b4b9 406static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 407 struct snd_ctl_elem_value *ucontrol)
408{
409 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 410 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 411 int ret = 0;
412
7427b4b9 413 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 414 return 0;
415 /* Do not allow changes while stream is running*/
416 if (codec->active)
417 return -EPERM;
418
419 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 420 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 421 ret = -EINVAL;
422 else
7427b4b9 423 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 424
425 return ret;
426}
427
7427b4b9
PU		 428/* Codec operation modes */
429static const char *dac33_fifo_mode_texts[] = {
28e05d98 430 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 431};
432
433static const struct soc_enum dac33_fifo_mode_enum =
434 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
435 dac33_fifo_mode_texts);
436
c8bf93f0
PU		 437/*
438 * DACL/R digital volume control:
439 * from 0 dB to -63.5 in 0.5 dB steps
440 * Need to be inverted later on:
441 * 0x00 == 0 dB
442 * 0x7f == -63.5 dB
443 */
444static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
445
446static const struct snd_kcontrol_new dac33_snd_controls[] = {
447 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
448 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
449 0, 0x7f, 1, dac_digivol_tlv),
450 SOC_DOUBLE_R("DAC Digital Playback Switch",
451 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
452 SOC_DOUBLE_R("Line to Line Out Volume",
453 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
454};
455
456static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
457 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
458 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 459 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
460 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 461};
462
463/* Analog bypass */
464static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
465 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
466
467static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
468 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
469
470static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
471 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
472 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
473
474 SND_SOC_DAPM_INPUT("LINEL"),
475 SND_SOC_DAPM_INPUT("LINER"),
476
477 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
478 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
479
480 /* Analog bypass */
481 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
482 &dac33_dapm_abypassl_control),
483 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
484 &dac33_dapm_abypassr_control),
485
486 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
487 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
488 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
489 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
490};
491
492static const struct snd_soc_dapm_route audio_map[] = {
493 /* Analog bypass */
494 {"Analog Left Bypass", "Switch", "LINEL"},
495 {"Analog Right Bypass", "Switch", "LINER"},
496
497 {"Output Left Amp Power", NULL, "DACL"},
498 {"Output Right Amp Power", NULL, "DACR"},
499
500 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
501 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
502
503 /* output */
504 {"LEFT_LO", NULL, "Output Left Amp Power"},
505 {"RIGHT_LO", NULL, "Output Right Amp Power"},
506};
507
508static int dac33_add_widgets(struct snd_soc_codec *codec)
509{
510 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
511 ARRAY_SIZE(dac33_dapm_widgets));
512
513 /* set up audio path interconnects */
514 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 515
516 return 0;
517}
518
519static int dac33_set_bias_level(struct snd_soc_codec *codec,
520 enum snd_soc_bias_level level)
521{
3a7aaed7
IK		 522 int ret;
523
c8bf93f0
PU		 524 switch (level) {
525 case SND_SOC_BIAS_ON:
526 dac33_soft_power(codec, 1);
527 break;
528 case SND_SOC_BIAS_PREPARE:
529 break;
530 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 531 if (codec->bias_level == SND_SOC_BIAS_OFF) {
532 ret = dac33_hard_power(codec, 1);
533 if (ret != 0)
534 return ret;
535 }
536
c8bf93f0
PU		 537 dac33_soft_power(codec, 0);
538 break;
539 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 540 ret = dac33_hard_power(codec, 0);
541 if (ret != 0)
542 return ret;
543
c8bf93f0
PU		 544 break;
545 }
546 codec->bias_level = level;
547
548 return 0;
549}
550
d4f102d4
PU		 551static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
552{
553 struct snd_soc_codec *codec;
554
555 codec = &dac33->codec;
556
557 switch (dac33->fifo_mode) {
558 case DAC33_FIFO_MODE1:
559 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 560 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
d4f102d4
PU		 561 dac33_write16(codec, DAC33_PREFILL_MSB,
562 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 563 /* Enable Alarm Threshold IRQ with a delay */
564 udelay(SAMPLES_TO_US(dac33->burst_rate,
565 dac33->alarm_threshold));
566 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 567 break;
28e05d98
PU		 568 case DAC33_FIFO_MODE7:
569 dac33_write16(codec, DAC33_PREFILL_MSB,
a5b5a064 570 DAC33_THRREG(10));
28e05d98 571 break;
d4f102d4
PU		 572 default:
573 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
574 dac33->fifo_mode);
575 break;
576 }
577}
578
579static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
580{
581 struct snd_soc_codec *codec;
582
583 codec = &dac33->codec;
584
585 switch (dac33->fifo_mode) {
586 case DAC33_FIFO_MODE1:
587 dac33_write16(codec, DAC33_NSAMPLE_MSB,
588 DAC33_THRREG(dac33->nsample));
589 break;
28e05d98
PU		 590 case DAC33_FIFO_MODE7:
591 /* At the moment we are not using interrupts in mode7 */
592 break;
d4f102d4
PU		 593 default:
594 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
595 dac33->fifo_mode);
596 break;
597 }
598}
599
c8bf93f0
PU		 600static void dac33_work(struct work_struct *work)
601{
602 struct snd_soc_codec *codec;
603 struct tlv320dac33_priv *dac33;
604 u8 reg;
605
606 dac33 = container_of(work, struct tlv320dac33_priv, work);
607 codec = &dac33->codec;
608
609 mutex_lock(&dac33->mutex);
610 switch (dac33->state) {
611 case DAC33_PREFILL:
612 dac33->state = DAC33_PLAYBACK;
d4f102d4 613 dac33_prefill_handler(dac33);
c8bf93f0
PU		 614 break;
615 case DAC33_PLAYBACK:
d4f102d4 616 dac33_playback_handler(dac33);
c8bf93f0
PU		 617 break;
618 case DAC33_IDLE:
619 break;
620 case DAC33_FLUSH:
621 dac33->state = DAC33_IDLE;
622 /* Mask all interrupts from dac33 */
623 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
624
625 /* flush fifo */
626 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
627 reg |= DAC33_FIFOFLUSH;
628 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
629 break;
630 }
631 mutex_unlock(&dac33->mutex);
632}
633
634static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
635{
636 struct snd_soc_codec *codec = dev;
b2c812e2 637 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 638
639 queue_work(dac33->dac33_wq, &dac33->work);
640
641 return IRQ_HANDLED;
642}
643
c8bf93f0
PU		 644static void dac33_oscwait(struct snd_soc_codec *codec)
645{
646 int timeout = 20;
647 u8 reg;
648
649 do {
650 msleep(1);
651 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
652 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
653 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
654 dev_err(codec->dev,
655 "internal oscillator calibration failed\n");
656}
657
658static int dac33_hw_params(struct snd_pcm_substream *substream,
659 struct snd_pcm_hw_params *params,
660 struct snd_soc_dai *dai)
661{
662 struct snd_soc_pcm_runtime *rtd = substream->private_data;
663 struct snd_soc_device *socdev = rtd->socdev;
664 struct snd_soc_codec *codec = socdev->card->codec;
665
666 /* Check parameters for validity */
667 switch (params_rate(params)) {
668 case 44100:
669 case 48000:
670 break;
671 default:
672 dev_err(codec->dev, "unsupported rate %d\n",
673 params_rate(params));
674 return -EINVAL;
675 }
676
677 switch (params_format(params)) {
678 case SNDRV_PCM_FORMAT_S16_LE:
679 break;
680 default:
681 dev_err(codec->dev, "unsupported format %d\n",
682 params_format(params));
683 return -EINVAL;
684 }
685
686 return 0;
687}
688
689#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 690 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 691#define CALC_RATIOSET(rate, refclk) ( \
692 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
693
694/*
695 * tlv320dac33 is strict on the sequence of the register writes, if the register
696 * writes happens in different order, than dac33 might end up in unknown state.
697 * Use the known, working sequence of register writes to initialize the dac33.
698 */
699static int dac33_prepare_chip(struct snd_pcm_substream *substream)
700{
701 struct snd_soc_pcm_runtime *rtd = substream->private_data;
702 struct snd_soc_device *socdev = rtd->socdev;
703 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 704 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 705 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 706 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 707
708 switch (substream->runtime->rate) {
709 case 44100:
710 case 48000:
711 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
712 ratioset = CALC_RATIOSET(substream->runtime->rate,
713 dac33->refclk);
714 break;
715 default:
716 dev_err(codec->dev, "unsupported rate %d\n",
717 substream->runtime->rate);
718 return -EINVAL;
719 }
720
721
722 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
723 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 724 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 725 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 726 fifoctrl_a &= ~DAC33_FIFOFLUSH;
727
c8bf93f0
PU		 728 fifoctrl_a &= ~DAC33_WIDTH;
729 switch (substream->runtime->format) {
730 case SNDRV_PCM_FORMAT_S16_LE:
731 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
732 fifoctrl_a |= DAC33_WIDTH;
733 break;
734 default:
735 dev_err(codec->dev, "unsupported format %d\n",
736 substream->runtime->format);
737 return -EINVAL;
738 }
739
740 mutex_lock(&dac33->mutex);
c3746a07 741 dac33_soft_power(codec, 0);
c8bf93f0
PU		 742 dac33_soft_power(codec, 1);
743
744 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
745 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
746
747 /* Write registers 0x08 and 0x09 (MSB, LSB) */
748 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
749
750 /* calib time: 128 is a nice number ;) */
751 dac33_write(codec, DAC33_CALIB_TIME, 128);
752
753 /* adjustment treshold & step */
754 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
755 DAC33_ADJSTEP(1));
756
757 /* div=4 / gain=1 / div */
758 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
759
760 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
761 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
762 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
763
764 dac33_oscwait(codec);
765
7427b4b9 766 if (dac33->fifo_mode) {
aec242dc 767 /* Generic for all FIFO modes */
c8bf93f0 768 /* 50-51 : ASRC Control registers */
fdb6b1e1 769 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 770 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
771
772 /* Write registers 0x34 and 0x35 (MSB, LSB) */
773 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
774
775 /* Set interrupts to high active */
776 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 777 } else {
aec242dc 778 /* FIFO bypass mode */
c8bf93f0
PU		 779 /* 50-51 : ASRC Control registers */
780 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
781 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
782 }
783
aec242dc
PU		 784 /* Interrupt behaviour configuration */
785 switch (dac33->fifo_mode) {
786 case DAC33_FIFO_MODE1:
787 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
788 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 789 break;
28e05d98
PU		 790 case DAC33_FIFO_MODE7:
791 /* Disable all interrupts */
792 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
793 break;
aec242dc
PU		 794 default:
795 /* in FIFO bypass mode, the interrupts are not used */
796 break;
797 }
798
799 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
800
801 switch (dac33->fifo_mode) {
802 case DAC33_FIFO_MODE1:
803 /*
804 * For mode1:
805 * Disable the FIFO bypass (Enable the use of FIFO)
806 * Select nSample mode
807 * BCLK is only running when data is needed by DAC33
808 */
c8bf93f0 809 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 810 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 811 if (dac33->keep_bclk)
812 aictrl_b |= DAC33_BCLKON;
813 else
814 aictrl_b &= ~DAC33_BCLKON;
aec242dc 815 break;
28e05d98
PU		 816 case DAC33_FIFO_MODE7:
817 /*
818 * For mode1:
819 * Disable the FIFO bypass (Enable the use of FIFO)
820 * Select Threshold mode
821 * BCLK is only running when data is needed by DAC33
822 */
823 fifoctrl_a &= ~DAC33_FBYPAS;
824 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 825 if (dac33->keep_bclk)
826 aictrl_b |= DAC33_BCLKON;
827 else
828 aictrl_b &= ~DAC33_BCLKON;
28e05d98 829 break;
aec242dc
PU		 830 default:
831 /*
832 * For FIFO bypass mode:
833 * Enable the FIFO bypass (Disable the FIFO use)
834 * Set the BCLK as continous
835 */
c8bf93f0 836 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 837 aictrl_b |= DAC33_BCLKON;
838 break;
839 }
c8bf93f0 840
aec242dc 841 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 842 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 843 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 844
6aceabb4
PU		 845 /*
846 * BCLK divide ratio
847 * 0: 1.5
848 * 1: 1
849 * 2: 2
850 * ...
851 * 254: 254
852 * 255: 255
853 */
6cd6cede 854 if (dac33->fifo_mode)
6aceabb4
PU		 855 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
856 dac33->burst_bclkdiv);
6cd6cede
PU		 857 else
858 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 859
6cd6cede
PU		 860 switch (dac33->fifo_mode) {
861 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 862 dac33_write16(codec, DAC33_ATHR_MSB,
863 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 864 break;
28e05d98
PU		 865 case DAC33_FIFO_MODE7:
866 /*
867 * Configure the threshold levels, and leave 10 sample space
868 * at the bottom, and also at the top of the FIFO
869 */
870 dac33_write16(codec, DAC33_UTHR_MSB,
871 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10));
872 dac33_write16(codec, DAC33_LTHR_MSB,
873 DAC33_THRREG(10));
874 break;
aec242dc 875 default:
aec242dc 876 break;
c8bf93f0
PU		 877 }
878
879 mutex_unlock(&dac33->mutex);
880
881 return 0;
882}
883
884static void dac33_calculate_times(struct snd_pcm_substream *substream)
885{
886 struct snd_soc_pcm_runtime *rtd = substream->private_data;
887 struct snd_soc_device *socdev = rtd->socdev;
888 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 889 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 890 unsigned int nsample_limit;
891
892 /* Number of samples (16bit, stereo) in one period */
893 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
894
895 /* Number of samples (16bit, stereo) in ALSA buffer */
896 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
897 /* Subtract one period from the total */
898 dac33->nsample_max -= dac33->nsample_min;
899
900 /* Number of samples for LATENCY_TIME_MS / 2 */
901 dac33->alarm_threshold = substream->runtime->rate /
902 (1000 / (LATENCY_TIME_MS / 2));
903
904 /* Find and fix up the lowest nsmaple limit */
905 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
906
907 if (dac33->nsample_min < nsample_limit)
908 dac33->nsample_min = nsample_limit;
909
910 if (dac33->nsample < dac33->nsample_min)
911 dac33->nsample = dac33->nsample_min;
912
913 /*
914 * Find and fix up the highest nsmaple limit
915 * In order to not overflow the DAC33 buffer substract the
916 * alarm_threshold value from the size of the DAC33 buffer
917 */
918 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
919
920 if (dac33->nsample_max > nsample_limit)
921 dac33->nsample_max = nsample_limit;
922
923 if (dac33->nsample > dac33->nsample_max)
924 dac33->nsample = dac33->nsample_max;
925}
926
927static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
928 struct snd_soc_dai *dai)
929{
930 dac33_calculate_times(substream);
931 dac33_prepare_chip(substream);
932
933 return 0;
934}
935
936static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
937 struct snd_soc_dai *dai)
938{
939 struct snd_soc_pcm_runtime *rtd = substream->private_data;
940 struct snd_soc_device *socdev = rtd->socdev;
941 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 942 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 943 int ret = 0;
944
945 switch (cmd) {
946 case SNDRV_PCM_TRIGGER_START:
947 case SNDRV_PCM_TRIGGER_RESUME:
948 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 949 if (dac33->fifo_mode) {
c8bf93f0
PU		 950 dac33->state = DAC33_PREFILL;
951 queue_work(dac33->dac33_wq, &dac33->work);
952 }
953 break;
954 case SNDRV_PCM_TRIGGER_STOP:
955 case SNDRV_PCM_TRIGGER_SUSPEND:
956 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 957 if (dac33->fifo_mode) {
c8bf93f0
PU		 958 dac33->state = DAC33_FLUSH;
959 queue_work(dac33->dac33_wq, &dac33->work);
960 }
961 break;
962 default:
963 ret = -EINVAL;
964 }
965
966 return ret;
967}
968
969static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
970 int clk_id, unsigned int freq, int dir)
971{
972 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 973 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 974 u8 ioc_reg, asrcb_reg;
975
976 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
977 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
978 switch (clk_id) {
979 case TLV320DAC33_MCLK:
980 ioc_reg |= DAC33_REFSEL;
981 asrcb_reg |= DAC33_SRCREFSEL;
982 break;
983 case TLV320DAC33_SLEEPCLK:
984 ioc_reg &= ~DAC33_REFSEL;
985 asrcb_reg &= ~DAC33_SRCREFSEL;
986 break;
987 default:
988 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
989 break;
990 }
991 dac33->refclk = freq;
992
993 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
994 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
995
996 return 0;
997}
998
999static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1000 unsigned int fmt)
1001{
1002 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1003 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1004 u8 aictrl_a, aictrl_b;
1005
1006 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1007 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1008 /* set master/slave audio interface */
1009 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1010 case SND_SOC_DAIFMT_CBM_CFM:
1011 /* Codec Master */
1012 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1013 break;
1014 case SND_SOC_DAIFMT_CBS_CFS:
1015 /* Codec Slave */
adcb8bc0
PU		 1016 if (dac33->fifo_mode) {
1017 dev_err(codec->dev, "FIFO mode requires master mode\n");
1018 return -EINVAL;
1019 } else
1020 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 aictrl_a &= ~DAC33_AFMT_MASK;
1027 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1028 case SND_SOC_DAIFMT_I2S:
1029 aictrl_a |= DAC33_AFMT_I2S;
1030 break;
1031 case SND_SOC_DAIFMT_DSP_A:
1032 aictrl_a |= DAC33_AFMT_DSP;
1033 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1034 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1035 break;
1036 case SND_SOC_DAIFMT_RIGHT_J:
1037 aictrl_a |= DAC33_AFMT_RIGHT_J;
1038 break;
1039 case SND_SOC_DAIFMT_LEFT_J:
1040 aictrl_a |= DAC33_AFMT_LEFT_J;
1041 break;
1042 default:
1043 dev_err(codec->dev, "Unsupported format (%u)\n",
1044 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1045 return -EINVAL;
1046 }
1047
1048 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1049 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1050
1051 return 0;
1052}
1053
1054static void dac33_init_chip(struct snd_soc_codec *codec)
1055{
1056 /* 44-46: DAC Control Registers */
1057 /* A : DAC sample rate Fsref/1.5 */
fdb6b1e1 1058 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
c8bf93f0
PU		 1059 /* B : DAC src=normal, not muted */
1060 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1061 DAC33_DACSRCL_LEFT);
1062 /* C : (defaults) */
1063 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1064
1065 /* 64-65 : L&R DAC power control
1066 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1067 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1068 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1069
1070 /* 73 : volume soft stepping control,
1071 clock source = internal osc (?) */
1072 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1073
1074 /* 66 : LOP/LOM Modes */
1075 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1076
1077 /* 68 : LOM inverted from LOP */
1078 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1079
1080 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1081}
1082
1083static int dac33_soc_probe(struct platform_device *pdev)
1084{
1085 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1086 struct snd_soc_codec *codec;
1087 struct tlv320dac33_priv *dac33;
1088 int ret = 0;
1089
1090 BUG_ON(!tlv320dac33_codec);
1091
1092 codec = tlv320dac33_codec;
1093 socdev->card->codec = codec;
b2c812e2 1094 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1095
1096 /* Power up the codec */
1097 dac33_hard_power(codec, 1);
1098 /* Set default configuration */
1099 dac33_init_chip(codec);
1100
1101 /* register pcms */
1102 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1103 if (ret < 0) {
1104 dev_err(codec->dev, "failed to create pcms\n");
1105 goto pcm_err;
1106 }
1107
1108 snd_soc_add_controls(codec, dac33_snd_controls,
1109 ARRAY_SIZE(dac33_snd_controls));
1110 /* Only add the nSample controls, if we have valid IRQ number */
1111 if (dac33->irq >= 0)
1112 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1113 ARRAY_SIZE(dac33_nsample_snd_controls));
1114
1115 dac33_add_widgets(codec);
1116
1117 /* power on device */
1118 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1119
3a7aaed7
IK		 1120 /* Bias level configuration has enabled regulator an extra time */
1121 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1122
c8bf93f0 1123 return 0;
fe3e78e0 1124
c8bf93f0
PU		 1125pcm_err:
1126 dac33_hard_power(codec, 0);
1127 return ret;
1128}
1129
1130static int dac33_soc_remove(struct platform_device *pdev)
1131{
1132 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1133 struct snd_soc_codec *codec = socdev->card->codec;
1134
1135 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1136
1137 snd_soc_free_pcms(socdev);
1138 snd_soc_dapm_free(socdev);
1139
1140 return 0;
1141}
1142
1143static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1144{
1145 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1146 struct snd_soc_codec *codec = socdev->card->codec;
1147
1148 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1149
1150 return 0;
1151}
1152
1153static int dac33_soc_resume(struct platform_device *pdev)
1154{
1155 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1156 struct snd_soc_codec *codec = socdev->card->codec;
1157
1158 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1159 dac33_set_bias_level(codec, codec->suspend_bias_level);
1160
1161 return 0;
1162}
1163
1164struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1165 .probe = dac33_soc_probe,
1166 .remove = dac33_soc_remove,
1167 .suspend = dac33_soc_suspend,
1168 .resume = dac33_soc_resume,
1169};
1170EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1171
1172#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1173 SNDRV_PCM_RATE_48000)
1174#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1175
1176static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1177 .hw_params = dac33_hw_params,
1178 .prepare = dac33_pcm_prepare,
1179 .trigger = dac33_pcm_trigger,
1180 .set_sysclk = dac33_set_dai_sysclk,
1181 .set_fmt = dac33_set_dai_fmt,
1182};
1183
1184struct snd_soc_dai dac33_dai = {
1185 .name = "tlv320dac33",
1186 .playback = {
1187 .stream_name = "Playback",
1188 .channels_min = 2,
1189 .channels_max = 2,
1190 .rates = DAC33_RATES,
1191 .formats = DAC33_FORMATS,},
1192 .ops = &dac33_dai_ops,
1193};
1194EXPORT_SYMBOL_GPL(dac33_dai);
1195
735fe4cf
MB		 1196static int __devinit dac33_i2c_probe(struct i2c_client *client,
1197 const struct i2c_device_id *id)
c8bf93f0
PU		 1198{
1199 struct tlv320dac33_platform_data *pdata;
1200 struct tlv320dac33_priv *dac33;
1201 struct snd_soc_codec *codec;
3a7aaed7 1202 int ret, i;
c8bf93f0
PU		 1203
1204 if (client->dev.platform_data == NULL) {
1205 dev_err(&client->dev, "Platform data not set\n");
1206 return -ENODEV;
1207 }
1208 pdata = client->dev.platform_data;
1209
1210 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1211 if (dac33 == NULL)
1212 return -ENOMEM;
1213
1214 codec = &dac33->codec;
b2c812e2 1215 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1216 codec->control_data = client;
1217
1218 mutex_init(&codec->mutex);
1219 mutex_init(&dac33->mutex);
1220 INIT_LIST_HEAD(&codec->dapm_widgets);
1221 INIT_LIST_HEAD(&codec->dapm_paths);
1222
1223 codec->name = "tlv320dac33";
1224 codec->owner = THIS_MODULE;
1225 codec->read = dac33_read_reg_cache;
1226 codec->write = dac33_write_locked;
1227 codec->hw_write = (hw_write_t) i2c_master_send;
1228 codec->bias_level = SND_SOC_BIAS_OFF;
1229 codec->set_bias_level = dac33_set_bias_level;
1230 codec->dai = &dac33_dai;
1231 codec->num_dai = 1;
1232 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1233 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1234 GFP_KERNEL);
1235 if (codec->reg_cache == NULL) {
1236 ret = -ENOMEM;
1237 goto error_reg;
1238 }
1239
1240 i2c_set_clientdata(client, dac33);
1241
1242 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1243 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1244 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1245 dac33->irq = client->irq;
1246 dac33->nsample = NSAMPLE_MAX;
1247 /* Disable FIFO use by default */
7427b4b9 1248 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1249
1250 tlv320dac33_codec = codec;
1251
1252 codec->dev = &client->dev;
1253 dac33_dai.dev = codec->dev;
1254
1255 /* Check if the reset GPIO number is valid and request it */
1256 if (dac33->power_gpio >= 0) {
1257 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1258 if (ret < 0) {
1259 dev_err(codec->dev,
1260 "Failed to request reset GPIO (%d)\n",
1261 dac33->power_gpio);
1262 snd_soc_unregister_dai(&dac33_dai);
1263 snd_soc_unregister_codec(codec);
1264 goto error_gpio;
1265 }
1266 gpio_direction_output(dac33->power_gpio, 0);
1267 } else {
1268 dac33->chip_power = 1;
1269 }
1270
1271 /* Check if the IRQ number is valid and request it */
1272 if (dac33->irq >= 0) {
1273 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1274 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1275 codec->name, codec);
1276 if (ret < 0) {
1277 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1278 dac33->irq, ret);
1279 dac33->irq = -1;
1280 }
1281 if (dac33->irq != -1) {
1282 /* Setup work queue */
74ea23aa
PU		 1283 dac33->dac33_wq =
1284 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1285 if (dac33->dac33_wq == NULL) {
1286 free_irq(dac33->irq, &dac33->codec);
1287 ret = -ENOMEM;
1288 goto error_wq;
1289 }
1290
1291 INIT_WORK(&dac33->work, dac33_work);
1292 }
1293 }
1294
3a7aaed7
IK		 1295 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1296 dac33->supplies[i].supply = dac33_supply_names[i];
1297
1298 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1299 dac33->supplies);
1300
1301 if (ret != 0) {
1302 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1303 goto err_get;
1304 }
1305
1306 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1307 dac33->supplies);
1308 if (ret != 0) {
1309 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1310 goto err_enable;
1311 }
1312
c8bf93f0
PU		 1313 ret = snd_soc_register_codec(codec);
1314 if (ret != 0) {
1315 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1316 goto error_codec;
1317 }
1318
1319 ret = snd_soc_register_dai(&dac33_dai);
1320 if (ret != 0) {
1321 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1322 snd_soc_unregister_codec(codec);
1323 goto error_codec;
1324 }
1325
1326 /* Shut down the codec for now */
1327 dac33_hard_power(codec, 0);
1328
1329 return ret;
1330
1331error_codec:
3a7aaed7
IK		 1332 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1333err_enable:
1334 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1335err_get:
c8bf93f0
PU		 1336 if (dac33->irq >= 0) {
1337 free_irq(dac33->irq, &dac33->codec);
1338 destroy_workqueue(dac33->dac33_wq);
1339 }
1340error_wq:
1341 if (dac33->power_gpio >= 0)
1342 gpio_free(dac33->power_gpio);
1343error_gpio:
1344 kfree(codec->reg_cache);
1345error_reg:
1346 tlv320dac33_codec = NULL;
1347 kfree(dac33);
1348
1349 return ret;
1350}
1351
735fe4cf 1352static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1353{
1354 struct tlv320dac33_priv *dac33;
1355
1356 dac33 = i2c_get_clientdata(client);
1357 dac33_hard_power(&dac33->codec, 0);
1358
1359 if (dac33->power_gpio >= 0)
1360 gpio_free(dac33->power_gpio);
1361 if (dac33->irq >= 0)
1362 free_irq(dac33->irq, &dac33->codec);
1363
3a7aaed7
IK		 1364 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1365
c8bf93f0
PU		 1366 destroy_workqueue(dac33->dac33_wq);
1367 snd_soc_unregister_dai(&dac33_dai);
1368 snd_soc_unregister_codec(&dac33->codec);
1369 kfree(dac33->codec.reg_cache);
1370 kfree(dac33);
1371 tlv320dac33_codec = NULL;
1372
1373 return 0;
1374}
1375
1376static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1377 {
1378 .name = "tlv320dac33",
1379 .driver_data = 0,
1380 },
1381 { },
1382};
1383
1384static struct i2c_driver tlv320dac33_i2c_driver = {
1385 .driver = {
1386 .name = "tlv320dac33",
1387 .owner = THIS_MODULE,
1388 },
1389 .probe = dac33_i2c_probe,
1390 .remove = __devexit_p(dac33_i2c_remove),
1391 .id_table = tlv320dac33_i2c_id,
1392};
1393
1394static int __init dac33_module_init(void)
1395{
1396 int r;
1397 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1398 if (r < 0) {
1399 printk(KERN_ERR "DAC33: driver registration failed\n");
1400 return r;
1401 }
1402 return 0;
1403}
1404module_init(dac33_module_init);
1405
1406static void __exit dac33_module_exit(void)
1407{
1408 i2c_del_driver(&tlv320dac33_i2c_driver);
1409}
1410module_exit(dac33_module_exit);
1411
1412
1413MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1414MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1415MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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