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ASoC: Samsung: Rename from s3c24xx to samsung
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
cc17557e 35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e 37
f0fba2ad
LG		 38/* Register descriptions are here */
39#include <linux/mfd/twl4030-codec.h>
40
41/* Shadow register used by the audio driver */
42#define TWL4030_REG_SW_SHADOW 0x4A
43#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
44
45/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
46#define TWL4030_HFL_EN 0x01
47#define TWL4030_HFR_EN 0x02
cc17557e
SS		 48
49/*
50 * twl4030 register cache & default register settings
51 */
52static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
53 0x00, /* this register not used */
33f92ed4 54 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 55 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 56 0x00, /* REG_UNKNOWN (0x3) */
57 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 58 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 59 0x00, /* REG_ANAMICR (0x6) */
60 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 61 0x00, /* REG_ADCMICSEL (0x8) */
62 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 63 0x0f, /* REG_ATXL1PGA (0xA) */
64 0x0f, /* REG_ATXR1PGA (0xB) */
65 0x0f, /* REG_AVTXL2PGA (0xC) */
66 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 67 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 68 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 69 0x3f, /* REG_ARXR1PGA (0x10) */
70 0x3f, /* REG_ARXL1PGA (0x11) */
71 0x3f, /* REG_ARXR2PGA (0x12) */
72 0x3f, /* REG_ARXL2PGA (0x13) */
73 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 74 0x00, /* REG_VSTPGA (0x15) */
75 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 76 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 77 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 78 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
79 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
80 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
81 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 82 0x00, /* REG_ATX2ARXPGA (0x1D) */
83 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 84 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 85 0x00, /* REG_BTSTPGA (0x20) */
86 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 87 0x00, /* REG_HS_SEL (0x22) */
88 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 89 0x00, /* REG_HS_POPN_SET (0x24) */
90 0x00, /* REG_PREDL_CTL (0x25) */
91 0x00, /* REG_PREDR_CTL (0x26) */
92 0x00, /* REG_PRECKL_CTL (0x27) */
93 0x00, /* REG_PRECKR_CTL (0x28) */
94 0x00, /* REG_HFL_CTL (0x29) */
95 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 96 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 97 0x00, /* REG_ALC_SET1 (0x2C) */
98 0x00, /* REG_ALC_SET2 (0x2D) */
99 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 100 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 101 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 102 0x00, /* REG_DTMF_TONEXT1H (0x31) */
103 0x00, /* REG_DTMF_TONEXT1L (0x32) */
104 0x00, /* REG_DTMF_TONEXT2H (0x33) */
105 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 106 0x79, /* REG_DTMF_TONOFF (0x35) */
107 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 108 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
109 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
110 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 111 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 112 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 113 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
114 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 115 0x00, /* REG_MISC_SET_1 (0x3E) */
116 0x00, /* REG_PCMBTMUX (0x3F) */
117 0x00, /* not used (0x40) */
118 0x00, /* not used (0x41) */
119 0x00, /* not used (0x42) */
120 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 121 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 122 0x00, /* REG_VIBRA_CTL (0x45) */
123 0x00, /* REG_VIBRA_SET (0x46) */
124 0x00, /* REG_VIBRA_PWM_SET (0x47) */
125 0x00, /* REG_ANAMIC_GAIN (0x48) */
126 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 127 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 128};
129
7393958f
PU		 130/* codec private data */
131struct twl4030_priv {
7a1fecf5
PU		 132 struct snd_soc_codec codec;
133
7393958f 134 unsigned int codec_powered;
7b4c734e
PU		 135
136 /* reference counts of AIF/APLL users */
2845fa13 137 unsigned int apll_enabled;
7220b9f4
PU		 138
139 struct snd_pcm_substream *master_substream;
140 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 141
142 unsigned int configured;
143 unsigned int rate;
144 unsigned int sample_bits;
145 unsigned int channels;
6943c92e
PU		 146
147 unsigned int sysclk;
148
c96907f2
PU		 149 /* Output (with associated amp) states */
150 u8 hsl_enabled, hsr_enabled;
151 u8 earpiece_enabled;
152 u8 predrivel_enabled, predriver_enabled;
153 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2
PU		 154
155 /* Delay needed after enabling the digimic interface */
156 unsigned int digimic_delay;
7393958f
PU		 157};
158
cc17557e
SS		 159/*
160 * read twl4030 register cache
161 */
162static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
163 unsigned int reg)
164{
d08664fd 165 u8 *cache = codec->reg_cache;
cc17557e 166
91432e97
IM		 167 if (reg >= TWL4030_CACHEREGNUM)
168 return -EIO;
169
cc17557e
SS		 170 return cache[reg];
171}
172
173/*
174 * write twl4030 register cache
175 */
176static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
177 u8 reg, u8 value)
178{
179 u8 *cache = codec->reg_cache;
180
181 if (reg >= TWL4030_CACHEREGNUM)
182 return;
183 cache[reg] = value;
184}
185
186/*
187 * write to the twl4030 register space
188 */
189static int twl4030_write(struct snd_soc_codec *codec,
190 unsigned int reg, unsigned int value)
191{
b2c812e2 192 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 193 int write_to_reg = 0;
194
cc17557e 195 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 196 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
197 /* Decide if the given register can be written */
198 switch (reg) {
199 case TWL4030_REG_EAR_CTL:
200 if (twl4030->earpiece_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PREDL_CTL:
204 if (twl4030->predrivel_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_PREDR_CTL:
208 if (twl4030->predriver_enabled)
209 write_to_reg = 1;
210 break;
211 case TWL4030_REG_PRECKL_CTL:
212 if (twl4030->carkitl_enabled)
213 write_to_reg = 1;
214 break;
215 case TWL4030_REG_PRECKR_CTL:
216 if (twl4030->carkitr_enabled)
217 write_to_reg = 1;
218 break;
219 case TWL4030_REG_HS_GAIN_SET:
220 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
221 write_to_reg = 1;
222 break;
223 default:
224 /* All other register can be written */
225 write_to_reg = 1;
226 break;
227 }
228 if (write_to_reg)
229 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
230 value, reg);
231 }
232 return 0;
cc17557e
SS		 233}
234
db04e2c5 235static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 236{
b2c812e2 237 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 238 int mode;
cc17557e 239
7393958f
PU		 240 if (enable == twl4030->codec_powered)
241 return;
242
db04e2c5 243 if (enable)
7a1fecf5 244 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 245 else
7a1fecf5 246 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 247
7a1fecf5
PU		 248 if (mode >= 0) {
249 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
250 twl4030->codec_powered = enable;
251 }
cc17557e
SS		 252
253 /* REVISIT: this delay is present in TI sample drivers */
254 /* but there seems to be no TRM requirement for it */
255 udelay(10);
256}
257
9fdcc0f7 258static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 259{
9fdcc0f7
PU		 260 int i, difference = 0;
261 u8 val;
262
263 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
264 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
265 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
266 if (val != twl4030_reg[i]) {
267 difference++;
268 dev_dbg(codec->dev,
269 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
270 i, val, twl4030_reg[i]);
271 }
272 }
273 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
274 difference, difference ? "Not OK" : "OK");
275}
cc17557e 276
a3a29b55
PU		 277static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
278{
279 int i;
cc17557e
SS		 280
281 /* set all audio section registers to reasonable defaults */
282 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 283 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 284 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 285
286}
287
f0fba2ad 288static void twl4030_init_chip(struct snd_soc_codec *codec)
7393958f 289{
f0fba2ad 290 struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev);
b2c812e2 291 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 292 u8 reg, byte;
293 int i = 0;
7393958f 294
9fdcc0f7 295 /* Check defaults, if instructed before anything else */
f0fba2ad 296 if (pdata && pdata->check_defaults)
9fdcc0f7 297 twl4030_check_defaults(codec);
7a1fecf5 298
a3a29b55 299 /* Reset registers, if no setup data or if instructed to do so */
f0fba2ad 300 if (!pdata || (pdata && pdata->reset_registers))
a3a29b55 301 twl4030_reset_registers(codec);
7393958f 302
ee4ccac7 303 /* Refresh APLL_CTL register from HW */
9fdcc0f7 304 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 305 TWL4030_REG_APLL_CTL);
306 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 307
ee4ccac7
PU		 308 /* anti-pop when changing analog gain */
309 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
310 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
311 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 312
ee4ccac7
PU		 313 twl4030_write(codec, TWL4030_REG_OPTION,
314 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
315 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 316
3c36cc68
PU		 317 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
318 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
319
ee4ccac7 320 /* Machine dependent setup */
f0fba2ad 321 if (!pdata)
7393958f
PU		 322 return;
323
f0fba2ad 324 twl4030->digimic_delay = pdata->digimic_delay;
ee4ccac7
PU		 325
326 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
327 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 328 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 329 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 330
331 /* initiate offset cancellation */
ee4ccac7
PU		 332 twl4030_codec_enable(codec, 1);
333
334 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
335 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 336 reg |= pdata->offset_cncl_path;
006f367e 337 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 338 reg | TWL4030_CNCL_OFFSET_START);
006f367e
PU		 339
340 /* wait for offset cancellation to complete */
341 do {
342 /* this takes a little while, so don't slam i2c */
343 udelay(2000);
fc7b92fc 344 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 345 TWL4030_REG_ANAMICL);
346 } while ((i++ < 100) &&
347 ((byte & TWL4030_CNCL_OFFSET_START) ==
348 TWL4030_CNCL_OFFSET_START));
349
350 /* Make sure that the reg_cache has the same value as the HW */
351 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
352
006f367e 353 twl4030_codec_enable(codec, 0);
006f367e
PU		 354}
355
ee4ccac7 356static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 357{
ee4ccac7
PU		 358 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
359 int status = -1;
360
361 if (enable) {
362 twl4030->apll_enabled++;
363 if (twl4030->apll_enabled == 1)
364 status = twl4030_codec_enable_resource(
365 TWL4030_CODEC_RES_APLL);
366 } else {
367 twl4030->apll_enabled--;
368 if (!twl4030->apll_enabled)
369 status = twl4030_codec_disable_resource(
370 TWL4030_CODEC_RES_APLL);
371 }
372
373 if (status >= 0)
374 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 375}
376
5e98a464 377/* Earpiece */
1a787e7a
JS		 378static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
379 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
380 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
381 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
382 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
383};
5e98a464 384
2a6f5c58 385/* PreDrive Left */
1a787e7a
JS		 386static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
387 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
388 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
389 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
390 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
391};
2a6f5c58
PU		 392
393/* PreDrive Right */
1a787e7a
JS		 394static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
395 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
396 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
397 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
398 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
399};
2a6f5c58 400
dfad21a2 401/* Headset Left */
1a787e7a
JS		 402static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
403 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
404 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
405 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
406};
dfad21a2
PU		 407
408/* Headset Right */
1a787e7a
JS		 409static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
410 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
411 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
412 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
413};
dfad21a2 414
5152d8c2 415/* Carkit Left */
1a787e7a
JS		 416static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
417 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
418 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
419 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
420};
5152d8c2
PU		 421
422/* Carkit Right */
1a787e7a
JS		 423static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
424 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
425 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
426 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
427};
5152d8c2 428
df339804
PU		 429/* Handsfree Left */
430static const char *twl4030_handsfreel_texts[] =
1a787e7a 431 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 432
433static const struct soc_enum twl4030_handsfreel_enum =
434 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
435 ARRAY_SIZE(twl4030_handsfreel_texts),
436 twl4030_handsfreel_texts);
437
438static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
439SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
440
0f89bdca
PU		 441/* Handsfree Left virtual mute */
442static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
443 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
444
df339804
PU		 445/* Handsfree Right */
446static const char *twl4030_handsfreer_texts[] =
1a787e7a 447 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 448
449static const struct soc_enum twl4030_handsfreer_enum =
450 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
451 ARRAY_SIZE(twl4030_handsfreer_texts),
452 twl4030_handsfreer_texts);
453
454static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
455SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
456
0f89bdca
PU		 457/* Handsfree Right virtual mute */
458static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
459 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
460
376f7839
PU		 461/* Vibra */
462/* Vibra audio path selection */
463static const char *twl4030_vibra_texts[] =
464 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
465
466static const struct soc_enum twl4030_vibra_enum =
467 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
468 ARRAY_SIZE(twl4030_vibra_texts),
469 twl4030_vibra_texts);
470
471static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
472SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
473
474/* Vibra path selection: local vibrator (PWM) or audio driven */
475static const char *twl4030_vibrapath_texts[] =
476 {"Local vibrator", "Audio"};
477
478static const struct soc_enum twl4030_vibrapath_enum =
479 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
480 ARRAY_SIZE(twl4030_vibrapath_texts),
481 twl4030_vibrapath_texts);
482
483static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
484SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
485
276c6222 486/* Left analog microphone selection */
97b8096d 487static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 488 SOC_DAPM_SINGLE("Main Mic Capture Switch",
489 TWL4030_REG_ANAMICL, 0, 1, 0),
490 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
491 TWL4030_REG_ANAMICL, 1, 1, 0),
492 SOC_DAPM_SINGLE("AUXL Capture Switch",
493 TWL4030_REG_ANAMICL, 2, 1, 0),
494 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
495 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 496};
276c6222
PU		 497
498/* Right analog microphone selection */
97b8096d 499static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 500 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
501 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 502};
276c6222
PU		 503
504/* TX1 L/R Analog/Digital microphone selection */
505static const char *twl4030_micpathtx1_texts[] =
506 {"Analog", "Digimic0"};
507
508static const struct soc_enum twl4030_micpathtx1_enum =
509 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
510 ARRAY_SIZE(twl4030_micpathtx1_texts),
511 twl4030_micpathtx1_texts);
512
513static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
514SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
515
516/* TX2 L/R Analog/Digital microphone selection */
517static const char *twl4030_micpathtx2_texts[] =
518 {"Analog", "Digimic1"};
519
520static const struct soc_enum twl4030_micpathtx2_enum =
521 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
522 ARRAY_SIZE(twl4030_micpathtx2_texts),
523 twl4030_micpathtx2_texts);
524
525static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
526SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
527
7393958f
PU		 528/* Analog bypass for AudioR1 */
529static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
530 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
531
532/* Analog bypass for AudioL1 */
533static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
534 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
535
536/* Analog bypass for AudioR2 */
537static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
538 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
539
540/* Analog bypass for AudioL2 */
541static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
542 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
543
fcd274a3
LCM		 544/* Analog bypass for Voice */
545static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
546 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
547
8b0d3153 548/* Digital bypass gain, mute instead of -30dB */
6bab83fd 549static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 550 TLV_DB_RANGE_HEAD(3),
551 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
552 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 553 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
554};
555
556/* Digital bypass left (TX1L -> RX2L) */
557static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
558 SOC_DAPM_SINGLE_TLV("Volume",
559 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
560 twl4030_dapm_dbypass_tlv);
561
562/* Digital bypass right (TX1R -> RX2R) */
563static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
564 SOC_DAPM_SINGLE_TLV("Volume",
565 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
566 twl4030_dapm_dbypass_tlv);
567
ee8f6894
LCM		 568/*
569 * Voice Sidetone GAIN volume control:
570 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
571 */
572static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
573
574/* Digital bypass voice: sidetone (VUL -> VDL)*/
575static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
576 SOC_DAPM_SINGLE_TLV("Volume",
577 TWL4030_REG_VSTPGA, 0, 0x29, 0,
578 twl4030_dapm_dbypassv_tlv);
579
9008adf9
PU		 580/*
581 * Output PGA builder:
582 * Handle the muting and unmuting of the given output (turning off the
583 * amplifier associated with the output pin)
c96907f2
PU		 584 * On mute bypass the reg_cache and write 0 to the register
585 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 586 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
587 */
588#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
589static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
590 struct snd_kcontrol *kcontrol, int event) \
591{ \
b2c812e2 592 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 593 \
594 switch (event) { \
595 case SND_SOC_DAPM_POST_PMU: \
c96907f2 596 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 597 twl4030_write(w->codec, reg, \
598 twl4030_read_reg_cache(w->codec, reg)); \
599 break; \
600 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 601 twl4030->pin_name##_enabled = 0; \
602 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
603 0, reg); \
9008adf9
PU		 604 break; \
605 } \
606 return 0; \
607}
608
609TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
610TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
611TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
612TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
613TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
614
5a2e9a48 615static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 616{
49d92c7d
SM		 617 unsigned char hs_ctl;
618
5a2e9a48 619 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 620
5a2e9a48
PU		 621 if (ramp) {
622 /* HF ramp-up */
623 hs_ctl |= TWL4030_HF_CTL_REF_EN;
624 twl4030_write(codec, reg, hs_ctl);
625 udelay(10);
49d92c7d 626 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 627 twl4030_write(codec, reg, hs_ctl);
628 udelay(40);
49d92c7d 629 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 630 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 631 twl4030_write(codec, reg, hs_ctl);
49d92c7d 632 } else {
5a2e9a48
PU		 633 /* HF ramp-down */
634 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
635 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
636 twl4030_write(codec, reg, hs_ctl);
637 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
638 twl4030_write(codec, reg, hs_ctl);
639 udelay(40);
640 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
641 twl4030_write(codec, reg, hs_ctl);
49d92c7d 642 }
5a2e9a48 643}
49d92c7d 644
5a2e9a48
PU		 645static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
646 struct snd_kcontrol *kcontrol, int event)
647{
648 switch (event) {
649 case SND_SOC_DAPM_POST_PMU:
650 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
651 break;
652 case SND_SOC_DAPM_POST_PMD:
653 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
654 break;
655 }
656 return 0;
657}
658
659static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
660 struct snd_kcontrol *kcontrol, int event)
661{
662 switch (event) {
663 case SND_SOC_DAPM_POST_PMU:
664 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
665 break;
666 case SND_SOC_DAPM_POST_PMD:
667 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
668 break;
669 }
49d92c7d
SM		 670 return 0;
671}
672
86139a13
JV		 673static int vibramux_event(struct snd_soc_dapm_widget *w,
674 struct snd_kcontrol *kcontrol, int event)
675{
676 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
677 return 0;
678}
679
7729cf74
PU		 680static int apll_event(struct snd_soc_dapm_widget *w,
681 struct snd_kcontrol *kcontrol, int event)
682{
683 switch (event) {
684 case SND_SOC_DAPM_PRE_PMU:
685 twl4030_apll_enable(w->codec, 1);
686 break;
687 case SND_SOC_DAPM_POST_PMD:
688 twl4030_apll_enable(w->codec, 0);
689 break;
690 }
691 return 0;
692}
693
7b4c734e
PU		 694static int aif_event(struct snd_soc_dapm_widget *w,
695 struct snd_kcontrol *kcontrol, int event)
696{
697 u8 audio_if;
698
699 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
700 switch (event) {
701 case SND_SOC_DAPM_PRE_PMU:
702 /* Enable AIF */
703 /* enable the PLL before we use it to clock the DAI */
704 twl4030_apll_enable(w->codec, 1);
705
706 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
707 audio_if | TWL4030_AIF_EN);
708 break;
709 case SND_SOC_DAPM_POST_PMD:
710 /* disable the DAI before we stop it's source PLL */
711 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
712 audio_if & ~TWL4030_AIF_EN);
713 twl4030_apll_enable(w->codec, 0);
714 break;
715 }
716 return 0;
717}
718
6943c92e 719static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 720{
f0fba2ad 721 struct twl4030_codec_audio_data *pdata = codec->dev->platform_data;
aad749e5 722 unsigned char hs_gain, hs_pop;
b2c812e2 723 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 724 /* Base values for ramp delay calculation: 2^19 - 2^26 */
725 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
726 8388608, 16777216, 33554432, 67108864};
aad749e5 727
6943c92e
PU		 728 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
729 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 730
4e49ffd1
CVJ		 731 /* Enable external mute control, this dramatically reduces
732 * the pop-noise */
f0fba2ad
LG		 733 if (pdata && pdata->hs_extmute) {
734 if (pdata->set_hs_extmute) {
735 pdata->set_hs_extmute(1);
4e49ffd1
CVJ		 736 } else {
737 hs_pop |= TWL4030_EXTMUTE;
738 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
739 }
740 }
741
6943c92e
PU		 742 if (ramp) {
743 /* Headset ramp-up according to the TRM */
aad749e5 744 hs_pop |= TWL4030_VMID_EN;
6943c92e 745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 746 /* Actually write to the register */
747 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
748 hs_gain,
749 TWL4030_REG_HS_GAIN_SET);
aad749e5 750 hs_pop |= TWL4030_RAMP_EN;
6943c92e 751 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 752 /* Wait ramp delay time + 1, so the VMID can settle */
753 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
754 twl4030->sysclk) + 1);
6943c92e
PU		 755 } else {
756 /* Headset ramp-down _not_ according to
757 * the TRM, but in a way that it is working */
aad749e5 758 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 759 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
760 /* Wait ramp delay time + 1, so the VMID can settle */
761 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
762 twl4030->sysclk) + 1);
aad749e5 763 /* Bypass the reg_cache to mute the headset */
fc7b92fc 764 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 765 hs_gain & (~0x0f),
766 TWL4030_REG_HS_GAIN_SET);
6943c92e 767
aad749e5 768 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 769 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
770 }
4e49ffd1
CVJ		 771
772 /* Disable external mute */
f0fba2ad
LG		 773 if (pdata && pdata->hs_extmute) {
774 if (pdata->set_hs_extmute) {
775 pdata->set_hs_extmute(0);
4e49ffd1
CVJ		 776 } else {
777 hs_pop &= ~TWL4030_EXTMUTE;
778 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
779 }
780 }
6943c92e
PU		 781}
782
783static int headsetlpga_event(struct snd_soc_dapm_widget *w,
784 struct snd_kcontrol *kcontrol, int event)
785{
b2c812e2 786 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 787
788 switch (event) {
789 case SND_SOC_DAPM_POST_PMU:
790 /* Do the ramp-up only once */
791 if (!twl4030->hsr_enabled)
792 headset_ramp(w->codec, 1);
793
794 twl4030->hsl_enabled = 1;
795 break;
796 case SND_SOC_DAPM_POST_PMD:
797 /* Do the ramp-down only if both headsetL/R is disabled */
798 if (!twl4030->hsr_enabled)
799 headset_ramp(w->codec, 0);
800
801 twl4030->hsl_enabled = 0;
802 break;
803 }
804 return 0;
805}
806
807static int headsetrpga_event(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809{
b2c812e2 810 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 811
812 switch (event) {
813 case SND_SOC_DAPM_POST_PMU:
814 /* Do the ramp-up only once */
815 if (!twl4030->hsl_enabled)
816 headset_ramp(w->codec, 1);
817
818 twl4030->hsr_enabled = 1;
819 break;
820 case SND_SOC_DAPM_POST_PMD:
821 /* Do the ramp-down only if both headsetL/R is disabled */
822 if (!twl4030->hsl_enabled)
823 headset_ramp(w->codec, 0);
824
825 twl4030->hsr_enabled = 0;
aad749e5
PU		 826 break;
827 }
828 return 0;
829}
830
01ea6ba2
PU		 831static int digimic_event(struct snd_soc_dapm_widget *w,
832 struct snd_kcontrol *kcontrol, int event)
833{
834 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
835
836 if (twl4030->digimic_delay)
837 mdelay(twl4030->digimic_delay);
838 return 0;
839}
840
b0bd53a7
PU		 841/*
842 * Some of the gain controls in TWL (mostly those which are associated with
843 * the outputs) are implemented in an interesting way:
844 * 0x0 : Power down (mute)
845 * 0x1 : 6dB
846 * 0x2 : 0 dB
847 * 0x3 : -6 dB
848 * Inverting not going to help with these.
849 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
850 */
851#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
852 xinvert, tlv_array) \
853{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
854 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
855 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
856 .tlv.p = (tlv_array), \
857 .info = snd_soc_info_volsw, \
858 .get = snd_soc_get_volsw_twl4030, \
859 .put = snd_soc_put_volsw_twl4030, \
860 .private_value = (unsigned long)&(struct soc_mixer_control) \
861 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
862 .max = xmax, .invert = xinvert} }
863#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
864 xinvert, tlv_array) \
865{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
866 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
867 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
868 .tlv.p = (tlv_array), \
869 .info = snd_soc_info_volsw_2r, \
870 .get = snd_soc_get_volsw_r2_twl4030,\
871 .put = snd_soc_put_volsw_r2_twl4030, \
872 .private_value = (unsigned long)&(struct soc_mixer_control) \
873 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 874 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 875#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
876 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
877 xinvert, tlv_array)
878
879static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_value *ucontrol)
881{
882 struct soc_mixer_control *mc =
883 (struct soc_mixer_control *)kcontrol->private_value;
884 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
885 unsigned int reg = mc->reg;
886 unsigned int shift = mc->shift;
887 unsigned int rshift = mc->rshift;
888 int max = mc->max;
889 int mask = (1 << fls(max)) - 1;
890
891 ucontrol->value.integer.value[0] =
892 (snd_soc_read(codec, reg) >> shift) & mask;
893 if (ucontrol->value.integer.value[0])
894 ucontrol->value.integer.value[0] =
895 max + 1 - ucontrol->value.integer.value[0];
896
897 if (shift != rshift) {
898 ucontrol->value.integer.value[1] =
899 (snd_soc_read(codec, reg) >> rshift) & mask;
900 if (ucontrol->value.integer.value[1])
901 ucontrol->value.integer.value[1] =
902 max + 1 - ucontrol->value.integer.value[1];
903 }
904
905 return 0;
906}
907
908static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
909 struct snd_ctl_elem_value *ucontrol)
910{
911 struct soc_mixer_control *mc =
912 (struct soc_mixer_control *)kcontrol->private_value;
913 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
914 unsigned int reg = mc->reg;
915 unsigned int shift = mc->shift;
916 unsigned int rshift = mc->rshift;
917 int max = mc->max;
918 int mask = (1 << fls(max)) - 1;
919 unsigned short val, val2, val_mask;
920
921 val = (ucontrol->value.integer.value[0] & mask);
922
923 val_mask = mask << shift;
924 if (val)
925 val = max + 1 - val;
926 val = val << shift;
927 if (shift != rshift) {
928 val2 = (ucontrol->value.integer.value[1] & mask);
929 val_mask |= mask << rshift;
930 if (val2)
931 val2 = max + 1 - val2;
932 val |= val2 << rshift;
933 }
934 return snd_soc_update_bits(codec, reg, val_mask, val);
935}
936
937static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
938 struct snd_ctl_elem_value *ucontrol)
939{
940 struct soc_mixer_control *mc =
941 (struct soc_mixer_control *)kcontrol->private_value;
942 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
943 unsigned int reg = mc->reg;
944 unsigned int reg2 = mc->rreg;
945 unsigned int shift = mc->shift;
946 int max = mc->max;
947 int mask = (1<<fls(max))-1;
948
949 ucontrol->value.integer.value[0] =
950 (snd_soc_read(codec, reg) >> shift) & mask;
951 ucontrol->value.integer.value[1] =
952 (snd_soc_read(codec, reg2) >> shift) & mask;
953
954 if (ucontrol->value.integer.value[0])
955 ucontrol->value.integer.value[0] =
956 max + 1 - ucontrol->value.integer.value[0];
957 if (ucontrol->value.integer.value[1])
958 ucontrol->value.integer.value[1] =
959 max + 1 - ucontrol->value.integer.value[1];
960
961 return 0;
962}
963
964static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
965 struct snd_ctl_elem_value *ucontrol)
966{
967 struct soc_mixer_control *mc =
968 (struct soc_mixer_control *)kcontrol->private_value;
969 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
970 unsigned int reg = mc->reg;
971 unsigned int reg2 = mc->rreg;
972 unsigned int shift = mc->shift;
973 int max = mc->max;
974 int mask = (1 << fls(max)) - 1;
975 int err;
976 unsigned short val, val2, val_mask;
977
978 val_mask = mask << shift;
979 val = (ucontrol->value.integer.value[0] & mask);
980 val2 = (ucontrol->value.integer.value[1] & mask);
981
982 if (val)
983 val = max + 1 - val;
984 if (val2)
985 val2 = max + 1 - val2;
986
987 val = val << shift;
988 val2 = val2 << shift;
989
990 err = snd_soc_update_bits(codec, reg, val_mask, val);
991 if (err < 0)
992 return err;
993
994 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
995 return err;
996}
997
b74bd40f
LCM		 998/* Codec operation modes */
999static const char *twl4030_op_modes_texts[] = {
1000 "Option 2 (voice/audio)", "Option 1 (audio)"
1001};
1002
1003static const struct soc_enum twl4030_op_modes_enum =
1004 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1005 ARRAY_SIZE(twl4030_op_modes_texts),
1006 twl4030_op_modes_texts);
1007
423c238d 1008static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1009 struct snd_ctl_elem_value *ucontrol)
1010{
1011 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1012 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1013 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1014 unsigned short val;
1015 unsigned short mask, bitmask;
1016
1017 if (twl4030->configured) {
1018 printk(KERN_ERR "twl4030 operation mode cannot be "
1019 "changed on-the-fly\n");
1020 return -EBUSY;
1021 }
1022
1023 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1024 ;
1025 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1026 return -EINVAL;
1027
1028 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1029 mask = (bitmask - 1) << e->shift_l;
1030 if (e->shift_l != e->shift_r) {
1031 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1032 return -EINVAL;
1033 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1034 mask |= (bitmask - 1) << e->shift_r;
1035 }
1036
1037 return snd_soc_update_bits(codec, e->reg, mask, val);
1038}
1039
c10b82cf
PU		 1040/*
1041 * FGAIN volume control:
1042 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1043 */
d889a72c 1044static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1045
0d33ea0b
PU		 1046/*
1047 * CGAIN volume control:
1048 * 0 dB to 12 dB in 6 dB steps
1049 * value 2 and 3 means 12 dB
1050 */
d889a72c
PU		 1051static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1052
1a787e7a
JS		 1053/*
1054 * Voice Downlink GAIN volume control:
1055 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1056 */
1057static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1058
d889a72c
PU		 1059/*
1060 * Analog playback gain
1061 * -24 dB to 12 dB in 2 dB steps
1062 */
1063static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1064
4290239c
PU		 1065/*
1066 * Gain controls tied to outputs
1067 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1068 */
1069static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1070
18cc8d8d
JS		 1071/*
1072 * Gain control for earpiece amplifier
1073 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1074 */
1075static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1076
381a22b5
PU		 1077/*
1078 * Capture gain after the ADCs
1079 * from 0 dB to 31 dB in 1 dB steps
1080 */
1081static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1082
5920b453
GI		 1083/*
1084 * Gain control for input amplifiers
1085 * 0 dB to 30 dB in 6 dB steps
1086 */
1087static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1088
328d0a13
LCM		 1089/* AVADC clock priority */
1090static const char *twl4030_avadc_clk_priority_texts[] = {
1091 "Voice high priority", "HiFi high priority"
1092};
1093
1094static const struct soc_enum twl4030_avadc_clk_priority_enum =
1095 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1096 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1097 twl4030_avadc_clk_priority_texts);
1098
89492be8
PU		 1099static const char *twl4030_rampdelay_texts[] = {
1100 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1101 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1102 "3495/2581/1748 ms"
1103};
1104
1105static const struct soc_enum twl4030_rampdelay_enum =
1106 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1107 ARRAY_SIZE(twl4030_rampdelay_texts),
1108 twl4030_rampdelay_texts);
1109
376f7839
PU		 1110/* Vibra H-bridge direction mode */
1111static const char *twl4030_vibradirmode_texts[] = {
1112 "Vibra H-bridge direction", "Audio data MSB",
1113};
1114
1115static const struct soc_enum twl4030_vibradirmode_enum =
1116 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1117 ARRAY_SIZE(twl4030_vibradirmode_texts),
1118 twl4030_vibradirmode_texts);
1119
1120/* Vibra H-bridge direction */
1121static const char *twl4030_vibradir_texts[] = {
1122 "Positive polarity", "Negative polarity",
1123};
1124
1125static const struct soc_enum twl4030_vibradir_enum =
1126 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1127 ARRAY_SIZE(twl4030_vibradir_texts),
1128 twl4030_vibradir_texts);
1129
36aeff61
PU		 1130/* Digimic Left and right swapping */
1131static const char *twl4030_digimicswap_texts[] = {
1132 "Not swapped", "Swapped",
1133};
1134
1135static const struct soc_enum twl4030_digimicswap_enum =
1136 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1137 ARRAY_SIZE(twl4030_digimicswap_texts),
1138 twl4030_digimicswap_texts);
1139
cc17557e 1140static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1141 /* Codec operation mode control */
1142 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1143 snd_soc_get_enum_double,
1144 snd_soc_put_twl4030_opmode_enum_double),
1145
d889a72c
PU		 1146 /* Common playback gain controls */
1147 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1148 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1149 0, 0x3f, 0, digital_fine_tlv),
1150 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1151 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1152 0, 0x3f, 0, digital_fine_tlv),
1153
1154 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1155 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1156 6, 0x2, 0, digital_coarse_tlv),
1157 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1158 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1159 6, 0x2, 0, digital_coarse_tlv),
1160
1161 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1162 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1163 3, 0x12, 1, analog_tlv),
1164 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1165 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1166 3, 0x12, 1, analog_tlv),
44c55870
PU		 1167 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1168 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1169 1, 1, 0),
1170 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1171 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1172 1, 1, 0),
381a22b5 1173
1a787e7a
JS		 1174 /* Common voice downlink gain controls */
1175 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1176 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1177
1178 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1179 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1180
1181 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1182 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1183
4290239c
PU		 1184 /* Separate output gain controls */
1185 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1186 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1187 4, 3, 0, output_tvl),
1188
1189 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1190 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1191
1192 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1193 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1194 4, 3, 0, output_tvl),
1195
1196 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1197 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1198
381a22b5 1199 /* Common capture gain controls */
276c6222 1200 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1201 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1202 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1203 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1204 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1205 0, 0x1f, 0, digital_capture_tlv),
5920b453 1206
276c6222 1207 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1208 0, 3, 5, 0, input_gain_tlv),
89492be8 1209
328d0a13
LCM		 1210 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1211
89492be8 1212 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1213
1214 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1215 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1216
1217 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1218};
1219
cc17557e 1220static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1221 /* Left channel inputs */
1222 SND_SOC_DAPM_INPUT("MAINMIC"),
1223 SND_SOC_DAPM_INPUT("HSMIC"),
1224 SND_SOC_DAPM_INPUT("AUXL"),
1225 SND_SOC_DAPM_INPUT("CARKITMIC"),
1226 /* Right channel inputs */
1227 SND_SOC_DAPM_INPUT("SUBMIC"),
1228 SND_SOC_DAPM_INPUT("AUXR"),
1229 /* Digital microphones (Stereo) */
1230 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1231 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1232
1233 /* Outputs */
5e98a464 1234 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1235 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1236 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1237 SND_SOC_DAPM_OUTPUT("HSOL"),
1238 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1239 SND_SOC_DAPM_OUTPUT("CARKITL"),
1240 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1241 SND_SOC_DAPM_OUTPUT("HFL"),
1242 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1243 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1244
7b4c734e
PU		 1245 /* AIF and APLL clocks for running DAIs (including loopback) */
1246 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1247 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1248 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1249
53b5047d 1250 /* DACs */
b4852b79 1251 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1252 SND_SOC_NOPM, 0, 0),
b4852b79 1253 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1254 SND_SOC_NOPM, 0, 0),
b4852b79 1255 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1256 SND_SOC_NOPM, 0, 0),
b4852b79 1257 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1258 SND_SOC_NOPM, 0, 0),
1a787e7a 1259 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1260 SND_SOC_NOPM, 0, 0),
cc17557e 1261
7393958f 1262 /* Analog bypasses */
78e08e2f
PU		 1263 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1264 &twl4030_dapm_abypassr1_control),
1265 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1266 &twl4030_dapm_abypassl1_control),
1267 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1268 &twl4030_dapm_abypassr2_control),
1269 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1270 &twl4030_dapm_abypassl2_control),
1271 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1272 &twl4030_dapm_abypassv_control),
1273
1274 /* Master analog loopback switch */
1275 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1276 NULL, 0),
7393958f 1277
6bab83fd 1278 /* Digital bypasses */
78e08e2f
PU		 1279 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1280 &twl4030_dapm_dbypassl_control),
1281 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1282 &twl4030_dapm_dbypassr_control),
1283 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1284 &twl4030_dapm_dbypassv_control),
6bab83fd 1285
4005d39a
PU		 1286 /* Digital mixers, power control for the physical DACs */
1287 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1288 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1289 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1290 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1291 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1292 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1293 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1294 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1295 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1296 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1297
1298 /* Analog mixers, power control for the physical PGAs */
1299 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1300 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1301 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1302 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1303 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1304 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1305 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1306 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1307 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1308 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1309
7729cf74
PU		 1310 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1311 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1312
7b4c734e
PU		 1313 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1314 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1315
1a787e7a 1316 /* Output MIXER controls */
5e98a464 1317 /* Earpiece */
1a787e7a
JS		 1318 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1319 &twl4030_dapm_earpiece_controls[0],
1320 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1321 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1322 0, 0, NULL, 0, earpiecepga_event,
1323 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1324 /* PreDrivL/R */
1a787e7a
JS		 1325 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1326 &twl4030_dapm_predrivel_controls[0],
1327 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1328 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1329 0, 0, NULL, 0, predrivelpga_event,
1330 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1331 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1332 &twl4030_dapm_predriver_controls[0],
1333 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1334 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1335 0, 0, NULL, 0, predriverpga_event,
1336 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1337 /* HeadsetL/R */
6943c92e 1338 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1339 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1340 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1341 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1342 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1343 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1344 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1345 &twl4030_dapm_hsor_controls[0],
1346 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1347 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1348 0, 0, NULL, 0, headsetrpga_event,
1349 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1350 /* CarkitL/R */
1a787e7a
JS		 1351 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1352 &twl4030_dapm_carkitl_controls[0],
1353 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1354 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1355 0, 0, NULL, 0, carkitlpga_event,
1356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1357 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1358 &twl4030_dapm_carkitr_controls[0],
1359 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1360 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1361 0, 0, NULL, 0, carkitrpga_event,
1362 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1363
1364 /* Output MUX controls */
df339804 1365 /* HandsfreeL/R */
5a2e9a48
PU		 1366 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1367 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1368 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1369 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1370 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1371 0, 0, NULL, 0, handsfreelpga_event,
1372 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1373 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1374 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1375 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1376 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1377 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1378 0, 0, NULL, 0, handsfreerpga_event,
1379 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1380 /* Vibra */
86139a13
JV		 1381 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1382 &twl4030_dapm_vibra_control, vibramux_event,
1383 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1384 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1385 &twl4030_dapm_vibrapath_control),
5e98a464 1386
276c6222
PU		 1387 /* Introducing four virtual ADC, since TWL4030 have four channel for
1388 capture */
1389 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1390 SND_SOC_NOPM, 0, 0),
1391 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1392 SND_SOC_NOPM, 0, 0),
1393 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1394 SND_SOC_NOPM, 0, 0),
1395 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1396 SND_SOC_NOPM, 0, 0),
1397
1398 /* Analog/Digital mic path selection.
1399 TX1 Left/Right: either analog Left/Right or Digimic0
1400 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1401 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1402 &twl4030_dapm_micpathtx1_control),
1403 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1404 &twl4030_dapm_micpathtx2_control),
276c6222 1405
97b8096d 1406 /* Analog input mixers for the capture amplifiers */
9028935d 1407 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1408 TWL4030_REG_ANAMICL, 4, 0,
1409 &twl4030_dapm_analoglmic_controls[0],
1410 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1411 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1412 TWL4030_REG_ANAMICR, 4, 0,
1413 &twl4030_dapm_analogrmic_controls[0],
1414 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1415
fb2a2f84
PU		 1416 SND_SOC_DAPM_PGA("ADC Physical Left",
1417 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1418 SND_SOC_DAPM_PGA("ADC Physical Right",
1419 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1420
01ea6ba2
PU		 1421 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1422 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1423 digimic_event, SND_SOC_DAPM_POST_PMU),
1424 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1425 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1426 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1427
bda7d2a8
PU		 1428 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1429 NULL, 0),
1430 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1431 NULL, 0),
1432
276c6222
PU		 1433 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1434 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1435 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1436
cc17557e
SS		 1437};
1438
1439static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1440 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1441 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1442 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1443 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1444 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1445
7729cf74 1446 /* Supply for the digital part (APLL) */
7729cf74
PU		 1447 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1448
27eeb1fe
PU		 1449 {"DAC Left1", NULL, "AIF Enable"},
1450 {"DAC Right1", NULL, "AIF Enable"},
1451 {"DAC Left2", NULL, "AIF Enable"},
1452 {"DAC Right1", NULL, "AIF Enable"},
1453
c42a59ea
PU		 1454 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1455 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1456
4005d39a
PU		 1457 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1458 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1459 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1460 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1461 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1462
5e98a464
PU		 1463 /* Internal playback routings */
1464 /* Earpiece */
4005d39a
PU		 1465 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1466 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1467 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1468 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1469 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1470 /* PreDrivL */
4005d39a
PU		 1471 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1472 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1473 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1474 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1475 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1476 /* PreDrivR */
4005d39a
PU		 1477 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1478 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1479 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1480 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1481 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1482 /* HeadsetL */
4005d39a
PU		 1483 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1484 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1485 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1486 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1487 /* HeadsetR */
4005d39a
PU		 1488 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1489 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1490 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1491 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1492 /* CarkitL */
4005d39a
PU		 1493 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1494 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1495 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1496 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1497 /* CarkitR */
4005d39a
PU		 1498 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1499 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1500 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1501 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1502 /* HandsfreeL */
4005d39a
PU		 1503 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1504 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1505 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1506 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1507 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1508 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1509 /* HandsfreeR */
4005d39a
PU		 1510 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1511 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1512 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1513 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1514 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1515 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1516 /* Vibra */
1517 {"Vibra Mux", "AudioL1", "DAC Left1"},
1518 {"Vibra Mux", "AudioR1", "DAC Right1"},
1519 {"Vibra Mux", "AudioL2", "DAC Left2"},
1520 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1521
cc17557e 1522 /* outputs */
7b4c734e 1523 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1524 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1525 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1526 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1527 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1528 /* Must be always connected (for APLL) */
1529 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1530 /* Physical outputs */
9008adf9
PU		 1531 {"EARPIECE", NULL, "Earpiece PGA"},
1532 {"PREDRIVEL", NULL, "PredriveL PGA"},
1533 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1534 {"HSOL", NULL, "HeadsetL PGA"},
1535 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1536 {"CARKITL", NULL, "CarkitL PGA"},
1537 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1538 {"HFL", NULL, "HandsfreeL PGA"},
1539 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1540 {"Vibra Route", "Audio", "Vibra Mux"},
1541 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1542
276c6222 1543 /* Capture path */
7b4c734e
PU		 1544 /* Must be always connected (for AIF and APLL) */
1545 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1546 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1547 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1548 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1549 /* Physical inputs */
9028935d
PU		 1550 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1551 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1552 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1553 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1554
9028935d
PU		 1555 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1556 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1557
9028935d
PU		 1558 {"ADC Physical Left", NULL, "Analog Left"},
1559 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1560
1561 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1562 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1563
bda7d2a8
PU		 1564 {"DIGIMIC0", NULL, "micbias1 select"},
1565 {"DIGIMIC1", NULL, "micbias2 select"},
1566
276c6222 1567 /* TX1 Left capture path */
fb2a2f84 1568 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1569 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1570 /* TX1 Right capture path */
fb2a2f84 1571 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1572 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1573 /* TX2 Left capture path */
fb2a2f84 1574 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1575 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1576 /* TX2 Right capture path */
fb2a2f84 1577 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1578 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1579
1580 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1581 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1582 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1583 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1584
c42a59ea
PU		 1585 {"ADC Virtual Left1", NULL, "AIF Enable"},
1586 {"ADC Virtual Right1", NULL, "AIF Enable"},
1587 {"ADC Virtual Left2", NULL, "AIF Enable"},
1588 {"ADC Virtual Right2", NULL, "AIF Enable"},
1589
7393958f 1590 /* Analog bypass routes */
9028935d
PU		 1591 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1592 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1593 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1594 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1595 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1596
78e08e2f
PU		 1597 /* Supply for the Analog loopbacks */
1598 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1599 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1600 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1601 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1602 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1603
7393958f
PU		 1604 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1605 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1606 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1607 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1608 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1609
6bab83fd
PU		 1610 /* Digital bypass routes */
1611 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1612 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1613 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1614
4005d39a
PU		 1615 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1616 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1617 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1618
cc17557e
SS		 1619};
1620
1621static int twl4030_add_widgets(struct snd_soc_codec *codec)
1622{
ce6120cc 1623 struct snd_soc_dapm_context *dapm = &codec->dapm;
cc17557e 1624
ce6120cc
LG		 1625 snd_soc_dapm_new_controls(dapm, twl4030_dapm_widgets,
1626 ARRAY_SIZE(twl4030_dapm_widgets));
1627 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
cc17557e 1628
cc17557e
SS		 1629 return 0;
1630}
1631
cc17557e
SS		 1632static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1633 enum snd_soc_bias_level level)
1634{
1635 switch (level) {
1636 case SND_SOC_BIAS_ON:
cc17557e
SS		 1637 break;
1638 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1639 break;
1640 case SND_SOC_BIAS_STANDBY:
ce6120cc 1641 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1642 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1643 break;
1644 case SND_SOC_BIAS_OFF:
cbd2db12 1645 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1646 break;
1647 }
ce6120cc 1648 codec->dapm.bias_level = level;
cc17557e
SS		 1649
1650 return 0;
1651}
1652
6b87a91f
PU		 1653static void twl4030_constraints(struct twl4030_priv *twl4030,
1654 struct snd_pcm_substream *mst_substream)
1655{
1656 struct snd_pcm_substream *slv_substream;
1657
1658 /* Pick the stream, which need to be constrained */
1659 if (mst_substream == twl4030->master_substream)
1660 slv_substream = twl4030->slave_substream;
1661 else if (mst_substream == twl4030->slave_substream)
1662 slv_substream = twl4030->master_substream;
1663 else /* This should not happen.. */
1664 return;
1665
1666 /* Set the constraints according to the already configured stream */
1667 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1668 SNDRV_PCM_HW_PARAM_RATE,
1669 twl4030->rate,
1670 twl4030->rate);
1671
1672 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1673 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1674 twl4030->sample_bits,
1675 twl4030->sample_bits);
1676
1677 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1678 SNDRV_PCM_HW_PARAM_CHANNELS,
1679 twl4030->channels,
1680 twl4030->channels);
1681}
1682
8a1f936a
PU		 1683/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1684 * capture has to be enabled/disabled. */
1685static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1686 int enable)
1687{
1688 u8 reg, mask;
1689
1690 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1691
1692 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1693 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1694 else
1695 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1696
1697 if (enable)
1698 reg |= mask;
1699 else
1700 reg &= ~mask;
1701
1702 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1703}
1704
d6648da1
PU		 1705static int twl4030_startup(struct snd_pcm_substream *substream,
1706 struct snd_soc_dai *dai)
7220b9f4
PU		 1707{
1708 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1709 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1710 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1711
7220b9f4 1712 if (twl4030->master_substream) {
7220b9f4 1713 twl4030->slave_substream = substream;
6b87a91f
PU		 1714 /* The DAI has one configuration for playback and capture, so
1715 * if the DAI has been already configured then constrain this
1716 * substream to match it. */
1717 if (twl4030->configured)
1718 twl4030_constraints(twl4030, twl4030->master_substream);
1719 } else {
8a1f936a
PU		 1720 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1721 TWL4030_OPTION_1)) {
1722 /* In option2 4 channel is not supported, set the
1723 * constraint for the first stream for channels, the
1724 * second stream will 'inherit' this cosntraint */
1725 snd_pcm_hw_constraint_minmax(substream->runtime,
1726 SNDRV_PCM_HW_PARAM_CHANNELS,
1727 2, 2);
1728 }
7220b9f4 1729 twl4030->master_substream = substream;
6b87a91f 1730 }
7220b9f4
PU		 1731
1732 return 0;
1733}
1734
d6648da1
PU		 1735static void twl4030_shutdown(struct snd_pcm_substream *substream,
1736 struct snd_soc_dai *dai)
7220b9f4
PU		 1737{
1738 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1739 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1740 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1741
1742 if (twl4030->master_substream == substream)
1743 twl4030->master_substream = twl4030->slave_substream;
1744
1745 twl4030->slave_substream = NULL;
6b87a91f
PU		 1746
1747 /* If all streams are closed, or the remaining stream has not yet
1748 * been configured than set the DAI as not configured. */
1749 if (!twl4030->master_substream)
1750 twl4030->configured = 0;
1751 else if (!twl4030->master_substream->runtime->channels)
1752 twl4030->configured = 0;
8a1f936a
PU		 1753
1754 /* If the closing substream had 4 channel, do the necessary cleanup */
1755 if (substream->runtime->channels == 4)
1756 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1757}
1758
cc17557e 1759static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1760 struct snd_pcm_hw_params *params,
1761 struct snd_soc_dai *dai)
cc17557e
SS		 1762{
1763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1764 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1765 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1766 u8 mode, old_mode, format, old_format;
1767
8a1f936a
PU		 1768 /* If the substream has 4 channel, do the necessary setup */
1769 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1770 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1771 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1772
1773 /* Safety check: are we in the correct operating mode and
1774 * the interface is in TDM mode? */
1775 if ((mode & TWL4030_OPTION_1) &&
1776 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1777 twl4030_tdm_enable(codec, substream->stream, 1);
1778 else
1779 return -EINVAL;
1780 }
1781
6b87a91f
PU		 1782 if (twl4030->configured)
1783 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1784 return 0;
1785
cc17557e
SS		 1786 /* bit rate */
1787 old_mode = twl4030_read_reg_cache(codec,
1788 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1789 mode = old_mode & ~TWL4030_APLL_RATE;
1790
1791 switch (params_rate(params)) {
1792 case 8000:
1793 mode |= TWL4030_APLL_RATE_8000;
1794 break;
1795 case 11025:
1796 mode |= TWL4030_APLL_RATE_11025;
1797 break;
1798 case 12000:
1799 mode |= TWL4030_APLL_RATE_12000;
1800 break;
1801 case 16000:
1802 mode |= TWL4030_APLL_RATE_16000;
1803 break;
1804 case 22050:
1805 mode |= TWL4030_APLL_RATE_22050;
1806 break;
1807 case 24000:
1808 mode |= TWL4030_APLL_RATE_24000;
1809 break;
1810 case 32000:
1811 mode |= TWL4030_APLL_RATE_32000;
1812 break;
1813 case 44100:
1814 mode |= TWL4030_APLL_RATE_44100;
1815 break;
1816 case 48000:
1817 mode |= TWL4030_APLL_RATE_48000;
1818 break;
103f211d
PU		 1819 case 96000:
1820 mode |= TWL4030_APLL_RATE_96000;
1821 break;
cc17557e
SS		 1822 default:
1823 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1824 params_rate(params));
1825 return -EINVAL;
1826 }
1827
cc17557e
SS		 1828 /* sample size */
1829 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1830 format = old_format;
1831 format &= ~TWL4030_DATA_WIDTH;
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 format |= TWL4030_DATA_WIDTH_16S_16W;
1835 break;
1836 case SNDRV_PCM_FORMAT_S24_LE:
1837 format |= TWL4030_DATA_WIDTH_32S_24W;
1838 break;
1839 default:
1840 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1841 params_format(params));
1842 return -EINVAL;
1843 }
1844
2046f175
PU		 1845 if (format != old_format || mode != old_mode) {
1846 if (twl4030->codec_powered) {
1847 /*
1848 * If the codec is powered, than we need to toggle the
1849 * codec power.
1850 */
1851 twl4030_codec_enable(codec, 0);
1852 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1853 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1854 twl4030_codec_enable(codec, 1);
1855 } else {
1856 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1857 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1858 }
cc17557e 1859 }
6b87a91f
PU		 1860
1861 /* Store the important parameters for the DAI configuration and set
1862 * the DAI as configured */
1863 twl4030->configured = 1;
1864 twl4030->rate = params_rate(params);
1865 twl4030->sample_bits = hw_param_interval(params,
1866 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1867 twl4030->channels = params_channels(params);
1868
1869 /* If both playback and capture streams are open, and one of them
1870 * is setting the hw parameters right now (since we are here), set
1871 * constraints to the other stream to match the current one. */
1872 if (twl4030->slave_substream)
1873 twl4030_constraints(twl4030, substream);
1874
cc17557e
SS		 1875 return 0;
1876}
1877
1878static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1879 int clk_id, unsigned int freq, int dir)
1880{
1881 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1882 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1883
1884 switch (freq) {
1885 case 19200000:
cc17557e 1886 case 26000000:
cc17557e 1887 case 38400000:
cc17557e
SS		 1888 break;
1889 default:
68d01955 1890 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1891 return -EINVAL;
1892 }
1893
68d01955
PU		 1894 if ((freq / 1000) != twl4030->sysclk) {
1895 dev_err(codec->dev,
1896 "Mismatch in APLL mclk: %u (configured: %u)\n",
1897 freq, twl4030->sysclk * 1000);
1898 return -EINVAL;
1899 }
cc17557e
SS		 1900
1901 return 0;
1902}
1903
1904static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1905 unsigned int fmt)
1906{
1907 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1908 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1909 u8 old_format, format;
1910
1911 /* get format */
1912 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1913 format = old_format;
1914
1915 /* set master/slave audio interface */
1916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1917 case SND_SOC_DAIFMT_CBM_CFM:
1918 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1919 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1920 break;
1921 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1922 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1923 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1924 break;
1925 default:
1926 return -EINVAL;
1927 }
1928
1929 /* interface format */
1930 format &= ~TWL4030_AIF_FORMAT;
1931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1932 case SND_SOC_DAIFMT_I2S:
1933 format |= TWL4030_AIF_FORMAT_CODEC;
1934 break;
8a1f936a
PU		 1935 case SND_SOC_DAIFMT_DSP_A:
1936 format |= TWL4030_AIF_FORMAT_TDM;
1937 break;
cc17557e
SS		 1938 default:
1939 return -EINVAL;
1940 }
1941
1942 if (format != old_format) {
2046f175
PU		 1943 if (twl4030->codec_powered) {
1944 /*
1945 * If the codec is powered, than we need to toggle the
1946 * codec power.
1947 */
1948 twl4030_codec_enable(codec, 0);
1949 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1950 twl4030_codec_enable(codec, 1);
1951 } else {
1952 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1953 }
cc17557e
SS		 1954 }
1955
1956 return 0;
1957}
1958
68140443
LCM		 1959static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1960{
1961 struct snd_soc_codec *codec = dai->codec;
1962 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1963
1964 if (tristate)
1965 reg |= TWL4030_AIF_TRI_EN;
1966 else
1967 reg &= ~TWL4030_AIF_TRI_EN;
1968
1969 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1970}
1971
b7a755a8
MLC		 1972/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1973 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1974static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1975 int enable)
1976{
1977 u8 reg, mask;
1978
1979 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1980
1981 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1982 mask = TWL4030_ARXL1_VRX_EN;
1983 else
1984 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1985
1986 if (enable)
1987 reg |= mask;
1988 else
1989 reg &= ~mask;
1990
1991 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1992}
1993
7154b3e8
JS		 1994static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1995 struct snd_soc_dai *dai)
1996{
1997 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1998 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1999 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2000 u8 mode;
2001
2002 /* If the system master clock is not 26MHz, the voice PCM interface is
2003 * not avilable.
2004 */
68d01955
PU		 2005 if (twl4030->sysclk != 26000) {
2006 dev_err(codec->dev, "The board is configured for %u Hz, while"
2007 "the Voice interface needs 26MHz APLL mclk\n",
2008 twl4030->sysclk * 1000);
7154b3e8
JS		 2009 return -EINVAL;
2010 }
2011
2012 /* If the codec mode is not option2, the voice PCM interface is not
2013 * avilable.
2014 */
2015 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2016 & TWL4030_OPT_MODE;
2017
2018 if (mode != TWL4030_OPTION_2) {
2019 printk(KERN_ERR "TWL4030 voice startup: "
2020 "the codec mode is not option2\n");
2021 return -EINVAL;
2022 }
2023
2024 return 0;
2025}
2026
b7a755a8
MLC		 2027static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2028 struct snd_soc_dai *dai)
2029{
2030 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 2031 struct snd_soc_codec *codec = rtd->codec;
b7a755a8
MLC		 2032
2033 /* Enable voice digital filters */
2034 twl4030_voice_enable(codec, substream->stream, 0);
2035}
2036
7154b3e8
JS		 2037static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2038 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2039{
2040 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 2041 struct snd_soc_codec *codec = rtd->codec;
2046f175 2042 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2043 u8 old_mode, mode;
2044
b7a755a8
MLC		 2045 /* Enable voice digital filters */
2046 twl4030_voice_enable(codec, substream->stream, 1);
2047
7154b3e8
JS		 2048 /* bit rate */
2049 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2050 & ~(TWL4030_CODECPDZ);
2051 mode = old_mode;
2052
2053 switch (params_rate(params)) {
2054 case 8000:
2055 mode &= ~(TWL4030_SEL_16K);
2056 break;
2057 case 16000:
2058 mode |= TWL4030_SEL_16K;
2059 break;
2060 default:
2061 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2062 params_rate(params));
2063 return -EINVAL;
2064 }
2065
2066 if (mode != old_mode) {
2046f175
PU		 2067 if (twl4030->codec_powered) {
2068 /*
2069 * If the codec is powered, than we need to toggle the
2070 * codec power.
2071 */
2072 twl4030_codec_enable(codec, 0);
2073 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2074 twl4030_codec_enable(codec, 1);
2075 } else {
2076 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2077 }
7154b3e8
JS		 2078 }
2079
2080 return 0;
2081}
2082
2083static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2084 int clk_id, unsigned int freq, int dir)
2085{
2086 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2087 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2088
68d01955
PU		 2089 if (freq != 26000000) {
2090 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2091 "interface needs 26MHz APLL mclk\n", freq);
2092 return -EINVAL;
2093 }
2094 if ((freq / 1000) != twl4030->sysclk) {
2095 dev_err(codec->dev,
2096 "Mismatch in APLL mclk: %u (configured: %u)\n",
2097 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2098 return -EINVAL;
2099 }
7154b3e8
JS		 2100 return 0;
2101}
2102
2103static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2104 unsigned int fmt)
2105{
2106 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2107 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2108 u8 old_format, format;
2109
2110 /* get format */
2111 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2112 format = old_format;
2113
2114 /* set master/slave audio interface */
2115 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2116 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2117 format &= ~(TWL4030_VIF_SLAVE_EN);
2118 break;
2119 case SND_SOC_DAIFMT_CBS_CFS:
2120 format |= TWL4030_VIF_SLAVE_EN;
2121 break;
2122 default:
2123 return -EINVAL;
2124 }
2125
2126 /* clock inversion */
2127 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2128 case SND_SOC_DAIFMT_IB_NF:
2129 format &= ~(TWL4030_VIF_FORMAT);
2130 break;
2131 case SND_SOC_DAIFMT_NB_IF:
2132 format |= TWL4030_VIF_FORMAT;
2133 break;
2134 default:
2135 return -EINVAL;
2136 }
2137
2138 if (format != old_format) {
2046f175
PU		 2139 if (twl4030->codec_powered) {
2140 /*
2141 * If the codec is powered, than we need to toggle the
2142 * codec power.
2143 */
2144 twl4030_codec_enable(codec, 0);
2145 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2146 twl4030_codec_enable(codec, 1);
2147 } else {
2148 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2149 }
7154b3e8
JS		 2150 }
2151
2152 return 0;
2153}
2154
68140443
LCM		 2155static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2156{
2157 struct snd_soc_codec *codec = dai->codec;
2158 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2159
2160 if (tristate)
2161 reg |= TWL4030_VIF_TRI_EN;
2162 else
2163 reg &= ~TWL4030_VIF_TRI_EN;
2164
2165 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2166}
2167
bbba9444 2168#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2169#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2170
f0fba2ad 2171static struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2172 .startup = twl4030_startup,
2173 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2174 .hw_params = twl4030_hw_params,
2175 .set_sysclk = twl4030_set_dai_sysclk,
2176 .set_fmt = twl4030_set_dai_fmt,
68140443 2177 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2178};
2179
7154b3e8
JS		 2180static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2181 .startup = twl4030_voice_startup,
b7a755a8 2182 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2183 .hw_params = twl4030_voice_hw_params,
2184 .set_sysclk = twl4030_voice_set_dai_sysclk,
2185 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2186 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2187};
2188
f0fba2ad 2189static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2190{
f0fba2ad 2191 .name = "twl4030-hifi",
cc17557e 2192 .playback = {
b4852b79 2193 .stream_name = "HiFi Playback",
cc17557e 2194 .channels_min = 2,
8a1f936a 2195 .channels_max = 4,
31ad0f31 2196 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2197 .formats = TWL4030_FORMATS,},
2198 .capture = {
2199 .stream_name = "Capture",
2200 .channels_min = 2,
8a1f936a 2201 .channels_max = 4,
cc17557e
SS		 2202 .rates = TWL4030_RATES,
2203 .formats = TWL4030_FORMATS,},
f0fba2ad 2204 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2205},
2206{
f0fba2ad 2207 .name = "twl4030-voice",
7154b3e8 2208 .playback = {
b4852b79 2209 .stream_name = "Voice Playback",
7154b3e8
JS		 2210 .channels_min = 1,
2211 .channels_max = 1,
2212 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2213 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2214 .capture = {
2215 .stream_name = "Capture",
2216 .channels_min = 1,
2217 .channels_max = 2,
2218 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2219 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2220 .ops = &twl4030_dai_voice_ops,
2221},
cc17557e 2222};
cc17557e 2223
f0fba2ad 2224static int twl4030_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
cc17557e 2225{
cc17557e 2226 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
cc17557e
SS		 2227 return 0;
2228}
2229
f0fba2ad 2230static int twl4030_soc_resume(struct snd_soc_codec *codec)
cc17557e 2231{
cc17557e 2232 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2233 return 0;
2234}
2235
f0fba2ad 2236static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2237{
f0fba2ad 2238 struct twl4030_priv *twl4030;
9da28c7b 2239
f0fba2ad
LG		 2240 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2241 if (twl4030 == NULL) {
2242 printk("Can not allocate memroy\n");
2243 return -ENOMEM;
cc17557e 2244 }
f0fba2ad
LG		 2245 snd_soc_codec_set_drvdata(codec, twl4030);
2246 /* Set the defaults, and power up the codec */
2247 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
ce6120cc 2248 codec->dapm.idle_bias_off = 1;
f0fba2ad
LG		 2249
2250 twl4030_init_chip(codec);
cc17557e 2251
3e8e1952
IM		 2252 snd_soc_add_controls(codec, twl4030_snd_controls,
2253 ARRAY_SIZE(twl4030_snd_controls));
cc17557e 2254 twl4030_add_widgets(codec);
7a1fecf5 2255 return 0;
cc17557e
SS		 2256}
2257
f0fba2ad 2258static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2259{
5dcba5d6
PU		 2260 /* Reset registers to their chip default before leaving */
2261 twl4030_reset_registers(codec);
7a1fecf5 2262 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
7a1fecf5
PU		 2263 return 0;
2264}
2265
f0fba2ad
LG		 2266static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2267 .probe = twl4030_soc_probe,
2268 .remove = twl4030_soc_remove,
2269 .suspend = twl4030_soc_suspend,
2270 .resume = twl4030_soc_resume,
2271 .read = twl4030_read_reg_cache,
2272 .write = twl4030_write,
2273 .set_bias_level = twl4030_set_bias_level,
2274 .reg_cache_size = sizeof(twl4030_reg),
2275 .reg_word_size = sizeof(u8),
2276 .reg_cache_default = twl4030_reg,
2277};
2278
7a1fecf5
PU		 2279static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2280{
2281 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2282
68d01955
PU		 2283 if (!pdata) {
2284 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2285 return -EINVAL;
2286 }
cc17557e 2287
f0fba2ad
LG		 2288 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2289 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2290}
2291
7a1fecf5 2292static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2293{
f0fba2ad 2294 struct twl4030_priv *twl4030 = dev_get_drvdata(&pdev->dev);
cc17557e 2295
f0fba2ad 2296 snd_soc_unregister_codec(&pdev->dev);
7a1fecf5 2297 kfree(twl4030);
cc17557e
SS		 2298 return 0;
2299}
2300
f0fba2ad 2301MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2302
2303static struct platform_driver twl4030_codec_driver = {
2304 .probe = twl4030_codec_probe,
2305 .remove = __devexit_p(twl4030_codec_remove),
2306 .driver = {
f0fba2ad 2307 .name = "twl4030-codec",
7a1fecf5
PU		 2308 .owner = THIS_MODULE,
2309 },
cc17557e 2310};
cc17557e 2311
24e07db8 2312static int __init twl4030_modinit(void)
64089b84 2313{
7a1fecf5 2314 return platform_driver_register(&twl4030_codec_driver);
64089b84 2315}
24e07db8 2316module_init(twl4030_modinit);
64089b84
MB		 2317
2318static void __exit twl4030_exit(void)
2319{
7a1fecf5 2320 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2321}
2322module_exit(twl4030_exit);
2323
cc17557e
SS		 2324MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2325MODULE_AUTHOR("Steve Sakoman");
2326MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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