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ASoC: twl4030: Remove reset registers functionality
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e
SS		 50
51/*
52 * twl4030 register cache & default register settings
53 */
54static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
55 0x00, /* this register not used */
33f92ed4 56 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 57 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 58 0x00, /* REG_UNKNOWN (0x3) */
59 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 60 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 61 0x00, /* REG_ANAMICR (0x6) */
62 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 63 0x00, /* REG_ADCMICSEL (0x8) */
64 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 65 0x0f, /* REG_ATXL1PGA (0xA) */
66 0x0f, /* REG_ATXR1PGA (0xB) */
67 0x0f, /* REG_AVTXL2PGA (0xC) */
68 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 69 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 70 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 71 0x3f, /* REG_ARXR1PGA (0x10) */
72 0x3f, /* REG_ARXL1PGA (0x11) */
73 0x3f, /* REG_ARXR2PGA (0x12) */
74 0x3f, /* REG_ARXL2PGA (0x13) */
75 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 76 0x00, /* REG_VSTPGA (0x15) */
77 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 78 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 79 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 80 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
81 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
82 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
83 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 84 0x00, /* REG_ATX2ARXPGA (0x1D) */
85 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 86 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 87 0x00, /* REG_BTSTPGA (0x20) */
88 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 89 0x00, /* REG_HS_SEL (0x22) */
90 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 91 0x00, /* REG_HS_POPN_SET (0x24) */
92 0x00, /* REG_PREDL_CTL (0x25) */
93 0x00, /* REG_PREDR_CTL (0x26) */
94 0x00, /* REG_PRECKL_CTL (0x27) */
95 0x00, /* REG_PRECKR_CTL (0x28) */
96 0x00, /* REG_HFL_CTL (0x29) */
97 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 98 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 99 0x00, /* REG_ALC_SET1 (0x2C) */
100 0x00, /* REG_ALC_SET2 (0x2D) */
101 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 102 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 103 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 104 0x00, /* REG_DTMF_TONEXT1H (0x31) */
105 0x00, /* REG_DTMF_TONEXT1L (0x32) */
106 0x00, /* REG_DTMF_TONEXT2H (0x33) */
107 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 108 0x79, /* REG_DTMF_TONOFF (0x35) */
109 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 110 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
111 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
112 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 113 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 114 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 115 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
116 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 117 0x00, /* REG_MISC_SET_1 (0x3E) */
118 0x00, /* REG_PCMBTMUX (0x3F) */
119 0x00, /* not used (0x40) */
120 0x00, /* not used (0x41) */
121 0x00, /* not used (0x42) */
122 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 123 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 124 0x00, /* REG_VIBRA_CTL (0x45) */
125 0x00, /* REG_VIBRA_SET (0x46) */
126 0x00, /* REG_VIBRA_PWM_SET (0x47) */
127 0x00, /* REG_ANAMIC_GAIN (0x48) */
128 0x00, /* REG_MISC_SET_2 (0x49) */
129};
130
7393958f
PU		 131/* codec private data */
132struct twl4030_priv {
7393958f 133 unsigned int codec_powered;
7b4c734e
PU		 134
135 /* reference counts of AIF/APLL users */
2845fa13 136 unsigned int apll_enabled;
7220b9f4
PU		 137
138 struct snd_pcm_substream *master_substream;
139 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 140
141 unsigned int configured;
142 unsigned int rate;
143 unsigned int sample_bits;
144 unsigned int channels;
6943c92e
PU		 145
146 unsigned int sysclk;
147
c96907f2
PU		 148 /* Output (with associated amp) states */
149 u8 hsl_enabled, hsr_enabled;
150 u8 earpiece_enabled;
151 u8 predrivel_enabled, predriver_enabled;
152 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2 153
182f73f6 154 struct twl4030_codec_data *pdata;
7393958f
PU		 155};
156
cc17557e
SS		 157/*
158 * read twl4030 register cache
159 */
160static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
161 unsigned int reg)
162{
d08664fd 163 u8 *cache = codec->reg_cache;
cc17557e 164
91432e97
IM		 165 if (reg >= TWL4030_CACHEREGNUM)
166 return -EIO;
167
cc17557e
SS		 168 return cache[reg];
169}
170
171/*
172 * write twl4030 register cache
173 */
174static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
175 u8 reg, u8 value)
176{
177 u8 *cache = codec->reg_cache;
178
179 if (reg >= TWL4030_CACHEREGNUM)
180 return;
181 cache[reg] = value;
182}
183
a8fc415c
PU		 184static bool twl4030_can_write_to_chip(struct snd_soc_codec *codec,
185 unsigned int reg)
cc17557e 186{
b2c812e2 187 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
a8fc415c 188 bool write_to_reg = false;
c96907f2 189
052901f4
LPC		 190 /* Decide if the given register can be written */
191 switch (reg) {
192 case TWL4030_REG_EAR_CTL:
193 if (twl4030->earpiece_enabled)
a8fc415c 194 write_to_reg = true;
052901f4
LPC		 195 break;
196 case TWL4030_REG_PREDL_CTL:
197 if (twl4030->predrivel_enabled)
a8fc415c 198 write_to_reg = true;
052901f4
LPC		 199 break;
200 case TWL4030_REG_PREDR_CTL:
201 if (twl4030->predriver_enabled)
a8fc415c 202 write_to_reg = true;
052901f4
LPC		 203 break;
204 case TWL4030_REG_PRECKL_CTL:
205 if (twl4030->carkitl_enabled)
a8fc415c 206 write_to_reg = true;
052901f4
LPC		 207 break;
208 case TWL4030_REG_PRECKR_CTL:
209 if (twl4030->carkitr_enabled)
a8fc415c 210 write_to_reg = true;
052901f4
LPC		 211 break;
212 case TWL4030_REG_HS_GAIN_SET:
213 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 214 write_to_reg = true;
052901f4
LPC		 215 break;
216 default:
217 /* All other register can be written */
a8fc415c 218 write_to_reg = true;
052901f4 219 break;
c96907f2 220 }
a8fc415c
PU		 221
222 return write_to_reg;
223}
224
225/*
226 * write to the twl4030 register space
227 */
228static int twl4030_write(struct snd_soc_codec *codec,
229 unsigned int reg, unsigned int value)
230{
231 twl4030_write_reg_cache(codec, reg, value);
232 if (twl4030_can_write_to_chip(codec, reg))
233 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 234
c96907f2 235 return 0;
cc17557e
SS		 236}
237
7e6120c5
PU		 238static inline void twl4030_wait_ms(int time)
239{
240 if (time < 60) {
241 time *= 1000;
242 usleep_range(time, time + 500);
243 } else {
244 msleep(time);
245 }
246}
247
db04e2c5 248static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 249{
b2c812e2 250 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 251 int mode;
cc17557e 252
7393958f
PU		 253 if (enable == twl4030->codec_powered)
254 return;
255
db04e2c5 256 if (enable)
57fe7251 257 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 258 else
57fe7251 259 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 260
7a1fecf5
PU		 261 if (mode >= 0) {
262 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
263 twl4030->codec_powered = enable;
264 }
cc17557e
SS		 265
266 /* REVISIT: this delay is present in TI sample drivers */
267 /* but there seems to be no TRM requirement for it */
268 udelay(10);
269}
270
2d6d649a
PU		 271static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
272 struct device_node *node)
273{
274 int value;
275
276 of_property_read_u32(node, "ti,digimic_delay",
277 &pdata->digimic_delay);
278 of_property_read_u32(node, "ti,ramp_delay_value",
279 &pdata->ramp_delay_value);
280 of_property_read_u32(node, "ti,offset_cncl_path",
281 &pdata->offset_cncl_path);
282 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
283 pdata->hs_extmute = value;
284
285 pdata->hs_extmute_gpio = of_get_named_gpio(node,
286 "ti,hs_extmute_gpio", 0);
287 if (gpio_is_valid(pdata->hs_extmute_gpio))
288 pdata->hs_extmute = 1;
289}
290
291static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 292{
4ae6df5e 293 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 294 struct device_node *twl4030_codec_node = NULL;
295
296 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
297 "codec");
298
299 if (!pdata && twl4030_codec_node) {
300 pdata = devm_kzalloc(codec->dev,
301 sizeof(struct twl4030_codec_data),
302 GFP_KERNEL);
303 if (!pdata) {
304 dev_err(codec->dev, "Can not allocate memory\n");
305 return NULL;
306 }
307 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
308 }
309
310 return pdata;
311}
312
313static void twl4030_init_chip(struct snd_soc_codec *codec)
314{
315 struct twl4030_codec_data *pdata;
b2c812e2 316 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 317 u8 reg, byte;
318 int i = 0;
7393958f 319
2d6d649a
PU		 320 pdata = twl4030_get_pdata(codec);
321
5712ded9
PU		 322 if (pdata && pdata->hs_extmute) {
323 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
324 int ret;
325
326 if (!pdata->hs_extmute_gpio)
327 dev_warn(codec->dev,
328 "Extmute GPIO is 0 is this correct?\n");
329
330 ret = gpio_request_one(pdata->hs_extmute_gpio,
331 GPIOF_OUT_INIT_LOW,
332 "hs_extmute");
333 if (ret) {
334 dev_err(codec->dev,
335 "Failed to get hs_extmute GPIO\n");
336 pdata->hs_extmute_gpio = -1;
337 }
338 } else {
339 u8 pin_mux;
340
341 /* Set TWL4030 GPIO6 as EXTMUTE signal */
342 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
343 TWL4030_PMBR1_REG);
344 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
345 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
346 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
347 TWL4030_PMBR1_REG);
281ecd16
PU		 348 }
349 }
350
ee4ccac7 351 /* Refresh APLL_CTL register from HW */
9fdcc0f7 352 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 353 TWL4030_REG_APLL_CTL);
354 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 355
ee4ccac7
PU		 356 /* anti-pop when changing analog gain */
357 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
358 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
359 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 360
ee4ccac7
PU		 361 twl4030_write(codec, TWL4030_REG_OPTION,
362 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
363 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 364
3c36cc68
PU		 365 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
366 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
367
ee4ccac7 368 /* Machine dependent setup */
f0fba2ad 369 if (!pdata)
7393958f
PU		 370 return;
371
182f73f6 372 twl4030->pdata = pdata;
ee4ccac7
PU		 373
374 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
375 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 376 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 377 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 378
379 /* initiate offset cancellation */
ee4ccac7
PU		 380 twl4030_codec_enable(codec, 1);
381
382 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
383 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 384 reg |= pdata->offset_cncl_path;
006f367e 385 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 386 reg | TWL4030_CNCL_OFFSET_START);
006f367e 387
7e6120c5
PU		 388 /*
389 * Wait for offset cancellation to complete.
390 * Since this takes a while, do not slam the i2c.
391 * Start polling the status after ~20ms.
392 */
393 msleep(20);
006f367e 394 do {
7e6120c5 395 usleep_range(1000, 2000);
fc7b92fc 396 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 397 TWL4030_REG_ANAMICL);
398 } while ((i++ < 100) &&
399 ((byte & TWL4030_CNCL_OFFSET_START) ==
400 TWL4030_CNCL_OFFSET_START));
401
402 /* Make sure that the reg_cache has the same value as the HW */
403 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
404
006f367e 405 twl4030_codec_enable(codec, 0);
006f367e
PU		 406}
407
ee4ccac7 408static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 409{
ee4ccac7
PU		 410 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
411 int status = -1;
412
413 if (enable) {
414 twl4030->apll_enabled++;
415 if (twl4030->apll_enabled == 1)
57fe7251
PU		 416 status = twl4030_audio_enable_resource(
417 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 418 } else {
419 twl4030->apll_enabled--;
420 if (!twl4030->apll_enabled)
57fe7251
PU		 421 status = twl4030_audio_disable_resource(
422 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 423 }
424
425 if (status >= 0)
426 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 427}
428
5e98a464 429/* Earpiece */
1a787e7a
JS		 430static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
431 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
432 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
433 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
434 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
435};
5e98a464 436
2a6f5c58 437/* PreDrive Left */
1a787e7a
JS		 438static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
439 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
440 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
441 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
442 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
443};
2a6f5c58
PU		 444
445/* PreDrive Right */
1a787e7a
JS		 446static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
447 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
448 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
449 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
450 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
451};
2a6f5c58 452
dfad21a2 453/* Headset Left */
1a787e7a
JS		 454static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
455 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
456 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
457 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
458};
dfad21a2
PU		 459
460/* Headset Right */
1a787e7a
JS		 461static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
462 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
463 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
464 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
465};
dfad21a2 466
5152d8c2 467/* Carkit Left */
1a787e7a
JS		 468static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
469 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
470 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
471 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
472};
5152d8c2
PU		 473
474/* Carkit Right */
1a787e7a
JS		 475static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
476 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
477 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
478 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
479};
5152d8c2 480
df339804
PU		 481/* Handsfree Left */
482static const char *twl4030_handsfreel_texts[] =
1a787e7a 483 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 484
485static const struct soc_enum twl4030_handsfreel_enum =
486 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
487 ARRAY_SIZE(twl4030_handsfreel_texts),
488 twl4030_handsfreel_texts);
489
490static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
491SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
492
0f89bdca
PU		 493/* Handsfree Left virtual mute */
494static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 495 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 496
df339804
PU		 497/* Handsfree Right */
498static const char *twl4030_handsfreer_texts[] =
1a787e7a 499 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 500
501static const struct soc_enum twl4030_handsfreer_enum =
502 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
503 ARRAY_SIZE(twl4030_handsfreer_texts),
504 twl4030_handsfreer_texts);
505
506static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
507SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
508
0f89bdca
PU		 509/* Handsfree Right virtual mute */
510static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 511 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 512
376f7839
PU		 513/* Vibra */
514/* Vibra audio path selection */
515static const char *twl4030_vibra_texts[] =
516 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
517
518static const struct soc_enum twl4030_vibra_enum =
519 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
520 ARRAY_SIZE(twl4030_vibra_texts),
521 twl4030_vibra_texts);
522
523static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
524SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
525
526/* Vibra path selection: local vibrator (PWM) or audio driven */
527static const char *twl4030_vibrapath_texts[] =
528 {"Local vibrator", "Audio"};
529
530static const struct soc_enum twl4030_vibrapath_enum =
531 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
532 ARRAY_SIZE(twl4030_vibrapath_texts),
533 twl4030_vibrapath_texts);
534
535static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
536SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
537
276c6222 538/* Left analog microphone selection */
97b8096d 539static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 540 SOC_DAPM_SINGLE("Main Mic Capture Switch",
541 TWL4030_REG_ANAMICL, 0, 1, 0),
542 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
543 TWL4030_REG_ANAMICL, 1, 1, 0),
544 SOC_DAPM_SINGLE("AUXL Capture Switch",
545 TWL4030_REG_ANAMICL, 2, 1, 0),
546 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
547 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 548};
276c6222
PU		 549
550/* Right analog microphone selection */
97b8096d 551static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 552 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
553 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 554};
276c6222
PU		 555
556/* TX1 L/R Analog/Digital microphone selection */
557static const char *twl4030_micpathtx1_texts[] =
558 {"Analog", "Digimic0"};
559
560static const struct soc_enum twl4030_micpathtx1_enum =
561 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
562 ARRAY_SIZE(twl4030_micpathtx1_texts),
563 twl4030_micpathtx1_texts);
564
565static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
566SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
567
568/* TX2 L/R Analog/Digital microphone selection */
569static const char *twl4030_micpathtx2_texts[] =
570 {"Analog", "Digimic1"};
571
572static const struct soc_enum twl4030_micpathtx2_enum =
573 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
574 ARRAY_SIZE(twl4030_micpathtx2_texts),
575 twl4030_micpathtx2_texts);
576
577static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
578SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
579
7393958f
PU		 580/* Analog bypass for AudioR1 */
581static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
582 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
583
584/* Analog bypass for AudioL1 */
585static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
586 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
587
588/* Analog bypass for AudioR2 */
589static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
590 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
591
592/* Analog bypass for AudioL2 */
593static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
594 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
595
fcd274a3
LCM		 596/* Analog bypass for Voice */
597static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
598 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
599
8b0d3153 600/* Digital bypass gain, mute instead of -30dB */
6bab83fd 601static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 602 TLV_DB_RANGE_HEAD(3),
603 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
604 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 605 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
606};
607
608/* Digital bypass left (TX1L -> RX2L) */
609static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
610 SOC_DAPM_SINGLE_TLV("Volume",
611 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
612 twl4030_dapm_dbypass_tlv);
613
614/* Digital bypass right (TX1R -> RX2R) */
615static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
616 SOC_DAPM_SINGLE_TLV("Volume",
617 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
618 twl4030_dapm_dbypass_tlv);
619
ee8f6894
LCM		 620/*
621 * Voice Sidetone GAIN volume control:
622 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
623 */
624static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
625
626/* Digital bypass voice: sidetone (VUL -> VDL)*/
627static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
628 SOC_DAPM_SINGLE_TLV("Volume",
629 TWL4030_REG_VSTPGA, 0, 0x29, 0,
630 twl4030_dapm_dbypassv_tlv);
631
9008adf9
PU		 632/*
633 * Output PGA builder:
634 * Handle the muting and unmuting of the given output (turning off the
635 * amplifier associated with the output pin)
c96907f2
PU		 636 * On mute bypass the reg_cache and write 0 to the register
637 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 638 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
639 */
640#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
641static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
642 struct snd_kcontrol *kcontrol, int event) \
643{ \
b2c812e2 644 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 645 \
646 switch (event) { \
647 case SND_SOC_DAPM_POST_PMU: \
c96907f2 648 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 649 twl4030_write(w->codec, reg, \
650 twl4030_read_reg_cache(w->codec, reg)); \
651 break; \
652 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 653 twl4030->pin_name##_enabled = 0; \
654 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
655 0, reg); \
9008adf9
PU		 656 break; \
657 } \
658 return 0; \
659}
660
661TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
662TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
663TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
664TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
665TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
666
5a2e9a48 667static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 668{
49d92c7d
SM		 669 unsigned char hs_ctl;
670
5a2e9a48 671 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 672
5a2e9a48
PU		 673 if (ramp) {
674 /* HF ramp-up */
675 hs_ctl |= TWL4030_HF_CTL_REF_EN;
676 twl4030_write(codec, reg, hs_ctl);
677 udelay(10);
49d92c7d 678 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 679 twl4030_write(codec, reg, hs_ctl);
680 udelay(40);
49d92c7d 681 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 682 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 683 twl4030_write(codec, reg, hs_ctl);
49d92c7d 684 } else {
5a2e9a48
PU		 685 /* HF ramp-down */
686 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
687 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
688 twl4030_write(codec, reg, hs_ctl);
689 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
690 twl4030_write(codec, reg, hs_ctl);
691 udelay(40);
692 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
693 twl4030_write(codec, reg, hs_ctl);
49d92c7d 694 }
5a2e9a48 695}
49d92c7d 696
5a2e9a48
PU		 697static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
698 struct snd_kcontrol *kcontrol, int event)
699{
700 switch (event) {
701 case SND_SOC_DAPM_POST_PMU:
702 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
703 break;
704 case SND_SOC_DAPM_POST_PMD:
705 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
706 break;
707 }
708 return 0;
709}
710
711static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol, int event)
713{
714 switch (event) {
715 case SND_SOC_DAPM_POST_PMU:
716 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
717 break;
718 case SND_SOC_DAPM_POST_PMD:
719 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
720 break;
721 }
49d92c7d
SM		 722 return 0;
723}
724
86139a13
JV		 725static int vibramux_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727{
728 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
729 return 0;
730}
731
7729cf74
PU		 732static int apll_event(struct snd_soc_dapm_widget *w,
733 struct snd_kcontrol *kcontrol, int event)
734{
735 switch (event) {
736 case SND_SOC_DAPM_PRE_PMU:
737 twl4030_apll_enable(w->codec, 1);
738 break;
739 case SND_SOC_DAPM_POST_PMD:
740 twl4030_apll_enable(w->codec, 0);
741 break;
742 }
743 return 0;
744}
745
7b4c734e
PU		 746static int aif_event(struct snd_soc_dapm_widget *w,
747 struct snd_kcontrol *kcontrol, int event)
748{
749 u8 audio_if;
750
751 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
752 switch (event) {
753 case SND_SOC_DAPM_PRE_PMU:
754 /* Enable AIF */
755 /* enable the PLL before we use it to clock the DAI */
756 twl4030_apll_enable(w->codec, 1);
757
758 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
759 audio_if | TWL4030_AIF_EN);
760 break;
761 case SND_SOC_DAPM_POST_PMD:
762 /* disable the DAI before we stop it's source PLL */
763 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
764 audio_if & ~TWL4030_AIF_EN);
765 twl4030_apll_enable(w->codec, 0);
766 break;
767 }
768 return 0;
769}
770
6943c92e 771static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 772{
773 unsigned char hs_gain, hs_pop;
b2c812e2 774 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 775 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 776 /* Base values for ramp delay calculation: 2^19 - 2^26 */
777 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
778 8388608, 16777216, 33554432, 67108864};
7e6120c5 779 unsigned int delay;
aad749e5 780
6943c92e
PU		 781 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
782 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 783 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
784 twl4030->sysclk) + 1;
aad749e5 785
4e49ffd1
CVJ		 786 /* Enable external mute control, this dramatically reduces
787 * the pop-noise */
f0fba2ad 788 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 789 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
790 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 791 } else {
792 hs_pop |= TWL4030_EXTMUTE;
793 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
794 }
795 }
796
6943c92e
PU		 797 if (ramp) {
798 /* Headset ramp-up according to the TRM */
aad749e5 799 hs_pop |= TWL4030_VMID_EN;
6943c92e 800 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 801 /* Actually write to the register */
802 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
803 hs_gain,
804 TWL4030_REG_HS_GAIN_SET);
aad749e5 805 hs_pop |= TWL4030_RAMP_EN;
6943c92e 806 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 807 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 808 twl4030_wait_ms(delay);
6943c92e
PU		 809 } else {
810 /* Headset ramp-down _not_ according to
811 * the TRM, but in a way that it is working */
aad749e5 812 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 813 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
814 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 815 twl4030_wait_ms(delay);
aad749e5 816 /* Bypass the reg_cache to mute the headset */
fc7b92fc 817 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 818 hs_gain & (~0x0f),
819 TWL4030_REG_HS_GAIN_SET);
6943c92e 820
aad749e5 821 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 822 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
823 }
4e49ffd1
CVJ		 824
825 /* Disable external mute */
f0fba2ad 826 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 827 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
828 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 829 } else {
830 hs_pop &= ~TWL4030_EXTMUTE;
831 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
832 }
833 }
6943c92e
PU		 834}
835
836static int headsetlpga_event(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
838{
b2c812e2 839 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 840
841 switch (event) {
842 case SND_SOC_DAPM_POST_PMU:
843 /* Do the ramp-up only once */
844 if (!twl4030->hsr_enabled)
845 headset_ramp(w->codec, 1);
846
847 twl4030->hsl_enabled = 1;
848 break;
849 case SND_SOC_DAPM_POST_PMD:
850 /* Do the ramp-down only if both headsetL/R is disabled */
851 if (!twl4030->hsr_enabled)
852 headset_ramp(w->codec, 0);
853
854 twl4030->hsl_enabled = 0;
855 break;
856 }
857 return 0;
858}
859
860static int headsetrpga_event(struct snd_soc_dapm_widget *w,
861 struct snd_kcontrol *kcontrol, int event)
862{
b2c812e2 863 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 864
865 switch (event) {
866 case SND_SOC_DAPM_POST_PMU:
867 /* Do the ramp-up only once */
868 if (!twl4030->hsl_enabled)
869 headset_ramp(w->codec, 1);
870
871 twl4030->hsr_enabled = 1;
872 break;
873 case SND_SOC_DAPM_POST_PMD:
874 /* Do the ramp-down only if both headsetL/R is disabled */
875 if (!twl4030->hsl_enabled)
876 headset_ramp(w->codec, 0);
877
878 twl4030->hsr_enabled = 0;
aad749e5
PU		 879 break;
880 }
881 return 0;
882}
883
01ea6ba2
PU		 884static int digimic_event(struct snd_soc_dapm_widget *w,
885 struct snd_kcontrol *kcontrol, int event)
886{
887 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 888 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 889
182f73f6
PU		 890 if (pdata && pdata->digimic_delay)
891 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 892 return 0;
893}
894
b0bd53a7
PU		 895/*
896 * Some of the gain controls in TWL (mostly those which are associated with
897 * the outputs) are implemented in an interesting way:
898 * 0x0 : Power down (mute)
899 * 0x1 : 6dB
900 * 0x2 : 0 dB
901 * 0x3 : -6 dB
902 * Inverting not going to help with these.
903 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
904 */
b0bd53a7
PU		 905static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
906 struct snd_ctl_elem_value *ucontrol)
907{
908 struct soc_mixer_control *mc =
909 (struct soc_mixer_control *)kcontrol->private_value;
910 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
911 unsigned int reg = mc->reg;
912 unsigned int shift = mc->shift;
913 unsigned int rshift = mc->rshift;
914 int max = mc->max;
915 int mask = (1 << fls(max)) - 1;
916
917 ucontrol->value.integer.value[0] =
918 (snd_soc_read(codec, reg) >> shift) & mask;
919 if (ucontrol->value.integer.value[0])
920 ucontrol->value.integer.value[0] =
921 max + 1 - ucontrol->value.integer.value[0];
922
923 if (shift != rshift) {
924 ucontrol->value.integer.value[1] =
925 (snd_soc_read(codec, reg) >> rshift) & mask;
926 if (ucontrol->value.integer.value[1])
927 ucontrol->value.integer.value[1] =
928 max + 1 - ucontrol->value.integer.value[1];
929 }
930
931 return 0;
932}
933
934static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936{
937 struct soc_mixer_control *mc =
938 (struct soc_mixer_control *)kcontrol->private_value;
939 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
940 unsigned int reg = mc->reg;
941 unsigned int shift = mc->shift;
942 unsigned int rshift = mc->rshift;
943 int max = mc->max;
944 int mask = (1 << fls(max)) - 1;
945 unsigned short val, val2, val_mask;
946
947 val = (ucontrol->value.integer.value[0] & mask);
948
949 val_mask = mask << shift;
950 if (val)
951 val = max + 1 - val;
952 val = val << shift;
953 if (shift != rshift) {
954 val2 = (ucontrol->value.integer.value[1] & mask);
955 val_mask |= mask << rshift;
956 if (val2)
957 val2 = max + 1 - val2;
958 val |= val2 << rshift;
959 }
960 return snd_soc_update_bits(codec, reg, val_mask, val);
961}
962
963static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
964 struct snd_ctl_elem_value *ucontrol)
965{
966 struct soc_mixer_control *mc =
967 (struct soc_mixer_control *)kcontrol->private_value;
968 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
969 unsigned int reg = mc->reg;
970 unsigned int reg2 = mc->rreg;
971 unsigned int shift = mc->shift;
972 int max = mc->max;
973 int mask = (1<<fls(max))-1;
974
975 ucontrol->value.integer.value[0] =
976 (snd_soc_read(codec, reg) >> shift) & mask;
977 ucontrol->value.integer.value[1] =
978 (snd_soc_read(codec, reg2) >> shift) & mask;
979
980 if (ucontrol->value.integer.value[0])
981 ucontrol->value.integer.value[0] =
982 max + 1 - ucontrol->value.integer.value[0];
983 if (ucontrol->value.integer.value[1])
984 ucontrol->value.integer.value[1] =
985 max + 1 - ucontrol->value.integer.value[1];
986
987 return 0;
988}
989
990static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
991 struct snd_ctl_elem_value *ucontrol)
992{
993 struct soc_mixer_control *mc =
994 (struct soc_mixer_control *)kcontrol->private_value;
995 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
996 unsigned int reg = mc->reg;
997 unsigned int reg2 = mc->rreg;
998 unsigned int shift = mc->shift;
999 int max = mc->max;
1000 int mask = (1 << fls(max)) - 1;
1001 int err;
1002 unsigned short val, val2, val_mask;
1003
1004 val_mask = mask << shift;
1005 val = (ucontrol->value.integer.value[0] & mask);
1006 val2 = (ucontrol->value.integer.value[1] & mask);
1007
1008 if (val)
1009 val = max + 1 - val;
1010 if (val2)
1011 val2 = max + 1 - val2;
1012
1013 val = val << shift;
1014 val2 = val2 << shift;
1015
1016 err = snd_soc_update_bits(codec, reg, val_mask, val);
1017 if (err < 0)
1018 return err;
1019
1020 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1021 return err;
1022}
1023
b74bd40f
LCM		 1024/* Codec operation modes */
1025static const char *twl4030_op_modes_texts[] = {
1026 "Option 2 (voice/audio)", "Option 1 (audio)"
1027};
1028
1029static const struct soc_enum twl4030_op_modes_enum =
1030 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1031 ARRAY_SIZE(twl4030_op_modes_texts),
1032 twl4030_op_modes_texts);
1033
423c238d 1034static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1035 struct snd_ctl_elem_value *ucontrol)
1036{
1037 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1038 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1039 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1040 unsigned short val;
86767b7d 1041 unsigned short mask;
b74bd40f
LCM		 1042
1043 if (twl4030->configured) {
3b8a0795
PU		 1044 dev_err(codec->dev,
1045 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 1046 return -EBUSY;
1047 }
1048
b74bd40f
LCM		 1049 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1050 return -EINVAL;
1051
1052 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 1053 mask = e->mask << e->shift_l;
b74bd40f
LCM		 1054 if (e->shift_l != e->shift_r) {
1055 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1056 return -EINVAL;
1057 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 1058 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 1059 }
1060
1061 return snd_soc_update_bits(codec, e->reg, mask, val);
1062}
1063
c10b82cf
PU		 1064/*
1065 * FGAIN volume control:
1066 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1067 */
d889a72c 1068static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1069
0d33ea0b
PU		 1070/*
1071 * CGAIN volume control:
1072 * 0 dB to 12 dB in 6 dB steps
1073 * value 2 and 3 means 12 dB
1074 */
d889a72c
PU		 1075static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1076
1a787e7a
JS		 1077/*
1078 * Voice Downlink GAIN volume control:
1079 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1080 */
1081static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1082
d889a72c
PU		 1083/*
1084 * Analog playback gain
1085 * -24 dB to 12 dB in 2 dB steps
1086 */
1087static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1088
4290239c
PU		 1089/*
1090 * Gain controls tied to outputs
1091 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1092 */
1093static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1094
18cc8d8d
JS		 1095/*
1096 * Gain control for earpiece amplifier
1097 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1098 */
1099static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1100
381a22b5
PU		 1101/*
1102 * Capture gain after the ADCs
1103 * from 0 dB to 31 dB in 1 dB steps
1104 */
1105static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1106
5920b453
GI		 1107/*
1108 * Gain control for input amplifiers
1109 * 0 dB to 30 dB in 6 dB steps
1110 */
1111static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1112
328d0a13
LCM		 1113/* AVADC clock priority */
1114static const char *twl4030_avadc_clk_priority_texts[] = {
1115 "Voice high priority", "HiFi high priority"
1116};
1117
1118static const struct soc_enum twl4030_avadc_clk_priority_enum =
1119 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1120 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1121 twl4030_avadc_clk_priority_texts);
1122
89492be8
PU		 1123static const char *twl4030_rampdelay_texts[] = {
1124 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1125 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1126 "3495/2581/1748 ms"
1127};
1128
1129static const struct soc_enum twl4030_rampdelay_enum =
1130 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1131 ARRAY_SIZE(twl4030_rampdelay_texts),
1132 twl4030_rampdelay_texts);
1133
376f7839
PU		 1134/* Vibra H-bridge direction mode */
1135static const char *twl4030_vibradirmode_texts[] = {
1136 "Vibra H-bridge direction", "Audio data MSB",
1137};
1138
1139static const struct soc_enum twl4030_vibradirmode_enum =
1140 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1141 ARRAY_SIZE(twl4030_vibradirmode_texts),
1142 twl4030_vibradirmode_texts);
1143
1144/* Vibra H-bridge direction */
1145static const char *twl4030_vibradir_texts[] = {
1146 "Positive polarity", "Negative polarity",
1147};
1148
1149static const struct soc_enum twl4030_vibradir_enum =
1150 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1151 ARRAY_SIZE(twl4030_vibradir_texts),
1152 twl4030_vibradir_texts);
1153
36aeff61
PU		 1154/* Digimic Left and right swapping */
1155static const char *twl4030_digimicswap_texts[] = {
1156 "Not swapped", "Swapped",
1157};
1158
1159static const struct soc_enum twl4030_digimicswap_enum =
1160 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1161 ARRAY_SIZE(twl4030_digimicswap_texts),
1162 twl4030_digimicswap_texts);
1163
cc17557e 1164static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1165 /* Codec operation mode control */
1166 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1167 snd_soc_get_enum_double,
1168 snd_soc_put_twl4030_opmode_enum_double),
1169
d889a72c
PU		 1170 /* Common playback gain controls */
1171 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1172 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1173 0, 0x3f, 0, digital_fine_tlv),
1174 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1175 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1176 0, 0x3f, 0, digital_fine_tlv),
1177
1178 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1179 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1180 6, 0x2, 0, digital_coarse_tlv),
1181 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1182 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1183 6, 0x2, 0, digital_coarse_tlv),
1184
1185 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1186 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1187 3, 0x12, 1, analog_tlv),
1188 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1189 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1190 3, 0x12, 1, analog_tlv),
44c55870
PU		 1191 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1192 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1193 1, 1, 0),
1194 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1195 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1196 1, 1, 0),
381a22b5 1197
1a787e7a
JS		 1198 /* Common voice downlink gain controls */
1199 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1200 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1201
1202 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1203 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1204
1205 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1206 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1207
4290239c 1208 /* Separate output gain controls */
0f9887d1 1209 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1210 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1211 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1212 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1213
0f9887d1
PU		 1214 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1215 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1216 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1217
0f9887d1 1218 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1219 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1220 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1221 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1222
0f9887d1
PU		 1223 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1224 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1225 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1226
381a22b5 1227 /* Common capture gain controls */
276c6222 1228 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1229 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1230 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1231 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1232 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1233 0, 0x1f, 0, digital_capture_tlv),
5920b453 1234
276c6222 1235 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1236 0, 3, 5, 0, input_gain_tlv),
89492be8 1237
328d0a13
LCM		 1238 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1239
89492be8 1240 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1241
1242 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1243 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1244
1245 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1246};
1247
cc17557e 1248static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1249 /* Left channel inputs */
1250 SND_SOC_DAPM_INPUT("MAINMIC"),
1251 SND_SOC_DAPM_INPUT("HSMIC"),
1252 SND_SOC_DAPM_INPUT("AUXL"),
1253 SND_SOC_DAPM_INPUT("CARKITMIC"),
1254 /* Right channel inputs */
1255 SND_SOC_DAPM_INPUT("SUBMIC"),
1256 SND_SOC_DAPM_INPUT("AUXR"),
1257 /* Digital microphones (Stereo) */
1258 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1259 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1260
1261 /* Outputs */
5e98a464 1262 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1263 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1264 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1265 SND_SOC_DAPM_OUTPUT("HSOL"),
1266 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1267 SND_SOC_DAPM_OUTPUT("CARKITL"),
1268 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1269 SND_SOC_DAPM_OUTPUT("HFL"),
1270 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1271 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1272
7b4c734e
PU		 1273 /* AIF and APLL clocks for running DAIs (including loopback) */
1274 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1275 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1276 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1277
53b5047d 1278 /* DACs */
7f51e7d3
PU		 1279 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1280 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1281 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1282 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1283 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1284
927a7747
PU		 1285 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1286 TWL4030_REG_VOICE_IF, 6, 0),
1287
7393958f 1288 /* Analog bypasses */
78e08e2f
PU		 1289 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1290 &twl4030_dapm_abypassr1_control),
1291 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1292 &twl4030_dapm_abypassl1_control),
1293 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1294 &twl4030_dapm_abypassr2_control),
1295 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1296 &twl4030_dapm_abypassl2_control),
1297 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1298 &twl4030_dapm_abypassv_control),
1299
1300 /* Master analog loopback switch */
1301 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1302 NULL, 0),
7393958f 1303
6bab83fd 1304 /* Digital bypasses */
78e08e2f
PU		 1305 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1306 &twl4030_dapm_dbypassl_control),
1307 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1308 &twl4030_dapm_dbypassr_control),
1309 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1310 &twl4030_dapm_dbypassv_control),
6bab83fd 1311
4005d39a
PU		 1312 /* Digital mixers, power control for the physical DACs */
1313 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1314 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1315 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1316 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1317 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1318 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1319 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1320 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1321 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1322 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1323
1324 /* Analog mixers, power control for the physical PGAs */
1325 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1326 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1327 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1328 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1329 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1330 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1331 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1332 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1333 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1334 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1335
7729cf74
PU		 1336 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1337 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1338
7b4c734e
PU		 1339 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1340 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1341
1a787e7a 1342 /* Output MIXER controls */
5e98a464 1343 /* Earpiece */
1a787e7a
JS		 1344 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1345 &twl4030_dapm_earpiece_controls[0],
1346 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1347 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1348 0, 0, NULL, 0, earpiecepga_event,
1349 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1350 /* PreDrivL/R */
1a787e7a
JS		 1351 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1352 &twl4030_dapm_predrivel_controls[0],
1353 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1354 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1355 0, 0, NULL, 0, predrivelpga_event,
1356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1357 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1358 &twl4030_dapm_predriver_controls[0],
1359 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1360 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1361 0, 0, NULL, 0, predriverpga_event,
1362 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1363 /* HeadsetL/R */
6943c92e 1364 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1365 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1366 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1367 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1368 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1369 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1370 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1371 &twl4030_dapm_hsor_controls[0],
1372 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1373 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1374 0, 0, NULL, 0, headsetrpga_event,
1375 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1376 /* CarkitL/R */
1a787e7a
JS		 1377 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1378 &twl4030_dapm_carkitl_controls[0],
1379 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1380 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1381 0, 0, NULL, 0, carkitlpga_event,
1382 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1383 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1384 &twl4030_dapm_carkitr_controls[0],
1385 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1386 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1387 0, 0, NULL, 0, carkitrpga_event,
1388 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1389
1390 /* Output MUX controls */
df339804 1391 /* HandsfreeL/R */
5a2e9a48
PU		 1392 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1393 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1394 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1395 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1396 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1397 0, 0, NULL, 0, handsfreelpga_event,
1398 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1399 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1400 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1401 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1402 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1403 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1404 0, 0, NULL, 0, handsfreerpga_event,
1405 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1406 /* Vibra */
86139a13
JV		 1407 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1408 &twl4030_dapm_vibra_control, vibramux_event,
1409 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1410 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1411 &twl4030_dapm_vibrapath_control),
5e98a464 1412
276c6222
PU		 1413 /* Introducing four virtual ADC, since TWL4030 have four channel for
1414 capture */
7f51e7d3
PU		 1415 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1416 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1417 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1418 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1419
927a7747
PU		 1420 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1421 TWL4030_REG_VOICE_IF, 5, 0),
1422
276c6222
PU		 1423 /* Analog/Digital mic path selection.
1424 TX1 Left/Right: either analog Left/Right or Digimic0
1425 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1426 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1427 &twl4030_dapm_micpathtx1_control),
1428 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1429 &twl4030_dapm_micpathtx2_control),
276c6222 1430
97b8096d 1431 /* Analog input mixers for the capture amplifiers */
9028935d 1432 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1433 TWL4030_REG_ANAMICL, 4, 0,
1434 &twl4030_dapm_analoglmic_controls[0],
1435 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1436 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1437 TWL4030_REG_ANAMICR, 4, 0,
1438 &twl4030_dapm_analogrmic_controls[0],
1439 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1440
fb2a2f84
PU		 1441 SND_SOC_DAPM_PGA("ADC Physical Left",
1442 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1443 SND_SOC_DAPM_PGA("ADC Physical Right",
1444 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1445
01ea6ba2
PU		 1446 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1447 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1448 digimic_event, SND_SOC_DAPM_POST_PMU),
1449 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1450 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1451 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1452
bda7d2a8
PU		 1453 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1454 NULL, 0),
1455 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1456 NULL, 0),
1457
e04d6e55
PU		 1458 /* Microphone bias */
1459 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1460 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1461 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1462 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1463 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1464 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1465
927a7747 1466 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1467};
1468
1469static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1470 /* Stream -> DAC mapping */
1471 {"DAC Right1", NULL, "HiFi Playback"},
1472 {"DAC Left1", NULL, "HiFi Playback"},
1473 {"DAC Right2", NULL, "HiFi Playback"},
1474 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1475 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1476
1477 /* ADC -> Stream mapping */
1478 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1479 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1480 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1481 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1482 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1483 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1484 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1485
4005d39a
PU		 1486 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1487 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1488 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1489 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1490 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1491
7729cf74 1492 /* Supply for the digital part (APLL) */
7729cf74
PU		 1493 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1494
27eeb1fe
PU		 1495 {"DAC Left1", NULL, "AIF Enable"},
1496 {"DAC Right1", NULL, "AIF Enable"},
1497 {"DAC Left2", NULL, "AIF Enable"},
1498 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1499 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1500
c42a59ea
PU		 1501 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1502 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1503
4005d39a
PU		 1504 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1505 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1506 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1507 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1508 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1509
5e98a464
PU		 1510 /* Internal playback routings */
1511 /* Earpiece */
4005d39a
PU		 1512 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1513 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1514 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1515 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1516 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1517 /* PreDrivL */
4005d39a
PU		 1518 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1519 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1520 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1521 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1522 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1523 /* PreDrivR */
4005d39a
PU		 1524 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1525 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1526 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1527 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1528 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1529 /* HeadsetL */
4005d39a
PU		 1530 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1531 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1532 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1533 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1534 /* HeadsetR */
4005d39a
PU		 1535 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1536 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1537 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1538 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1539 /* CarkitL */
4005d39a
PU		 1540 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1541 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1542 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1543 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1544 /* CarkitR */
4005d39a
PU		 1545 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1546 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1547 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1548 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1549 /* HandsfreeL */
4005d39a
PU		 1550 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1551 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1552 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1553 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1554 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1555 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1556 /* HandsfreeR */
4005d39a
PU		 1557 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1558 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1559 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1560 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1561 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1562 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1563 /* Vibra */
1564 {"Vibra Mux", "AudioL1", "DAC Left1"},
1565 {"Vibra Mux", "AudioR1", "DAC Right1"},
1566 {"Vibra Mux", "AudioL2", "DAC Left2"},
1567 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1568
cc17557e 1569 /* outputs */
7b4c734e 1570 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1571 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1572 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1573 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1574 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1575 /* Must be always connected (for APLL) */
1576 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1577 /* Physical outputs */
9008adf9
PU		 1578 {"EARPIECE", NULL, "Earpiece PGA"},
1579 {"PREDRIVEL", NULL, "PredriveL PGA"},
1580 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1581 {"HSOL", NULL, "HeadsetL PGA"},
1582 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1583 {"CARKITL", NULL, "CarkitL PGA"},
1584 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1585 {"HFL", NULL, "HandsfreeL PGA"},
1586 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1587 {"Vibra Route", "Audio", "Vibra Mux"},
1588 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1589
276c6222 1590 /* Capture path */
7b4c734e
PU		 1591 /* Must be always connected (for AIF and APLL) */
1592 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1593 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1594 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1595 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1596 /* Physical inputs */
9028935d
PU		 1597 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1598 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1599 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1600 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1601
9028935d
PU		 1602 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1603 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1604
9028935d
PU		 1605 {"ADC Physical Left", NULL, "Analog Left"},
1606 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1607
1608 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1609 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1610
bda7d2a8
PU		 1611 {"DIGIMIC0", NULL, "micbias1 select"},
1612 {"DIGIMIC1", NULL, "micbias2 select"},
1613
276c6222 1614 /* TX1 Left capture path */
fb2a2f84 1615 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1616 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1617 /* TX1 Right capture path */
fb2a2f84 1618 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1619 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1620 /* TX2 Left capture path */
fb2a2f84 1621 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1622 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1623 /* TX2 Right capture path */
fb2a2f84 1624 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1625 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1626
1627 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1628 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1629 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1630 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1631
c42a59ea
PU		 1632 {"ADC Virtual Left1", NULL, "AIF Enable"},
1633 {"ADC Virtual Right1", NULL, "AIF Enable"},
1634 {"ADC Virtual Left2", NULL, "AIF Enable"},
1635 {"ADC Virtual Right2", NULL, "AIF Enable"},
1636
7393958f 1637 /* Analog bypass routes */
9028935d
PU		 1638 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1639 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1640 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1641 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1642 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1643
78e08e2f
PU		 1644 /* Supply for the Analog loopbacks */
1645 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1646 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1647 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1648 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1649 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1650
7393958f
PU		 1651 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1652 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1653 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1654 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1655 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1656
6bab83fd
PU		 1657 /* Digital bypass routes */
1658 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1659 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1660 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1661
4005d39a
PU		 1662 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1663 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1664 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1665
cc17557e
SS		 1666};
1667
cc17557e
SS		 1668static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1669 enum snd_soc_bias_level level)
1670{
1671 switch (level) {
1672 case SND_SOC_BIAS_ON:
cc17557e
SS		 1673 break;
1674 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1675 break;
1676 case SND_SOC_BIAS_STANDBY:
ce6120cc 1677 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1678 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1679 break;
1680 case SND_SOC_BIAS_OFF:
cbd2db12 1681 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1682 break;
1683 }
ce6120cc 1684 codec->dapm.bias_level = level;
cc17557e
SS		 1685
1686 return 0;
1687}
1688
6b87a91f
PU		 1689static void twl4030_constraints(struct twl4030_priv *twl4030,
1690 struct snd_pcm_substream *mst_substream)
1691{
1692 struct snd_pcm_substream *slv_substream;
1693
1694 /* Pick the stream, which need to be constrained */
1695 if (mst_substream == twl4030->master_substream)
1696 slv_substream = twl4030->slave_substream;
1697 else if (mst_substream == twl4030->slave_substream)
1698 slv_substream = twl4030->master_substream;
1699 else /* This should not happen.. */
1700 return;
1701
1702 /* Set the constraints according to the already configured stream */
1703 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1704 SNDRV_PCM_HW_PARAM_RATE,
1705 twl4030->rate,
1706 twl4030->rate);
1707
1708 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1709 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1710 twl4030->sample_bits,
1711 twl4030->sample_bits);
1712
1713 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1714 SNDRV_PCM_HW_PARAM_CHANNELS,
1715 twl4030->channels,
1716 twl4030->channels);
1717}
1718
8a1f936a
PU		 1719/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1720 * capture has to be enabled/disabled. */
1721static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1722 int enable)
1723{
1724 u8 reg, mask;
1725
1726 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1727
1728 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1729 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1730 else
1731 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1732
1733 if (enable)
1734 reg |= mask;
1735 else
1736 reg &= ~mask;
1737
1738 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1739}
1740
d6648da1
PU		 1741static int twl4030_startup(struct snd_pcm_substream *substream,
1742 struct snd_soc_dai *dai)
7220b9f4 1743{
e6968a17 1744 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1745 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1746
7220b9f4 1747 if (twl4030->master_substream) {
7220b9f4 1748 twl4030->slave_substream = substream;
6b87a91f
PU		 1749 /* The DAI has one configuration for playback and capture, so
1750 * if the DAI has been already configured then constrain this
1751 * substream to match it. */
1752 if (twl4030->configured)
1753 twl4030_constraints(twl4030, twl4030->master_substream);
1754 } else {
8a1f936a
PU		 1755 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1756 TWL4030_OPTION_1)) {
1757 /* In option2 4 channel is not supported, set the
1758 * constraint for the first stream for channels, the
1759 * second stream will 'inherit' this cosntraint */
1760 snd_pcm_hw_constraint_minmax(substream->runtime,
1761 SNDRV_PCM_HW_PARAM_CHANNELS,
1762 2, 2);
1763 }
7220b9f4 1764 twl4030->master_substream = substream;
6b87a91f 1765 }
7220b9f4
PU		 1766
1767 return 0;
1768}
1769
d6648da1
PU		 1770static void twl4030_shutdown(struct snd_pcm_substream *substream,
1771 struct snd_soc_dai *dai)
7220b9f4 1772{
e6968a17 1773 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1774 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1775
1776 if (twl4030->master_substream == substream)
1777 twl4030->master_substream = twl4030->slave_substream;
1778
1779 twl4030->slave_substream = NULL;
6b87a91f
PU		 1780
1781 /* If all streams are closed, or the remaining stream has not yet
1782 * been configured than set the DAI as not configured. */
1783 if (!twl4030->master_substream)
1784 twl4030->configured = 0;
1785 else if (!twl4030->master_substream->runtime->channels)
1786 twl4030->configured = 0;
8a1f936a
PU		 1787
1788 /* If the closing substream had 4 channel, do the necessary cleanup */
1789 if (substream->runtime->channels == 4)
1790 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1791}
1792
cc17557e 1793static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1794 struct snd_pcm_hw_params *params,
1795 struct snd_soc_dai *dai)
cc17557e 1796{
e6968a17 1797 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1798 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1799 u8 mode, old_mode, format, old_format;
1800
8a1f936a
PU		 1801 /* If the substream has 4 channel, do the necessary setup */
1802 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1803 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1804 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1805
1806 /* Safety check: are we in the correct operating mode and
1807 * the interface is in TDM mode? */
1808 if ((mode & TWL4030_OPTION_1) &&
1809 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1810 twl4030_tdm_enable(codec, substream->stream, 1);
1811 else
1812 return -EINVAL;
1813 }
1814
6b87a91f
PU		 1815 if (twl4030->configured)
1816 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1817 return 0;
1818
cc17557e
SS		 1819 /* bit rate */
1820 old_mode = twl4030_read_reg_cache(codec,
1821 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1822 mode = old_mode & ~TWL4030_APLL_RATE;
1823
1824 switch (params_rate(params)) {
1825 case 8000:
1826 mode |= TWL4030_APLL_RATE_8000;
1827 break;
1828 case 11025:
1829 mode |= TWL4030_APLL_RATE_11025;
1830 break;
1831 case 12000:
1832 mode |= TWL4030_APLL_RATE_12000;
1833 break;
1834 case 16000:
1835 mode |= TWL4030_APLL_RATE_16000;
1836 break;
1837 case 22050:
1838 mode |= TWL4030_APLL_RATE_22050;
1839 break;
1840 case 24000:
1841 mode |= TWL4030_APLL_RATE_24000;
1842 break;
1843 case 32000:
1844 mode |= TWL4030_APLL_RATE_32000;
1845 break;
1846 case 44100:
1847 mode |= TWL4030_APLL_RATE_44100;
1848 break;
1849 case 48000:
1850 mode |= TWL4030_APLL_RATE_48000;
1851 break;
103f211d
PU		 1852 case 96000:
1853 mode |= TWL4030_APLL_RATE_96000;
1854 break;
cc17557e 1855 default:
3b8a0795 1856 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1857 params_rate(params));
1858 return -EINVAL;
1859 }
1860
cc17557e
SS		 1861 /* sample size */
1862 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1863 format = old_format;
1864 format &= ~TWL4030_DATA_WIDTH;
1865 switch (params_format(params)) {
1866 case SNDRV_PCM_FORMAT_S16_LE:
1867 format |= TWL4030_DATA_WIDTH_16S_16W;
1868 break;
dcdeda4a 1869 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1870 format |= TWL4030_DATA_WIDTH_32S_24W;
1871 break;
1872 default:
3b8a0795 1873 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1874 params_format(params));
1875 return -EINVAL;
1876 }
1877
2046f175
PU		 1878 if (format != old_format || mode != old_mode) {
1879 if (twl4030->codec_powered) {
1880 /*
1881 * If the codec is powered, than we need to toggle the
1882 * codec power.
1883 */
1884 twl4030_codec_enable(codec, 0);
1885 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1886 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1887 twl4030_codec_enable(codec, 1);
1888 } else {
1889 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1890 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1891 }
cc17557e 1892 }
6b87a91f
PU		 1893
1894 /* Store the important parameters for the DAI configuration and set
1895 * the DAI as configured */
1896 twl4030->configured = 1;
1897 twl4030->rate = params_rate(params);
1898 twl4030->sample_bits = hw_param_interval(params,
1899 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1900 twl4030->channels = params_channels(params);
1901
1902 /* If both playback and capture streams are open, and one of them
1903 * is setting the hw parameters right now (since we are here), set
1904 * constraints to the other stream to match the current one. */
1905 if (twl4030->slave_substream)
1906 twl4030_constraints(twl4030, substream);
1907
cc17557e
SS		 1908 return 0;
1909}
1910
1911static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1912 int clk_id, unsigned int freq, int dir)
1913{
1914 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1915 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1916
1917 switch (freq) {
1918 case 19200000:
cc17557e 1919 case 26000000:
cc17557e 1920 case 38400000:
cc17557e
SS		 1921 break;
1922 default:
3b8a0795 1923 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1924 return -EINVAL;
1925 }
1926
68d01955
PU		 1927 if ((freq / 1000) != twl4030->sysclk) {
1928 dev_err(codec->dev,
3b8a0795 1929 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1930 freq, twl4030->sysclk * 1000);
1931 return -EINVAL;
1932 }
cc17557e
SS		 1933
1934 return 0;
1935}
1936
1937static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1938 unsigned int fmt)
1939{
1940 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1941 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1942 u8 old_format, format;
1943
1944 /* get format */
1945 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1946 format = old_format;
1947
1948 /* set master/slave audio interface */
1949 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1950 case SND_SOC_DAIFMT_CBM_CFM:
1951 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1952 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1953 break;
1954 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1955 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1956 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1957 break;
1958 default:
1959 return -EINVAL;
1960 }
1961
1962 /* interface format */
1963 format &= ~TWL4030_AIF_FORMAT;
1964 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1965 case SND_SOC_DAIFMT_I2S:
1966 format |= TWL4030_AIF_FORMAT_CODEC;
1967 break;
8a1f936a
PU		 1968 case SND_SOC_DAIFMT_DSP_A:
1969 format |= TWL4030_AIF_FORMAT_TDM;
1970 break;
cc17557e
SS		 1971 default:
1972 return -EINVAL;
1973 }
1974
1975 if (format != old_format) {
2046f175
PU		 1976 if (twl4030->codec_powered) {
1977 /*
1978 * If the codec is powered, than we need to toggle the
1979 * codec power.
1980 */
1981 twl4030_codec_enable(codec, 0);
1982 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1983 twl4030_codec_enable(codec, 1);
1984 } else {
1985 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1986 }
cc17557e
SS		 1987 }
1988
1989 return 0;
1990}
1991
68140443
LCM		 1992static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1993{
1994 struct snd_soc_codec *codec = dai->codec;
1995 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1996
1997 if (tristate)
1998 reg |= TWL4030_AIF_TRI_EN;
1999 else
2000 reg &= ~TWL4030_AIF_TRI_EN;
2001
2002 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2003}
2004
b7a755a8
MLC		 2005/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2006 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2007static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2008 int enable)
2009{
2010 u8 reg, mask;
2011
2012 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2013
2014 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2015 mask = TWL4030_ARXL1_VRX_EN;
2016 else
2017 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2018
2019 if (enable)
2020 reg |= mask;
2021 else
2022 reg &= ~mask;
2023
2024 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2025}
2026
7154b3e8
JS		 2027static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2028 struct snd_soc_dai *dai)
2029{
e6968a17 2030 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2031 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2032 u8 mode;
2033
2034 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 2035 * not available.
7154b3e8 2036 */
68d01955 2037 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 2038 dev_err(codec->dev,
2039 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2040 __func__, twl4030->sysclk);
7154b3e8
JS		 2041 return -EINVAL;
2042 }
2043
2044 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 2045 * available.
7154b3e8
JS		 2046 */
2047 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2048 & TWL4030_OPT_MODE;
2049
2050 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 2051 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2052 __func__);
7154b3e8
JS		 2053 return -EINVAL;
2054 }
2055
2056 return 0;
2057}
2058
b7a755a8
MLC		 2059static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2060 struct snd_soc_dai *dai)
2061{
e6968a17 2062 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 2063
2064 /* Enable voice digital filters */
2065 twl4030_voice_enable(codec, substream->stream, 0);
2066}
2067
7154b3e8
JS		 2068static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2069 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2070{
e6968a17 2071 struct snd_soc_codec *codec = dai->codec;
2046f175 2072 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2073 u8 old_mode, mode;
2074
b7a755a8
MLC		 2075 /* Enable voice digital filters */
2076 twl4030_voice_enable(codec, substream->stream, 1);
2077
7154b3e8
JS		 2078 /* bit rate */
2079 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2080 & ~(TWL4030_CODECPDZ);
2081 mode = old_mode;
2082
2083 switch (params_rate(params)) {
2084 case 8000:
2085 mode &= ~(TWL4030_SEL_16K);
2086 break;
2087 case 16000:
2088 mode |= TWL4030_SEL_16K;
2089 break;
2090 default:
3b8a0795 2091 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2092 params_rate(params));
2093 return -EINVAL;
2094 }
2095
2096 if (mode != old_mode) {
2046f175
PU		 2097 if (twl4030->codec_powered) {
2098 /*
2099 * If the codec is powered, than we need to toggle the
2100 * codec power.
2101 */
2102 twl4030_codec_enable(codec, 0);
2103 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2104 twl4030_codec_enable(codec, 1);
2105 } else {
2106 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2107 }
7154b3e8
JS		 2108 }
2109
2110 return 0;
2111}
2112
2113static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2114 int clk_id, unsigned int freq, int dir)
2115{
2116 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2117 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2118
68d01955 2119 if (freq != 26000000) {
3b8a0795
PU		 2120 dev_err(codec->dev,
2121 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2122 __func__, freq / 1000);
68d01955
PU		 2123 return -EINVAL;
2124 }
2125 if ((freq / 1000) != twl4030->sysclk) {
2126 dev_err(codec->dev,
3b8a0795 2127 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2128 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2129 return -EINVAL;
2130 }
7154b3e8
JS		 2131 return 0;
2132}
2133
2134static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2135 unsigned int fmt)
2136{
2137 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2138 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2139 u8 old_format, format;
2140
2141 /* get format */
2142 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2143 format = old_format;
2144
2145 /* set master/slave audio interface */
2146 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2147 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2148 format &= ~(TWL4030_VIF_SLAVE_EN);
2149 break;
2150 case SND_SOC_DAIFMT_CBS_CFS:
2151 format |= TWL4030_VIF_SLAVE_EN;
2152 break;
2153 default:
2154 return -EINVAL;
2155 }
2156
2157 /* clock inversion */
2158 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2159 case SND_SOC_DAIFMT_IB_NF:
2160 format &= ~(TWL4030_VIF_FORMAT);
2161 break;
2162 case SND_SOC_DAIFMT_NB_IF:
2163 format |= TWL4030_VIF_FORMAT;
2164 break;
2165 default:
2166 return -EINVAL;
2167 }
2168
2169 if (format != old_format) {
2046f175
PU		 2170 if (twl4030->codec_powered) {
2171 /*
2172 * If the codec is powered, than we need to toggle the
2173 * codec power.
2174 */
2175 twl4030_codec_enable(codec, 0);
2176 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2177 twl4030_codec_enable(codec, 1);
2178 } else {
2179 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2180 }
7154b3e8
JS		 2181 }
2182
2183 return 0;
2184}
2185
68140443
LCM		 2186static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2187{
2188 struct snd_soc_codec *codec = dai->codec;
2189 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2190
2191 if (tristate)
2192 reg |= TWL4030_VIF_TRI_EN;
2193 else
2194 reg &= ~TWL4030_VIF_TRI_EN;
2195
2196 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2197}
2198
bbba9444 2199#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2200#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2201
85e7652d 2202static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2203 .startup = twl4030_startup,
2204 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2205 .hw_params = twl4030_hw_params,
2206 .set_sysclk = twl4030_set_dai_sysclk,
2207 .set_fmt = twl4030_set_dai_fmt,
68140443 2208 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2209};
2210
85e7652d 2211static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2212 .startup = twl4030_voice_startup,
b7a755a8 2213 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2214 .hw_params = twl4030_voice_hw_params,
2215 .set_sysclk = twl4030_voice_set_dai_sysclk,
2216 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2217 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2218};
2219
f0fba2ad 2220static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2221{
f0fba2ad 2222 .name = "twl4030-hifi",
cc17557e 2223 .playback = {
b4852b79 2224 .stream_name = "HiFi Playback",
cc17557e 2225 .channels_min = 2,
8a1f936a 2226 .channels_max = 4,
31ad0f31 2227 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2228 .formats = TWL4030_FORMATS,
2229 .sig_bits = 24,},
cc17557e 2230 .capture = {
7f51e7d3 2231 .stream_name = "HiFi Capture",
cc17557e 2232 .channels_min = 2,
8a1f936a 2233 .channels_max = 4,
cc17557e 2234 .rates = TWL4030_RATES,
8819f65c
PU		 2235 .formats = TWL4030_FORMATS,
2236 .sig_bits = 24,},
f0fba2ad 2237 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2238},
2239{
f0fba2ad 2240 .name = "twl4030-voice",
7154b3e8 2241 .playback = {
b4852b79 2242 .stream_name = "Voice Playback",
7154b3e8
JS		 2243 .channels_min = 1,
2244 .channels_max = 1,
2245 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2246 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2247 .capture = {
7f51e7d3 2248 .stream_name = "Voice Capture",
7154b3e8
JS		 2249 .channels_min = 1,
2250 .channels_max = 2,
2251 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2252 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2253 .ops = &twl4030_dai_voice_ops,
2254},
cc17557e 2255};
cc17557e 2256
f0fba2ad 2257static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2258{
f0fba2ad 2259 struct twl4030_priv *twl4030;
9da28c7b 2260
f2b1ce49
PU		 2261 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2262 GFP_KERNEL);
f0fba2ad 2263 if (twl4030 == NULL) {
3b8a0795 2264 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2265 return -ENOMEM;
cc17557e 2266 }
f0fba2ad
LG		 2267 snd_soc_codec_set_drvdata(codec, twl4030);
2268 /* Set the defaults, and power up the codec */
57fe7251 2269 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2270
2271 twl4030_init_chip(codec);
cc17557e 2272
7a1fecf5 2273 return 0;
cc17557e
SS		 2274}
2275
f0fba2ad 2276static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2277{
5b3b0fa8 2278 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2279 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2280
7a1fecf5 2281 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2282
2283 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2284 gpio_free(pdata->hs_extmute_gpio);
2285
7a1fecf5
PU		 2286 return 0;
2287}
2288
f0fba2ad
LG		 2289static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2290 .probe = twl4030_soc_probe,
2291 .remove = twl4030_soc_remove,
f0fba2ad
LG		 2292 .read = twl4030_read_reg_cache,
2293 .write = twl4030_write,
2294 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2295 .idle_bias_off = true,
f0fba2ad
LG		 2296 .reg_cache_size = sizeof(twl4030_reg),
2297 .reg_word_size = sizeof(u8),
2298 .reg_cache_default = twl4030_reg,
f7c93f01
PU		 2299
2300 .controls = twl4030_snd_controls,
2301 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2302 .dapm_widgets = twl4030_dapm_widgets,
2303 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2304 .dapm_routes = intercon,
2305 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2306};
2307
05c4c6f7 2308static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2309{
f0fba2ad
LG		 2310 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2311 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2312}
2313
05c4c6f7 2314static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2315{
f0fba2ad 2316 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2317 return 0;
2318}
2319
f0fba2ad 2320MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2321
2322static struct platform_driver twl4030_codec_driver = {
2323 .probe = twl4030_codec_probe,
05c4c6f7 2324 .remove = twl4030_codec_remove,
7a1fecf5 2325 .driver = {
f0fba2ad 2326 .name = "twl4030-codec",
7a1fecf5
PU		 2327 .owner = THIS_MODULE,
2328 },
cc17557e 2329};
cc17557e 2330
5bbcc3c0 2331module_platform_driver(twl4030_codec_driver);
64089b84 2332
cc17557e
SS		 2333MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2334MODULE_AUTHOR("Steve Sakoman");
2335MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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