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ASoC: TWL6040: Correct widget handling for drivers
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
c10b82cf 37#include <sound/tlv.h>
cc17557e
SS		 38
39#include "twl4030.h"
40
41/*
42 * twl4030 register cache & default register settings
43 */
44static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
45 0x00, /* this register not used */
33f92ed4 46 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 47 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 48 0x00, /* REG_UNKNOWN (0x3) */
49 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 50 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 51 0x00, /* REG_ANAMICR (0x6) */
52 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 53 0x00, /* REG_ADCMICSEL (0x8) */
54 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 55 0x0f, /* REG_ATXL1PGA (0xA) */
56 0x0f, /* REG_ATXR1PGA (0xB) */
57 0x0f, /* REG_AVTXL2PGA (0xC) */
58 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 59 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 60 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 61 0x3f, /* REG_ARXR1PGA (0x10) */
62 0x3f, /* REG_ARXL1PGA (0x11) */
63 0x3f, /* REG_ARXR2PGA (0x12) */
64 0x3f, /* REG_ARXL2PGA (0x13) */
65 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 66 0x00, /* REG_VSTPGA (0x15) */
67 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 68 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 69 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 70 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
71 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
72 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
73 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 74 0x00, /* REG_ATX2ARXPGA (0x1D) */
75 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 76 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 77 0x00, /* REG_BTSTPGA (0x20) */
78 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 79 0x00, /* REG_HS_SEL (0x22) */
80 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 81 0x00, /* REG_HS_POPN_SET (0x24) */
82 0x00, /* REG_PREDL_CTL (0x25) */
83 0x00, /* REG_PREDR_CTL (0x26) */
84 0x00, /* REG_PRECKL_CTL (0x27) */
85 0x00, /* REG_PRECKR_CTL (0x28) */
86 0x00, /* REG_HFL_CTL (0x29) */
87 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 88 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 89 0x00, /* REG_ALC_SET1 (0x2C) */
90 0x00, /* REG_ALC_SET2 (0x2D) */
91 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 92 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 93 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 94 0x00, /* REG_DTMF_TONEXT1H (0x31) */
95 0x00, /* REG_DTMF_TONEXT1L (0x32) */
96 0x00, /* REG_DTMF_TONEXT2H (0x33) */
97 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 98 0x79, /* REG_DTMF_TONOFF (0x35) */
99 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 100 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
102 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 103 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 104 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 105 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
106 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 107 0x00, /* REG_MISC_SET_1 (0x3E) */
108 0x00, /* REG_PCMBTMUX (0x3F) */
109 0x00, /* not used (0x40) */
110 0x00, /* not used (0x41) */
111 0x00, /* not used (0x42) */
112 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 113 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 114 0x00, /* REG_VIBRA_CTL (0x45) */
115 0x00, /* REG_VIBRA_SET (0x46) */
116 0x00, /* REG_VIBRA_PWM_SET (0x47) */
117 0x00, /* REG_ANAMIC_GAIN (0x48) */
118 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 119 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 120};
121
7393958f
PU		 122/* codec private data */
123struct twl4030_priv {
7a1fecf5
PU		 124 struct snd_soc_codec codec;
125
7393958f 126 unsigned int codec_powered;
7b4c734e
PU		 127
128 /* reference counts of AIF/APLL users */
2845fa13 129 unsigned int apll_enabled;
7220b9f4
PU		 130
131 struct snd_pcm_substream *master_substream;
132 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 133
134 unsigned int configured;
135 unsigned int rate;
136 unsigned int sample_bits;
137 unsigned int channels;
6943c92e
PU		 138
139 unsigned int sysclk;
140
c96907f2
PU		 141 /* Output (with associated amp) states */
142 u8 hsl_enabled, hsr_enabled;
143 u8 earpiece_enabled;
144 u8 predrivel_enabled, predriver_enabled;
145 u8 carkitl_enabled, carkitr_enabled;
7393958f
PU		 146};
147
cc17557e
SS		 148/*
149 * read twl4030 register cache
150 */
151static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
152 unsigned int reg)
153{
d08664fd 154 u8 *cache = codec->reg_cache;
cc17557e 155
91432e97
IM		 156 if (reg >= TWL4030_CACHEREGNUM)
157 return -EIO;
158
cc17557e
SS		 159 return cache[reg];
160}
161
162/*
163 * write twl4030 register cache
164 */
165static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
166 u8 reg, u8 value)
167{
168 u8 *cache = codec->reg_cache;
169
170 if (reg >= TWL4030_CACHEREGNUM)
171 return;
172 cache[reg] = value;
173}
174
175/*
176 * write to the twl4030 register space
177 */
178static int twl4030_write(struct snd_soc_codec *codec,
179 unsigned int reg, unsigned int value)
180{
b2c812e2 181 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 182 int write_to_reg = 0;
183
cc17557e 184 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 185 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
186 /* Decide if the given register can be written */
187 switch (reg) {
188 case TWL4030_REG_EAR_CTL:
189 if (twl4030->earpiece_enabled)
190 write_to_reg = 1;
191 break;
192 case TWL4030_REG_PREDL_CTL:
193 if (twl4030->predrivel_enabled)
194 write_to_reg = 1;
195 break;
196 case TWL4030_REG_PREDR_CTL:
197 if (twl4030->predriver_enabled)
198 write_to_reg = 1;
199 break;
200 case TWL4030_REG_PRECKL_CTL:
201 if (twl4030->carkitl_enabled)
202 write_to_reg = 1;
203 break;
204 case TWL4030_REG_PRECKR_CTL:
205 if (twl4030->carkitr_enabled)
206 write_to_reg = 1;
207 break;
208 case TWL4030_REG_HS_GAIN_SET:
209 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
210 write_to_reg = 1;
211 break;
212 default:
213 /* All other register can be written */
214 write_to_reg = 1;
215 break;
216 }
217 if (write_to_reg)
218 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
219 value, reg);
220 }
221 return 0;
cc17557e
SS		 222}
223
db04e2c5 224static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 225{
b2c812e2 226 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 227 int mode;
cc17557e 228
7393958f
PU		 229 if (enable == twl4030->codec_powered)
230 return;
231
db04e2c5 232 if (enable)
7a1fecf5 233 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 234 else
7a1fecf5 235 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 236
7a1fecf5
PU		 237 if (mode >= 0) {
238 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
239 twl4030->codec_powered = enable;
240 }
cc17557e
SS		 241
242 /* REVISIT: this delay is present in TI sample drivers */
243 /* but there seems to be no TRM requirement for it */
244 udelay(10);
245}
246
9fdcc0f7 247static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 248{
9fdcc0f7
PU		 249 int i, difference = 0;
250 u8 val;
251
252 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
253 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
254 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
255 if (val != twl4030_reg[i]) {
256 difference++;
257 dev_dbg(codec->dev,
258 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
259 i, val, twl4030_reg[i]);
260 }
261 }
262 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
263 difference, difference ? "Not OK" : "OK");
264}
cc17557e 265
a3a29b55
PU		 266static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
267{
268 int i;
cc17557e
SS		 269
270 /* set all audio section registers to reasonable defaults */
271 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 272 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 273 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 274
275}
276
ee4ccac7 277static void twl4030_init_chip(struct platform_device *pdev)
7393958f 278{
ee4ccac7
PU		 279 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
280 struct twl4030_setup_data *setup = socdev->codec_data;
281 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 282 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 283 u8 reg, byte;
284 int i = 0;
7393958f 285
9fdcc0f7
PU		 286 /* Check defaults, if instructed before anything else */
287 if (setup && setup->check_defaults)
288 twl4030_check_defaults(codec);
7a1fecf5 289
a3a29b55
PU		 290 /* Reset registers, if no setup data or if instructed to do so */
291 if (!setup || (setup && setup->reset_registers))
292 twl4030_reset_registers(codec);
7393958f 293
ee4ccac7 294 /* Refresh APLL_CTL register from HW */
9fdcc0f7 295 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 296 TWL4030_REG_APLL_CTL);
297 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 298
ee4ccac7
PU		 299 /* anti-pop when changing analog gain */
300 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
301 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
302 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 303
ee4ccac7
PU		 304 twl4030_write(codec, TWL4030_REG_OPTION,
305 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
306 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 307
3c36cc68
PU		 308 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
309 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
310
ee4ccac7
PU		 311 /* Machine dependent setup */
312 if (!setup)
7393958f
PU		 313 return;
314
ee4ccac7
PU		 315 /* Configuration for headset ramp delay from setup data */
316 if (setup->sysclk != twl4030->sysclk)
317 dev_warn(codec->dev,
318 "Mismatch in APLL mclk: %u (configured: %u)\n",
319 setup->sysclk, twl4030->sysclk);
320
321 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
322 reg &= ~TWL4030_RAMP_DELAY;
323 reg |= (setup->ramp_delay_value << 2);
324 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 325
326 /* initiate offset cancellation */
ee4ccac7
PU		 327 twl4030_codec_enable(codec, 1);
328
329 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
330 reg &= ~TWL4030_OFFSET_CNCL_SEL;
331 reg |= setup->offset_cncl_path;
006f367e 332 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 333 reg | TWL4030_CNCL_OFFSET_START);
006f367e
PU		 334
335 /* wait for offset cancellation to complete */
336 do {
337 /* this takes a little while, so don't slam i2c */
338 udelay(2000);
fc7b92fc 339 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 340 TWL4030_REG_ANAMICL);
341 } while ((i++ < 100) &&
342 ((byte & TWL4030_CNCL_OFFSET_START) ==
343 TWL4030_CNCL_OFFSET_START));
344
345 /* Make sure that the reg_cache has the same value as the HW */
346 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
347
006f367e 348 twl4030_codec_enable(codec, 0);
006f367e
PU		 349}
350
ee4ccac7 351static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 352{
ee4ccac7
PU		 353 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
354 int status = -1;
355
356 if (enable) {
357 twl4030->apll_enabled++;
358 if (twl4030->apll_enabled == 1)
359 status = twl4030_codec_enable_resource(
360 TWL4030_CODEC_RES_APLL);
361 } else {
362 twl4030->apll_enabled--;
363 if (!twl4030->apll_enabled)
364 status = twl4030_codec_disable_resource(
365 TWL4030_CODEC_RES_APLL);
366 }
367
368 if (status >= 0)
369 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 370}
371
5e98a464 372/* Earpiece */
1a787e7a
JS		 373static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
377 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
378};
5e98a464 379
2a6f5c58 380/* PreDrive Left */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
385 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
386};
2a6f5c58
PU		 387
388/* PreDrive Right */
1a787e7a
JS		 389static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
390 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
391 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
392 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
393 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
394};
2a6f5c58 395
dfad21a2 396/* Headset Left */
1a787e7a
JS		 397static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
398 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
399 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
400 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
401};
dfad21a2
PU		 402
403/* Headset Right */
1a787e7a
JS		 404static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
405 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
406 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
407 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
408};
dfad21a2 409
5152d8c2 410/* Carkit Left */
1a787e7a
JS		 411static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
412 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
413 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
414 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
415};
5152d8c2
PU		 416
417/* Carkit Right */
1a787e7a
JS		 418static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
419 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
420 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
421 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
422};
5152d8c2 423
df339804
PU		 424/* Handsfree Left */
425static const char *twl4030_handsfreel_texts[] =
1a787e7a 426 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 427
428static const struct soc_enum twl4030_handsfreel_enum =
429 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
430 ARRAY_SIZE(twl4030_handsfreel_texts),
431 twl4030_handsfreel_texts);
432
433static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
434SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
435
0f89bdca
PU		 436/* Handsfree Left virtual mute */
437static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
438 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
439
df339804
PU		 440/* Handsfree Right */
441static const char *twl4030_handsfreer_texts[] =
1a787e7a 442 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 443
444static const struct soc_enum twl4030_handsfreer_enum =
445 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
446 ARRAY_SIZE(twl4030_handsfreer_texts),
447 twl4030_handsfreer_texts);
448
449static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
450SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
451
0f89bdca
PU		 452/* Handsfree Right virtual mute */
453static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
454 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
455
376f7839
PU		 456/* Vibra */
457/* Vibra audio path selection */
458static const char *twl4030_vibra_texts[] =
459 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
460
461static const struct soc_enum twl4030_vibra_enum =
462 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
463 ARRAY_SIZE(twl4030_vibra_texts),
464 twl4030_vibra_texts);
465
466static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
467SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
468
469/* Vibra path selection: local vibrator (PWM) or audio driven */
470static const char *twl4030_vibrapath_texts[] =
471 {"Local vibrator", "Audio"};
472
473static const struct soc_enum twl4030_vibrapath_enum =
474 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
475 ARRAY_SIZE(twl4030_vibrapath_texts),
476 twl4030_vibrapath_texts);
477
478static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
479SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
480
276c6222 481/* Left analog microphone selection */
97b8096d 482static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 483 SOC_DAPM_SINGLE("Main Mic Capture Switch",
484 TWL4030_REG_ANAMICL, 0, 1, 0),
485 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
486 TWL4030_REG_ANAMICL, 1, 1, 0),
487 SOC_DAPM_SINGLE("AUXL Capture Switch",
488 TWL4030_REG_ANAMICL, 2, 1, 0),
489 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
490 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 491};
276c6222
PU		 492
493/* Right analog microphone selection */
97b8096d 494static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 495 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
496 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 497};
276c6222
PU		 498
499/* TX1 L/R Analog/Digital microphone selection */
500static const char *twl4030_micpathtx1_texts[] =
501 {"Analog", "Digimic0"};
502
503static const struct soc_enum twl4030_micpathtx1_enum =
504 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
505 ARRAY_SIZE(twl4030_micpathtx1_texts),
506 twl4030_micpathtx1_texts);
507
508static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
509SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
510
511/* TX2 L/R Analog/Digital microphone selection */
512static const char *twl4030_micpathtx2_texts[] =
513 {"Analog", "Digimic1"};
514
515static const struct soc_enum twl4030_micpathtx2_enum =
516 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
517 ARRAY_SIZE(twl4030_micpathtx2_texts),
518 twl4030_micpathtx2_texts);
519
520static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
521SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
522
7393958f
PU		 523/* Analog bypass for AudioR1 */
524static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
525 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
526
527/* Analog bypass for AudioL1 */
528static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
529 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
530
531/* Analog bypass for AudioR2 */
532static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
533 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
534
535/* Analog bypass for AudioL2 */
536static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
537 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
538
fcd274a3
LCM		 539/* Analog bypass for Voice */
540static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
541 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
542
8b0d3153 543/* Digital bypass gain, mute instead of -30dB */
6bab83fd 544static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 545 TLV_DB_RANGE_HEAD(3),
546 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
547 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 548 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
549};
550
551/* Digital bypass left (TX1L -> RX2L) */
552static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
553 SOC_DAPM_SINGLE_TLV("Volume",
554 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
555 twl4030_dapm_dbypass_tlv);
556
557/* Digital bypass right (TX1R -> RX2R) */
558static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
559 SOC_DAPM_SINGLE_TLV("Volume",
560 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
561 twl4030_dapm_dbypass_tlv);
562
ee8f6894
LCM		 563/*
564 * Voice Sidetone GAIN volume control:
565 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
566 */
567static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
568
569/* Digital bypass voice: sidetone (VUL -> VDL)*/
570static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
571 SOC_DAPM_SINGLE_TLV("Volume",
572 TWL4030_REG_VSTPGA, 0, 0x29, 0,
573 twl4030_dapm_dbypassv_tlv);
574
276c6222
PU		 575static int micpath_event(struct snd_soc_dapm_widget *w,
576 struct snd_kcontrol *kcontrol, int event)
577{
578 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
579 unsigned char adcmicsel, micbias_ctl;
580
581 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
582 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
583 /* Prepare the bits for the given TX path:
584 * shift_l == 0: TX1 microphone path
585 * shift_l == 2: TX2 microphone path */
586 if (e->shift_l) {
587 /* TX2 microphone path */
588 if (adcmicsel & TWL4030_TX2IN_SEL)
589 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
590 else
591 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
592 } else {
593 /* TX1 microphone path */
594 if (adcmicsel & TWL4030_TX1IN_SEL)
595 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
596 else
597 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
598 }
599
600 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
601
602 return 0;
603}
604
9008adf9
PU		 605/*
606 * Output PGA builder:
607 * Handle the muting and unmuting of the given output (turning off the
608 * amplifier associated with the output pin)
c96907f2
PU		 609 * On mute bypass the reg_cache and write 0 to the register
610 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 611 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
612 */
613#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
614static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
615 struct snd_kcontrol *kcontrol, int event) \
616{ \
b2c812e2 617 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 618 \
619 switch (event) { \
620 case SND_SOC_DAPM_POST_PMU: \
c96907f2 621 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 622 twl4030_write(w->codec, reg, \
623 twl4030_read_reg_cache(w->codec, reg)); \
624 break; \
625 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 626 twl4030->pin_name##_enabled = 0; \
627 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
628 0, reg); \
9008adf9
PU		 629 break; \
630 } \
631 return 0; \
632}
633
634TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
635TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
636TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
637TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
638TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
639
5a2e9a48 640static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 641{
49d92c7d
SM		 642 unsigned char hs_ctl;
643
5a2e9a48 644 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 645
5a2e9a48
PU		 646 if (ramp) {
647 /* HF ramp-up */
648 hs_ctl |= TWL4030_HF_CTL_REF_EN;
649 twl4030_write(codec, reg, hs_ctl);
650 udelay(10);
49d92c7d 651 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 652 twl4030_write(codec, reg, hs_ctl);
653 udelay(40);
49d92c7d 654 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 655 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 656 twl4030_write(codec, reg, hs_ctl);
49d92c7d 657 } else {
5a2e9a48
PU		 658 /* HF ramp-down */
659 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
660 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
661 twl4030_write(codec, reg, hs_ctl);
662 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
663 twl4030_write(codec, reg, hs_ctl);
664 udelay(40);
665 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
666 twl4030_write(codec, reg, hs_ctl);
49d92c7d 667 }
5a2e9a48 668}
49d92c7d 669
5a2e9a48
PU		 670static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
671 struct snd_kcontrol *kcontrol, int event)
672{
673 switch (event) {
674 case SND_SOC_DAPM_POST_PMU:
675 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
676 break;
677 case SND_SOC_DAPM_POST_PMD:
678 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
679 break;
680 }
681 return 0;
682}
683
684static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
685 struct snd_kcontrol *kcontrol, int event)
686{
687 switch (event) {
688 case SND_SOC_DAPM_POST_PMU:
689 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
690 break;
691 case SND_SOC_DAPM_POST_PMD:
692 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
693 break;
694 }
49d92c7d
SM		 695 return 0;
696}
697
86139a13
JV		 698static int vibramux_event(struct snd_soc_dapm_widget *w,
699 struct snd_kcontrol *kcontrol, int event)
700{
701 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
702 return 0;
703}
704
7729cf74
PU		 705static int apll_event(struct snd_soc_dapm_widget *w,
706 struct snd_kcontrol *kcontrol, int event)
707{
708 switch (event) {
709 case SND_SOC_DAPM_PRE_PMU:
710 twl4030_apll_enable(w->codec, 1);
711 break;
712 case SND_SOC_DAPM_POST_PMD:
713 twl4030_apll_enable(w->codec, 0);
714 break;
715 }
716 return 0;
717}
718
7b4c734e
PU		 719static int aif_event(struct snd_soc_dapm_widget *w,
720 struct snd_kcontrol *kcontrol, int event)
721{
722 u8 audio_if;
723
724 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
725 switch (event) {
726 case SND_SOC_DAPM_PRE_PMU:
727 /* Enable AIF */
728 /* enable the PLL before we use it to clock the DAI */
729 twl4030_apll_enable(w->codec, 1);
730
731 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
732 audio_if | TWL4030_AIF_EN);
733 break;
734 case SND_SOC_DAPM_POST_PMD:
735 /* disable the DAI before we stop it's source PLL */
736 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
737 audio_if & ~TWL4030_AIF_EN);
738 twl4030_apll_enable(w->codec, 0);
739 break;
740 }
741 return 0;
742}
743
6943c92e 744static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 745{
4e49ffd1
CVJ		 746 struct snd_soc_device *socdev = codec->socdev;
747 struct twl4030_setup_data *setup = socdev->codec_data;
748
aad749e5 749 unsigned char hs_gain, hs_pop;
b2c812e2 750 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 751 /* Base values for ramp delay calculation: 2^19 - 2^26 */
752 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
753 8388608, 16777216, 33554432, 67108864};
aad749e5 754
6943c92e
PU		 755 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
756 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 757
4e49ffd1
CVJ		 758 /* Enable external mute control, this dramatically reduces
759 * the pop-noise */
760 if (setup && setup->hs_extmute) {
761 if (setup->set_hs_extmute) {
762 setup->set_hs_extmute(1);
763 } else {
764 hs_pop |= TWL4030_EXTMUTE;
765 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
766 }
767 }
768
6943c92e
PU		 769 if (ramp) {
770 /* Headset ramp-up according to the TRM */
aad749e5 771 hs_pop |= TWL4030_VMID_EN;
6943c92e 772 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 773 /* Actually write to the register */
774 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
775 hs_gain,
776 TWL4030_REG_HS_GAIN_SET);
aad749e5 777 hs_pop |= TWL4030_RAMP_EN;
6943c92e 778 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 779 /* Wait ramp delay time + 1, so the VMID can settle */
780 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
781 twl4030->sysclk) + 1);
6943c92e
PU		 782 } else {
783 /* Headset ramp-down _not_ according to
784 * the TRM, but in a way that it is working */
aad749e5 785 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 786 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
787 /* Wait ramp delay time + 1, so the VMID can settle */
788 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
789 twl4030->sysclk) + 1);
aad749e5 790 /* Bypass the reg_cache to mute the headset */
fc7b92fc 791 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 792 hs_gain & (~0x0f),
793 TWL4030_REG_HS_GAIN_SET);
6943c92e 794
aad749e5 795 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 796 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
797 }
4e49ffd1
CVJ		 798
799 /* Disable external mute */
800 if (setup && setup->hs_extmute) {
801 if (setup->set_hs_extmute) {
802 setup->set_hs_extmute(0);
803 } else {
804 hs_pop &= ~TWL4030_EXTMUTE;
805 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
806 }
807 }
6943c92e
PU		 808}
809
810static int headsetlpga_event(struct snd_soc_dapm_widget *w,
811 struct snd_kcontrol *kcontrol, int event)
812{
b2c812e2 813 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 814
815 switch (event) {
816 case SND_SOC_DAPM_POST_PMU:
817 /* Do the ramp-up only once */
818 if (!twl4030->hsr_enabled)
819 headset_ramp(w->codec, 1);
820
821 twl4030->hsl_enabled = 1;
822 break;
823 case SND_SOC_DAPM_POST_PMD:
824 /* Do the ramp-down only if both headsetL/R is disabled */
825 if (!twl4030->hsr_enabled)
826 headset_ramp(w->codec, 0);
827
828 twl4030->hsl_enabled = 0;
829 break;
830 }
831 return 0;
832}
833
834static int headsetrpga_event(struct snd_soc_dapm_widget *w,
835 struct snd_kcontrol *kcontrol, int event)
836{
b2c812e2 837 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 838
839 switch (event) {
840 case SND_SOC_DAPM_POST_PMU:
841 /* Do the ramp-up only once */
842 if (!twl4030->hsl_enabled)
843 headset_ramp(w->codec, 1);
844
845 twl4030->hsr_enabled = 1;
846 break;
847 case SND_SOC_DAPM_POST_PMD:
848 /* Do the ramp-down only if both headsetL/R is disabled */
849 if (!twl4030->hsl_enabled)
850 headset_ramp(w->codec, 0);
851
852 twl4030->hsr_enabled = 0;
aad749e5
PU		 853 break;
854 }
855 return 0;
856}
857
b0bd53a7
PU		 858/*
859 * Some of the gain controls in TWL (mostly those which are associated with
860 * the outputs) are implemented in an interesting way:
861 * 0x0 : Power down (mute)
862 * 0x1 : 6dB
863 * 0x2 : 0 dB
864 * 0x3 : -6 dB
865 * Inverting not going to help with these.
866 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
867 */
868#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
869 xinvert, tlv_array) \
870{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
871 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
872 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
873 .tlv.p = (tlv_array), \
874 .info = snd_soc_info_volsw, \
875 .get = snd_soc_get_volsw_twl4030, \
876 .put = snd_soc_put_volsw_twl4030, \
877 .private_value = (unsigned long)&(struct soc_mixer_control) \
878 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
879 .max = xmax, .invert = xinvert} }
880#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
881 xinvert, tlv_array) \
882{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
883 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
884 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
885 .tlv.p = (tlv_array), \
886 .info = snd_soc_info_volsw_2r, \
887 .get = snd_soc_get_volsw_r2_twl4030,\
888 .put = snd_soc_put_volsw_r2_twl4030, \
889 .private_value = (unsigned long)&(struct soc_mixer_control) \
890 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 891 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 892#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
893 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
894 xinvert, tlv_array)
895
896static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
897 struct snd_ctl_elem_value *ucontrol)
898{
899 struct soc_mixer_control *mc =
900 (struct soc_mixer_control *)kcontrol->private_value;
901 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
902 unsigned int reg = mc->reg;
903 unsigned int shift = mc->shift;
904 unsigned int rshift = mc->rshift;
905 int max = mc->max;
906 int mask = (1 << fls(max)) - 1;
907
908 ucontrol->value.integer.value[0] =
909 (snd_soc_read(codec, reg) >> shift) & mask;
910 if (ucontrol->value.integer.value[0])
911 ucontrol->value.integer.value[0] =
912 max + 1 - ucontrol->value.integer.value[0];
913
914 if (shift != rshift) {
915 ucontrol->value.integer.value[1] =
916 (snd_soc_read(codec, reg) >> rshift) & mask;
917 if (ucontrol->value.integer.value[1])
918 ucontrol->value.integer.value[1] =
919 max + 1 - ucontrol->value.integer.value[1];
920 }
921
922 return 0;
923}
924
925static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
926 struct snd_ctl_elem_value *ucontrol)
927{
928 struct soc_mixer_control *mc =
929 (struct soc_mixer_control *)kcontrol->private_value;
930 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
931 unsigned int reg = mc->reg;
932 unsigned int shift = mc->shift;
933 unsigned int rshift = mc->rshift;
934 int max = mc->max;
935 int mask = (1 << fls(max)) - 1;
936 unsigned short val, val2, val_mask;
937
938 val = (ucontrol->value.integer.value[0] & mask);
939
940 val_mask = mask << shift;
941 if (val)
942 val = max + 1 - val;
943 val = val << shift;
944 if (shift != rshift) {
945 val2 = (ucontrol->value.integer.value[1] & mask);
946 val_mask |= mask << rshift;
947 if (val2)
948 val2 = max + 1 - val2;
949 val |= val2 << rshift;
950 }
951 return snd_soc_update_bits(codec, reg, val_mask, val);
952}
953
954static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
955 struct snd_ctl_elem_value *ucontrol)
956{
957 struct soc_mixer_control *mc =
958 (struct soc_mixer_control *)kcontrol->private_value;
959 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
960 unsigned int reg = mc->reg;
961 unsigned int reg2 = mc->rreg;
962 unsigned int shift = mc->shift;
963 int max = mc->max;
964 int mask = (1<<fls(max))-1;
965
966 ucontrol->value.integer.value[0] =
967 (snd_soc_read(codec, reg) >> shift) & mask;
968 ucontrol->value.integer.value[1] =
969 (snd_soc_read(codec, reg2) >> shift) & mask;
970
971 if (ucontrol->value.integer.value[0])
972 ucontrol->value.integer.value[0] =
973 max + 1 - ucontrol->value.integer.value[0];
974 if (ucontrol->value.integer.value[1])
975 ucontrol->value.integer.value[1] =
976 max + 1 - ucontrol->value.integer.value[1];
977
978 return 0;
979}
980
981static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
982 struct snd_ctl_elem_value *ucontrol)
983{
984 struct soc_mixer_control *mc =
985 (struct soc_mixer_control *)kcontrol->private_value;
986 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
987 unsigned int reg = mc->reg;
988 unsigned int reg2 = mc->rreg;
989 unsigned int shift = mc->shift;
990 int max = mc->max;
991 int mask = (1 << fls(max)) - 1;
992 int err;
993 unsigned short val, val2, val_mask;
994
995 val_mask = mask << shift;
996 val = (ucontrol->value.integer.value[0] & mask);
997 val2 = (ucontrol->value.integer.value[1] & mask);
998
999 if (val)
1000 val = max + 1 - val;
1001 if (val2)
1002 val2 = max + 1 - val2;
1003
1004 val = val << shift;
1005 val2 = val2 << shift;
1006
1007 err = snd_soc_update_bits(codec, reg, val_mask, val);
1008 if (err < 0)
1009 return err;
1010
1011 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1012 return err;
1013}
1014
b74bd40f
LCM		 1015/* Codec operation modes */
1016static const char *twl4030_op_modes_texts[] = {
1017 "Option 2 (voice/audio)", "Option 1 (audio)"
1018};
1019
1020static const struct soc_enum twl4030_op_modes_enum =
1021 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1022 ARRAY_SIZE(twl4030_op_modes_texts),
1023 twl4030_op_modes_texts);
1024
423c238d 1025static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1026 struct snd_ctl_elem_value *ucontrol)
1027{
1028 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1029 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1030 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1031 unsigned short val;
1032 unsigned short mask, bitmask;
1033
1034 if (twl4030->configured) {
1035 printk(KERN_ERR "twl4030 operation mode cannot be "
1036 "changed on-the-fly\n");
1037 return -EBUSY;
1038 }
1039
1040 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1041 ;
1042 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1043 return -EINVAL;
1044
1045 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1046 mask = (bitmask - 1) << e->shift_l;
1047 if (e->shift_l != e->shift_r) {
1048 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1049 return -EINVAL;
1050 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1051 mask |= (bitmask - 1) << e->shift_r;
1052 }
1053
1054 return snd_soc_update_bits(codec, e->reg, mask, val);
1055}
1056
c10b82cf
PU		 1057/*
1058 * FGAIN volume control:
1059 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1060 */
d889a72c 1061static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1062
0d33ea0b
PU		 1063/*
1064 * CGAIN volume control:
1065 * 0 dB to 12 dB in 6 dB steps
1066 * value 2 and 3 means 12 dB
1067 */
d889a72c
PU		 1068static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1069
1a787e7a
JS		 1070/*
1071 * Voice Downlink GAIN volume control:
1072 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1073 */
1074static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1075
d889a72c
PU		 1076/*
1077 * Analog playback gain
1078 * -24 dB to 12 dB in 2 dB steps
1079 */
1080static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1081
4290239c
PU		 1082/*
1083 * Gain controls tied to outputs
1084 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1085 */
1086static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1087
18cc8d8d
JS		 1088/*
1089 * Gain control for earpiece amplifier
1090 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1091 */
1092static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1093
381a22b5
PU		 1094/*
1095 * Capture gain after the ADCs
1096 * from 0 dB to 31 dB in 1 dB steps
1097 */
1098static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1099
5920b453
GI		 1100/*
1101 * Gain control for input amplifiers
1102 * 0 dB to 30 dB in 6 dB steps
1103 */
1104static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1105
328d0a13
LCM		 1106/* AVADC clock priority */
1107static const char *twl4030_avadc_clk_priority_texts[] = {
1108 "Voice high priority", "HiFi high priority"
1109};
1110
1111static const struct soc_enum twl4030_avadc_clk_priority_enum =
1112 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1113 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1114 twl4030_avadc_clk_priority_texts);
1115
89492be8
PU		 1116static const char *twl4030_rampdelay_texts[] = {
1117 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1118 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1119 "3495/2581/1748 ms"
1120};
1121
1122static const struct soc_enum twl4030_rampdelay_enum =
1123 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1124 ARRAY_SIZE(twl4030_rampdelay_texts),
1125 twl4030_rampdelay_texts);
1126
376f7839
PU		 1127/* Vibra H-bridge direction mode */
1128static const char *twl4030_vibradirmode_texts[] = {
1129 "Vibra H-bridge direction", "Audio data MSB",
1130};
1131
1132static const struct soc_enum twl4030_vibradirmode_enum =
1133 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1134 ARRAY_SIZE(twl4030_vibradirmode_texts),
1135 twl4030_vibradirmode_texts);
1136
1137/* Vibra H-bridge direction */
1138static const char *twl4030_vibradir_texts[] = {
1139 "Positive polarity", "Negative polarity",
1140};
1141
1142static const struct soc_enum twl4030_vibradir_enum =
1143 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1144 ARRAY_SIZE(twl4030_vibradir_texts),
1145 twl4030_vibradir_texts);
1146
36aeff61
PU		 1147/* Digimic Left and right swapping */
1148static const char *twl4030_digimicswap_texts[] = {
1149 "Not swapped", "Swapped",
1150};
1151
1152static const struct soc_enum twl4030_digimicswap_enum =
1153 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1154 ARRAY_SIZE(twl4030_digimicswap_texts),
1155 twl4030_digimicswap_texts);
1156
cc17557e 1157static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1158 /* Codec operation mode control */
1159 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1160 snd_soc_get_enum_double,
1161 snd_soc_put_twl4030_opmode_enum_double),
1162
d889a72c
PU		 1163 /* Common playback gain controls */
1164 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1165 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1166 0, 0x3f, 0, digital_fine_tlv),
1167 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1168 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1169 0, 0x3f, 0, digital_fine_tlv),
1170
1171 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1172 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1173 6, 0x2, 0, digital_coarse_tlv),
1174 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1175 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1176 6, 0x2, 0, digital_coarse_tlv),
1177
1178 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1179 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1180 3, 0x12, 1, analog_tlv),
1181 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1182 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1183 3, 0x12, 1, analog_tlv),
44c55870
PU		 1184 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1185 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1186 1, 1, 0),
1187 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1188 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1189 1, 1, 0),
381a22b5 1190
1a787e7a
JS		 1191 /* Common voice downlink gain controls */
1192 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1193 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1194
1195 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1196 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1197
1198 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1199 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1200
4290239c
PU		 1201 /* Separate output gain controls */
1202 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1203 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1204 4, 3, 0, output_tvl),
1205
1206 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1207 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1208
1209 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1210 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1211 4, 3, 0, output_tvl),
1212
1213 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1214 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1215
381a22b5 1216 /* Common capture gain controls */
276c6222 1217 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1218 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1219 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1220 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1221 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1222 0, 0x1f, 0, digital_capture_tlv),
5920b453 1223
276c6222 1224 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1225 0, 3, 5, 0, input_gain_tlv),
89492be8 1226
328d0a13
LCM		 1227 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1228
89492be8 1229 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1230
1231 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1232 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1233
1234 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1235};
1236
cc17557e 1237static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1238 /* Left channel inputs */
1239 SND_SOC_DAPM_INPUT("MAINMIC"),
1240 SND_SOC_DAPM_INPUT("HSMIC"),
1241 SND_SOC_DAPM_INPUT("AUXL"),
1242 SND_SOC_DAPM_INPUT("CARKITMIC"),
1243 /* Right channel inputs */
1244 SND_SOC_DAPM_INPUT("SUBMIC"),
1245 SND_SOC_DAPM_INPUT("AUXR"),
1246 /* Digital microphones (Stereo) */
1247 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1248 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1249
1250 /* Outputs */
5e98a464 1251 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1252 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1253 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1254 SND_SOC_DAPM_OUTPUT("HSOL"),
1255 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1256 SND_SOC_DAPM_OUTPUT("CARKITL"),
1257 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1258 SND_SOC_DAPM_OUTPUT("HFL"),
1259 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1260 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1261
7b4c734e
PU		 1262 /* AIF and APLL clocks for running DAIs (including loopback) */
1263 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1264 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1265 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1266
53b5047d 1267 /* DACs */
b4852b79 1268 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1269 SND_SOC_NOPM, 0, 0),
b4852b79 1270 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1271 SND_SOC_NOPM, 0, 0),
b4852b79 1272 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1273 SND_SOC_NOPM, 0, 0),
b4852b79 1274 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1275 SND_SOC_NOPM, 0, 0),
1a787e7a 1276 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1277 SND_SOC_NOPM, 0, 0),
cc17557e 1278
7393958f 1279 /* Analog bypasses */
78e08e2f
PU		 1280 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_abypassr1_control),
1282 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1283 &twl4030_dapm_abypassl1_control),
1284 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_abypassr2_control),
1286 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1287 &twl4030_dapm_abypassl2_control),
1288 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1289 &twl4030_dapm_abypassv_control),
1290
1291 /* Master analog loopback switch */
1292 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1293 NULL, 0),
7393958f 1294
6bab83fd 1295 /* Digital bypasses */
78e08e2f
PU		 1296 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1297 &twl4030_dapm_dbypassl_control),
1298 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1299 &twl4030_dapm_dbypassr_control),
1300 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1301 &twl4030_dapm_dbypassv_control),
6bab83fd 1302
4005d39a
PU		 1303 /* Digital mixers, power control for the physical DACs */
1304 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1305 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1306 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1307 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1308 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1309 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1310 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1311 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1312 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1313 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1314
1315 /* Analog mixers, power control for the physical PGAs */
1316 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1317 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1318 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1319 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1320 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1321 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1322 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1323 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1324 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1325 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1326
7729cf74
PU		 1327 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1328 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1329
7b4c734e
PU		 1330 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1331 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1332
1a787e7a 1333 /* Output MIXER controls */
5e98a464 1334 /* Earpiece */
1a787e7a
JS		 1335 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1336 &twl4030_dapm_earpiece_controls[0],
1337 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1338 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1339 0, 0, NULL, 0, earpiecepga_event,
1340 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1341 /* PreDrivL/R */
1a787e7a
JS		 1342 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1343 &twl4030_dapm_predrivel_controls[0],
1344 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1345 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1346 0, 0, NULL, 0, predrivelpga_event,
1347 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1348 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1349 &twl4030_dapm_predriver_controls[0],
1350 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1351 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1352 0, 0, NULL, 0, predriverpga_event,
1353 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1354 /* HeadsetL/R */
6943c92e 1355 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1356 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1357 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1358 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1359 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1360 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1361 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1362 &twl4030_dapm_hsor_controls[0],
1363 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1364 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1365 0, 0, NULL, 0, headsetrpga_event,
1366 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1367 /* CarkitL/R */
1a787e7a
JS		 1368 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1369 &twl4030_dapm_carkitl_controls[0],
1370 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1371 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1372 0, 0, NULL, 0, carkitlpga_event,
1373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1374 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1375 &twl4030_dapm_carkitr_controls[0],
1376 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1377 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1378 0, 0, NULL, 0, carkitrpga_event,
1379 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1380
1381 /* Output MUX controls */
df339804 1382 /* HandsfreeL/R */
5a2e9a48
PU		 1383 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1384 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1385 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1386 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1387 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1388 0, 0, NULL, 0, handsfreelpga_event,
1389 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1390 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1391 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1392 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1393 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1394 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1395 0, 0, NULL, 0, handsfreerpga_event,
1396 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1397 /* Vibra */
86139a13
JV		 1398 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1399 &twl4030_dapm_vibra_control, vibramux_event,
1400 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1401 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1402 &twl4030_dapm_vibrapath_control),
5e98a464 1403
276c6222
PU		 1404 /* Introducing four virtual ADC, since TWL4030 have four channel for
1405 capture */
1406 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1407 SND_SOC_NOPM, 0, 0),
1408 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1409 SND_SOC_NOPM, 0, 0),
1410 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1411 SND_SOC_NOPM, 0, 0),
1412 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1413 SND_SOC_NOPM, 0, 0),
1414
1415 /* Analog/Digital mic path selection.
1416 TX1 Left/Right: either analog Left/Right or Digimic0
1417 TX2 Left/Right: either analog Left/Right or Digimic1 */
1418 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1419 &twl4030_dapm_micpathtx1_control, micpath_event,
1420 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1421 SND_SOC_DAPM_POST_REG),
1422 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1423 &twl4030_dapm_micpathtx2_control, micpath_event,
1424 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1425 SND_SOC_DAPM_POST_REG),
1426
97b8096d 1427 /* Analog input mixers for the capture amplifiers */
9028935d 1428 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1429 TWL4030_REG_ANAMICL, 4, 0,
1430 &twl4030_dapm_analoglmic_controls[0],
1431 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1432 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1433 TWL4030_REG_ANAMICR, 4, 0,
1434 &twl4030_dapm_analogrmic_controls[0],
1435 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1436
fb2a2f84
PU		 1437 SND_SOC_DAPM_PGA("ADC Physical Left",
1438 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1439 SND_SOC_DAPM_PGA("ADC Physical Right",
1440 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1441
1442 SND_SOC_DAPM_PGA("Digimic0 Enable",
1443 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1444 SND_SOC_DAPM_PGA("Digimic1 Enable",
1445 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1446
1447 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1448 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1449 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1450
cc17557e
SS		 1451};
1452
1453static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1454 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1455 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1456 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1457 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1458 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1459
7729cf74 1460 /* Supply for the digital part (APLL) */
7729cf74
PU		 1461 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1462
27eeb1fe
PU		 1463 {"DAC Left1", NULL, "AIF Enable"},
1464 {"DAC Right1", NULL, "AIF Enable"},
1465 {"DAC Left2", NULL, "AIF Enable"},
1466 {"DAC Right1", NULL, "AIF Enable"},
1467
c42a59ea
PU		 1468 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1469 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1470
4005d39a
PU		 1471 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1472 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1473 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1474 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1475 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1476
5e98a464
PU		 1477 /* Internal playback routings */
1478 /* Earpiece */
4005d39a
PU		 1479 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1480 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1481 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1482 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1483 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1484 /* PreDrivL */
4005d39a
PU		 1485 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1486 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1487 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1488 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1489 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1490 /* PreDrivR */
4005d39a
PU		 1491 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1492 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1493 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1494 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1495 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1496 /* HeadsetL */
4005d39a
PU		 1497 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1498 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1499 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1500 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1501 /* HeadsetR */
4005d39a
PU		 1502 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1503 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1504 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1505 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1506 /* CarkitL */
4005d39a
PU		 1507 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1508 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1509 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1510 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1511 /* CarkitR */
4005d39a
PU		 1512 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1513 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1514 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1515 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1516 /* HandsfreeL */
4005d39a
PU		 1517 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1518 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1519 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1520 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1521 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1522 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1523 /* HandsfreeR */
4005d39a
PU		 1524 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1525 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1526 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1527 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1528 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1529 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1530 /* Vibra */
1531 {"Vibra Mux", "AudioL1", "DAC Left1"},
1532 {"Vibra Mux", "AudioR1", "DAC Right1"},
1533 {"Vibra Mux", "AudioL2", "DAC Left2"},
1534 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1535
cc17557e 1536 /* outputs */
7b4c734e 1537 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1538 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1539 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1540 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1541 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1542 /* Must be always connected (for APLL) */
1543 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1544 /* Physical outputs */
9008adf9
PU		 1545 {"EARPIECE", NULL, "Earpiece PGA"},
1546 {"PREDRIVEL", NULL, "PredriveL PGA"},
1547 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1548 {"HSOL", NULL, "HeadsetL PGA"},
1549 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1550 {"CARKITL", NULL, "CarkitL PGA"},
1551 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1552 {"HFL", NULL, "HandsfreeL PGA"},
1553 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1554 {"Vibra Route", "Audio", "Vibra Mux"},
1555 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1556
276c6222 1557 /* Capture path */
7b4c734e
PU		 1558 /* Must be always connected (for AIF and APLL) */
1559 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1560 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1561 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1562 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1563 /* Physical inputs */
9028935d
PU		 1564 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1565 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1566 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1567 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1568
9028935d
PU		 1569 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1570 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1571
9028935d
PU		 1572 {"ADC Physical Left", NULL, "Analog Left"},
1573 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1574
1575 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1576 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1577
1578 /* TX1 Left capture path */
fb2a2f84 1579 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1580 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1581 /* TX1 Right capture path */
fb2a2f84 1582 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1583 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1584 /* TX2 Left capture path */
fb2a2f84 1585 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1586 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1587 /* TX2 Right capture path */
fb2a2f84 1588 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1589 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1590
1591 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1592 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1593 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1594 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1595
c42a59ea
PU		 1596 {"ADC Virtual Left1", NULL, "AIF Enable"},
1597 {"ADC Virtual Right1", NULL, "AIF Enable"},
1598 {"ADC Virtual Left2", NULL, "AIF Enable"},
1599 {"ADC Virtual Right2", NULL, "AIF Enable"},
1600
7393958f 1601 /* Analog bypass routes */
9028935d
PU		 1602 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1603 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1604 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1605 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1606 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1607
78e08e2f
PU		 1608 /* Supply for the Analog loopbacks */
1609 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1610 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1611 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1612 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1613 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1614
7393958f
PU		 1615 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1616 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1617 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1618 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1619 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1620
6bab83fd
PU		 1621 /* Digital bypass routes */
1622 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1623 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1624 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1625
4005d39a
PU		 1626 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1627 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1628 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1629
cc17557e
SS		 1630};
1631
1632static int twl4030_add_widgets(struct snd_soc_codec *codec)
1633{
1634 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1635 ARRAY_SIZE(twl4030_dapm_widgets));
1636
1637 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1638
cc17557e
SS		 1639 return 0;
1640}
1641
cc17557e
SS		 1642static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1643 enum snd_soc_bias_level level)
1644{
1645 switch (level) {
1646 case SND_SOC_BIAS_ON:
cc17557e
SS		 1647 break;
1648 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1649 break;
1650 case SND_SOC_BIAS_STANDBY:
78e08e2f 1651 if (codec->bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1652 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1653 break;
1654 case SND_SOC_BIAS_OFF:
cbd2db12 1655 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1656 break;
1657 }
1658 codec->bias_level = level;
1659
1660 return 0;
1661}
1662
6b87a91f
PU		 1663static void twl4030_constraints(struct twl4030_priv *twl4030,
1664 struct snd_pcm_substream *mst_substream)
1665{
1666 struct snd_pcm_substream *slv_substream;
1667
1668 /* Pick the stream, which need to be constrained */
1669 if (mst_substream == twl4030->master_substream)
1670 slv_substream = twl4030->slave_substream;
1671 else if (mst_substream == twl4030->slave_substream)
1672 slv_substream = twl4030->master_substream;
1673 else /* This should not happen.. */
1674 return;
1675
1676 /* Set the constraints according to the already configured stream */
1677 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1678 SNDRV_PCM_HW_PARAM_RATE,
1679 twl4030->rate,
1680 twl4030->rate);
1681
1682 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1683 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1684 twl4030->sample_bits,
1685 twl4030->sample_bits);
1686
1687 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1688 SNDRV_PCM_HW_PARAM_CHANNELS,
1689 twl4030->channels,
1690 twl4030->channels);
1691}
1692
8a1f936a
PU		 1693/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1694 * capture has to be enabled/disabled. */
1695static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1696 int enable)
1697{
1698 u8 reg, mask;
1699
1700 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1701
1702 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1703 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1704 else
1705 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1706
1707 if (enable)
1708 reg |= mask;
1709 else
1710 reg &= ~mask;
1711
1712 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1713}
1714
d6648da1
PU		 1715static int twl4030_startup(struct snd_pcm_substream *substream,
1716 struct snd_soc_dai *dai)
7220b9f4
PU		 1717{
1718 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1719 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1720 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1721 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1722
7220b9f4 1723 if (twl4030->master_substream) {
7220b9f4 1724 twl4030->slave_substream = substream;
6b87a91f
PU		 1725 /* The DAI has one configuration for playback and capture, so
1726 * if the DAI has been already configured then constrain this
1727 * substream to match it. */
1728 if (twl4030->configured)
1729 twl4030_constraints(twl4030, twl4030->master_substream);
1730 } else {
8a1f936a
PU		 1731 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1732 TWL4030_OPTION_1)) {
1733 /* In option2 4 channel is not supported, set the
1734 * constraint for the first stream for channels, the
1735 * second stream will 'inherit' this cosntraint */
1736 snd_pcm_hw_constraint_minmax(substream->runtime,
1737 SNDRV_PCM_HW_PARAM_CHANNELS,
1738 2, 2);
1739 }
7220b9f4 1740 twl4030->master_substream = substream;
6b87a91f 1741 }
7220b9f4
PU		 1742
1743 return 0;
1744}
1745
d6648da1
PU		 1746static void twl4030_shutdown(struct snd_pcm_substream *substream,
1747 struct snd_soc_dai *dai)
7220b9f4
PU		 1748{
1749 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1750 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1751 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1752 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1753
1754 if (twl4030->master_substream == substream)
1755 twl4030->master_substream = twl4030->slave_substream;
1756
1757 twl4030->slave_substream = NULL;
6b87a91f
PU		 1758
1759 /* If all streams are closed, or the remaining stream has not yet
1760 * been configured than set the DAI as not configured. */
1761 if (!twl4030->master_substream)
1762 twl4030->configured = 0;
1763 else if (!twl4030->master_substream->runtime->channels)
1764 twl4030->configured = 0;
8a1f936a
PU		 1765
1766 /* If the closing substream had 4 channel, do the necessary cleanup */
1767 if (substream->runtime->channels == 4)
1768 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1769}
1770
cc17557e 1771static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1772 struct snd_pcm_hw_params *params,
1773 struct snd_soc_dai *dai)
cc17557e
SS		 1774{
1775 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1776 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1777 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1778 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1779 u8 mode, old_mode, format, old_format;
1780
8a1f936a
PU		 1781 /* If the substream has 4 channel, do the necessary setup */
1782 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1783 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1784 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1785
1786 /* Safety check: are we in the correct operating mode and
1787 * the interface is in TDM mode? */
1788 if ((mode & TWL4030_OPTION_1) &&
1789 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1790 twl4030_tdm_enable(codec, substream->stream, 1);
1791 else
1792 return -EINVAL;
1793 }
1794
6b87a91f
PU		 1795 if (twl4030->configured)
1796 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1797 return 0;
1798
cc17557e
SS		 1799 /* bit rate */
1800 old_mode = twl4030_read_reg_cache(codec,
1801 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1802 mode = old_mode & ~TWL4030_APLL_RATE;
1803
1804 switch (params_rate(params)) {
1805 case 8000:
1806 mode |= TWL4030_APLL_RATE_8000;
1807 break;
1808 case 11025:
1809 mode |= TWL4030_APLL_RATE_11025;
1810 break;
1811 case 12000:
1812 mode |= TWL4030_APLL_RATE_12000;
1813 break;
1814 case 16000:
1815 mode |= TWL4030_APLL_RATE_16000;
1816 break;
1817 case 22050:
1818 mode |= TWL4030_APLL_RATE_22050;
1819 break;
1820 case 24000:
1821 mode |= TWL4030_APLL_RATE_24000;
1822 break;
1823 case 32000:
1824 mode |= TWL4030_APLL_RATE_32000;
1825 break;
1826 case 44100:
1827 mode |= TWL4030_APLL_RATE_44100;
1828 break;
1829 case 48000:
1830 mode |= TWL4030_APLL_RATE_48000;
1831 break;
103f211d
PU		 1832 case 96000:
1833 mode |= TWL4030_APLL_RATE_96000;
1834 break;
cc17557e
SS		 1835 default:
1836 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1837 params_rate(params));
1838 return -EINVAL;
1839 }
1840
cc17557e
SS		 1841 /* sample size */
1842 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1843 format = old_format;
1844 format &= ~TWL4030_DATA_WIDTH;
1845 switch (params_format(params)) {
1846 case SNDRV_PCM_FORMAT_S16_LE:
1847 format |= TWL4030_DATA_WIDTH_16S_16W;
1848 break;
1849 case SNDRV_PCM_FORMAT_S24_LE:
1850 format |= TWL4030_DATA_WIDTH_32S_24W;
1851 break;
1852 default:
1853 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1854 params_format(params));
1855 return -EINVAL;
1856 }
1857
2046f175
PU		 1858 if (format != old_format || mode != old_mode) {
1859 if (twl4030->codec_powered) {
1860 /*
1861 * If the codec is powered, than we need to toggle the
1862 * codec power.
1863 */
1864 twl4030_codec_enable(codec, 0);
1865 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1866 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1867 twl4030_codec_enable(codec, 1);
1868 } else {
1869 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1870 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1871 }
cc17557e 1872 }
6b87a91f
PU		 1873
1874 /* Store the important parameters for the DAI configuration and set
1875 * the DAI as configured */
1876 twl4030->configured = 1;
1877 twl4030->rate = params_rate(params);
1878 twl4030->sample_bits = hw_param_interval(params,
1879 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1880 twl4030->channels = params_channels(params);
1881
1882 /* If both playback and capture streams are open, and one of them
1883 * is setting the hw parameters right now (since we are here), set
1884 * constraints to the other stream to match the current one. */
1885 if (twl4030->slave_substream)
1886 twl4030_constraints(twl4030, substream);
1887
cc17557e
SS		 1888 return 0;
1889}
1890
1891static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1892 int clk_id, unsigned int freq, int dir)
1893{
1894 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1895 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1896
1897 switch (freq) {
1898 case 19200000:
cc17557e 1899 case 26000000:
cc17557e 1900 case 38400000:
cc17557e
SS		 1901 break;
1902 default:
68d01955 1903 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1904 return -EINVAL;
1905 }
1906
68d01955
PU		 1907 if ((freq / 1000) != twl4030->sysclk) {
1908 dev_err(codec->dev,
1909 "Mismatch in APLL mclk: %u (configured: %u)\n",
1910 freq, twl4030->sysclk * 1000);
1911 return -EINVAL;
1912 }
cc17557e
SS		 1913
1914 return 0;
1915}
1916
1917static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1918 unsigned int fmt)
1919{
1920 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1921 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1922 u8 old_format, format;
1923
1924 /* get format */
1925 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1926 format = old_format;
1927
1928 /* set master/slave audio interface */
1929 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1930 case SND_SOC_DAIFMT_CBM_CFM:
1931 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1932 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1933 break;
1934 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1935 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1936 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1937 break;
1938 default:
1939 return -EINVAL;
1940 }
1941
1942 /* interface format */
1943 format &= ~TWL4030_AIF_FORMAT;
1944 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1945 case SND_SOC_DAIFMT_I2S:
1946 format |= TWL4030_AIF_FORMAT_CODEC;
1947 break;
8a1f936a
PU		 1948 case SND_SOC_DAIFMT_DSP_A:
1949 format |= TWL4030_AIF_FORMAT_TDM;
1950 break;
cc17557e
SS		 1951 default:
1952 return -EINVAL;
1953 }
1954
1955 if (format != old_format) {
2046f175
PU		 1956 if (twl4030->codec_powered) {
1957 /*
1958 * If the codec is powered, than we need to toggle the
1959 * codec power.
1960 */
1961 twl4030_codec_enable(codec, 0);
1962 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1963 twl4030_codec_enable(codec, 1);
1964 } else {
1965 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1966 }
cc17557e
SS		 1967 }
1968
1969 return 0;
1970}
1971
68140443
LCM		 1972static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1973{
1974 struct snd_soc_codec *codec = dai->codec;
1975 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1976
1977 if (tristate)
1978 reg |= TWL4030_AIF_TRI_EN;
1979 else
1980 reg &= ~TWL4030_AIF_TRI_EN;
1981
1982 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1983}
1984
b7a755a8
MLC		 1985/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1986 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1987static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1988 int enable)
1989{
1990 u8 reg, mask;
1991
1992 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1993
1994 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1995 mask = TWL4030_ARXL1_VRX_EN;
1996 else
1997 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1998
1999 if (enable)
2000 reg |= mask;
2001 else
2002 reg &= ~mask;
2003
2004 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2005}
2006
7154b3e8
JS		 2007static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2008 struct snd_soc_dai *dai)
2009{
2010 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2011 struct snd_soc_device *socdev = rtd->socdev;
2012 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 2013 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2014 u8 mode;
2015
2016 /* If the system master clock is not 26MHz, the voice PCM interface is
2017 * not avilable.
2018 */
68d01955
PU		 2019 if (twl4030->sysclk != 26000) {
2020 dev_err(codec->dev, "The board is configured for %u Hz, while"
2021 "the Voice interface needs 26MHz APLL mclk\n",
2022 twl4030->sysclk * 1000);
7154b3e8
JS		 2023 return -EINVAL;
2024 }
2025
2026 /* If the codec mode is not option2, the voice PCM interface is not
2027 * avilable.
2028 */
2029 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2030 & TWL4030_OPT_MODE;
2031
2032 if (mode != TWL4030_OPTION_2) {
2033 printk(KERN_ERR "TWL4030 voice startup: "
2034 "the codec mode is not option2\n");
2035 return -EINVAL;
2036 }
2037
2038 return 0;
2039}
2040
b7a755a8
MLC		 2041static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2042 struct snd_soc_dai *dai)
2043{
2044 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2045 struct snd_soc_device *socdev = rtd->socdev;
2046 struct snd_soc_codec *codec = socdev->card->codec;
2047
2048 /* Enable voice digital filters */
2049 twl4030_voice_enable(codec, substream->stream, 0);
2050}
2051
7154b3e8
JS		 2052static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2053 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2054{
2055 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2056 struct snd_soc_device *socdev = rtd->socdev;
2057 struct snd_soc_codec *codec = socdev->card->codec;
2046f175 2058 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2059 u8 old_mode, mode;
2060
b7a755a8
MLC		 2061 /* Enable voice digital filters */
2062 twl4030_voice_enable(codec, substream->stream, 1);
2063
7154b3e8
JS		 2064 /* bit rate */
2065 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2066 & ~(TWL4030_CODECPDZ);
2067 mode = old_mode;
2068
2069 switch (params_rate(params)) {
2070 case 8000:
2071 mode &= ~(TWL4030_SEL_16K);
2072 break;
2073 case 16000:
2074 mode |= TWL4030_SEL_16K;
2075 break;
2076 default:
2077 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2078 params_rate(params));
2079 return -EINVAL;
2080 }
2081
2082 if (mode != old_mode) {
2046f175
PU		 2083 if (twl4030->codec_powered) {
2084 /*
2085 * If the codec is powered, than we need to toggle the
2086 * codec power.
2087 */
2088 twl4030_codec_enable(codec, 0);
2089 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2090 twl4030_codec_enable(codec, 1);
2091 } else {
2092 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2093 }
7154b3e8
JS		 2094 }
2095
2096 return 0;
2097}
2098
2099static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2100 int clk_id, unsigned int freq, int dir)
2101{
2102 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2103 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2104
68d01955
PU		 2105 if (freq != 26000000) {
2106 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2107 "interface needs 26MHz APLL mclk\n", freq);
2108 return -EINVAL;
2109 }
2110 if ((freq / 1000) != twl4030->sysclk) {
2111 dev_err(codec->dev,
2112 "Mismatch in APLL mclk: %u (configured: %u)\n",
2113 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2114 return -EINVAL;
2115 }
7154b3e8
JS		 2116 return 0;
2117}
2118
2119static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2120 unsigned int fmt)
2121{
2122 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2123 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2124 u8 old_format, format;
2125
2126 /* get format */
2127 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2128 format = old_format;
2129
2130 /* set master/slave audio interface */
2131 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2132 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2133 format &= ~(TWL4030_VIF_SLAVE_EN);
2134 break;
2135 case SND_SOC_DAIFMT_CBS_CFS:
2136 format |= TWL4030_VIF_SLAVE_EN;
2137 break;
2138 default:
2139 return -EINVAL;
2140 }
2141
2142 /* clock inversion */
2143 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2144 case SND_SOC_DAIFMT_IB_NF:
2145 format &= ~(TWL4030_VIF_FORMAT);
2146 break;
2147 case SND_SOC_DAIFMT_NB_IF:
2148 format |= TWL4030_VIF_FORMAT;
2149 break;
2150 default:
2151 return -EINVAL;
2152 }
2153
2154 if (format != old_format) {
2046f175
PU		 2155 if (twl4030->codec_powered) {
2156 /*
2157 * If the codec is powered, than we need to toggle the
2158 * codec power.
2159 */
2160 twl4030_codec_enable(codec, 0);
2161 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2162 twl4030_codec_enable(codec, 1);
2163 } else {
2164 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2165 }
7154b3e8
JS		 2166 }
2167
2168 return 0;
2169}
2170
68140443
LCM		 2171static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2172{
2173 struct snd_soc_codec *codec = dai->codec;
2174 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2175
2176 if (tristate)
2177 reg |= TWL4030_VIF_TRI_EN;
2178 else
2179 reg &= ~TWL4030_VIF_TRI_EN;
2180
2181 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2182}
2183
bbba9444 2184#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2185#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2186
10d9e3d9 2187static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2188 .startup = twl4030_startup,
2189 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2190 .hw_params = twl4030_hw_params,
2191 .set_sysclk = twl4030_set_dai_sysclk,
2192 .set_fmt = twl4030_set_dai_fmt,
68140443 2193 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2194};
2195
7154b3e8
JS		 2196static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2197 .startup = twl4030_voice_startup,
b7a755a8 2198 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2199 .hw_params = twl4030_voice_hw_params,
2200 .set_sysclk = twl4030_voice_set_dai_sysclk,
2201 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2202 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2203};
2204
2205struct snd_soc_dai twl4030_dai[] = {
2206{
cc17557e
SS		 2207 .name = "twl4030",
2208 .playback = {
b4852b79 2209 .stream_name = "HiFi Playback",
cc17557e 2210 .channels_min = 2,
8a1f936a 2211 .channels_max = 4,
31ad0f31 2212 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2213 .formats = TWL4030_FORMATS,},
2214 .capture = {
2215 .stream_name = "Capture",
2216 .channels_min = 2,
8a1f936a 2217 .channels_max = 4,
cc17557e
SS		 2218 .rates = TWL4030_RATES,
2219 .formats = TWL4030_FORMATS,},
10d9e3d9 2220 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2221},
2222{
2223 .name = "twl4030 Voice",
2224 .playback = {
b4852b79 2225 .stream_name = "Voice Playback",
7154b3e8
JS		 2226 .channels_min = 1,
2227 .channels_max = 1,
2228 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2229 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2230 .capture = {
2231 .stream_name = "Capture",
2232 .channels_min = 1,
2233 .channels_max = 2,
2234 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2235 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2236 .ops = &twl4030_dai_voice_ops,
2237},
cc17557e
SS		 2238};
2239EXPORT_SYMBOL_GPL(twl4030_dai);
2240
7a1fecf5 2241static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2242{
2243 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2244 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2245
2246 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2247
2248 return 0;
2249}
2250
7a1fecf5 2251static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2252{
2253 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2254 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2255
2256 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2257 return 0;
2258}
2259
7a1fecf5 2260static struct snd_soc_codec *twl4030_codec;
cc17557e 2261
7a1fecf5 2262static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2263{
7a1fecf5 2264 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5 2265 struct snd_soc_codec *codec;
7a1fecf5 2266 int ret;
cc17557e 2267
7a1fecf5 2268 BUG_ON(!twl4030_codec);
cc17557e 2269
7a1fecf5 2270 codec = twl4030_codec;
7a1fecf5 2271 socdev->card->codec = codec;
cc17557e 2272
ee4ccac7 2273 twl4030_init_chip(pdev);
9da28c7b 2274
cc17557e
SS		 2275 /* register pcms */
2276 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2277 if (ret < 0) {
7a1fecf5
PU		 2278 dev_err(&pdev->dev, "failed to create pcms\n");
2279 return ret;
cc17557e
SS		 2280 }
2281
3e8e1952
IM		 2282 snd_soc_add_controls(codec, twl4030_snd_controls,
2283 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2284 twl4030_add_widgets(codec);
2285
7a1fecf5 2286 return 0;
cc17557e
SS		 2287}
2288
7a1fecf5 2289static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2290{
2291 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2292 struct snd_soc_codec *codec = socdev->card->codec;
2293
a3a29b55
PU		 2294 /* Reset registers to their chip default before leaving */
2295 twl4030_reset_registers(codec);
7a1fecf5
PU		 2296 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2297 snd_soc_free_pcms(socdev);
2298 snd_soc_dapm_free(socdev);
7a1fecf5
PU		 2299
2300 return 0;
2301}
2302
2303static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2304{
2305 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2306 struct snd_soc_codec *codec;
7393958f 2307 struct twl4030_priv *twl4030;
7a1fecf5 2308 int ret;
cc17557e 2309
68d01955
PU		 2310 if (!pdata) {
2311 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2312 return -EINVAL;
2313 }
cc17557e 2314
7393958f
PU		 2315 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2316 if (twl4030 == NULL) {
7a1fecf5 2317 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2318 return -ENOMEM;
2319 }
2320
7a1fecf5 2321 codec = &twl4030->codec;
b2c812e2 2322 snd_soc_codec_set_drvdata(codec, twl4030);
7a1fecf5
PU		 2323 codec->dev = &pdev->dev;
2324 twl4030_dai[0].dev = &pdev->dev;
2325 twl4030_dai[1].dev = &pdev->dev;
2326
cc17557e
SS		 2327 mutex_init(&codec->mutex);
2328 INIT_LIST_HEAD(&codec->dapm_widgets);
2329 INIT_LIST_HEAD(&codec->dapm_paths);
2330
7a1fecf5
PU		 2331 codec->name = "twl4030";
2332 codec->owner = THIS_MODULE;
2333 codec->read = twl4030_read_reg_cache;
2334 codec->write = twl4030_write;
2335 codec->set_bias_level = twl4030_set_bias_level;
2046f175 2336 codec->idle_bias_off = 1;
7a1fecf5 2337 codec->dai = twl4030_dai;
fd63df22 2338 codec->num_dai = ARRAY_SIZE(twl4030_dai);
7a1fecf5
PU		 2339 codec->reg_cache_size = sizeof(twl4030_reg);
2340 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2341 GFP_KERNEL);
2342 if (codec->reg_cache == NULL) {
2343 ret = -ENOMEM;
2344 goto error_cache;
2345 }
2346
2347 platform_set_drvdata(pdev, twl4030);
2348 twl4030_codec = codec;
2349
2350 /* Set the defaults, and power up the codec */
68d01955 2351 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
b3f5a272 2352 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2353
2354 ret = snd_soc_register_codec(codec);
2355 if (ret != 0) {
2356 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2357 goto error_codec;
2358 }
2359
2360 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2361 if (ret != 0) {
2362 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2363 snd_soc_unregister_codec(codec);
2364 goto error_codec;
2365 }
cc17557e
SS		 2366
2367 return 0;
7a1fecf5
PU		 2368
2369error_codec:
cbd2db12 2370 twl4030_codec_enable(codec, 0);
7a1fecf5
PU		 2371 kfree(codec->reg_cache);
2372error_cache:
2373 kfree(twl4030);
2374 return ret;
cc17557e
SS		 2375}
2376
7a1fecf5 2377static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2378{
7a1fecf5 2379 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2380
cb67286d
PU		 2381 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2382 snd_soc_unregister_codec(&twl4030->codec);
2383 kfree(twl4030->codec.reg_cache);
7a1fecf5 2384 kfree(twl4030);
cc17557e 2385
7a1fecf5 2386 twl4030_codec = NULL;
cc17557e
SS		 2387 return 0;
2388}
2389
7a1fecf5
PU		 2390MODULE_ALIAS("platform:twl4030_codec_audio");
2391
2392static struct platform_driver twl4030_codec_driver = {
2393 .probe = twl4030_codec_probe,
2394 .remove = __devexit_p(twl4030_codec_remove),
2395 .driver = {
2396 .name = "twl4030_codec_audio",
2397 .owner = THIS_MODULE,
2398 },
cc17557e 2399};
cc17557e 2400
24e07db8 2401static int __init twl4030_modinit(void)
64089b84 2402{
7a1fecf5 2403 return platform_driver_register(&twl4030_codec_driver);
64089b84 2404}
24e07db8 2405module_init(twl4030_modinit);
64089b84
MB		 2406
2407static void __exit twl4030_exit(void)
2408{
7a1fecf5 2409 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2410}
2411module_exit(twl4030_exit);
2412
7a1fecf5
PU		 2413struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2414 .probe = twl4030_soc_probe,
2415 .remove = twl4030_soc_remove,
2416 .suspend = twl4030_soc_suspend,
2417 .resume = twl4030_soc_resume,
2418};
2419EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2420
cc17557e
SS		 2421MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2422MODULE_AUTHOR("Steve Sakoman");
2423MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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