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Merge branch 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
5e98a464
PU		 193/* Earpiece */
194static const char *twl4030_earpiece_texts[] =
2f423577 195 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 196
2f423577
PU		 197static const unsigned int twl4030_earpiece_values[] =
198 {0x0, 0x1, 0x2, 0x4};
199
cb1ace04 200static const struct soc_enum twl4030_earpiece_enum =
2f423577 201 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 202 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 203 twl4030_earpiece_texts,
204 twl4030_earpiece_values);
5e98a464
PU		 205
206static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 207SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 208
2a6f5c58
PU		 209/* PreDrive Left */
210static const char *twl4030_predrivel_texts[] =
2f423577
PU		 211 {"Off", "DACL1", "DACL2", "DACR2"};
212
213static const unsigned int twl4030_predrivel_values[] =
214 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 215
cb1ace04 216static const struct soc_enum twl4030_predrivel_enum =
2f423577 217 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 218 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 219 twl4030_predrivel_texts,
220 twl4030_predrivel_values);
2a6f5c58
PU		 221
222static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 223SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 224
225/* PreDrive Right */
226static const char *twl4030_predriver_texts[] =
2f423577 227 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 228
2f423577
PU		 229static const unsigned int twl4030_predriver_values[] =
230 {0x0, 0x1, 0x2, 0x4};
231
cb1ace04 232static const struct soc_enum twl4030_predriver_enum =
2f423577 233 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 234 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 235 twl4030_predriver_texts,
236 twl4030_predriver_values);
2a6f5c58
PU		 237
238static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 239SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 240
dfad21a2
PU		 241/* Headset Left */
242static const char *twl4030_hsol_texts[] =
243 {"Off", "DACL1", "DACL2"};
244
245static const struct soc_enum twl4030_hsol_enum =
246 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
247 ARRAY_SIZE(twl4030_hsol_texts),
248 twl4030_hsol_texts);
249
250static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
251SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
252
253/* Headset Right */
254static const char *twl4030_hsor_texts[] =
255 {"Off", "DACR1", "DACR2"};
256
257static const struct soc_enum twl4030_hsor_enum =
258 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
259 ARRAY_SIZE(twl4030_hsor_texts),
260 twl4030_hsor_texts);
261
262static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
263SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
264
5152d8c2
PU		 265/* Carkit Left */
266static const char *twl4030_carkitl_texts[] =
267 {"Off", "DACL1", "DACL2"};
268
269static const struct soc_enum twl4030_carkitl_enum =
270 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
271 ARRAY_SIZE(twl4030_carkitl_texts),
272 twl4030_carkitl_texts);
273
274static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
275SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
276
277/* Carkit Right */
278static const char *twl4030_carkitr_texts[] =
279 {"Off", "DACR1", "DACR2"};
280
281static const struct soc_enum twl4030_carkitr_enum =
282 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
283 ARRAY_SIZE(twl4030_carkitr_texts),
284 twl4030_carkitr_texts);
285
286static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
287SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
288
df339804
PU		 289/* Handsfree Left */
290static const char *twl4030_handsfreel_texts[] =
291 {"Voice", "DACL1", "DACL2", "DACR2"};
292
293static const struct soc_enum twl4030_handsfreel_enum =
294 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
295 ARRAY_SIZE(twl4030_handsfreel_texts),
296 twl4030_handsfreel_texts);
297
298static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
299SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
300
301/* Handsfree Right */
302static const char *twl4030_handsfreer_texts[] =
303 {"Voice", "DACR1", "DACR2", "DACL2"};
304
305static const struct soc_enum twl4030_handsfreer_enum =
306 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
307 ARRAY_SIZE(twl4030_handsfreer_texts),
308 twl4030_handsfreer_texts);
309
310static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
311SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
312
276c6222
PU		 313/* Left analog microphone selection */
314static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 315 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
316
317static const unsigned int twl4030_analoglmic_values[] =
318 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 319
cb1ace04 320static const struct soc_enum twl4030_analoglmic_enum =
2f423577 321 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 322 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 323 twl4030_analoglmic_texts,
324 twl4030_analoglmic_values);
276c6222
PU		 325
326static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 327SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 328
329/* Right analog microphone selection */
330static const char *twl4030_analogrmic_texts[] =
2f423577 331 {"Off", "Sub mic", "AUXR"};
276c6222 332
2f423577
PU		 333static const unsigned int twl4030_analogrmic_values[] =
334 {0x0, 0x1, 0x4};
335
cb1ace04 336static const struct soc_enum twl4030_analogrmic_enum =
2f423577 337 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 338 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 339 twl4030_analogrmic_texts,
340 twl4030_analogrmic_values);
276c6222
PU		 341
342static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 343SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 344
345/* TX1 L/R Analog/Digital microphone selection */
346static const char *twl4030_micpathtx1_texts[] =
347 {"Analog", "Digimic0"};
348
349static const struct soc_enum twl4030_micpathtx1_enum =
350 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
351 ARRAY_SIZE(twl4030_micpathtx1_texts),
352 twl4030_micpathtx1_texts);
353
354static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
355SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
356
357/* TX2 L/R Analog/Digital microphone selection */
358static const char *twl4030_micpathtx2_texts[] =
359 {"Analog", "Digimic1"};
360
361static const struct soc_enum twl4030_micpathtx2_enum =
362 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
363 ARRAY_SIZE(twl4030_micpathtx2_texts),
364 twl4030_micpathtx2_texts);
365
366static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
367SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
368
276c6222
PU		 369static int micpath_event(struct snd_soc_dapm_widget *w,
370 struct snd_kcontrol *kcontrol, int event)
371{
372 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
373 unsigned char adcmicsel, micbias_ctl;
374
375 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
376 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
377 /* Prepare the bits for the given TX path:
378 * shift_l == 0: TX1 microphone path
379 * shift_l == 2: TX2 microphone path */
380 if (e->shift_l) {
381 /* TX2 microphone path */
382 if (adcmicsel & TWL4030_TX2IN_SEL)
383 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
384 else
385 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
386 } else {
387 /* TX1 microphone path */
388 if (adcmicsel & TWL4030_TX1IN_SEL)
389 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
390 else
391 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
392 }
393
394 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
395
396 return 0;
397}
398
49d92c7d
SM		 399static int handsfree_event(struct snd_soc_dapm_widget *w,
400 struct snd_kcontrol *kcontrol, int event)
401{
402 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
403 unsigned char hs_ctl;
404
405 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
406
407 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
408 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
409 twl4030_write(w->codec, e->reg, hs_ctl);
410 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
411 twl4030_write(w->codec, e->reg, hs_ctl);
412 hs_ctl |= TWL4030_HF_CTL_HB_EN;
413 twl4030_write(w->codec, e->reg, hs_ctl);
414 } else {
415 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
416 | TWL4030_HF_CTL_HB_EN);
417 twl4030_write(w->codec, e->reg, hs_ctl);
418 }
419
420 return 0;
421}
422
b0bd53a7
PU		 423/*
424 * Some of the gain controls in TWL (mostly those which are associated with
425 * the outputs) are implemented in an interesting way:
426 * 0x0 : Power down (mute)
427 * 0x1 : 6dB
428 * 0x2 : 0 dB
429 * 0x3 : -6 dB
430 * Inverting not going to help with these.
431 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
432 */
433#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
434 xinvert, tlv_array) \
435{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
436 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
437 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
438 .tlv.p = (tlv_array), \
439 .info = snd_soc_info_volsw, \
440 .get = snd_soc_get_volsw_twl4030, \
441 .put = snd_soc_put_volsw_twl4030, \
442 .private_value = (unsigned long)&(struct soc_mixer_control) \
443 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
444 .max = xmax, .invert = xinvert} }
445#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
446 xinvert, tlv_array) \
447{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
448 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
449 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
450 .tlv.p = (tlv_array), \
451 .info = snd_soc_info_volsw_2r, \
452 .get = snd_soc_get_volsw_r2_twl4030,\
453 .put = snd_soc_put_volsw_r2_twl4030, \
454 .private_value = (unsigned long)&(struct soc_mixer_control) \
455 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 456 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 457#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
458 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
459 xinvert, tlv_array)
460
461static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct soc_mixer_control *mc =
465 (struct soc_mixer_control *)kcontrol->private_value;
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467 unsigned int reg = mc->reg;
468 unsigned int shift = mc->shift;
469 unsigned int rshift = mc->rshift;
470 int max = mc->max;
471 int mask = (1 << fls(max)) - 1;
472
473 ucontrol->value.integer.value[0] =
474 (snd_soc_read(codec, reg) >> shift) & mask;
475 if (ucontrol->value.integer.value[0])
476 ucontrol->value.integer.value[0] =
477 max + 1 - ucontrol->value.integer.value[0];
478
479 if (shift != rshift) {
480 ucontrol->value.integer.value[1] =
481 (snd_soc_read(codec, reg) >> rshift) & mask;
482 if (ucontrol->value.integer.value[1])
483 ucontrol->value.integer.value[1] =
484 max + 1 - ucontrol->value.integer.value[1];
485 }
486
487 return 0;
488}
489
490static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
491 struct snd_ctl_elem_value *ucontrol)
492{
493 struct soc_mixer_control *mc =
494 (struct soc_mixer_control *)kcontrol->private_value;
495 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
496 unsigned int reg = mc->reg;
497 unsigned int shift = mc->shift;
498 unsigned int rshift = mc->rshift;
499 int max = mc->max;
500 int mask = (1 << fls(max)) - 1;
501 unsigned short val, val2, val_mask;
502
503 val = (ucontrol->value.integer.value[0] & mask);
504
505 val_mask = mask << shift;
506 if (val)
507 val = max + 1 - val;
508 val = val << shift;
509 if (shift != rshift) {
510 val2 = (ucontrol->value.integer.value[1] & mask);
511 val_mask |= mask << rshift;
512 if (val2)
513 val2 = max + 1 - val2;
514 val |= val2 << rshift;
515 }
516 return snd_soc_update_bits(codec, reg, val_mask, val);
517}
518
519static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
520 struct snd_ctl_elem_value *ucontrol)
521{
522 struct soc_mixer_control *mc =
523 (struct soc_mixer_control *)kcontrol->private_value;
524 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
525 unsigned int reg = mc->reg;
526 unsigned int reg2 = mc->rreg;
527 unsigned int shift = mc->shift;
528 int max = mc->max;
529 int mask = (1<<fls(max))-1;
530
531 ucontrol->value.integer.value[0] =
532 (snd_soc_read(codec, reg) >> shift) & mask;
533 ucontrol->value.integer.value[1] =
534 (snd_soc_read(codec, reg2) >> shift) & mask;
535
536 if (ucontrol->value.integer.value[0])
537 ucontrol->value.integer.value[0] =
538 max + 1 - ucontrol->value.integer.value[0];
539 if (ucontrol->value.integer.value[1])
540 ucontrol->value.integer.value[1] =
541 max + 1 - ucontrol->value.integer.value[1];
542
543 return 0;
544}
545
546static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
548{
549 struct soc_mixer_control *mc =
550 (struct soc_mixer_control *)kcontrol->private_value;
551 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
552 unsigned int reg = mc->reg;
553 unsigned int reg2 = mc->rreg;
554 unsigned int shift = mc->shift;
555 int max = mc->max;
556 int mask = (1 << fls(max)) - 1;
557 int err;
558 unsigned short val, val2, val_mask;
559
560 val_mask = mask << shift;
561 val = (ucontrol->value.integer.value[0] & mask);
562 val2 = (ucontrol->value.integer.value[1] & mask);
563
564 if (val)
565 val = max + 1 - val;
566 if (val2)
567 val2 = max + 1 - val2;
568
569 val = val << shift;
570 val2 = val2 << shift;
571
572 err = snd_soc_update_bits(codec, reg, val_mask, val);
573 if (err < 0)
574 return err;
575
576 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
577 return err;
578}
579
c10b82cf
PU		 580/*
581 * FGAIN volume control:
582 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
583 */
d889a72c 584static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 585
0d33ea0b
PU		 586/*
587 * CGAIN volume control:
588 * 0 dB to 12 dB in 6 dB steps
589 * value 2 and 3 means 12 dB
590 */
d889a72c
PU		 591static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
592
593/*
594 * Analog playback gain
595 * -24 dB to 12 dB in 2 dB steps
596 */
597static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 598
4290239c
PU		 599/*
600 * Gain controls tied to outputs
601 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
602 */
603static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
604
381a22b5
PU		 605/*
606 * Capture gain after the ADCs
607 * from 0 dB to 31 dB in 1 dB steps
608 */
609static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
610
5920b453
GI		 611/*
612 * Gain control for input amplifiers
613 * 0 dB to 30 dB in 6 dB steps
614 */
615static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
616
cc17557e 617static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 618 /* Common playback gain controls */
619 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
620 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
621 0, 0x3f, 0, digital_fine_tlv),
622 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
623 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
624 0, 0x3f, 0, digital_fine_tlv),
625
626 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
627 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
628 6, 0x2, 0, digital_coarse_tlv),
629 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
630 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
631 6, 0x2, 0, digital_coarse_tlv),
632
633 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
634 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
635 3, 0x12, 1, analog_tlv),
636 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
637 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
638 3, 0x12, 1, analog_tlv),
44c55870
PU		 639 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
640 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
641 1, 1, 0),
642 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
643 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
644 1, 1, 0),
381a22b5 645
4290239c
PU		 646 /* Separate output gain controls */
647 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
648 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
649 4, 3, 0, output_tvl),
650
651 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
652 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
653
654 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
655 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
656 4, 3, 0, output_tvl),
657
658 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
659 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
660
381a22b5 661 /* Common capture gain controls */
276c6222 662 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 663 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
664 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 665 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
666 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
667 0, 0x1f, 0, digital_capture_tlv),
5920b453 668
276c6222 669 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 670 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 671};
672
673/* add non dapm controls */
674static int twl4030_add_controls(struct snd_soc_codec *codec)
675{
676 int err, i;
677
678 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
679 err = snd_ctl_add(codec->card,
680 snd_soc_cnew(&twl4030_snd_controls[i],
681 codec, NULL));
682 if (err < 0)
683 return err;
684 }
685
686 return 0;
687}
688
689static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 690 /* Left channel inputs */
691 SND_SOC_DAPM_INPUT("MAINMIC"),
692 SND_SOC_DAPM_INPUT("HSMIC"),
693 SND_SOC_DAPM_INPUT("AUXL"),
694 SND_SOC_DAPM_INPUT("CARKITMIC"),
695 /* Right channel inputs */
696 SND_SOC_DAPM_INPUT("SUBMIC"),
697 SND_SOC_DAPM_INPUT("AUXR"),
698 /* Digital microphones (Stereo) */
699 SND_SOC_DAPM_INPUT("DIGIMIC0"),
700 SND_SOC_DAPM_INPUT("DIGIMIC1"),
701
702 /* Outputs */
cc17557e
SS		 703 SND_SOC_DAPM_OUTPUT("OUTL"),
704 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 705 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 706 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
707 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 708 SND_SOC_DAPM_OUTPUT("HSOL"),
709 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 710 SND_SOC_DAPM_OUTPUT("CARKITL"),
711 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 712 SND_SOC_DAPM_OUTPUT("HFL"),
713 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 714
53b5047d 715 /* DACs */
1e5fa31f 716 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
53b5047d 717 TWL4030_REG_AVDAC_CTL, 0, 0),
1e5fa31f 718 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
53b5047d 719 TWL4030_REG_AVDAC_CTL, 1, 0),
1e5fa31f 720 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
53b5047d 721 TWL4030_REG_AVDAC_CTL, 2, 0),
1e5fa31f 722 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
53b5047d 723 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 724
44c55870
PU		 725 /* Analog PGAs */
726 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
727 0, 0, NULL, 0),
728 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
729 0, 0, NULL, 0),
730 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
731 0, 0, NULL, 0),
732 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
733 0, 0, NULL, 0),
734
5e98a464
PU		 735 /* Output MUX controls */
736 /* Earpiece */
2f423577
PU		 737 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
738 &twl4030_dapm_earpiece_control),
2a6f5c58 739 /* PreDrivL/R */
2f423577
PU		 740 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
741 &twl4030_dapm_predrivel_control),
742 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
743 &twl4030_dapm_predriver_control),
dfad21a2
PU		 744 /* HeadsetL/R */
745 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
746 &twl4030_dapm_hsol_control),
747 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
748 &twl4030_dapm_hsor_control),
5152d8c2
PU		 749 /* CarkitL/R */
750 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
751 &twl4030_dapm_carkitl_control),
752 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
753 &twl4030_dapm_carkitr_control),
df339804 754 /* HandsfreeL/R */
49d92c7d
SM		 755 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
756 &twl4030_dapm_handsfreel_control, handsfree_event,
757 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
758 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
759 &twl4030_dapm_handsfreer_control, handsfree_event,
760 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 761
276c6222
PU		 762 /* Introducing four virtual ADC, since TWL4030 have four channel for
763 capture */
764 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
765 SND_SOC_NOPM, 0, 0),
766 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
767 SND_SOC_NOPM, 0, 0),
768 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
769 SND_SOC_NOPM, 0, 0),
770 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
771 SND_SOC_NOPM, 0, 0),
772
773 /* Analog/Digital mic path selection.
774 TX1 Left/Right: either analog Left/Right or Digimic0
775 TX2 Left/Right: either analog Left/Right or Digimic1 */
776 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
777 &twl4030_dapm_micpathtx1_control, micpath_event,
778 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
779 SND_SOC_DAPM_POST_REG),
780 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
781 &twl4030_dapm_micpathtx2_control, micpath_event,
782 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
783 SND_SOC_DAPM_POST_REG),
784
785 /* Analog input muxes with power switch for the physical ADCL/R */
2f423577
PU		 786 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
787 TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
788 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
789 TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
276c6222
PU		 790
791 SND_SOC_DAPM_PGA("Analog Left Amplifier",
792 TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
793 SND_SOC_DAPM_PGA("Analog Right Amplifier",
794 TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
795
796 SND_SOC_DAPM_PGA("Digimic0 Enable",
797 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
798 SND_SOC_DAPM_PGA("Digimic1 Enable",
799 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
800
801 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
802 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
803 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
cc17557e
SS		 804};
805
806static const struct snd_soc_dapm_route intercon[] = {
1e5fa31f
PU		 807 {"ARXL1_APGA", NULL, "DAC Left1"},
808 {"ARXR1_APGA", NULL, "DAC Right1"},
809 {"ARXL2_APGA", NULL, "DAC Left2"},
810 {"ARXR2_APGA", NULL, "DAC Right2"},
44c55870 811
5e98a464
PU		 812 /* Internal playback routings */
813 /* Earpiece */
814 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
815 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
816 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 817 /* PreDrivL */
818 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
819 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
820 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
821 /* PreDrivR */
822 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
823 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
824 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 825 /* HeadsetL */
826 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
827 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
828 /* HeadsetR */
829 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
830 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 831 /* CarkitL */
832 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
833 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
834 /* CarkitR */
835 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
836 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 837 /* HandsfreeL */
838 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
839 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
840 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
841 /* HandsfreeR */
842 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
843 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
844 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 845
cc17557e 846 /* outputs */
44c55870
PU		 847 {"OUTL", NULL, "ARXL2_APGA"},
848 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 849 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 850 {"PREDRIVEL", NULL, "PredriveL Mux"},
851 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 852 {"HSOL", NULL, "HeadsetL Mux"},
853 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 854 {"CARKITL", NULL, "CarkitL Mux"},
855 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 856 {"HFL", NULL, "HandsfreeL Mux"},
857 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 858
276c6222
PU		 859 /* Capture path */
860 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
861 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
862 {"Analog Left Capture Route", "AUXL", "AUXL"},
863 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
864
865 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
866 {"Analog Right Capture Route", "AUXR", "AUXR"},
867
868 {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
869 {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
870
871 {"Digimic0 Enable", NULL, "DIGIMIC0"},
872 {"Digimic1 Enable", NULL, "DIGIMIC1"},
873
874 /* TX1 Left capture path */
875 {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
876 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
877 /* TX1 Right capture path */
878 {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
879 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
880 /* TX2 Left capture path */
881 {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
882 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
883 /* TX2 Right capture path */
884 {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
885 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
886
887 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
888 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
889 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
890 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
891
cc17557e
SS		 892};
893
894static int twl4030_add_widgets(struct snd_soc_codec *codec)
895{
896 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
897 ARRAY_SIZE(twl4030_dapm_widgets));
898
899 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
900
901 snd_soc_dapm_new_widgets(codec);
902 return 0;
903}
904
905static void twl4030_power_up(struct snd_soc_codec *codec)
906{
ca4513fe 907 u8 anamicl, regmisc1, byte, popn;
cc17557e
SS		 908 int i = 0;
909
910 /* set CODECPDZ to turn on codec */
911 twl4030_set_codecpdz(codec);
912
913 /* initiate offset cancellation */
914 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
915 twl4030_write(codec, TWL4030_REG_ANAMICL,
916 anamicl | TWL4030_CNCL_OFFSET_START);
917
276c6222 918
cc17557e
SS		 919 /* wait for offset cancellation to complete */
920 do {
921 /* this takes a little while, so don't slam i2c */
922 udelay(2000);
923 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
924 TWL4030_REG_ANAMICL);
925 } while ((i++ < 100) &&
926 ((byte & TWL4030_CNCL_OFFSET_START) ==
927 TWL4030_CNCL_OFFSET_START));
928
929 /* anti-pop when changing analog gain */
930 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
931 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
932 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
933
934 /* toggle CODECPDZ as per TRM */
935 twl4030_clear_codecpdz(codec);
936 twl4030_set_codecpdz(codec);
937
938 /* program anti-pop with bias ramp delay */
939 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
940 popn &= TWL4030_RAMP_DELAY;
941 popn |= TWL4030_RAMP_DELAY_645MS;
942 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
943 popn |= TWL4030_VMID_EN;
944 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
945
cc17557e
SS		 946 /* enable anti-pop ramp */
947 popn |= TWL4030_RAMP_EN;
948 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
949}
950
951static void twl4030_power_down(struct snd_soc_codec *codec)
952{
ca4513fe 953 u8 popn;
cc17557e
SS		 954
955 /* disable anti-pop ramp */
956 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
957 popn &= ~TWL4030_RAMP_EN;
958 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
959
cc17557e
SS		 960 /* disable bias out */
961 popn &= ~TWL4030_VMID_EN;
962 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
963
964 /* power down */
965 twl4030_clear_codecpdz(codec);
966}
967
968static int twl4030_set_bias_level(struct snd_soc_codec *codec,
969 enum snd_soc_bias_level level)
970{
971 switch (level) {
972 case SND_SOC_BIAS_ON:
973 twl4030_power_up(codec);
974 break;
975 case SND_SOC_BIAS_PREPARE:
976 /* TODO: develop a twl4030_prepare function */
977 break;
978 case SND_SOC_BIAS_STANDBY:
979 /* TODO: develop a twl4030_standby function */
980 twl4030_power_down(codec);
981 break;
982 case SND_SOC_BIAS_OFF:
983 twl4030_power_down(codec);
984 break;
985 }
986 codec->bias_level = level;
987
988 return 0;
989}
990
991static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 992 struct snd_pcm_hw_params *params,
993 struct snd_soc_dai *dai)
cc17557e
SS		 994{
995 struct snd_soc_pcm_runtime *rtd = substream->private_data;
996 struct snd_soc_device *socdev = rtd->socdev;
997 struct snd_soc_codec *codec = socdev->codec;
998 u8 mode, old_mode, format, old_format;
999
1000
1001 /* bit rate */
1002 old_mode = twl4030_read_reg_cache(codec,
1003 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1004 mode = old_mode & ~TWL4030_APLL_RATE;
1005
1006 switch (params_rate(params)) {
1007 case 8000:
1008 mode |= TWL4030_APLL_RATE_8000;
1009 break;
1010 case 11025:
1011 mode |= TWL4030_APLL_RATE_11025;
1012 break;
1013 case 12000:
1014 mode |= TWL4030_APLL_RATE_12000;
1015 break;
1016 case 16000:
1017 mode |= TWL4030_APLL_RATE_16000;
1018 break;
1019 case 22050:
1020 mode |= TWL4030_APLL_RATE_22050;
1021 break;
1022 case 24000:
1023 mode |= TWL4030_APLL_RATE_24000;
1024 break;
1025 case 32000:
1026 mode |= TWL4030_APLL_RATE_32000;
1027 break;
1028 case 44100:
1029 mode |= TWL4030_APLL_RATE_44100;
1030 break;
1031 case 48000:
1032 mode |= TWL4030_APLL_RATE_48000;
1033 break;
1034 default:
1035 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1036 params_rate(params));
1037 return -EINVAL;
1038 }
1039
1040 if (mode != old_mode) {
1041 /* change rate and set CODECPDZ */
1042 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1043 twl4030_set_codecpdz(codec);
1044 }
1045
1046 /* sample size */
1047 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1048 format = old_format;
1049 format &= ~TWL4030_DATA_WIDTH;
1050 switch (params_format(params)) {
1051 case SNDRV_PCM_FORMAT_S16_LE:
1052 format |= TWL4030_DATA_WIDTH_16S_16W;
1053 break;
1054 case SNDRV_PCM_FORMAT_S24_LE:
1055 format |= TWL4030_DATA_WIDTH_32S_24W;
1056 break;
1057 default:
1058 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1059 params_format(params));
1060 return -EINVAL;
1061 }
1062
1063 if (format != old_format) {
1064
1065 /* clear CODECPDZ before changing format (codec requirement) */
1066 twl4030_clear_codecpdz(codec);
1067
1068 /* change format */
1069 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1070
1071 /* set CODECPDZ afterwards */
1072 twl4030_set_codecpdz(codec);
1073 }
1074 return 0;
1075}
1076
1077static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1078 int clk_id, unsigned int freq, int dir)
1079{
1080 struct snd_soc_codec *codec = codec_dai->codec;
1081 u8 infreq;
1082
1083 switch (freq) {
1084 case 19200000:
1085 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1086 break;
1087 case 26000000:
1088 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1089 break;
1090 case 38400000:
1091 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1092 break;
1093 default:
1094 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1095 freq);
1096 return -EINVAL;
1097 }
1098
1099 infreq |= TWL4030_APLL_EN;
1100 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1101
1102 return 0;
1103}
1104
1105static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1106 unsigned int fmt)
1107{
1108 struct snd_soc_codec *codec = codec_dai->codec;
1109 u8 old_format, format;
1110
1111 /* get format */
1112 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1113 format = old_format;
1114
1115 /* set master/slave audio interface */
1116 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1117 case SND_SOC_DAIFMT_CBM_CFM:
1118 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1119 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1120 break;
1121 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1122 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1123 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 /* interface format */
1130 format &= ~TWL4030_AIF_FORMAT;
1131 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1132 case SND_SOC_DAIFMT_I2S:
1133 format |= TWL4030_AIF_FORMAT_CODEC;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138
1139 if (format != old_format) {
1140
1141 /* clear CODECPDZ before changing format (codec requirement) */
1142 twl4030_clear_codecpdz(codec);
1143
1144 /* change format */
1145 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1146
1147 /* set CODECPDZ afterwards */
1148 twl4030_set_codecpdz(codec);
1149 }
1150
1151 return 0;
1152}
1153
bbba9444 1154#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1155#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1156
1157struct snd_soc_dai twl4030_dai = {
1158 .name = "twl4030",
1159 .playback = {
1160 .stream_name = "Playback",
1161 .channels_min = 2,
1162 .channels_max = 2,
1163 .rates = TWL4030_RATES,
1164 .formats = TWL4030_FORMATS,},
1165 .capture = {
1166 .stream_name = "Capture",
1167 .channels_min = 2,
1168 .channels_max = 2,
1169 .rates = TWL4030_RATES,
1170 .formats = TWL4030_FORMATS,},
1171 .ops = {
1172 .hw_params = twl4030_hw_params,
cc17557e
SS		 1173 .set_sysclk = twl4030_set_dai_sysclk,
1174 .set_fmt = twl4030_set_dai_fmt,
1175 }
1176};
1177EXPORT_SYMBOL_GPL(twl4030_dai);
1178
1179static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1180{
1181 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1182 struct snd_soc_codec *codec = socdev->codec;
1183
1184 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1185
1186 return 0;
1187}
1188
1189static int twl4030_resume(struct platform_device *pdev)
1190{
1191 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1192 struct snd_soc_codec *codec = socdev->codec;
1193
1194 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1195 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1196 return 0;
1197}
1198
1199/*
1200 * initialize the driver
1201 * register the mixer and dsp interfaces with the kernel
1202 */
1203
1204static int twl4030_init(struct snd_soc_device *socdev)
1205{
1206 struct snd_soc_codec *codec = socdev->codec;
1207 int ret = 0;
1208
1209 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1210
1211 codec->name = "twl4030";
1212 codec->owner = THIS_MODULE;
1213 codec->read = twl4030_read_reg_cache;
1214 codec->write = twl4030_write;
1215 codec->set_bias_level = twl4030_set_bias_level;
1216 codec->dai = &twl4030_dai;
1217 codec->num_dai = 1;
1218 codec->reg_cache_size = sizeof(twl4030_reg);
1219 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1220 GFP_KERNEL);
1221 if (codec->reg_cache == NULL)
1222 return -ENOMEM;
1223
1224 /* register pcms */
1225 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1226 if (ret < 0) {
1227 printk(KERN_ERR "twl4030: failed to create pcms\n");
1228 goto pcm_err;
1229 }
1230
1231 twl4030_init_chip(codec);
1232
1233 /* power on device */
1234 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1235
1236 twl4030_add_controls(codec);
1237 twl4030_add_widgets(codec);
1238
968a6025 1239 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1240 if (ret < 0) {
1241 printk(KERN_ERR "twl4030: failed to register card\n");
1242 goto card_err;
1243 }
1244
1245 return ret;
1246
1247card_err:
1248 snd_soc_free_pcms(socdev);
1249 snd_soc_dapm_free(socdev);
1250pcm_err:
1251 kfree(codec->reg_cache);
1252 return ret;
1253}
1254
1255static struct snd_soc_device *twl4030_socdev;
1256
1257static int twl4030_probe(struct platform_device *pdev)
1258{
1259 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1260 struct snd_soc_codec *codec;
1261
1262 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1263 if (codec == NULL)
1264 return -ENOMEM;
1265
1266 socdev->codec = codec;
1267 mutex_init(&codec->mutex);
1268 INIT_LIST_HEAD(&codec->dapm_widgets);
1269 INIT_LIST_HEAD(&codec->dapm_paths);
1270
1271 twl4030_socdev = socdev;
1272 twl4030_init(socdev);
1273
1274 return 0;
1275}
1276
1277static int twl4030_remove(struct platform_device *pdev)
1278{
1279 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1280 struct snd_soc_codec *codec = socdev->codec;
1281
1282 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
c6d1662b
PU		 1283 snd_soc_free_pcms(socdev);
1284 snd_soc_dapm_free(socdev);
cc17557e
SS		 1285 kfree(codec);
1286
1287 return 0;
1288}
1289
1290struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1291 .probe = twl4030_probe,
1292 .remove = twl4030_remove,
1293 .suspend = twl4030_suspend,
1294 .resume = twl4030_resume,
1295};
1296EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1297
24e07db8 1298static int __init twl4030_modinit(void)
64089b84
MB		 1299{
1300 return snd_soc_register_dai(&twl4030_dai);
1301}
24e07db8 1302module_init(twl4030_modinit);
64089b84
MB		 1303
1304static void __exit twl4030_exit(void)
1305{
1306 snd_soc_unregister_dai(&twl4030_dai);
1307}
1308module_exit(twl4030_exit);
1309
cc17557e
SS		 1310MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1311MODULE_AUTHOR("Steve Sakoman");
1312MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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