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mfd: Clarify twl4030 return value for read and write
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
7a1fecf5
PU		 123 struct snd_soc_codec codec;
124
7393958f 125 unsigned int codec_powered;
2845fa13 126 unsigned int apll_enabled;
7220b9f4
PU		 127
128 struct snd_pcm_substream *master_substream;
129 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 130
131 unsigned int configured;
132 unsigned int rate;
133 unsigned int sample_bits;
134 unsigned int channels;
6943c92e
PU		 135
136 unsigned int sysclk;
137
138 /* Headset output state handling */
139 unsigned int hsl_enabled;
140 unsigned int hsr_enabled;
7393958f
PU		 141};
142
cc17557e
SS		 143/*
144 * read twl4030 register cache
145 */
146static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
147 unsigned int reg)
148{
d08664fd 149 u8 *cache = codec->reg_cache;
cc17557e 150
91432e97
IM		 151 if (reg >= TWL4030_CACHEREGNUM)
152 return -EIO;
153
cc17557e
SS		 154 return cache[reg];
155}
156
157/*
158 * write twl4030 register cache
159 */
160static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
161 u8 reg, u8 value)
162{
163 u8 *cache = codec->reg_cache;
164
165 if (reg >= TWL4030_CACHEREGNUM)
166 return;
167 cache[reg] = value;
168}
169
170/*
171 * write to the twl4030 register space
172 */
173static int twl4030_write(struct snd_soc_codec *codec,
174 unsigned int reg, unsigned int value)
175{
176 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 177 if (likely(reg < TWL4030_REG_SW_SHADOW))
178 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
179 reg);
180 else
181 return 0;
cc17557e
SS		 182}
183
db04e2c5 184static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 185{
7393958f 186 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 187 int mode;
cc17557e 188
7393958f
PU		 189 if (enable == twl4030->codec_powered)
190 return;
191
db04e2c5 192 if (enable)
7a1fecf5 193 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 194 else
7a1fecf5 195 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 196
7a1fecf5
PU		 197 if (mode >= 0) {
198 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
199 twl4030->codec_powered = enable;
200 }
cc17557e
SS		 201
202 /* REVISIT: this delay is present in TI sample drivers */
203 /* but there seems to be no TRM requirement for it */
204 udelay(10);
205}
206
207static void twl4030_init_chip(struct snd_soc_codec *codec)
208{
16a30fbb 209 u8 *cache = codec->reg_cache;
cc17557e
SS		 210 int i;
211
212 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 213 twl4030_codec_enable(codec, 0);
cc17557e
SS		 214
215 /* set all audio section registers to reasonable defaults */
216 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955
PU		 217 if (i != TWL4030_REG_APLL_CTL)
218 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 219
220}
221
2845fa13 222static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
7393958f
PU		 223{
224 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 225 int status;
7393958f 226
2845fa13 227 if (enable == twl4030->apll_enabled)
7393958f
PU		 228 return;
229
2845fa13 230 if (enable)
7393958f 231 /* Enable PLL */
7a1fecf5 232 status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
2845fa13
PU		 233 else
234 /* Disable PLL */
235 status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
7a1fecf5
PU		 236
237 if (status >= 0)
238 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
7393958f 239
2845fa13 240 twl4030->apll_enabled = enable;
7393958f
PU		 241}
242
006f367e
PU		 243static void twl4030_power_up(struct snd_soc_codec *codec)
244{
7393958f 245 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 246 u8 anamicl, regmisc1, byte;
247 int i = 0;
248
7393958f
PU		 249 if (twl4030->codec_powered)
250 return;
251
006f367e
PU		 252 /* set CODECPDZ to turn on codec */
253 twl4030_codec_enable(codec, 1);
254
255 /* initiate offset cancellation */
256 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
257 twl4030_write(codec, TWL4030_REG_ANAMICL,
258 anamicl | TWL4030_CNCL_OFFSET_START);
259
260 /* wait for offset cancellation to complete */
261 do {
262 /* this takes a little while, so don't slam i2c */
263 udelay(2000);
264 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
265 TWL4030_REG_ANAMICL);
266 } while ((i++ < 100) &&
267 ((byte & TWL4030_CNCL_OFFSET_START) ==
268 TWL4030_CNCL_OFFSET_START));
269
270 /* Make sure that the reg_cache has the same value as the HW */
271 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
272
273 /* anti-pop when changing analog gain */
274 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
275 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
276 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
277
278 /* toggle CODECPDZ as per TRM */
279 twl4030_codec_enable(codec, 0);
280 twl4030_codec_enable(codec, 1);
281}
282
7393958f
PU		 283/*
284 * Unconditional power down
285 */
006f367e
PU		 286static void twl4030_power_down(struct snd_soc_codec *codec)
287{
288 /* power down */
289 twl4030_codec_enable(codec, 0);
290}
291
5e98a464 292/* Earpiece */
1a787e7a
JS		 293static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
294 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
295 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
296 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
297 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
298};
5e98a464 299
2a6f5c58 300/* PreDrive Left */
1a787e7a
JS		 301static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
302 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
303 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
304 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
305 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
306};
2a6f5c58
PU		 307
308/* PreDrive Right */
1a787e7a
JS		 309static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
310 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
311 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
312 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
313 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
314};
2a6f5c58 315
dfad21a2 316/* Headset Left */
1a787e7a
JS		 317static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
318 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
319 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
320 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
321};
dfad21a2
PU		 322
323/* Headset Right */
1a787e7a
JS		 324static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
326 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
327 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
328};
dfad21a2 329
5152d8c2 330/* Carkit Left */
1a787e7a
JS		 331static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
332 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
333 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
334 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
335};
5152d8c2
PU		 336
337/* Carkit Right */
1a787e7a
JS		 338static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
339 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
341 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
342};
5152d8c2 343
df339804
PU		 344/* Handsfree Left */
345static const char *twl4030_handsfreel_texts[] =
1a787e7a 346 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 347
348static const struct soc_enum twl4030_handsfreel_enum =
349 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
350 ARRAY_SIZE(twl4030_handsfreel_texts),
351 twl4030_handsfreel_texts);
352
353static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
354SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
355
0f89bdca
PU		 356/* Handsfree Left virtual mute */
357static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
358 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
359
df339804
PU		 360/* Handsfree Right */
361static const char *twl4030_handsfreer_texts[] =
1a787e7a 362 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 363
364static const struct soc_enum twl4030_handsfreer_enum =
365 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
366 ARRAY_SIZE(twl4030_handsfreer_texts),
367 twl4030_handsfreer_texts);
368
369static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
370SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
371
0f89bdca
PU		 372/* Handsfree Right virtual mute */
373static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
374 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
375
376f7839
PU		 376/* Vibra */
377/* Vibra audio path selection */
378static const char *twl4030_vibra_texts[] =
379 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
380
381static const struct soc_enum twl4030_vibra_enum =
382 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
383 ARRAY_SIZE(twl4030_vibra_texts),
384 twl4030_vibra_texts);
385
386static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
387SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
388
389/* Vibra path selection: local vibrator (PWM) or audio driven */
390static const char *twl4030_vibrapath_texts[] =
391 {"Local vibrator", "Audio"};
392
393static const struct soc_enum twl4030_vibrapath_enum =
394 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
395 ARRAY_SIZE(twl4030_vibrapath_texts),
396 twl4030_vibrapath_texts);
397
398static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
399SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
400
276c6222 401/* Left analog microphone selection */
97b8096d 402static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 403 SOC_DAPM_SINGLE("Main Mic Capture Switch",
404 TWL4030_REG_ANAMICL, 0, 1, 0),
405 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
406 TWL4030_REG_ANAMICL, 1, 1, 0),
407 SOC_DAPM_SINGLE("AUXL Capture Switch",
408 TWL4030_REG_ANAMICL, 2, 1, 0),
409 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
410 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 411};
276c6222
PU		 412
413/* Right analog microphone selection */
97b8096d 414static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 415 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
416 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 417};
276c6222
PU		 418
419/* TX1 L/R Analog/Digital microphone selection */
420static const char *twl4030_micpathtx1_texts[] =
421 {"Analog", "Digimic0"};
422
423static const struct soc_enum twl4030_micpathtx1_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
425 ARRAY_SIZE(twl4030_micpathtx1_texts),
426 twl4030_micpathtx1_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
429SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
430
431/* TX2 L/R Analog/Digital microphone selection */
432static const char *twl4030_micpathtx2_texts[] =
433 {"Analog", "Digimic1"};
434
435static const struct soc_enum twl4030_micpathtx2_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
437 ARRAY_SIZE(twl4030_micpathtx2_texts),
438 twl4030_micpathtx2_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
441SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
442
7393958f
PU		 443/* Analog bypass for AudioR1 */
444static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
445 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
446
447/* Analog bypass for AudioL1 */
448static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
449 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
450
451/* Analog bypass for AudioR2 */
452static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
453 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
454
455/* Analog bypass for AudioL2 */
456static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
457 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
458
fcd274a3
LCM		 459/* Analog bypass for Voice */
460static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
461 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
462
6bab83fd
PU		 463/* Digital bypass gain, 0 mutes the bypass */
464static const unsigned int twl4030_dapm_dbypass_tlv[] = {
465 TLV_DB_RANGE_HEAD(2),
466 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
467 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
468};
469
470/* Digital bypass left (TX1L -> RX2L) */
471static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
472 SOC_DAPM_SINGLE_TLV("Volume",
473 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
474 twl4030_dapm_dbypass_tlv);
475
476/* Digital bypass right (TX1R -> RX2R) */
477static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
478 SOC_DAPM_SINGLE_TLV("Volume",
479 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
480 twl4030_dapm_dbypass_tlv);
481
ee8f6894
LCM		 482/*
483 * Voice Sidetone GAIN volume control:
484 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
485 */
486static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
487
488/* Digital bypass voice: sidetone (VUL -> VDL)*/
489static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
490 SOC_DAPM_SINGLE_TLV("Volume",
491 TWL4030_REG_VSTPGA, 0, 0x29, 0,
492 twl4030_dapm_dbypassv_tlv);
493
276c6222
PU		 494static int micpath_event(struct snd_soc_dapm_widget *w,
495 struct snd_kcontrol *kcontrol, int event)
496{
497 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
498 unsigned char adcmicsel, micbias_ctl;
499
500 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
501 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
502 /* Prepare the bits for the given TX path:
503 * shift_l == 0: TX1 microphone path
504 * shift_l == 2: TX2 microphone path */
505 if (e->shift_l) {
506 /* TX2 microphone path */
507 if (adcmicsel & TWL4030_TX2IN_SEL)
508 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
509 else
510 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
511 } else {
512 /* TX1 microphone path */
513 if (adcmicsel & TWL4030_TX1IN_SEL)
514 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
515 else
516 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
517 }
518
519 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
520
521 return 0;
522}
523
9008adf9
PU		 524/*
525 * Output PGA builder:
526 * Handle the muting and unmuting of the given output (turning off the
527 * amplifier associated with the output pin)
528 * On mute bypass the reg_cache and mute the volume
529 * On unmute: restore the register content
530 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
531 */
532#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
533static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
534 struct snd_kcontrol *kcontrol, int event) \
535{ \
536 u8 reg_val; \
537 \
538 switch (event) { \
539 case SND_SOC_DAPM_POST_PMU: \
540 twl4030_write(w->codec, reg, \
541 twl4030_read_reg_cache(w->codec, reg)); \
542 break; \
543 case SND_SOC_DAPM_POST_PMD: \
544 reg_val = twl4030_read_reg_cache(w->codec, reg); \
545 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
546 reg_val & (~mask), \
547 reg); \
548 break; \
549 } \
550 return 0; \
551}
552
553TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
554TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
555TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
556TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
557TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
558
5a2e9a48 559static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 560{
49d92c7d
SM		 561 unsigned char hs_ctl;
562
5a2e9a48 563 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 564
5a2e9a48
PU		 565 if (ramp) {
566 /* HF ramp-up */
567 hs_ctl |= TWL4030_HF_CTL_REF_EN;
568 twl4030_write(codec, reg, hs_ctl);
569 udelay(10);
49d92c7d 570 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 571 twl4030_write(codec, reg, hs_ctl);
572 udelay(40);
49d92c7d 573 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 575 twl4030_write(codec, reg, hs_ctl);
49d92c7d 576 } else {
5a2e9a48
PU		 577 /* HF ramp-down */
578 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
579 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
580 twl4030_write(codec, reg, hs_ctl);
581 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
582 twl4030_write(codec, reg, hs_ctl);
583 udelay(40);
584 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
585 twl4030_write(codec, reg, hs_ctl);
49d92c7d 586 }
5a2e9a48 587}
49d92c7d 588
5a2e9a48
PU		 589static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
590 struct snd_kcontrol *kcontrol, int event)
591{
592 switch (event) {
593 case SND_SOC_DAPM_POST_PMU:
594 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
595 break;
596 case SND_SOC_DAPM_POST_PMD:
597 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
598 break;
599 }
600 return 0;
601}
602
603static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
604 struct snd_kcontrol *kcontrol, int event)
605{
606 switch (event) {
607 case SND_SOC_DAPM_POST_PMU:
608 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
609 break;
610 case SND_SOC_DAPM_POST_PMD:
611 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
612 break;
613 }
49d92c7d
SM		 614 return 0;
615}
616
86139a13
JV		 617static int vibramux_event(struct snd_soc_dapm_widget *w,
618 struct snd_kcontrol *kcontrol, int event)
619{
620 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
621 return 0;
622}
623
7729cf74
PU		 624static int apll_event(struct snd_soc_dapm_widget *w,
625 struct snd_kcontrol *kcontrol, int event)
626{
627 switch (event) {
628 case SND_SOC_DAPM_PRE_PMU:
629 twl4030_apll_enable(w->codec, 1);
630 break;
631 case SND_SOC_DAPM_POST_PMD:
632 twl4030_apll_enable(w->codec, 0);
633 break;
634 }
635 return 0;
636}
637
6943c92e 638static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 639{
4e49ffd1
CVJ		 640 struct snd_soc_device *socdev = codec->socdev;
641 struct twl4030_setup_data *setup = socdev->codec_data;
642
aad749e5 643 unsigned char hs_gain, hs_pop;
6943c92e
PU		 644 struct twl4030_priv *twl4030 = codec->private_data;
645 /* Base values for ramp delay calculation: 2^19 - 2^26 */
646 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
647 8388608, 16777216, 33554432, 67108864};
aad749e5 648
6943c92e
PU		 649 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
650 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 651
4e49ffd1
CVJ		 652 /* Enable external mute control, this dramatically reduces
653 * the pop-noise */
654 if (setup && setup->hs_extmute) {
655 if (setup->set_hs_extmute) {
656 setup->set_hs_extmute(1);
657 } else {
658 hs_pop |= TWL4030_EXTMUTE;
659 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
660 }
661 }
662
6943c92e
PU		 663 if (ramp) {
664 /* Headset ramp-up according to the TRM */
aad749e5 665 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 666 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
667 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 668 hs_pop |= TWL4030_RAMP_EN;
6943c92e 669 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 670 /* Wait ramp delay time + 1, so the VMID can settle */
671 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
672 twl4030->sysclk) + 1);
6943c92e
PU		 673 } else {
674 /* Headset ramp-down _not_ according to
675 * the TRM, but in a way that it is working */
aad749e5 676 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 677 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
678 /* Wait ramp delay time + 1, so the VMID can settle */
679 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
680 twl4030->sysclk) + 1);
aad749e5
PU		 681 /* Bypass the reg_cache to mute the headset */
682 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
683 hs_gain & (~0x0f),
684 TWL4030_REG_HS_GAIN_SET);
6943c92e 685
aad749e5 686 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 687 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
688 }
4e49ffd1
CVJ		 689
690 /* Disable external mute */
691 if (setup && setup->hs_extmute) {
692 if (setup->set_hs_extmute) {
693 setup->set_hs_extmute(0);
694 } else {
695 hs_pop &= ~TWL4030_EXTMUTE;
696 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
697 }
698 }
6943c92e
PU		 699}
700
701static int headsetlpga_event(struct snd_soc_dapm_widget *w,
702 struct snd_kcontrol *kcontrol, int event)
703{
704 struct twl4030_priv *twl4030 = w->codec->private_data;
705
706 switch (event) {
707 case SND_SOC_DAPM_POST_PMU:
708 /* Do the ramp-up only once */
709 if (!twl4030->hsr_enabled)
710 headset_ramp(w->codec, 1);
711
712 twl4030->hsl_enabled = 1;
713 break;
714 case SND_SOC_DAPM_POST_PMD:
715 /* Do the ramp-down only if both headsetL/R is disabled */
716 if (!twl4030->hsr_enabled)
717 headset_ramp(w->codec, 0);
718
719 twl4030->hsl_enabled = 0;
720 break;
721 }
722 return 0;
723}
724
725static int headsetrpga_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727{
728 struct twl4030_priv *twl4030 = w->codec->private_data;
729
730 switch (event) {
731 case SND_SOC_DAPM_POST_PMU:
732 /* Do the ramp-up only once */
733 if (!twl4030->hsl_enabled)
734 headset_ramp(w->codec, 1);
735
736 twl4030->hsr_enabled = 1;
737 break;
738 case SND_SOC_DAPM_POST_PMD:
739 /* Do the ramp-down only if both headsetL/R is disabled */
740 if (!twl4030->hsl_enabled)
741 headset_ramp(w->codec, 0);
742
743 twl4030->hsr_enabled = 0;
aad749e5
PU		 744 break;
745 }
746 return 0;
747}
748
b0bd53a7
PU		 749/*
750 * Some of the gain controls in TWL (mostly those which are associated with
751 * the outputs) are implemented in an interesting way:
752 * 0x0 : Power down (mute)
753 * 0x1 : 6dB
754 * 0x2 : 0 dB
755 * 0x3 : -6 dB
756 * Inverting not going to help with these.
757 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
758 */
759#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
760 xinvert, tlv_array) \
761{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
762 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
763 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
764 .tlv.p = (tlv_array), \
765 .info = snd_soc_info_volsw, \
766 .get = snd_soc_get_volsw_twl4030, \
767 .put = snd_soc_put_volsw_twl4030, \
768 .private_value = (unsigned long)&(struct soc_mixer_control) \
769 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
770 .max = xmax, .invert = xinvert} }
771#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
772 xinvert, tlv_array) \
773{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
774 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
775 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
776 .tlv.p = (tlv_array), \
777 .info = snd_soc_info_volsw_2r, \
778 .get = snd_soc_get_volsw_r2_twl4030,\
779 .put = snd_soc_put_volsw_r2_twl4030, \
780 .private_value = (unsigned long)&(struct soc_mixer_control) \
781 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 782 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 783#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
784 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
785 xinvert, tlv_array)
786
787static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
788 struct snd_ctl_elem_value *ucontrol)
789{
790 struct soc_mixer_control *mc =
791 (struct soc_mixer_control *)kcontrol->private_value;
792 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
793 unsigned int reg = mc->reg;
794 unsigned int shift = mc->shift;
795 unsigned int rshift = mc->rshift;
796 int max = mc->max;
797 int mask = (1 << fls(max)) - 1;
798
799 ucontrol->value.integer.value[0] =
800 (snd_soc_read(codec, reg) >> shift) & mask;
801 if (ucontrol->value.integer.value[0])
802 ucontrol->value.integer.value[0] =
803 max + 1 - ucontrol->value.integer.value[0];
804
805 if (shift != rshift) {
806 ucontrol->value.integer.value[1] =
807 (snd_soc_read(codec, reg) >> rshift) & mask;
808 if (ucontrol->value.integer.value[1])
809 ucontrol->value.integer.value[1] =
810 max + 1 - ucontrol->value.integer.value[1];
811 }
812
813 return 0;
814}
815
816static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
817 struct snd_ctl_elem_value *ucontrol)
818{
819 struct soc_mixer_control *mc =
820 (struct soc_mixer_control *)kcontrol->private_value;
821 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
822 unsigned int reg = mc->reg;
823 unsigned int shift = mc->shift;
824 unsigned int rshift = mc->rshift;
825 int max = mc->max;
826 int mask = (1 << fls(max)) - 1;
827 unsigned short val, val2, val_mask;
828
829 val = (ucontrol->value.integer.value[0] & mask);
830
831 val_mask = mask << shift;
832 if (val)
833 val = max + 1 - val;
834 val = val << shift;
835 if (shift != rshift) {
836 val2 = (ucontrol->value.integer.value[1] & mask);
837 val_mask |= mask << rshift;
838 if (val2)
839 val2 = max + 1 - val2;
840 val |= val2 << rshift;
841 }
842 return snd_soc_update_bits(codec, reg, val_mask, val);
843}
844
845static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
846 struct snd_ctl_elem_value *ucontrol)
847{
848 struct soc_mixer_control *mc =
849 (struct soc_mixer_control *)kcontrol->private_value;
850 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
851 unsigned int reg = mc->reg;
852 unsigned int reg2 = mc->rreg;
853 unsigned int shift = mc->shift;
854 int max = mc->max;
855 int mask = (1<<fls(max))-1;
856
857 ucontrol->value.integer.value[0] =
858 (snd_soc_read(codec, reg) >> shift) & mask;
859 ucontrol->value.integer.value[1] =
860 (snd_soc_read(codec, reg2) >> shift) & mask;
861
862 if (ucontrol->value.integer.value[0])
863 ucontrol->value.integer.value[0] =
864 max + 1 - ucontrol->value.integer.value[0];
865 if (ucontrol->value.integer.value[1])
866 ucontrol->value.integer.value[1] =
867 max + 1 - ucontrol->value.integer.value[1];
868
869 return 0;
870}
871
872static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
873 struct snd_ctl_elem_value *ucontrol)
874{
875 struct soc_mixer_control *mc =
876 (struct soc_mixer_control *)kcontrol->private_value;
877 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
878 unsigned int reg = mc->reg;
879 unsigned int reg2 = mc->rreg;
880 unsigned int shift = mc->shift;
881 int max = mc->max;
882 int mask = (1 << fls(max)) - 1;
883 int err;
884 unsigned short val, val2, val_mask;
885
886 val_mask = mask << shift;
887 val = (ucontrol->value.integer.value[0] & mask);
888 val2 = (ucontrol->value.integer.value[1] & mask);
889
890 if (val)
891 val = max + 1 - val;
892 if (val2)
893 val2 = max + 1 - val2;
894
895 val = val << shift;
896 val2 = val2 << shift;
897
898 err = snd_soc_update_bits(codec, reg, val_mask, val);
899 if (err < 0)
900 return err;
901
902 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
903 return err;
904}
905
b74bd40f
LCM		 906/* Codec operation modes */
907static const char *twl4030_op_modes_texts[] = {
908 "Option 2 (voice/audio)", "Option 1 (audio)"
909};
910
911static const struct soc_enum twl4030_op_modes_enum =
912 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
913 ARRAY_SIZE(twl4030_op_modes_texts),
914 twl4030_op_modes_texts);
915
423c238d 916static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 917 struct snd_ctl_elem_value *ucontrol)
918{
919 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
920 struct twl4030_priv *twl4030 = codec->private_data;
921 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
922 unsigned short val;
923 unsigned short mask, bitmask;
924
925 if (twl4030->configured) {
926 printk(KERN_ERR "twl4030 operation mode cannot be "
927 "changed on-the-fly\n");
928 return -EBUSY;
929 }
930
931 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
932 ;
933 if (ucontrol->value.enumerated.item[0] > e->max - 1)
934 return -EINVAL;
935
936 val = ucontrol->value.enumerated.item[0] << e->shift_l;
937 mask = (bitmask - 1) << e->shift_l;
938 if (e->shift_l != e->shift_r) {
939 if (ucontrol->value.enumerated.item[1] > e->max - 1)
940 return -EINVAL;
941 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
942 mask |= (bitmask - 1) << e->shift_r;
943 }
944
945 return snd_soc_update_bits(codec, e->reg, mask, val);
946}
947
c10b82cf
PU		 948/*
949 * FGAIN volume control:
950 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
951 */
d889a72c 952static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 953
0d33ea0b
PU		 954/*
955 * CGAIN volume control:
956 * 0 dB to 12 dB in 6 dB steps
957 * value 2 and 3 means 12 dB
958 */
d889a72c
PU		 959static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
960
1a787e7a
JS		 961/*
962 * Voice Downlink GAIN volume control:
963 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
964 */
965static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
966
d889a72c
PU		 967/*
968 * Analog playback gain
969 * -24 dB to 12 dB in 2 dB steps
970 */
971static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 972
4290239c
PU		 973/*
974 * Gain controls tied to outputs
975 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
976 */
977static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
978
18cc8d8d
JS		 979/*
980 * Gain control for earpiece amplifier
981 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
982 */
983static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
984
381a22b5
PU		 985/*
986 * Capture gain after the ADCs
987 * from 0 dB to 31 dB in 1 dB steps
988 */
989static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
990
5920b453
GI		 991/*
992 * Gain control for input amplifiers
993 * 0 dB to 30 dB in 6 dB steps
994 */
995static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
996
328d0a13
LCM		 997/* AVADC clock priority */
998static const char *twl4030_avadc_clk_priority_texts[] = {
999 "Voice high priority", "HiFi high priority"
1000};
1001
1002static const struct soc_enum twl4030_avadc_clk_priority_enum =
1003 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1004 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1005 twl4030_avadc_clk_priority_texts);
1006
89492be8
PU		 1007static const char *twl4030_rampdelay_texts[] = {
1008 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1009 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1010 "3495/2581/1748 ms"
1011};
1012
1013static const struct soc_enum twl4030_rampdelay_enum =
1014 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1015 ARRAY_SIZE(twl4030_rampdelay_texts),
1016 twl4030_rampdelay_texts);
1017
376f7839
PU		 1018/* Vibra H-bridge direction mode */
1019static const char *twl4030_vibradirmode_texts[] = {
1020 "Vibra H-bridge direction", "Audio data MSB",
1021};
1022
1023static const struct soc_enum twl4030_vibradirmode_enum =
1024 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1025 ARRAY_SIZE(twl4030_vibradirmode_texts),
1026 twl4030_vibradirmode_texts);
1027
1028/* Vibra H-bridge direction */
1029static const char *twl4030_vibradir_texts[] = {
1030 "Positive polarity", "Negative polarity",
1031};
1032
1033static const struct soc_enum twl4030_vibradir_enum =
1034 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1035 ARRAY_SIZE(twl4030_vibradir_texts),
1036 twl4030_vibradir_texts);
1037
cc17557e 1038static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1039 /* Codec operation mode control */
1040 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1041 snd_soc_get_enum_double,
1042 snd_soc_put_twl4030_opmode_enum_double),
1043
d889a72c
PU		 1044 /* Common playback gain controls */
1045 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1046 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1047 0, 0x3f, 0, digital_fine_tlv),
1048 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1049 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1050 0, 0x3f, 0, digital_fine_tlv),
1051
1052 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1053 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1054 6, 0x2, 0, digital_coarse_tlv),
1055 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1056 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1057 6, 0x2, 0, digital_coarse_tlv),
1058
1059 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1060 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1061 3, 0x12, 1, analog_tlv),
1062 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1063 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1064 3, 0x12, 1, analog_tlv),
44c55870
PU		 1065 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1066 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1067 1, 1, 0),
1068 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1069 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1070 1, 1, 0),
381a22b5 1071
1a787e7a
JS		 1072 /* Common voice downlink gain controls */
1073 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1074 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1075
1076 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1077 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1078
1079 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1080 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1081
4290239c
PU		 1082 /* Separate output gain controls */
1083 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1084 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1085 4, 3, 0, output_tvl),
1086
1087 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1088 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1089
1090 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1091 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1092 4, 3, 0, output_tvl),
1093
1094 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1095 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1096
381a22b5 1097 /* Common capture gain controls */
276c6222 1098 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1099 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1100 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1101 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1102 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1103 0, 0x1f, 0, digital_capture_tlv),
5920b453 1104
276c6222 1105 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1106 0, 3, 5, 0, input_gain_tlv),
89492be8 1107
328d0a13
LCM		 1108 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1109
89492be8 1110 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1111
1112 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1113 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1114};
1115
cc17557e 1116static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1117 /* Left channel inputs */
1118 SND_SOC_DAPM_INPUT("MAINMIC"),
1119 SND_SOC_DAPM_INPUT("HSMIC"),
1120 SND_SOC_DAPM_INPUT("AUXL"),
1121 SND_SOC_DAPM_INPUT("CARKITMIC"),
1122 /* Right channel inputs */
1123 SND_SOC_DAPM_INPUT("SUBMIC"),
1124 SND_SOC_DAPM_INPUT("AUXR"),
1125 /* Digital microphones (Stereo) */
1126 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1127 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1128
1129 /* Outputs */
cc17557e
SS		 1130 SND_SOC_DAPM_OUTPUT("OUTL"),
1131 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1132 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1133 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1134 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1135 SND_SOC_DAPM_OUTPUT("HSOL"),
1136 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1137 SND_SOC_DAPM_OUTPUT("CARKITL"),
1138 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1139 SND_SOC_DAPM_OUTPUT("HFL"),
1140 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1141 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1142
53b5047d 1143 /* DACs */
b4852b79 1144 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1145 SND_SOC_NOPM, 0, 0),
b4852b79 1146 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1147 SND_SOC_NOPM, 0, 0),
b4852b79 1148 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1149 SND_SOC_NOPM, 0, 0),
b4852b79 1150 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1151 SND_SOC_NOPM, 0, 0),
1a787e7a 1152 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1153 SND_SOC_NOPM, 0, 0),
cc17557e 1154
7393958f 1155 /* Analog bypasses */
78e08e2f
PU		 1156 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1157 &twl4030_dapm_abypassr1_control),
1158 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1159 &twl4030_dapm_abypassl1_control),
1160 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1161 &twl4030_dapm_abypassr2_control),
1162 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1163 &twl4030_dapm_abypassl2_control),
1164 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1165 &twl4030_dapm_abypassv_control),
1166
1167 /* Master analog loopback switch */
1168 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1169 NULL, 0),
7393958f 1170
6bab83fd 1171 /* Digital bypasses */
78e08e2f
PU		 1172 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1173 &twl4030_dapm_dbypassl_control),
1174 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1175 &twl4030_dapm_dbypassr_control),
1176 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1177 &twl4030_dapm_dbypassv_control),
6bab83fd 1178
4005d39a
PU		 1179 /* Digital mixers, power control for the physical DACs */
1180 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1181 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1182 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1183 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1184 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1185 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1186 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1187 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1188 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1189 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1190
1191 /* Analog mixers, power control for the physical PGAs */
1192 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1193 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1194 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1195 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1196 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1197 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1198 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1199 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1200 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1201 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1202
7729cf74
PU		 1203 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1204 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1205
1a787e7a 1206 /* Output MIXER controls */
5e98a464 1207 /* Earpiece */
1a787e7a
JS		 1208 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1209 &twl4030_dapm_earpiece_controls[0],
1210 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1211 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1212 0, 0, NULL, 0, earpiecepga_event,
1213 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1214 /* PreDrivL/R */
1a787e7a
JS		 1215 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1216 &twl4030_dapm_predrivel_controls[0],
1217 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1218 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1219 0, 0, NULL, 0, predrivelpga_event,
1220 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1221 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1222 &twl4030_dapm_predriver_controls[0],
1223 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1224 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1225 0, 0, NULL, 0, predriverpga_event,
1226 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1227 /* HeadsetL/R */
6943c92e 1228 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1229 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1230 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1231 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1232 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1233 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1234 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1235 &twl4030_dapm_hsor_controls[0],
1236 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1237 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1238 0, 0, NULL, 0, headsetrpga_event,
1239 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1240 /* CarkitL/R */
1a787e7a
JS		 1241 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1242 &twl4030_dapm_carkitl_controls[0],
1243 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1244 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1245 0, 0, NULL, 0, carkitlpga_event,
1246 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1247 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1248 &twl4030_dapm_carkitr_controls[0],
1249 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1250 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1251 0, 0, NULL, 0, carkitrpga_event,
1252 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1253
1254 /* Output MUX controls */
df339804 1255 /* HandsfreeL/R */
5a2e9a48
PU		 1256 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1257 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1258 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1259 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1260 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1261 0, 0, NULL, 0, handsfreelpga_event,
1262 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1263 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1264 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1265 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1266 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1267 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1268 0, 0, NULL, 0, handsfreerpga_event,
1269 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1270 /* Vibra */
86139a13
JV		 1271 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1272 &twl4030_dapm_vibra_control, vibramux_event,
1273 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1274 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1275 &twl4030_dapm_vibrapath_control),
5e98a464 1276
276c6222
PU		 1277 /* Introducing four virtual ADC, since TWL4030 have four channel for
1278 capture */
1279 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1280 SND_SOC_NOPM, 0, 0),
1281 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1282 SND_SOC_NOPM, 0, 0),
1283 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1284 SND_SOC_NOPM, 0, 0),
1285 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1286 SND_SOC_NOPM, 0, 0),
1287
1288 /* Analog/Digital mic path selection.
1289 TX1 Left/Right: either analog Left/Right or Digimic0
1290 TX2 Left/Right: either analog Left/Right or Digimic1 */
1291 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1292 &twl4030_dapm_micpathtx1_control, micpath_event,
1293 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1294 SND_SOC_DAPM_POST_REG),
1295 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1296 &twl4030_dapm_micpathtx2_control, micpath_event,
1297 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1298 SND_SOC_DAPM_POST_REG),
1299
97b8096d 1300 /* Analog input mixers for the capture amplifiers */
9028935d 1301 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1302 TWL4030_REG_ANAMICL, 4, 0,
1303 &twl4030_dapm_analoglmic_controls[0],
1304 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1305 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1306 TWL4030_REG_ANAMICR, 4, 0,
1307 &twl4030_dapm_analogrmic_controls[0],
1308 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1309
fb2a2f84
PU		 1310 SND_SOC_DAPM_PGA("ADC Physical Left",
1311 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1312 SND_SOC_DAPM_PGA("ADC Physical Right",
1313 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1314
1315 SND_SOC_DAPM_PGA("Digimic0 Enable",
1316 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1317 SND_SOC_DAPM_PGA("Digimic1 Enable",
1318 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1319
1320 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1321 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1322 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1323
cc17557e
SS		 1324};
1325
1326static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1327 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1328 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1329 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1330 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1331 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1332
7729cf74
PU		 1333 /* Supply for the digital part (APLL) */
1334 {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
1335 {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
1336 {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
1337 {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
1338 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1339
4005d39a
PU		 1340 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1341 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1342 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1343 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1344 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1345
5e98a464
PU		 1346 /* Internal playback routings */
1347 /* Earpiece */
4005d39a
PU		 1348 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1349 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1350 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1351 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1352 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1353 /* PreDrivL */
4005d39a
PU		 1354 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1355 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1356 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1357 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1358 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1359 /* PreDrivR */
4005d39a
PU		 1360 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1361 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1362 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1363 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1364 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1365 /* HeadsetL */
4005d39a
PU		 1366 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1367 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1368 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1369 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1370 /* HeadsetR */
4005d39a
PU		 1371 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1372 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1373 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1374 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1375 /* CarkitL */
4005d39a
PU		 1376 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1377 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1378 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1379 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1380 /* CarkitR */
4005d39a
PU		 1381 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1382 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1383 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1384 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1385 /* HandsfreeL */
4005d39a
PU		 1386 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1387 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1388 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1389 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1390 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1391 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1392 /* HandsfreeR */
4005d39a
PU		 1393 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1394 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1395 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1396 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1397 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1398 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1399 /* Vibra */
1400 {"Vibra Mux", "AudioL1", "DAC Left1"},
1401 {"Vibra Mux", "AudioR1", "DAC Right1"},
1402 {"Vibra Mux", "AudioL2", "DAC Left2"},
1403 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1404
cc17557e 1405 /* outputs */
4005d39a
PU		 1406 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1407 {"OUTR", NULL, "Analog R2 Playback Mixer"},
9008adf9
PU		 1408 {"EARPIECE", NULL, "Earpiece PGA"},
1409 {"PREDRIVEL", NULL, "PredriveL PGA"},
1410 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1411 {"HSOL", NULL, "HeadsetL PGA"},
1412 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1413 {"CARKITL", NULL, "CarkitL PGA"},
1414 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1415 {"HFL", NULL, "HandsfreeL PGA"},
1416 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1417 {"Vibra Route", "Audio", "Vibra Mux"},
1418 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1419
276c6222 1420 /* Capture path */
9028935d
PU		 1421 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1422 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1423 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1424 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1425
9028935d
PU		 1426 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1427 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1428
9028935d
PU		 1429 {"ADC Physical Left", NULL, "Analog Left"},
1430 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1431
1432 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1433 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1434
1435 /* TX1 Left capture path */
fb2a2f84 1436 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1437 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1438 /* TX1 Right capture path */
fb2a2f84 1439 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1440 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1441 /* TX2 Left capture path */
fb2a2f84 1442 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1443 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1444 /* TX2 Right capture path */
fb2a2f84 1445 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1446 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1447
1448 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1449 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1450 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1451 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1452
1c3d2002
PU		 1453 {"ADC Virtual Left1", NULL, "APLL Enable"},
1454 {"ADC Virtual Right1", NULL, "APLL Enable"},
1455 {"ADC Virtual Left2", NULL, "APLL Enable"},
1456 {"ADC Virtual Right2", NULL, "APLL Enable"},
1457
7393958f 1458 /* Analog bypass routes */
9028935d
PU		 1459 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1460 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1461 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1462 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1463 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1464
78e08e2f
PU		 1465 /* Supply for the Analog loopbacks */
1466 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1467 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1468 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1469 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1470 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1471
7393958f
PU		 1472 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1473 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1474 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1475 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1476 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1477
6bab83fd
PU		 1478 /* Digital bypass routes */
1479 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1480 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1481 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1482
4005d39a
PU		 1483 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1484 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1485 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1486
cc17557e
SS		 1487};
1488
1489static int twl4030_add_widgets(struct snd_soc_codec *codec)
1490{
1491 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1492 ARRAY_SIZE(twl4030_dapm_widgets));
1493
1494 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1495
cc17557e
SS		 1496 return 0;
1497}
1498
cc17557e
SS		 1499static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1500 enum snd_soc_bias_level level)
1501{
1502 switch (level) {
1503 case SND_SOC_BIAS_ON:
cc17557e
SS		 1504 break;
1505 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1506 break;
1507 case SND_SOC_BIAS_STANDBY:
78e08e2f
PU		 1508 if (codec->bias_level == SND_SOC_BIAS_OFF)
1509 twl4030_power_up(codec);
cc17557e
SS		 1510 break;
1511 case SND_SOC_BIAS_OFF:
1512 twl4030_power_down(codec);
1513 break;
1514 }
1515 codec->bias_level = level;
1516
1517 return 0;
1518}
1519
6b87a91f
PU		 1520static void twl4030_constraints(struct twl4030_priv *twl4030,
1521 struct snd_pcm_substream *mst_substream)
1522{
1523 struct snd_pcm_substream *slv_substream;
1524
1525 /* Pick the stream, which need to be constrained */
1526 if (mst_substream == twl4030->master_substream)
1527 slv_substream = twl4030->slave_substream;
1528 else if (mst_substream == twl4030->slave_substream)
1529 slv_substream = twl4030->master_substream;
1530 else /* This should not happen.. */
1531 return;
1532
1533 /* Set the constraints according to the already configured stream */
1534 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1535 SNDRV_PCM_HW_PARAM_RATE,
1536 twl4030->rate,
1537 twl4030->rate);
1538
1539 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1540 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1541 twl4030->sample_bits,
1542 twl4030->sample_bits);
1543
1544 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1545 SNDRV_PCM_HW_PARAM_CHANNELS,
1546 twl4030->channels,
1547 twl4030->channels);
1548}
1549
8a1f936a
PU		 1550/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1551 * capture has to be enabled/disabled. */
1552static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1553 int enable)
1554{
1555 u8 reg, mask;
1556
1557 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1558
1559 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1560 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1561 else
1562 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1563
1564 if (enable)
1565 reg |= mask;
1566 else
1567 reg &= ~mask;
1568
1569 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1570}
1571
d6648da1
PU		 1572static int twl4030_startup(struct snd_pcm_substream *substream,
1573 struct snd_soc_dai *dai)
7220b9f4
PU		 1574{
1575 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1576 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1577 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1578 struct twl4030_priv *twl4030 = codec->private_data;
1579
7220b9f4 1580 if (twl4030->master_substream) {
7220b9f4 1581 twl4030->slave_substream = substream;
6b87a91f
PU		 1582 /* The DAI has one configuration for playback and capture, so
1583 * if the DAI has been already configured then constrain this
1584 * substream to match it. */
1585 if (twl4030->configured)
1586 twl4030_constraints(twl4030, twl4030->master_substream);
1587 } else {
8a1f936a
PU		 1588 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1589 TWL4030_OPTION_1)) {
1590 /* In option2 4 channel is not supported, set the
1591 * constraint for the first stream for channels, the
1592 * second stream will 'inherit' this cosntraint */
1593 snd_pcm_hw_constraint_minmax(substream->runtime,
1594 SNDRV_PCM_HW_PARAM_CHANNELS,
1595 2, 2);
1596 }
7220b9f4 1597 twl4030->master_substream = substream;
6b87a91f 1598 }
7220b9f4
PU		 1599
1600 return 0;
1601}
1602
d6648da1
PU		 1603static void twl4030_shutdown(struct snd_pcm_substream *substream,
1604 struct snd_soc_dai *dai)
7220b9f4
PU		 1605{
1606 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1607 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1608 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1609 struct twl4030_priv *twl4030 = codec->private_data;
1610
1611 if (twl4030->master_substream == substream)
1612 twl4030->master_substream = twl4030->slave_substream;
1613
1614 twl4030->slave_substream = NULL;
6b87a91f
PU		 1615
1616 /* If all streams are closed, or the remaining stream has not yet
1617 * been configured than set the DAI as not configured. */
1618 if (!twl4030->master_substream)
1619 twl4030->configured = 0;
1620 else if (!twl4030->master_substream->runtime->channels)
1621 twl4030->configured = 0;
8a1f936a
PU		 1622
1623 /* If the closing substream had 4 channel, do the necessary cleanup */
1624 if (substream->runtime->channels == 4)
1625 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1626}
1627
cc17557e 1628static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1629 struct snd_pcm_hw_params *params,
1630 struct snd_soc_dai *dai)
cc17557e
SS		 1631{
1632 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1633 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1634 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1635 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1636 u8 mode, old_mode, format, old_format;
1637
8a1f936a
PU		 1638 /* If the substream has 4 channel, do the necessary setup */
1639 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1640 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1641 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1642
1643 /* Safety check: are we in the correct operating mode and
1644 * the interface is in TDM mode? */
1645 if ((mode & TWL4030_OPTION_1) &&
1646 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1647 twl4030_tdm_enable(codec, substream->stream, 1);
1648 else
1649 return -EINVAL;
1650 }
1651
6b87a91f
PU		 1652 if (twl4030->configured)
1653 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1654 return 0;
1655
cc17557e
SS		 1656 /* bit rate */
1657 old_mode = twl4030_read_reg_cache(codec,
1658 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1659 mode = old_mode & ~TWL4030_APLL_RATE;
1660
1661 switch (params_rate(params)) {
1662 case 8000:
1663 mode |= TWL4030_APLL_RATE_8000;
1664 break;
1665 case 11025:
1666 mode |= TWL4030_APLL_RATE_11025;
1667 break;
1668 case 12000:
1669 mode |= TWL4030_APLL_RATE_12000;
1670 break;
1671 case 16000:
1672 mode |= TWL4030_APLL_RATE_16000;
1673 break;
1674 case 22050:
1675 mode |= TWL4030_APLL_RATE_22050;
1676 break;
1677 case 24000:
1678 mode |= TWL4030_APLL_RATE_24000;
1679 break;
1680 case 32000:
1681 mode |= TWL4030_APLL_RATE_32000;
1682 break;
1683 case 44100:
1684 mode |= TWL4030_APLL_RATE_44100;
1685 break;
1686 case 48000:
1687 mode |= TWL4030_APLL_RATE_48000;
1688 break;
103f211d
PU		 1689 case 96000:
1690 mode |= TWL4030_APLL_RATE_96000;
1691 break;
cc17557e
SS		 1692 default:
1693 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1694 params_rate(params));
1695 return -EINVAL;
1696 }
1697
1698 if (mode != old_mode) {
1699 /* change rate and set CODECPDZ */
7393958f 1700 twl4030_codec_enable(codec, 0);
cc17557e 1701 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1702 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1703 }
1704
1705 /* sample size */
1706 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1707 format = old_format;
1708 format &= ~TWL4030_DATA_WIDTH;
1709 switch (params_format(params)) {
1710 case SNDRV_PCM_FORMAT_S16_LE:
1711 format |= TWL4030_DATA_WIDTH_16S_16W;
1712 break;
1713 case SNDRV_PCM_FORMAT_S24_LE:
1714 format |= TWL4030_DATA_WIDTH_32S_24W;
1715 break;
1716 default:
1717 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1718 params_format(params));
1719 return -EINVAL;
1720 }
1721
1722 if (format != old_format) {
1723
1724 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1725 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1726
1727 /* change format */
1728 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1729
1730 /* set CODECPDZ afterwards */
db04e2c5 1731 twl4030_codec_enable(codec, 1);
cc17557e 1732 }
6b87a91f
PU		 1733
1734 /* Store the important parameters for the DAI configuration and set
1735 * the DAI as configured */
1736 twl4030->configured = 1;
1737 twl4030->rate = params_rate(params);
1738 twl4030->sample_bits = hw_param_interval(params,
1739 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1740 twl4030->channels = params_channels(params);
1741
1742 /* If both playback and capture streams are open, and one of them
1743 * is setting the hw parameters right now (since we are here), set
1744 * constraints to the other stream to match the current one. */
1745 if (twl4030->slave_substream)
1746 twl4030_constraints(twl4030, substream);
1747
cc17557e
SS		 1748 return 0;
1749}
1750
1751static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1752 int clk_id, unsigned int freq, int dir)
1753{
1754 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1755 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1756
1757 switch (freq) {
1758 case 19200000:
cc17557e 1759 case 26000000:
cc17557e 1760 case 38400000:
cc17557e
SS		 1761 break;
1762 default:
68d01955 1763 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1764 return -EINVAL;
1765 }
1766
68d01955
PU		 1767 if ((freq / 1000) != twl4030->sysclk) {
1768 dev_err(codec->dev,
1769 "Mismatch in APLL mclk: %u (configured: %u)\n",
1770 freq, twl4030->sysclk * 1000);
1771 return -EINVAL;
1772 }
cc17557e
SS		 1773
1774 return 0;
1775}
1776
1777static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1778 unsigned int fmt)
1779{
1780 struct snd_soc_codec *codec = codec_dai->codec;
1781 u8 old_format, format;
1782
1783 /* get format */
1784 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1785 format = old_format;
1786
1787 /* set master/slave audio interface */
1788 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1789 case SND_SOC_DAIFMT_CBM_CFM:
1790 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1791 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1792 break;
1793 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1794 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1795 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1796 break;
1797 default:
1798 return -EINVAL;
1799 }
1800
1801 /* interface format */
1802 format &= ~TWL4030_AIF_FORMAT;
1803 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1804 case SND_SOC_DAIFMT_I2S:
1805 format |= TWL4030_AIF_FORMAT_CODEC;
1806 break;
8a1f936a
PU		 1807 case SND_SOC_DAIFMT_DSP_A:
1808 format |= TWL4030_AIF_FORMAT_TDM;
1809 break;
cc17557e
SS		 1810 default:
1811 return -EINVAL;
1812 }
1813
1814 if (format != old_format) {
1815
1816 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1817 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1818
1819 /* change format */
1820 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1821
1822 /* set CODECPDZ afterwards */
db04e2c5 1823 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1824 }
1825
1826 return 0;
1827}
1828
68140443
LCM		 1829static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1830{
1831 struct snd_soc_codec *codec = dai->codec;
1832 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1833
1834 if (tristate)
1835 reg |= TWL4030_AIF_TRI_EN;
1836 else
1837 reg &= ~TWL4030_AIF_TRI_EN;
1838
1839 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1840}
1841
b7a755a8
MLC		 1842/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1843 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1844static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1845 int enable)
1846{
1847 u8 reg, mask;
1848
1849 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1850
1851 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1852 mask = TWL4030_ARXL1_VRX_EN;
1853 else
1854 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1855
1856 if (enable)
1857 reg |= mask;
1858 else
1859 reg &= ~mask;
1860
1861 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1862}
1863
7154b3e8
JS		 1864static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1865 struct snd_soc_dai *dai)
1866{
1867 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1868 struct snd_soc_device *socdev = rtd->socdev;
1869 struct snd_soc_codec *codec = socdev->card->codec;
68d01955 1870 struct twl4030_priv *twl4030 = codec->private_data;
7154b3e8
JS		 1871 u8 mode;
1872
1873 /* If the system master clock is not 26MHz, the voice PCM interface is
1874 * not avilable.
1875 */
68d01955
PU		 1876 if (twl4030->sysclk != 26000) {
1877 dev_err(codec->dev, "The board is configured for %u Hz, while"
1878 "the Voice interface needs 26MHz APLL mclk\n",
1879 twl4030->sysclk * 1000);
7154b3e8
JS		 1880 return -EINVAL;
1881 }
1882
1883 /* If the codec mode is not option2, the voice PCM interface is not
1884 * avilable.
1885 */
1886 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1887 & TWL4030_OPT_MODE;
1888
1889 if (mode != TWL4030_OPTION_2) {
1890 printk(KERN_ERR "TWL4030 voice startup: "
1891 "the codec mode is not option2\n");
1892 return -EINVAL;
1893 }
1894
1895 return 0;
1896}
1897
b7a755a8
MLC		 1898static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1899 struct snd_soc_dai *dai)
1900{
1901 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1902 struct snd_soc_device *socdev = rtd->socdev;
1903 struct snd_soc_codec *codec = socdev->card->codec;
1904
1905 /* Enable voice digital filters */
1906 twl4030_voice_enable(codec, substream->stream, 0);
1907}
1908
7154b3e8
JS		 1909static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1910 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1911{
1912 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1913 struct snd_soc_device *socdev = rtd->socdev;
1914 struct snd_soc_codec *codec = socdev->card->codec;
1915 u8 old_mode, mode;
1916
b7a755a8
MLC		 1917 /* Enable voice digital filters */
1918 twl4030_voice_enable(codec, substream->stream, 1);
1919
7154b3e8
JS		 1920 /* bit rate */
1921 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1922 & ~(TWL4030_CODECPDZ);
1923 mode = old_mode;
1924
1925 switch (params_rate(params)) {
1926 case 8000:
1927 mode &= ~(TWL4030_SEL_16K);
1928 break;
1929 case 16000:
1930 mode |= TWL4030_SEL_16K;
1931 break;
1932 default:
1933 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1934 params_rate(params));
1935 return -EINVAL;
1936 }
1937
1938 if (mode != old_mode) {
1939 /* change rate and set CODECPDZ */
1940 twl4030_codec_enable(codec, 0);
1941 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1942 twl4030_codec_enable(codec, 1);
1943 }
1944
1945 return 0;
1946}
1947
1948static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1949 int clk_id, unsigned int freq, int dir)
1950{
1951 struct snd_soc_codec *codec = codec_dai->codec;
68d01955 1952 struct twl4030_priv *twl4030 = codec->private_data;
7154b3e8 1953
68d01955
PU		 1954 if (freq != 26000000) {
1955 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
1956 "interface needs 26MHz APLL mclk\n", freq);
1957 return -EINVAL;
1958 }
1959 if ((freq / 1000) != twl4030->sysclk) {
1960 dev_err(codec->dev,
1961 "Mismatch in APLL mclk: %u (configured: %u)\n",
1962 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 1963 return -EINVAL;
1964 }
7154b3e8
JS		 1965 return 0;
1966}
1967
1968static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1969 unsigned int fmt)
1970{
1971 struct snd_soc_codec *codec = codec_dai->codec;
1972 u8 old_format, format;
1973
1974 /* get format */
1975 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1976 format = old_format;
1977
1978 /* set master/slave audio interface */
1979 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 1980 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 1981 format &= ~(TWL4030_VIF_SLAVE_EN);
1982 break;
1983 case SND_SOC_DAIFMT_CBS_CFS:
1984 format |= TWL4030_VIF_SLAVE_EN;
1985 break;
1986 default:
1987 return -EINVAL;
1988 }
1989
1990 /* clock inversion */
1991 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1992 case SND_SOC_DAIFMT_IB_NF:
1993 format &= ~(TWL4030_VIF_FORMAT);
1994 break;
1995 case SND_SOC_DAIFMT_NB_IF:
1996 format |= TWL4030_VIF_FORMAT;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 if (format != old_format) {
2003 /* change format and set CODECPDZ */
2004 twl4030_codec_enable(codec, 0);
2005 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2006 twl4030_codec_enable(codec, 1);
2007 }
2008
2009 return 0;
2010}
2011
68140443
LCM		 2012static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2013{
2014 struct snd_soc_codec *codec = dai->codec;
2015 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2016
2017 if (tristate)
2018 reg |= TWL4030_VIF_TRI_EN;
2019 else
2020 reg &= ~TWL4030_VIF_TRI_EN;
2021
2022 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2023}
2024
bbba9444 2025#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2026#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2027
10d9e3d9 2028static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2029 .startup = twl4030_startup,
2030 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2031 .hw_params = twl4030_hw_params,
2032 .set_sysclk = twl4030_set_dai_sysclk,
2033 .set_fmt = twl4030_set_dai_fmt,
68140443 2034 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2035};
2036
7154b3e8
JS		 2037static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2038 .startup = twl4030_voice_startup,
b7a755a8 2039 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2040 .hw_params = twl4030_voice_hw_params,
2041 .set_sysclk = twl4030_voice_set_dai_sysclk,
2042 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2043 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2044};
2045
2046struct snd_soc_dai twl4030_dai[] = {
2047{
cc17557e
SS		 2048 .name = "twl4030",
2049 .playback = {
b4852b79 2050 .stream_name = "HiFi Playback",
cc17557e 2051 .channels_min = 2,
8a1f936a 2052 .channels_max = 4,
31ad0f31 2053 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2054 .formats = TWL4030_FORMATS,},
2055 .capture = {
2056 .stream_name = "Capture",
2057 .channels_min = 2,
8a1f936a 2058 .channels_max = 4,
cc17557e
SS		 2059 .rates = TWL4030_RATES,
2060 .formats = TWL4030_FORMATS,},
10d9e3d9 2061 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2062},
2063{
2064 .name = "twl4030 Voice",
2065 .playback = {
b4852b79 2066 .stream_name = "Voice Playback",
7154b3e8
JS		 2067 .channels_min = 1,
2068 .channels_max = 1,
2069 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2070 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2071 .capture = {
2072 .stream_name = "Capture",
2073 .channels_min = 1,
2074 .channels_max = 2,
2075 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2076 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2077 .ops = &twl4030_dai_voice_ops,
2078},
cc17557e
SS		 2079};
2080EXPORT_SYMBOL_GPL(twl4030_dai);
2081
7a1fecf5 2082static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2083{
2084 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2085 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2086
2087 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2088
2089 return 0;
2090}
2091
7a1fecf5 2092static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2093{
2094 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2095 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2096
2097 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2098 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2099 return 0;
2100}
2101
7a1fecf5 2102static struct snd_soc_codec *twl4030_codec;
cc17557e 2103
7a1fecf5 2104static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2105{
7a1fecf5 2106 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
9da28c7b 2107 struct twl4030_setup_data *setup = socdev->codec_data;
7a1fecf5
PU		 2108 struct snd_soc_codec *codec;
2109 struct twl4030_priv *twl4030;
2110 int ret;
cc17557e 2111
7a1fecf5 2112 BUG_ON(!twl4030_codec);
cc17557e 2113
7a1fecf5
PU		 2114 codec = twl4030_codec;
2115 twl4030 = codec->private_data;
2116 socdev->card->codec = codec;
cc17557e 2117
9da28c7b
PU		 2118 /* Configuration for headset ramp delay from setup data */
2119 if (setup) {
2120 unsigned char hs_pop;
2121
68d01955
PU		 2122 if (setup->sysclk != twl4030->sysclk)
2123 dev_warn(&pdev->dev,
2124 "Mismatch in APLL mclk: %u (configured: %u)\n",
2125 setup->sysclk, twl4030->sysclk);
9da28c7b
PU		 2126
2127 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2128 hs_pop &= ~TWL4030_RAMP_DELAY;
2129 hs_pop |= (setup->ramp_delay_value << 2);
2130 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
9da28c7b
PU		 2131 }
2132
cc17557e
SS		 2133 /* register pcms */
2134 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2135 if (ret < 0) {
7a1fecf5
PU		 2136 dev_err(&pdev->dev, "failed to create pcms\n");
2137 return ret;
cc17557e
SS		 2138 }
2139
3e8e1952
IM		 2140 snd_soc_add_controls(codec, twl4030_snd_controls,
2141 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2142 twl4030_add_widgets(codec);
2143
7a1fecf5 2144 return 0;
cc17557e
SS		 2145}
2146
7a1fecf5 2147static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2148{
2149 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2150 struct snd_soc_codec *codec = socdev->card->codec;
2151
2152 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2153 snd_soc_free_pcms(socdev);
2154 snd_soc_dapm_free(socdev);
2155 kfree(codec->private_data);
2156 kfree(codec);
2157
2158 return 0;
2159}
2160
2161static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2162{
2163 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2164 struct snd_soc_codec *codec;
7393958f 2165 struct twl4030_priv *twl4030;
7a1fecf5 2166 int ret;
cc17557e 2167
68d01955
PU		 2168 if (!pdata) {
2169 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2170 return -EINVAL;
2171 }
cc17557e 2172
7393958f
PU		 2173 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2174 if (twl4030 == NULL) {
7a1fecf5 2175 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2176 return -ENOMEM;
2177 }
2178
7a1fecf5 2179 codec = &twl4030->codec;
7393958f 2180 codec->private_data = twl4030;
7a1fecf5
PU		 2181 codec->dev = &pdev->dev;
2182 twl4030_dai[0].dev = &pdev->dev;
2183 twl4030_dai[1].dev = &pdev->dev;
2184
cc17557e
SS		 2185 mutex_init(&codec->mutex);
2186 INIT_LIST_HEAD(&codec->dapm_widgets);
2187 INIT_LIST_HEAD(&codec->dapm_paths);
2188
7a1fecf5
PU		 2189 codec->name = "twl4030";
2190 codec->owner = THIS_MODULE;
2191 codec->read = twl4030_read_reg_cache;
2192 codec->write = twl4030_write;
2193 codec->set_bias_level = twl4030_set_bias_level;
2194 codec->dai = twl4030_dai;
2195 codec->num_dai = ARRAY_SIZE(twl4030_dai),
2196 codec->reg_cache_size = sizeof(twl4030_reg);
2197 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2198 GFP_KERNEL);
2199 if (codec->reg_cache == NULL) {
2200 ret = -ENOMEM;
2201 goto error_cache;
2202 }
2203
2204 platform_set_drvdata(pdev, twl4030);
2205 twl4030_codec = codec;
2206
2207 /* Set the defaults, and power up the codec */
68d01955 2208 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
7a1fecf5 2209 twl4030_init_chip(codec);
b3f5a272 2210 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2211 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2212
2213 ret = snd_soc_register_codec(codec);
2214 if (ret != 0) {
2215 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2216 goto error_codec;
2217 }
2218
2219 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2220 if (ret != 0) {
2221 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2222 snd_soc_unregister_codec(codec);
2223 goto error_codec;
2224 }
cc17557e
SS		 2225
2226 return 0;
7a1fecf5
PU		 2227
2228error_codec:
2229 twl4030_power_down(codec);
2230 kfree(codec->reg_cache);
2231error_cache:
2232 kfree(twl4030);
2233 return ret;
cc17557e
SS		 2234}
2235
7a1fecf5 2236static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2237{
7a1fecf5 2238 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2239
7a1fecf5 2240 kfree(twl4030);
cc17557e 2241
7a1fecf5 2242 twl4030_codec = NULL;
cc17557e
SS		 2243 return 0;
2244}
2245
7a1fecf5
PU		 2246MODULE_ALIAS("platform:twl4030_codec_audio");
2247
2248static struct platform_driver twl4030_codec_driver = {
2249 .probe = twl4030_codec_probe,
2250 .remove = __devexit_p(twl4030_codec_remove),
2251 .driver = {
2252 .name = "twl4030_codec_audio",
2253 .owner = THIS_MODULE,
2254 },
cc17557e 2255};
cc17557e 2256
24e07db8 2257static int __init twl4030_modinit(void)
64089b84 2258{
7a1fecf5 2259 return platform_driver_register(&twl4030_codec_driver);
64089b84 2260}
24e07db8 2261module_init(twl4030_modinit);
64089b84
MB		 2262
2263static void __exit twl4030_exit(void)
2264{
7a1fecf5 2265 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2266}
2267module_exit(twl4030_exit);
2268
7a1fecf5
PU		 2269struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2270 .probe = twl4030_soc_probe,
2271 .remove = twl4030_soc_remove,
2272 .suspend = twl4030_soc_suspend,
2273 .resume = twl4030_soc_resume,
2274};
2275EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2276
cc17557e
SS		 2277MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2278MODULE_AUTHOR("Steve Sakoman");
2279MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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