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ASoC: TWL4030: Fix Analog capture path for AUXR
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
7393958f
PU		 133};
134
cc17557e
SS		 135/*
136 * read twl4030 register cache
137 */
138static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140{
141 u8 *cache = codec->reg_cache;
142
91432e97
IM		 143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
cc17557e
SS		 146 return cache[reg];
147}
148
149/*
150 * write twl4030 register cache
151 */
152static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154{
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160}
161
162/*
163 * write to the twl4030 register space
164 */
165static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167{
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170}
171
db04e2c5 172static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 173{
7393958f 174 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 175 u8 mode;
176
7393958f
PU		 177 if (enable == twl4030->codec_powered)
178 return;
179
cc17557e 180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
cc17557e 185
db04e2c5 186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 187 twl4030->codec_powered = enable;
cc17557e
SS		 188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192}
193
194static void twl4030_init_chip(struct snd_soc_codec *codec)
195{
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 199 twl4030_codec_enable(codec, 0);
cc17557e
SS		 200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205}
206
7393958f
PU		 207static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208{
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 240 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272}
273
006f367e
PU		 274static void twl4030_power_up(struct snd_soc_codec *codec)
275{
7393958f 276 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
7393958f
PU		 280 if (twl4030->codec_powered)
281 return;
282
006f367e
PU		 283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312}
313
7393958f
PU		 314/*
315 * Unconditional power down
316 */
006f367e
PU		 317static void twl4030_power_down(struct snd_soc_codec *codec)
318{
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321}
322
5e98a464 323/* Earpiece */
1a787e7a
JS		 324static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
326 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
327 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
328 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
329};
5e98a464 330
2a6f5c58 331/* PreDrive Left */
1a787e7a
JS		 332static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
337};
2a6f5c58
PU		 338
339/* PreDrive Right */
1a787e7a
JS		 340static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
345};
2a6f5c58 346
dfad21a2 347/* Headset Left */
1a787e7a
JS		 348static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
352};
dfad21a2
PU		 353
354/* Headset Right */
1a787e7a
JS		 355static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
357 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
358 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
359};
dfad21a2 360
5152d8c2 361/* Carkit Left */
1a787e7a
JS		 362static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
366};
5152d8c2
PU		 367
368/* Carkit Right */
1a787e7a
JS		 369static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
370 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
371 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
372 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
373};
5152d8c2 374
df339804
PU		 375/* Handsfree Left */
376static const char *twl4030_handsfreel_texts[] =
1a787e7a 377 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 378
379static const struct soc_enum twl4030_handsfreel_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
381 ARRAY_SIZE(twl4030_handsfreel_texts),
382 twl4030_handsfreel_texts);
383
384static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
385SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
386
387/* Handsfree Right */
388static const char *twl4030_handsfreer_texts[] =
1a787e7a 389 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreer_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreer_texts),
394 twl4030_handsfreer_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
398
376f7839
PU		 399/* Vibra */
400/* Vibra audio path selection */
401static const char *twl4030_vibra_texts[] =
402 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
403
404static const struct soc_enum twl4030_vibra_enum =
405 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
406 ARRAY_SIZE(twl4030_vibra_texts),
407 twl4030_vibra_texts);
408
409static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
410SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
411
412/* Vibra path selection: local vibrator (PWM) or audio driven */
413static const char *twl4030_vibrapath_texts[] =
414 {"Local vibrator", "Audio"};
415
416static const struct soc_enum twl4030_vibrapath_enum =
417 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
418 ARRAY_SIZE(twl4030_vibrapath_texts),
419 twl4030_vibrapath_texts);
420
421static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
422SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
423
276c6222 424/* Left analog microphone selection */
97b8096d
JS		 425static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
426 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
427 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
428 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
429 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
430};
276c6222
PU		 431
432/* Right analog microphone selection */
97b8096d
JS		 433static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
434 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 435 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 436};
276c6222
PU		 437
438/* TX1 L/R Analog/Digital microphone selection */
439static const char *twl4030_micpathtx1_texts[] =
440 {"Analog", "Digimic0"};
441
442static const struct soc_enum twl4030_micpathtx1_enum =
443 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
444 ARRAY_SIZE(twl4030_micpathtx1_texts),
445 twl4030_micpathtx1_texts);
446
447static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
448SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
449
450/* TX2 L/R Analog/Digital microphone selection */
451static const char *twl4030_micpathtx2_texts[] =
452 {"Analog", "Digimic1"};
453
454static const struct soc_enum twl4030_micpathtx2_enum =
455 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
456 ARRAY_SIZE(twl4030_micpathtx2_texts),
457 twl4030_micpathtx2_texts);
458
459static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
460SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
461
7393958f
PU		 462/* Analog bypass for AudioR1 */
463static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
464 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
465
466/* Analog bypass for AudioL1 */
467static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
468 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
469
470/* Analog bypass for AudioR2 */
471static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
472 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
473
474/* Analog bypass for AudioL2 */
475static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
476 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
477
fcd274a3
LCM		 478/* Analog bypass for Voice */
479static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
480 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
481
6bab83fd
PU		 482/* Digital bypass gain, 0 mutes the bypass */
483static const unsigned int twl4030_dapm_dbypass_tlv[] = {
484 TLV_DB_RANGE_HEAD(2),
485 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
486 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
487};
488
489/* Digital bypass left (TX1L -> RX2L) */
490static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
491 SOC_DAPM_SINGLE_TLV("Volume",
492 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
493 twl4030_dapm_dbypass_tlv);
494
495/* Digital bypass right (TX1R -> RX2R) */
496static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
497 SOC_DAPM_SINGLE_TLV("Volume",
498 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
499 twl4030_dapm_dbypass_tlv);
500
ee8f6894
LCM		 501/*
502 * Voice Sidetone GAIN volume control:
503 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
504 */
505static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
506
507/* Digital bypass voice: sidetone (VUL -> VDL)*/
508static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
509 SOC_DAPM_SINGLE_TLV("Volume",
510 TWL4030_REG_VSTPGA, 0, 0x29, 0,
511 twl4030_dapm_dbypassv_tlv);
512
276c6222
PU		 513static int micpath_event(struct snd_soc_dapm_widget *w,
514 struct snd_kcontrol *kcontrol, int event)
515{
516 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
517 unsigned char adcmicsel, micbias_ctl;
518
519 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
520 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
521 /* Prepare the bits for the given TX path:
522 * shift_l == 0: TX1 microphone path
523 * shift_l == 2: TX2 microphone path */
524 if (e->shift_l) {
525 /* TX2 microphone path */
526 if (adcmicsel & TWL4030_TX2IN_SEL)
527 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
528 else
529 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
530 } else {
531 /* TX1 microphone path */
532 if (adcmicsel & TWL4030_TX1IN_SEL)
533 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
534 else
535 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
536 }
537
538 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
539
540 return 0;
541}
542
49d92c7d
SM		 543static int handsfree_event(struct snd_soc_dapm_widget *w,
544 struct snd_kcontrol *kcontrol, int event)
545{
546 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
547 unsigned char hs_ctl;
548
549 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
550
551 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
552 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
553 twl4030_write(w->codec, e->reg, hs_ctl);
554 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
555 twl4030_write(w->codec, e->reg, hs_ctl);
556 hs_ctl |= TWL4030_HF_CTL_HB_EN;
557 twl4030_write(w->codec, e->reg, hs_ctl);
558 } else {
559 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
560 | TWL4030_HF_CTL_HB_EN);
561 twl4030_write(w->codec, e->reg, hs_ctl);
562 }
563
564 return 0;
565}
566
aad749e5
PU		 567static int headsetl_event(struct snd_soc_dapm_widget *w,
568 struct snd_kcontrol *kcontrol, int event)
569{
570 unsigned char hs_gain, hs_pop;
571
572 /* Save the current volume */
573 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
89492be8 574 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
aad749e5
PU		 575
576 switch (event) {
577 case SND_SOC_DAPM_POST_PMU:
578 /* Do the anti-pop/bias ramp enable according to the TRM */
aad749e5
PU		 579 hs_pop |= TWL4030_VMID_EN;
580 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
581 /* Is this needed? Can we just use whatever gain here? */
582 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
583 (hs_gain & (~0x0f)) | 0x0a);
584 hs_pop |= TWL4030_RAMP_EN;
585 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
586
587 /* Restore the original volume */
588 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
589 break;
590 case SND_SOC_DAPM_POST_PMD:
591 /* Do the anti-pop/bias ramp disable according to the TRM */
aad749e5
PU		 592 hs_pop &= ~TWL4030_RAMP_EN;
593 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
594 /* Bypass the reg_cache to mute the headset */
595 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
596 hs_gain & (~0x0f),
597 TWL4030_REG_HS_GAIN_SET);
598 hs_pop &= ~TWL4030_VMID_EN;
599 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
600 break;
601 }
602 return 0;
603}
604
7393958f
PU		 605static int bypass_event(struct snd_soc_dapm_widget *w,
606 struct snd_kcontrol *kcontrol, int event)
607{
608 struct soc_mixer_control *m =
609 (struct soc_mixer_control *)w->kcontrols->private_value;
610 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 611 unsigned char reg, misc;
7393958f
PU		 612
613 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 614
615 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
616 /* Analog bypass */
617 if (reg & (1 << m->shift))
618 twl4030->bypass_state |=
619 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
620 else
621 twl4030->bypass_state &=
622 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 623 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
624 /* Analog voice bypass */
625 if (reg & (1 << m->shift))
626 twl4030->bypass_state |= (1 << 4);
627 else
628 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 629 } else if (m->reg == TWL4030_REG_VSTPGA) {
630 /* Voice digital bypass */
631 if (reg)
632 twl4030->bypass_state |= (1 << 5);
633 else
634 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 635 } else {
636 /* Digital bypass */
637 if (reg & (0x7 << m->shift))
ee8f6894 638 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 639 else
ee8f6894 640 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 641 }
7393958f 642
fcd274a3
LCM		 643 /* Enable master analog loopback mode if any analog switch is enabled*/
644 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
645 if (twl4030->bypass_state & 0x1F)
646 misc |= TWL4030_FMLOOP_EN;
647 else
648 misc &= ~TWL4030_FMLOOP_EN;
649 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
650
7393958f
PU		 651 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
652 if (twl4030->bypass_state)
653 twl4030_codec_mute(w->codec, 0);
654 else
655 twl4030_codec_mute(w->codec, 1);
656 }
657 return 0;
658}
659
b0bd53a7
PU		 660/*
661 * Some of the gain controls in TWL (mostly those which are associated with
662 * the outputs) are implemented in an interesting way:
663 * 0x0 : Power down (mute)
664 * 0x1 : 6dB
665 * 0x2 : 0 dB
666 * 0x3 : -6 dB
667 * Inverting not going to help with these.
668 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
669 */
670#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
671 xinvert, tlv_array) \
672{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
673 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
674 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
675 .tlv.p = (tlv_array), \
676 .info = snd_soc_info_volsw, \
677 .get = snd_soc_get_volsw_twl4030, \
678 .put = snd_soc_put_volsw_twl4030, \
679 .private_value = (unsigned long)&(struct soc_mixer_control) \
680 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
681 .max = xmax, .invert = xinvert} }
682#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
683 xinvert, tlv_array) \
684{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
685 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
686 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
687 .tlv.p = (tlv_array), \
688 .info = snd_soc_info_volsw_2r, \
689 .get = snd_soc_get_volsw_r2_twl4030,\
690 .put = snd_soc_put_volsw_r2_twl4030, \
691 .private_value = (unsigned long)&(struct soc_mixer_control) \
692 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 693 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 694#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
695 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
696 xinvert, tlv_array)
697
698static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700{
701 struct soc_mixer_control *mc =
702 (struct soc_mixer_control *)kcontrol->private_value;
703 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
704 unsigned int reg = mc->reg;
705 unsigned int shift = mc->shift;
706 unsigned int rshift = mc->rshift;
707 int max = mc->max;
708 int mask = (1 << fls(max)) - 1;
709
710 ucontrol->value.integer.value[0] =
711 (snd_soc_read(codec, reg) >> shift) & mask;
712 if (ucontrol->value.integer.value[0])
713 ucontrol->value.integer.value[0] =
714 max + 1 - ucontrol->value.integer.value[0];
715
716 if (shift != rshift) {
717 ucontrol->value.integer.value[1] =
718 (snd_soc_read(codec, reg) >> rshift) & mask;
719 if (ucontrol->value.integer.value[1])
720 ucontrol->value.integer.value[1] =
721 max + 1 - ucontrol->value.integer.value[1];
722 }
723
724 return 0;
725}
726
727static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_value *ucontrol)
729{
730 struct soc_mixer_control *mc =
731 (struct soc_mixer_control *)kcontrol->private_value;
732 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
733 unsigned int reg = mc->reg;
734 unsigned int shift = mc->shift;
735 unsigned int rshift = mc->rshift;
736 int max = mc->max;
737 int mask = (1 << fls(max)) - 1;
738 unsigned short val, val2, val_mask;
739
740 val = (ucontrol->value.integer.value[0] & mask);
741
742 val_mask = mask << shift;
743 if (val)
744 val = max + 1 - val;
745 val = val << shift;
746 if (shift != rshift) {
747 val2 = (ucontrol->value.integer.value[1] & mask);
748 val_mask |= mask << rshift;
749 if (val2)
750 val2 = max + 1 - val2;
751 val |= val2 << rshift;
752 }
753 return snd_soc_update_bits(codec, reg, val_mask, val);
754}
755
756static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_value *ucontrol)
758{
759 struct soc_mixer_control *mc =
760 (struct soc_mixer_control *)kcontrol->private_value;
761 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
762 unsigned int reg = mc->reg;
763 unsigned int reg2 = mc->rreg;
764 unsigned int shift = mc->shift;
765 int max = mc->max;
766 int mask = (1<<fls(max))-1;
767
768 ucontrol->value.integer.value[0] =
769 (snd_soc_read(codec, reg) >> shift) & mask;
770 ucontrol->value.integer.value[1] =
771 (snd_soc_read(codec, reg2) >> shift) & mask;
772
773 if (ucontrol->value.integer.value[0])
774 ucontrol->value.integer.value[0] =
775 max + 1 - ucontrol->value.integer.value[0];
776 if (ucontrol->value.integer.value[1])
777 ucontrol->value.integer.value[1] =
778 max + 1 - ucontrol->value.integer.value[1];
779
780 return 0;
781}
782
783static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785{
786 struct soc_mixer_control *mc =
787 (struct soc_mixer_control *)kcontrol->private_value;
788 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
789 unsigned int reg = mc->reg;
790 unsigned int reg2 = mc->rreg;
791 unsigned int shift = mc->shift;
792 int max = mc->max;
793 int mask = (1 << fls(max)) - 1;
794 int err;
795 unsigned short val, val2, val_mask;
796
797 val_mask = mask << shift;
798 val = (ucontrol->value.integer.value[0] & mask);
799 val2 = (ucontrol->value.integer.value[1] & mask);
800
801 if (val)
802 val = max + 1 - val;
803 if (val2)
804 val2 = max + 1 - val2;
805
806 val = val << shift;
807 val2 = val2 << shift;
808
809 err = snd_soc_update_bits(codec, reg, val_mask, val);
810 if (err < 0)
811 return err;
812
813 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
814 return err;
815}
816
c10b82cf
PU		 817/*
818 * FGAIN volume control:
819 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
820 */
d889a72c 821static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 822
0d33ea0b
PU		 823/*
824 * CGAIN volume control:
825 * 0 dB to 12 dB in 6 dB steps
826 * value 2 and 3 means 12 dB
827 */
d889a72c
PU		 828static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
829
1a787e7a
JS		 830/*
831 * Voice Downlink GAIN volume control:
832 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
833 */
834static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
835
d889a72c
PU		 836/*
837 * Analog playback gain
838 * -24 dB to 12 dB in 2 dB steps
839 */
840static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 841
4290239c
PU		 842/*
843 * Gain controls tied to outputs
844 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
845 */
846static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
847
18cc8d8d
JS		 848/*
849 * Gain control for earpiece amplifier
850 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
851 */
852static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
853
381a22b5
PU		 854/*
855 * Capture gain after the ADCs
856 * from 0 dB to 31 dB in 1 dB steps
857 */
858static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
859
5920b453
GI		 860/*
861 * Gain control for input amplifiers
862 * 0 dB to 30 dB in 6 dB steps
863 */
864static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
865
89492be8
PU		 866static const char *twl4030_rampdelay_texts[] = {
867 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
868 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
869 "3495/2581/1748 ms"
870};
871
872static const struct soc_enum twl4030_rampdelay_enum =
873 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
874 ARRAY_SIZE(twl4030_rampdelay_texts),
875 twl4030_rampdelay_texts);
876
376f7839
PU		 877/* Vibra H-bridge direction mode */
878static const char *twl4030_vibradirmode_texts[] = {
879 "Vibra H-bridge direction", "Audio data MSB",
880};
881
882static const struct soc_enum twl4030_vibradirmode_enum =
883 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
884 ARRAY_SIZE(twl4030_vibradirmode_texts),
885 twl4030_vibradirmode_texts);
886
887/* Vibra H-bridge direction */
888static const char *twl4030_vibradir_texts[] = {
889 "Positive polarity", "Negative polarity",
890};
891
892static const struct soc_enum twl4030_vibradir_enum =
893 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
894 ARRAY_SIZE(twl4030_vibradir_texts),
895 twl4030_vibradir_texts);
896
cc17557e 897static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 898 /* Common playback gain controls */
899 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
900 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
901 0, 0x3f, 0, digital_fine_tlv),
902 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
903 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
904 0, 0x3f, 0, digital_fine_tlv),
905
906 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
907 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
908 6, 0x2, 0, digital_coarse_tlv),
909 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
910 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
911 6, 0x2, 0, digital_coarse_tlv),
912
913 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
914 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
915 3, 0x12, 1, analog_tlv),
916 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
917 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
918 3, 0x12, 1, analog_tlv),
44c55870
PU		 919 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
920 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
921 1, 1, 0),
922 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
923 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
924 1, 1, 0),
381a22b5 925
1a787e7a
JS		 926 /* Common voice downlink gain controls */
927 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
928 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
929
930 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
931 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
932
933 SOC_SINGLE("DAC Voice Analog Downlink Switch",
934 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
935
4290239c
PU		 936 /* Separate output gain controls */
937 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
938 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
939 4, 3, 0, output_tvl),
940
941 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
942 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
943
944 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
945 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
946 4, 3, 0, output_tvl),
947
948 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 949 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 950
381a22b5 951 /* Common capture gain controls */
276c6222 952 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 953 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
954 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 955 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
956 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
957 0, 0x1f, 0, digital_capture_tlv),
5920b453 958
276c6222 959 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 960 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 961
962 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 963
964 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
965 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 966};
967
cc17557e 968static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 969 /* Left channel inputs */
970 SND_SOC_DAPM_INPUT("MAINMIC"),
971 SND_SOC_DAPM_INPUT("HSMIC"),
972 SND_SOC_DAPM_INPUT("AUXL"),
973 SND_SOC_DAPM_INPUT("CARKITMIC"),
974 /* Right channel inputs */
975 SND_SOC_DAPM_INPUT("SUBMIC"),
976 SND_SOC_DAPM_INPUT("AUXR"),
977 /* Digital microphones (Stereo) */
978 SND_SOC_DAPM_INPUT("DIGIMIC0"),
979 SND_SOC_DAPM_INPUT("DIGIMIC1"),
980
981 /* Outputs */
cc17557e
SS		 982 SND_SOC_DAPM_OUTPUT("OUTL"),
983 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 984 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 985 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
986 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 987 SND_SOC_DAPM_OUTPUT("HSOL"),
988 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 989 SND_SOC_DAPM_OUTPUT("CARKITL"),
990 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 991 SND_SOC_DAPM_OUTPUT("HFL"),
992 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 993 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 994
53b5047d 995 /* DACs */
1e5fa31f 996 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 997 SND_SOC_NOPM, 0, 0),
1e5fa31f 998 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 999 SND_SOC_NOPM, 0, 0),
1e5fa31f 1000 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 1001 SND_SOC_NOPM, 0, 0),
1e5fa31f 1002 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 1003 SND_SOC_NOPM, 0, 0),
1a787e7a 1004 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1005 SND_SOC_NOPM, 0, 0),
cc17557e 1006
44c55870
PU		 1007 /* Analog PGAs */
1008 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
1009 0, 0, NULL, 0),
1010 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
1011 0, 0, NULL, 0),
1012 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
1013 0, 0, NULL, 0),
1014 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
1015 0, 0, NULL, 0),
1a787e7a
JS		 1016 SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
1017 0, 0, NULL, 0),
44c55870 1018
7393958f
PU		 1019 /* Analog bypasses */
1020 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1021 &twl4030_dapm_abypassr1_control, bypass_event,
1022 SND_SOC_DAPM_POST_REG),
1023 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1024 &twl4030_dapm_abypassl1_control,
1025 bypass_event, SND_SOC_DAPM_POST_REG),
1026 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1027 &twl4030_dapm_abypassr2_control,
1028 bypass_event, SND_SOC_DAPM_POST_REG),
1029 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1030 &twl4030_dapm_abypassl2_control,
1031 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1032 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1033 &twl4030_dapm_abypassv_control,
1034 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1035
6bab83fd
PU		 1036 /* Digital bypasses */
1037 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1038 &twl4030_dapm_dbypassl_control, bypass_event,
1039 SND_SOC_DAPM_POST_REG),
1040 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1041 &twl4030_dapm_dbypassr_control, bypass_event,
1042 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1043 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1044 &twl4030_dapm_dbypassv_control, bypass_event,
1045 SND_SOC_DAPM_POST_REG),
6bab83fd 1046
7393958f
PU		 1047 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1048 0, 0, NULL, 0),
1049 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1050 1, 0, NULL, 0),
1051 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1052 2, 0, NULL, 0),
1053 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1054 3, 0, NULL, 0),
fcd274a3
LCM		 1055 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", TWL4030_REG_AVDAC_CTL,
1056 4, 0, NULL, 0),
7393958f 1057
1a787e7a 1058 /* Output MIXER controls */
5e98a464 1059 /* Earpiece */
1a787e7a
JS		 1060 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1061 &twl4030_dapm_earpiece_controls[0],
1062 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1063 /* PreDrivL/R */
1a787e7a
JS		 1064 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1065 &twl4030_dapm_predrivel_controls[0],
1066 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1067 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1068 &twl4030_dapm_predriver_controls[0],
1069 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1070 /* HeadsetL/R */
1a787e7a
JS		 1071 SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1072 &twl4030_dapm_hsol_controls[0],
1073 ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
1074 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1075 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1076 &twl4030_dapm_hsor_controls[0],
1077 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
5152d8c2 1078 /* CarkitL/R */
1a787e7a
JS		 1079 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1080 &twl4030_dapm_carkitl_controls[0],
1081 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1082 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1083 &twl4030_dapm_carkitr_controls[0],
1084 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1085
1086 /* Output MUX controls */
df339804 1087 /* HandsfreeL/R */
49d92c7d
SM		 1088 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1089 &twl4030_dapm_handsfreel_control, handsfree_event,
1090 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1091 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1092 &twl4030_dapm_handsfreer_control, handsfree_event,
1093 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1094 /* Vibra */
1095 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1096 &twl4030_dapm_vibra_control),
1097 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1098 &twl4030_dapm_vibrapath_control),
5e98a464 1099
276c6222
PU		 1100 /* Introducing four virtual ADC, since TWL4030 have four channel for
1101 capture */
1102 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1103 SND_SOC_NOPM, 0, 0),
1104 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1105 SND_SOC_NOPM, 0, 0),
1106 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1107 SND_SOC_NOPM, 0, 0),
1108 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1109 SND_SOC_NOPM, 0, 0),
1110
1111 /* Analog/Digital mic path selection.
1112 TX1 Left/Right: either analog Left/Right or Digimic0
1113 TX2 Left/Right: either analog Left/Right or Digimic1 */
1114 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1115 &twl4030_dapm_micpathtx1_control, micpath_event,
1116 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1117 SND_SOC_DAPM_POST_REG),
1118 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1119 &twl4030_dapm_micpathtx2_control, micpath_event,
1120 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1121 SND_SOC_DAPM_POST_REG),
1122
97b8096d
JS		 1123 /* Analog input mixers for the capture amplifiers */
1124 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1125 TWL4030_REG_ANAMICL, 4, 0,
1126 &twl4030_dapm_analoglmic_controls[0],
1127 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1128 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1129 TWL4030_REG_ANAMICR, 4, 0,
1130 &twl4030_dapm_analogrmic_controls[0],
1131 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1132
fb2a2f84
PU		 1133 SND_SOC_DAPM_PGA("ADC Physical Left",
1134 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1135 SND_SOC_DAPM_PGA("ADC Physical Right",
1136 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1137
1138 SND_SOC_DAPM_PGA("Digimic0 Enable",
1139 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1140 SND_SOC_DAPM_PGA("Digimic1 Enable",
1141 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1142
1143 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1144 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1145 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1146
cc17557e
SS		 1147};
1148
1149static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1150 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1151 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1152 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1153 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
fcd274a3 1154 {"Analog Voice Playback Mixer", NULL, "DAC Voice"},
7393958f
PU		 1155
1156 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1157 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1158 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1159 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
fcd274a3 1160 {"VDL_APGA", NULL, "Analog Voice Playback Mixer"},
1a787e7a 1161
5e98a464
PU		 1162 /* Internal playback routings */
1163 /* Earpiece */
1a787e7a
JS		 1164 {"Earpiece Mixer", "Voice", "VDL_APGA"},
1165 {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
1166 {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
1167 {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
2a6f5c58 1168 /* PreDrivL */
1a787e7a
JS		 1169 {"PredriveL Mixer", "Voice", "VDL_APGA"},
1170 {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
1171 {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
1172 {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
2a6f5c58 1173 /* PreDrivR */
1a787e7a
JS		 1174 {"PredriveR Mixer", "Voice", "VDL_APGA"},
1175 {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
1176 {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
1177 {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1178 /* HeadsetL */
1a787e7a
JS		 1179 {"HeadsetL Mixer", "Voice", "VDL_APGA"},
1180 {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
1181 {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1182 /* HeadsetR */
1a787e7a
JS		 1183 {"HeadsetR Mixer", "Voice", "VDL_APGA"},
1184 {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
1185 {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
5152d8c2 1186 /* CarkitL */
1a787e7a
JS		 1187 {"CarkitL Mixer", "Voice", "VDL_APGA"},
1188 {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
1189 {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
5152d8c2 1190 /* CarkitR */
1a787e7a
JS		 1191 {"CarkitR Mixer", "Voice", "VDL_APGA"},
1192 {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
1193 {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
df339804 1194 /* HandsfreeL */
1a787e7a
JS		 1195 {"HandsfreeL Mux", "Voice", "VDL_APGA"},
1196 {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
1197 {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
1198 {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
df339804 1199 /* HandsfreeR */
1a787e7a
JS		 1200 {"HandsfreeR Mux", "Voice", "VDL_APGA"},
1201 {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
1202 {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
1203 {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
376f7839
PU		 1204 /* Vibra */
1205 {"Vibra Mux", "AudioL1", "DAC Left1"},
1206 {"Vibra Mux", "AudioR1", "DAC Right1"},
1207 {"Vibra Mux", "AudioL2", "DAC Left2"},
1208 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1209
cc17557e 1210 /* outputs */
44c55870
PU		 1211 {"OUTL", NULL, "ARXL2_APGA"},
1212 {"OUTR", NULL, "ARXR2_APGA"},
1a787e7a
JS		 1213 {"EARPIECE", NULL, "Earpiece Mixer"},
1214 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1215 {"PREDRIVER", NULL, "PredriveR Mixer"},
1216 {"HSOL", NULL, "HeadsetL Mixer"},
1217 {"HSOR", NULL, "HeadsetR Mixer"},
1218 {"CARKITL", NULL, "CarkitL Mixer"},
1219 {"CARKITR", NULL, "CarkitR Mixer"},
df339804
PU		 1220 {"HFL", NULL, "HandsfreeL Mux"},
1221 {"HFR", NULL, "HandsfreeR Mux"},
376f7839
PU		 1222 {"Vibra Route", "Audio", "Vibra Mux"},
1223 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1224
276c6222
PU		 1225 /* Capture path */
1226 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1227 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1228 {"Analog Left Capture Route", "AUXL", "AUXL"},
1229 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1230
1231 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1232 {"Analog Right Capture Route", "AUXR", "AUXR"},
1233
fb2a2f84
PU		 1234 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1235 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1236
1237 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1238 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1239
1240 /* TX1 Left capture path */
fb2a2f84 1241 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1242 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1243 /* TX1 Right capture path */
fb2a2f84 1244 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1245 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1246 /* TX2 Left capture path */
fb2a2f84 1247 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1248 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1249 /* TX2 Right capture path */
fb2a2f84 1250 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1251 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1252
1253 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1254 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1255 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1256 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1257
7393958f
PU		 1258 /* Analog bypass routes */
1259 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1260 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1261 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1262 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1263 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1264
1265 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1266 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1267 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1268 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1269 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1270
6bab83fd
PU		 1271 /* Digital bypass routes */
1272 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1273 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1274 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd
PU		 1275
1276 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1277 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
ee8f6894 1278 {"Analog Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1279
cc17557e
SS		 1280};
1281
1282static int twl4030_add_widgets(struct snd_soc_codec *codec)
1283{
1284 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1285 ARRAY_SIZE(twl4030_dapm_widgets));
1286
1287 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1288
1289 snd_soc_dapm_new_widgets(codec);
1290 return 0;
1291}
1292
cc17557e
SS		 1293static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1294 enum snd_soc_bias_level level)
1295{
7393958f
PU		 1296 struct twl4030_priv *twl4030 = codec->private_data;
1297
cc17557e
SS		 1298 switch (level) {
1299 case SND_SOC_BIAS_ON:
7393958f 1300 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1301 break;
1302 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1303 twl4030_power_up(codec);
1304 if (twl4030->bypass_state)
1305 twl4030_codec_mute(codec, 0);
1306 else
1307 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1308 break;
1309 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1310 twl4030_power_up(codec);
1311 if (twl4030->bypass_state)
1312 twl4030_codec_mute(codec, 0);
1313 else
1314 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1315 break;
1316 case SND_SOC_BIAS_OFF:
1317 twl4030_power_down(codec);
1318 break;
1319 }
1320 codec->bias_level = level;
1321
1322 return 0;
1323}
1324
6b87a91f
PU		 1325static void twl4030_constraints(struct twl4030_priv *twl4030,
1326 struct snd_pcm_substream *mst_substream)
1327{
1328 struct snd_pcm_substream *slv_substream;
1329
1330 /* Pick the stream, which need to be constrained */
1331 if (mst_substream == twl4030->master_substream)
1332 slv_substream = twl4030->slave_substream;
1333 else if (mst_substream == twl4030->slave_substream)
1334 slv_substream = twl4030->master_substream;
1335 else /* This should not happen.. */
1336 return;
1337
1338 /* Set the constraints according to the already configured stream */
1339 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1340 SNDRV_PCM_HW_PARAM_RATE,
1341 twl4030->rate,
1342 twl4030->rate);
1343
1344 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1345 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1346 twl4030->sample_bits,
1347 twl4030->sample_bits);
1348
1349 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1350 SNDRV_PCM_HW_PARAM_CHANNELS,
1351 twl4030->channels,
1352 twl4030->channels);
1353}
1354
8a1f936a
PU		 1355/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1356 * capture has to be enabled/disabled. */
1357static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1358 int enable)
1359{
1360 u8 reg, mask;
1361
1362 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1363
1364 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1365 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1366 else
1367 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1368
1369 if (enable)
1370 reg |= mask;
1371 else
1372 reg &= ~mask;
1373
1374 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1375}
1376
d6648da1
PU		 1377static int twl4030_startup(struct snd_pcm_substream *substream,
1378 struct snd_soc_dai *dai)
7220b9f4
PU		 1379{
1380 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1381 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1382 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1383 struct twl4030_priv *twl4030 = codec->private_data;
1384
7220b9f4 1385 if (twl4030->master_substream) {
7220b9f4 1386 twl4030->slave_substream = substream;
6b87a91f
PU		 1387 /* The DAI has one configuration for playback and capture, so
1388 * if the DAI has been already configured then constrain this
1389 * substream to match it. */
1390 if (twl4030->configured)
1391 twl4030_constraints(twl4030, twl4030->master_substream);
1392 } else {
8a1f936a
PU		 1393 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1394 TWL4030_OPTION_1)) {
1395 /* In option2 4 channel is not supported, set the
1396 * constraint for the first stream for channels, the
1397 * second stream will 'inherit' this cosntraint */
1398 snd_pcm_hw_constraint_minmax(substream->runtime,
1399 SNDRV_PCM_HW_PARAM_CHANNELS,
1400 2, 2);
1401 }
7220b9f4 1402 twl4030->master_substream = substream;
6b87a91f 1403 }
7220b9f4
PU		 1404
1405 return 0;
1406}
1407
d6648da1
PU		 1408static void twl4030_shutdown(struct snd_pcm_substream *substream,
1409 struct snd_soc_dai *dai)
7220b9f4
PU		 1410{
1411 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1412 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1413 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1414 struct twl4030_priv *twl4030 = codec->private_data;
1415
1416 if (twl4030->master_substream == substream)
1417 twl4030->master_substream = twl4030->slave_substream;
1418
1419 twl4030->slave_substream = NULL;
6b87a91f
PU		 1420
1421 /* If all streams are closed, or the remaining stream has not yet
1422 * been configured than set the DAI as not configured. */
1423 if (!twl4030->master_substream)
1424 twl4030->configured = 0;
1425 else if (!twl4030->master_substream->runtime->channels)
1426 twl4030->configured = 0;
8a1f936a
PU		 1427
1428 /* If the closing substream had 4 channel, do the necessary cleanup */
1429 if (substream->runtime->channels == 4)
1430 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1431}
1432
cc17557e 1433static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1434 struct snd_pcm_hw_params *params,
1435 struct snd_soc_dai *dai)
cc17557e
SS		 1436{
1437 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1438 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1439 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1440 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1441 u8 mode, old_mode, format, old_format;
1442
8a1f936a
PU		 1443 /* If the substream has 4 channel, do the necessary setup */
1444 if (params_channels(params) == 4) {
1445 /* Safety check: are we in the correct operating mode? */
1446 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1447 TWL4030_OPTION_1))
1448 twl4030_tdm_enable(codec, substream->stream, 1);
1449 else
1450 return -EINVAL;
1451 }
1452
6b87a91f
PU		 1453 if (twl4030->configured)
1454 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1455 return 0;
1456
cc17557e
SS		 1457 /* bit rate */
1458 old_mode = twl4030_read_reg_cache(codec,
1459 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1460 mode = old_mode & ~TWL4030_APLL_RATE;
1461
1462 switch (params_rate(params)) {
1463 case 8000:
1464 mode |= TWL4030_APLL_RATE_8000;
1465 break;
1466 case 11025:
1467 mode |= TWL4030_APLL_RATE_11025;
1468 break;
1469 case 12000:
1470 mode |= TWL4030_APLL_RATE_12000;
1471 break;
1472 case 16000:
1473 mode |= TWL4030_APLL_RATE_16000;
1474 break;
1475 case 22050:
1476 mode |= TWL4030_APLL_RATE_22050;
1477 break;
1478 case 24000:
1479 mode |= TWL4030_APLL_RATE_24000;
1480 break;
1481 case 32000:
1482 mode |= TWL4030_APLL_RATE_32000;
1483 break;
1484 case 44100:
1485 mode |= TWL4030_APLL_RATE_44100;
1486 break;
1487 case 48000:
1488 mode |= TWL4030_APLL_RATE_48000;
1489 break;
103f211d
PU		 1490 case 96000:
1491 mode |= TWL4030_APLL_RATE_96000;
1492 break;
cc17557e
SS		 1493 default:
1494 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1495 params_rate(params));
1496 return -EINVAL;
1497 }
1498
1499 if (mode != old_mode) {
1500 /* change rate and set CODECPDZ */
7393958f 1501 twl4030_codec_enable(codec, 0);
cc17557e 1502 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1503 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1504 }
1505
1506 /* sample size */
1507 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1508 format = old_format;
1509 format &= ~TWL4030_DATA_WIDTH;
1510 switch (params_format(params)) {
1511 case SNDRV_PCM_FORMAT_S16_LE:
1512 format |= TWL4030_DATA_WIDTH_16S_16W;
1513 break;
1514 case SNDRV_PCM_FORMAT_S24_LE:
1515 format |= TWL4030_DATA_WIDTH_32S_24W;
1516 break;
1517 default:
1518 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1519 params_format(params));
1520 return -EINVAL;
1521 }
1522
1523 if (format != old_format) {
1524
1525 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1526 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1527
1528 /* change format */
1529 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1530
1531 /* set CODECPDZ afterwards */
db04e2c5 1532 twl4030_codec_enable(codec, 1);
cc17557e 1533 }
6b87a91f
PU		 1534
1535 /* Store the important parameters for the DAI configuration and set
1536 * the DAI as configured */
1537 twl4030->configured = 1;
1538 twl4030->rate = params_rate(params);
1539 twl4030->sample_bits = hw_param_interval(params,
1540 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1541 twl4030->channels = params_channels(params);
1542
1543 /* If both playback and capture streams are open, and one of them
1544 * is setting the hw parameters right now (since we are here), set
1545 * constraints to the other stream to match the current one. */
1546 if (twl4030->slave_substream)
1547 twl4030_constraints(twl4030, substream);
1548
cc17557e
SS		 1549 return 0;
1550}
1551
1552static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1553 int clk_id, unsigned int freq, int dir)
1554{
1555 struct snd_soc_codec *codec = codec_dai->codec;
1556 u8 infreq;
1557
1558 switch (freq) {
1559 case 19200000:
1560 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1561 break;
1562 case 26000000:
1563 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1564 break;
1565 case 38400000:
1566 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1567 break;
1568 default:
1569 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1570 freq);
1571 return -EINVAL;
1572 }
1573
1574 infreq |= TWL4030_APLL_EN;
1575 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1576
1577 return 0;
1578}
1579
1580static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1581 unsigned int fmt)
1582{
1583 struct snd_soc_codec *codec = codec_dai->codec;
1584 u8 old_format, format;
1585
1586 /* get format */
1587 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1588 format = old_format;
1589
1590 /* set master/slave audio interface */
1591 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1592 case SND_SOC_DAIFMT_CBM_CFM:
1593 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1594 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1595 break;
1596 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1597 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1598 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1599 break;
1600 default:
1601 return -EINVAL;
1602 }
1603
1604 /* interface format */
1605 format &= ~TWL4030_AIF_FORMAT;
1606 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1607 case SND_SOC_DAIFMT_I2S:
1608 format |= TWL4030_AIF_FORMAT_CODEC;
1609 break;
8a1f936a
PU		 1610 case SND_SOC_DAIFMT_DSP_A:
1611 format |= TWL4030_AIF_FORMAT_TDM;
1612 break;
cc17557e
SS		 1613 default:
1614 return -EINVAL;
1615 }
1616
1617 if (format != old_format) {
1618
1619 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1620 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1621
1622 /* change format */
1623 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1624
1625 /* set CODECPDZ afterwards */
db04e2c5 1626 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1627 }
1628
1629 return 0;
1630}
1631
b7a755a8
MLC		 1632/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1633 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1634static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1635 int enable)
1636{
1637 u8 reg, mask;
1638
1639 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1640
1641 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1642 mask = TWL4030_ARXL1_VRX_EN;
1643 else
1644 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1645
1646 if (enable)
1647 reg |= mask;
1648 else
1649 reg &= ~mask;
1650
1651 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1652}
1653
7154b3e8
JS		 1654static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1655 struct snd_soc_dai *dai)
1656{
1657 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1658 struct snd_soc_device *socdev = rtd->socdev;
1659 struct snd_soc_codec *codec = socdev->card->codec;
1660 u8 infreq;
1661 u8 mode;
1662
1663 /* If the system master clock is not 26MHz, the voice PCM interface is
1664 * not avilable.
1665 */
1666 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1667 & TWL4030_APLL_INFREQ;
1668
1669 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1670 printk(KERN_ERR "TWL4030 voice startup: "
1671 "MCLK is not 26MHz, call set_sysclk() on init\n");
1672 return -EINVAL;
1673 }
1674
1675 /* If the codec mode is not option2, the voice PCM interface is not
1676 * avilable.
1677 */
1678 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1679 & TWL4030_OPT_MODE;
1680
1681 if (mode != TWL4030_OPTION_2) {
1682 printk(KERN_ERR "TWL4030 voice startup: "
1683 "the codec mode is not option2\n");
1684 return -EINVAL;
1685 }
1686
1687 return 0;
1688}
1689
b7a755a8
MLC		 1690static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1691 struct snd_soc_dai *dai)
1692{
1693 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1694 struct snd_soc_device *socdev = rtd->socdev;
1695 struct snd_soc_codec *codec = socdev->card->codec;
1696
1697 /* Enable voice digital filters */
1698 twl4030_voice_enable(codec, substream->stream, 0);
1699}
1700
7154b3e8
JS		 1701static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1702 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1703{
1704 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1705 struct snd_soc_device *socdev = rtd->socdev;
1706 struct snd_soc_codec *codec = socdev->card->codec;
1707 u8 old_mode, mode;
1708
b7a755a8
MLC		 1709 /* Enable voice digital filters */
1710 twl4030_voice_enable(codec, substream->stream, 1);
1711
7154b3e8
JS		 1712 /* bit rate */
1713 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1714 & ~(TWL4030_CODECPDZ);
1715 mode = old_mode;
1716
1717 switch (params_rate(params)) {
1718 case 8000:
1719 mode &= ~(TWL4030_SEL_16K);
1720 break;
1721 case 16000:
1722 mode |= TWL4030_SEL_16K;
1723 break;
1724 default:
1725 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1726 params_rate(params));
1727 return -EINVAL;
1728 }
1729
1730 if (mode != old_mode) {
1731 /* change rate and set CODECPDZ */
1732 twl4030_codec_enable(codec, 0);
1733 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1734 twl4030_codec_enable(codec, 1);
1735 }
1736
1737 return 0;
1738}
1739
1740static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1741 int clk_id, unsigned int freq, int dir)
1742{
1743 struct snd_soc_codec *codec = codec_dai->codec;
1744 u8 infreq;
1745
1746 switch (freq) {
1747 case 26000000:
1748 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1749 break;
1750 default:
1751 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1752 freq);
1753 return -EINVAL;
1754 }
1755
1756 infreq |= TWL4030_APLL_EN;
1757 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1758
1759 return 0;
1760}
1761
1762static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1763 unsigned int fmt)
1764{
1765 struct snd_soc_codec *codec = codec_dai->codec;
1766 u8 old_format, format;
1767
1768 /* get format */
1769 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1770 format = old_format;
1771
1772 /* set master/slave audio interface */
1773 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1774 case SND_SOC_DAIFMT_CBS_CFM:
1775 format &= ~(TWL4030_VIF_SLAVE_EN);
1776 break;
1777 case SND_SOC_DAIFMT_CBS_CFS:
1778 format |= TWL4030_VIF_SLAVE_EN;
1779 break;
1780 default:
1781 return -EINVAL;
1782 }
1783
1784 /* clock inversion */
1785 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1786 case SND_SOC_DAIFMT_IB_NF:
1787 format &= ~(TWL4030_VIF_FORMAT);
1788 break;
1789 case SND_SOC_DAIFMT_NB_IF:
1790 format |= TWL4030_VIF_FORMAT;
1791 break;
1792 default:
1793 return -EINVAL;
1794 }
1795
1796 if (format != old_format) {
1797 /* change format and set CODECPDZ */
1798 twl4030_codec_enable(codec, 0);
1799 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1800 twl4030_codec_enable(codec, 1);
1801 }
1802
1803 return 0;
1804}
1805
bbba9444 1806#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1807#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1808
10d9e3d9 1809static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1810 .startup = twl4030_startup,
1811 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1812 .hw_params = twl4030_hw_params,
1813 .set_sysclk = twl4030_set_dai_sysclk,
1814 .set_fmt = twl4030_set_dai_fmt,
1815};
1816
7154b3e8
JS		 1817static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1818 .startup = twl4030_voice_startup,
b7a755a8 1819 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 1820 .hw_params = twl4030_voice_hw_params,
1821 .set_sysclk = twl4030_voice_set_dai_sysclk,
1822 .set_fmt = twl4030_voice_set_dai_fmt,
1823};
1824
1825struct snd_soc_dai twl4030_dai[] = {
1826{
cc17557e
SS		 1827 .name = "twl4030",
1828 .playback = {
1829 .stream_name = "Playback",
1830 .channels_min = 2,
8a1f936a 1831 .channels_max = 4,
31ad0f31 1832 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1833 .formats = TWL4030_FORMATS,},
1834 .capture = {
1835 .stream_name = "Capture",
1836 .channels_min = 2,
8a1f936a 1837 .channels_max = 4,
cc17557e
SS		 1838 .rates = TWL4030_RATES,
1839 .formats = TWL4030_FORMATS,},
10d9e3d9 1840 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1841},
1842{
1843 .name = "twl4030 Voice",
1844 .playback = {
1845 .stream_name = "Playback",
1846 .channels_min = 1,
1847 .channels_max = 1,
1848 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1849 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1850 .capture = {
1851 .stream_name = "Capture",
1852 .channels_min = 1,
1853 .channels_max = 2,
1854 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1855 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1856 .ops = &twl4030_dai_voice_ops,
1857},
cc17557e
SS		 1858};
1859EXPORT_SYMBOL_GPL(twl4030_dai);
1860
1861static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1862{
1863 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1864 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1865
1866 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1867
1868 return 0;
1869}
1870
1871static int twl4030_resume(struct platform_device *pdev)
1872{
1873 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1874 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1875
1876 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1877 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1878 return 0;
1879}
1880
1881/*
1882 * initialize the driver
1883 * register the mixer and dsp interfaces with the kernel
1884 */
1885
1886static int twl4030_init(struct snd_soc_device *socdev)
1887{
6627a653 1888 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1889 int ret = 0;
1890
1891 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1892
1893 codec->name = "twl4030";
1894 codec->owner = THIS_MODULE;
1895 codec->read = twl4030_read_reg_cache;
1896 codec->write = twl4030_write;
1897 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 1898 codec->dai = twl4030_dai;
1899 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 1900 codec->reg_cache_size = sizeof(twl4030_reg);
1901 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1902 GFP_KERNEL);
1903 if (codec->reg_cache == NULL)
1904 return -ENOMEM;
1905
1906 /* register pcms */
1907 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1908 if (ret < 0) {
1909 printk(KERN_ERR "twl4030: failed to create pcms\n");
1910 goto pcm_err;
1911 }
1912
1913 twl4030_init_chip(codec);
1914
1915 /* power on device */
1916 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1917
3e8e1952
IM		 1918 snd_soc_add_controls(codec, twl4030_snd_controls,
1919 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1920 twl4030_add_widgets(codec);
1921
968a6025 1922 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1923 if (ret < 0) {
1924 printk(KERN_ERR "twl4030: failed to register card\n");
1925 goto card_err;
1926 }
1927
1928 return ret;
1929
1930card_err:
1931 snd_soc_free_pcms(socdev);
1932 snd_soc_dapm_free(socdev);
1933pcm_err:
1934 kfree(codec->reg_cache);
1935 return ret;
1936}
1937
1938static struct snd_soc_device *twl4030_socdev;
1939
1940static int twl4030_probe(struct platform_device *pdev)
1941{
1942 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1943 struct snd_soc_codec *codec;
7393958f 1944 struct twl4030_priv *twl4030;
cc17557e
SS		 1945
1946 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1947 if (codec == NULL)
1948 return -ENOMEM;
1949
7393958f
PU		 1950 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1951 if (twl4030 == NULL) {
1952 kfree(codec);
1953 return -ENOMEM;
1954 }
1955
1956 codec->private_data = twl4030;
6627a653 1957 socdev->card->codec = codec;
cc17557e
SS		 1958 mutex_init(&codec->mutex);
1959 INIT_LIST_HEAD(&codec->dapm_widgets);
1960 INIT_LIST_HEAD(&codec->dapm_paths);
1961
1962 twl4030_socdev = socdev;
1963 twl4030_init(socdev);
1964
1965 return 0;
1966}
1967
1968static int twl4030_remove(struct platform_device *pdev)
1969{
1970 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1971 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1972
1973 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1974 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1975 snd_soc_free_pcms(socdev);
1976 snd_soc_dapm_free(socdev);
7393958f 1977 kfree(codec->private_data);
cc17557e
SS		 1978 kfree(codec);
1979
1980 return 0;
1981}
1982
1983struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1984 .probe = twl4030_probe,
1985 .remove = twl4030_remove,
1986 .suspend = twl4030_suspend,
1987 .resume = twl4030_resume,
1988};
1989EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1990
24e07db8 1991static int __init twl4030_modinit(void)
64089b84 1992{
7154b3e8 1993 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 1994}
24e07db8 1995module_init(twl4030_modinit);
64089b84
MB		 1996
1997static void __exit twl4030_exit(void)
1998{
7154b3e8 1999 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2000}
2001module_exit(twl4030_exit);
2002
cc17557e
SS		 2003MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2004MODULE_AUTHOR("Steve Sakoman");
2005MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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