projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Implement WM8903 digital sidetone support
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
7393958f
PU		 133};
134
cc17557e
SS		 135/*
136 * read twl4030 register cache
137 */
138static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140{
141 u8 *cache = codec->reg_cache;
142
91432e97
IM		 143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
cc17557e
SS		 146 return cache[reg];
147}
148
149/*
150 * write twl4030 register cache
151 */
152static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154{
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160}
161
162/*
163 * write to the twl4030 register space
164 */
165static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167{
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170}
171
db04e2c5 172static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 173{
7393958f 174 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 175 u8 mode;
176
7393958f
PU		 177 if (enable == twl4030->codec_powered)
178 return;
179
cc17557e 180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
cc17557e 185
db04e2c5 186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 187 twl4030->codec_powered = enable;
cc17557e
SS		 188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192}
193
194static void twl4030_init_chip(struct snd_soc_codec *codec)
195{
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 199 twl4030_codec_enable(codec, 0);
cc17557e
SS		 200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205}
206
7393958f
PU		 207static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208{
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
240 reg_val & (~TWL4030_PRECKL_GAIN),
241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272}
273
006f367e
PU		 274static void twl4030_power_up(struct snd_soc_codec *codec)
275{
7393958f 276 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
7393958f
PU		 280 if (twl4030->codec_powered)
281 return;
282
006f367e
PU		 283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312}
313
7393958f
PU		 314/*
315 * Unconditional power down
316 */
006f367e
PU		 317static void twl4030_power_down(struct snd_soc_codec *codec)
318{
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321}
322
5e98a464
PU		 323/* Earpiece */
324static const char *twl4030_earpiece_texts[] =
2f423577 325 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 326
2f423577
PU		 327static const unsigned int twl4030_earpiece_values[] =
328 {0x0, 0x1, 0x2, 0x4};
329
cb1ace04 330static const struct soc_enum twl4030_earpiece_enum =
2f423577 331 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 332 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 333 twl4030_earpiece_texts,
334 twl4030_earpiece_values);
5e98a464
PU		 335
336static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 337SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 338
2a6f5c58
PU		 339/* PreDrive Left */
340static const char *twl4030_predrivel_texts[] =
2f423577
PU		 341 {"Off", "DACL1", "DACL2", "DACR2"};
342
343static const unsigned int twl4030_predrivel_values[] =
344 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 345
cb1ace04 346static const struct soc_enum twl4030_predrivel_enum =
2f423577 347 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 348 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 349 twl4030_predrivel_texts,
350 twl4030_predrivel_values);
2a6f5c58
PU		 351
352static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 353SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 354
355/* PreDrive Right */
356static const char *twl4030_predriver_texts[] =
2f423577 357 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 358
2f423577
PU		 359static const unsigned int twl4030_predriver_values[] =
360 {0x0, 0x1, 0x2, 0x4};
361
cb1ace04 362static const struct soc_enum twl4030_predriver_enum =
2f423577 363 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 364 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 365 twl4030_predriver_texts,
366 twl4030_predriver_values);
2a6f5c58
PU		 367
368static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 369SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 370
dfad21a2
PU		 371/* Headset Left */
372static const char *twl4030_hsol_texts[] =
373 {"Off", "DACL1", "DACL2"};
374
375static const struct soc_enum twl4030_hsol_enum =
376 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
377 ARRAY_SIZE(twl4030_hsol_texts),
378 twl4030_hsol_texts);
379
380static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
381SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
382
383/* Headset Right */
384static const char *twl4030_hsor_texts[] =
385 {"Off", "DACR1", "DACR2"};
386
387static const struct soc_enum twl4030_hsor_enum =
388 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
389 ARRAY_SIZE(twl4030_hsor_texts),
390 twl4030_hsor_texts);
391
392static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
393SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
394
5152d8c2
PU		 395/* Carkit Left */
396static const char *twl4030_carkitl_texts[] =
397 {"Off", "DACL1", "DACL2"};
398
399static const struct soc_enum twl4030_carkitl_enum =
400 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
401 ARRAY_SIZE(twl4030_carkitl_texts),
402 twl4030_carkitl_texts);
403
404static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
405SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
406
407/* Carkit Right */
408static const char *twl4030_carkitr_texts[] =
409 {"Off", "DACR1", "DACR2"};
410
411static const struct soc_enum twl4030_carkitr_enum =
412 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
413 ARRAY_SIZE(twl4030_carkitr_texts),
414 twl4030_carkitr_texts);
415
416static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
417SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
418
df339804
PU		 419/* Handsfree Left */
420static const char *twl4030_handsfreel_texts[] =
421 {"Voice", "DACL1", "DACL2", "DACR2"};
422
423static const struct soc_enum twl4030_handsfreel_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
425 ARRAY_SIZE(twl4030_handsfreel_texts),
426 twl4030_handsfreel_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
429SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
430
431/* Handsfree Right */
432static const char *twl4030_handsfreer_texts[] =
433 {"Voice", "DACR1", "DACR2", "DACL2"};
434
435static const struct soc_enum twl4030_handsfreer_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
437 ARRAY_SIZE(twl4030_handsfreer_texts),
438 twl4030_handsfreer_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
441SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
442
276c6222
PU		 443/* Left analog microphone selection */
444static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 445 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
446
447static const unsigned int twl4030_analoglmic_values[] =
448 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 449
cb1ace04 450static const struct soc_enum twl4030_analoglmic_enum =
2f423577 451 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 452 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 453 twl4030_analoglmic_texts,
454 twl4030_analoglmic_values);
276c6222
PU		 455
456static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 457SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 458
459/* Right analog microphone selection */
460static const char *twl4030_analogrmic_texts[] =
2f423577 461 {"Off", "Sub mic", "AUXR"};
276c6222 462
2f423577
PU		 463static const unsigned int twl4030_analogrmic_values[] =
464 {0x0, 0x1, 0x4};
465
cb1ace04 466static const struct soc_enum twl4030_analogrmic_enum =
2f423577 467 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 468 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 469 twl4030_analogrmic_texts,
470 twl4030_analogrmic_values);
276c6222
PU		 471
472static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 473SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 474
475/* TX1 L/R Analog/Digital microphone selection */
476static const char *twl4030_micpathtx1_texts[] =
477 {"Analog", "Digimic0"};
478
479static const struct soc_enum twl4030_micpathtx1_enum =
480 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
481 ARRAY_SIZE(twl4030_micpathtx1_texts),
482 twl4030_micpathtx1_texts);
483
484static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
485SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
486
487/* TX2 L/R Analog/Digital microphone selection */
488static const char *twl4030_micpathtx2_texts[] =
489 {"Analog", "Digimic1"};
490
491static const struct soc_enum twl4030_micpathtx2_enum =
492 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
493 ARRAY_SIZE(twl4030_micpathtx2_texts),
494 twl4030_micpathtx2_texts);
495
496static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
497SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
498
7393958f
PU		 499/* Analog bypass for AudioR1 */
500static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
501 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
502
503/* Analog bypass for AudioL1 */
504static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
505 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
506
507/* Analog bypass for AudioR2 */
508static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
509 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
510
511/* Analog bypass for AudioL2 */
512static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
513 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
514
6bab83fd
PU		 515/* Digital bypass gain, 0 mutes the bypass */
516static const unsigned int twl4030_dapm_dbypass_tlv[] = {
517 TLV_DB_RANGE_HEAD(2),
518 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
519 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
520};
521
522/* Digital bypass left (TX1L -> RX2L) */
523static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
524 SOC_DAPM_SINGLE_TLV("Volume",
525 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
526 twl4030_dapm_dbypass_tlv);
527
528/* Digital bypass right (TX1R -> RX2R) */
529static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
530 SOC_DAPM_SINGLE_TLV("Volume",
531 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
532 twl4030_dapm_dbypass_tlv);
533
276c6222
PU		 534static int micpath_event(struct snd_soc_dapm_widget *w,
535 struct snd_kcontrol *kcontrol, int event)
536{
537 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
538 unsigned char adcmicsel, micbias_ctl;
539
540 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
541 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
542 /* Prepare the bits for the given TX path:
543 * shift_l == 0: TX1 microphone path
544 * shift_l == 2: TX2 microphone path */
545 if (e->shift_l) {
546 /* TX2 microphone path */
547 if (adcmicsel & TWL4030_TX2IN_SEL)
548 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
549 else
550 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
551 } else {
552 /* TX1 microphone path */
553 if (adcmicsel & TWL4030_TX1IN_SEL)
554 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
555 else
556 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
557 }
558
559 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
560
561 return 0;
562}
563
49d92c7d
SM		 564static int handsfree_event(struct snd_soc_dapm_widget *w,
565 struct snd_kcontrol *kcontrol, int event)
566{
567 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
568 unsigned char hs_ctl;
569
570 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
571
572 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
573 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
574 twl4030_write(w->codec, e->reg, hs_ctl);
575 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
576 twl4030_write(w->codec, e->reg, hs_ctl);
577 hs_ctl |= TWL4030_HF_CTL_HB_EN;
578 twl4030_write(w->codec, e->reg, hs_ctl);
579 } else {
580 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
581 | TWL4030_HF_CTL_HB_EN);
582 twl4030_write(w->codec, e->reg, hs_ctl);
583 }
584
585 return 0;
586}
587
aad749e5
PU		 588static int headsetl_event(struct snd_soc_dapm_widget *w,
589 struct snd_kcontrol *kcontrol, int event)
590{
591 unsigned char hs_gain, hs_pop;
592
593 /* Save the current volume */
594 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
89492be8 595 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
aad749e5
PU		 596
597 switch (event) {
598 case SND_SOC_DAPM_POST_PMU:
599 /* Do the anti-pop/bias ramp enable according to the TRM */
aad749e5
PU		 600 hs_pop |= TWL4030_VMID_EN;
601 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
602 /* Is this needed? Can we just use whatever gain here? */
603 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
604 (hs_gain & (~0x0f)) | 0x0a);
605 hs_pop |= TWL4030_RAMP_EN;
606 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
607
608 /* Restore the original volume */
609 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
610 break;
611 case SND_SOC_DAPM_POST_PMD:
612 /* Do the anti-pop/bias ramp disable according to the TRM */
aad749e5
PU		 613 hs_pop &= ~TWL4030_RAMP_EN;
614 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
615 /* Bypass the reg_cache to mute the headset */
616 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
617 hs_gain & (~0x0f),
618 TWL4030_REG_HS_GAIN_SET);
619 hs_pop &= ~TWL4030_VMID_EN;
620 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
621 break;
622 }
623 return 0;
624}
625
7393958f
PU		 626static int bypass_event(struct snd_soc_dapm_widget *w,
627 struct snd_kcontrol *kcontrol, int event)
628{
629 struct soc_mixer_control *m =
630 (struct soc_mixer_control *)w->kcontrols->private_value;
631 struct twl4030_priv *twl4030 = w->codec->private_data;
632 unsigned char reg;
633
634 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 635
636 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
637 /* Analog bypass */
638 if (reg & (1 << m->shift))
639 twl4030->bypass_state |=
640 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
641 else
642 twl4030->bypass_state &=
643 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
644 } else {
645 /* Digital bypass */
646 if (reg & (0x7 << m->shift))
647 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
648 else
649 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
650 }
7393958f
PU		 651
652 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
653 if (twl4030->bypass_state)
654 twl4030_codec_mute(w->codec, 0);
655 else
656 twl4030_codec_mute(w->codec, 1);
657 }
658 return 0;
659}
660
b0bd53a7
PU		 661/*
662 * Some of the gain controls in TWL (mostly those which are associated with
663 * the outputs) are implemented in an interesting way:
664 * 0x0 : Power down (mute)
665 * 0x1 : 6dB
666 * 0x2 : 0 dB
667 * 0x3 : -6 dB
668 * Inverting not going to help with these.
669 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
670 */
671#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
672 xinvert, tlv_array) \
673{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
674 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
675 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
676 .tlv.p = (tlv_array), \
677 .info = snd_soc_info_volsw, \
678 .get = snd_soc_get_volsw_twl4030, \
679 .put = snd_soc_put_volsw_twl4030, \
680 .private_value = (unsigned long)&(struct soc_mixer_control) \
681 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
682 .max = xmax, .invert = xinvert} }
683#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
684 xinvert, tlv_array) \
685{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
686 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
687 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
688 .tlv.p = (tlv_array), \
689 .info = snd_soc_info_volsw_2r, \
690 .get = snd_soc_get_volsw_r2_twl4030,\
691 .put = snd_soc_put_volsw_r2_twl4030, \
692 .private_value = (unsigned long)&(struct soc_mixer_control) \
693 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 694 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 695#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
696 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
697 xinvert, tlv_array)
698
699static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701{
702 struct soc_mixer_control *mc =
703 (struct soc_mixer_control *)kcontrol->private_value;
704 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
705 unsigned int reg = mc->reg;
706 unsigned int shift = mc->shift;
707 unsigned int rshift = mc->rshift;
708 int max = mc->max;
709 int mask = (1 << fls(max)) - 1;
710
711 ucontrol->value.integer.value[0] =
712 (snd_soc_read(codec, reg) >> shift) & mask;
713 if (ucontrol->value.integer.value[0])
714 ucontrol->value.integer.value[0] =
715 max + 1 - ucontrol->value.integer.value[0];
716
717 if (shift != rshift) {
718 ucontrol->value.integer.value[1] =
719 (snd_soc_read(codec, reg) >> rshift) & mask;
720 if (ucontrol->value.integer.value[1])
721 ucontrol->value.integer.value[1] =
722 max + 1 - ucontrol->value.integer.value[1];
723 }
724
725 return 0;
726}
727
728static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
729 struct snd_ctl_elem_value *ucontrol)
730{
731 struct soc_mixer_control *mc =
732 (struct soc_mixer_control *)kcontrol->private_value;
733 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
734 unsigned int reg = mc->reg;
735 unsigned int shift = mc->shift;
736 unsigned int rshift = mc->rshift;
737 int max = mc->max;
738 int mask = (1 << fls(max)) - 1;
739 unsigned short val, val2, val_mask;
740
741 val = (ucontrol->value.integer.value[0] & mask);
742
743 val_mask = mask << shift;
744 if (val)
745 val = max + 1 - val;
746 val = val << shift;
747 if (shift != rshift) {
748 val2 = (ucontrol->value.integer.value[1] & mask);
749 val_mask |= mask << rshift;
750 if (val2)
751 val2 = max + 1 - val2;
752 val |= val2 << rshift;
753 }
754 return snd_soc_update_bits(codec, reg, val_mask, val);
755}
756
757static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
758 struct snd_ctl_elem_value *ucontrol)
759{
760 struct soc_mixer_control *mc =
761 (struct soc_mixer_control *)kcontrol->private_value;
762 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
763 unsigned int reg = mc->reg;
764 unsigned int reg2 = mc->rreg;
765 unsigned int shift = mc->shift;
766 int max = mc->max;
767 int mask = (1<<fls(max))-1;
768
769 ucontrol->value.integer.value[0] =
770 (snd_soc_read(codec, reg) >> shift) & mask;
771 ucontrol->value.integer.value[1] =
772 (snd_soc_read(codec, reg2) >> shift) & mask;
773
774 if (ucontrol->value.integer.value[0])
775 ucontrol->value.integer.value[0] =
776 max + 1 - ucontrol->value.integer.value[0];
777 if (ucontrol->value.integer.value[1])
778 ucontrol->value.integer.value[1] =
779 max + 1 - ucontrol->value.integer.value[1];
780
781 return 0;
782}
783
784static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
786{
787 struct soc_mixer_control *mc =
788 (struct soc_mixer_control *)kcontrol->private_value;
789 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
790 unsigned int reg = mc->reg;
791 unsigned int reg2 = mc->rreg;
792 unsigned int shift = mc->shift;
793 int max = mc->max;
794 int mask = (1 << fls(max)) - 1;
795 int err;
796 unsigned short val, val2, val_mask;
797
798 val_mask = mask << shift;
799 val = (ucontrol->value.integer.value[0] & mask);
800 val2 = (ucontrol->value.integer.value[1] & mask);
801
802 if (val)
803 val = max + 1 - val;
804 if (val2)
805 val2 = max + 1 - val2;
806
807 val = val << shift;
808 val2 = val2 << shift;
809
810 err = snd_soc_update_bits(codec, reg, val_mask, val);
811 if (err < 0)
812 return err;
813
814 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
815 return err;
816}
817
c10b82cf
PU		 818/*
819 * FGAIN volume control:
820 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
821 */
d889a72c 822static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 823
0d33ea0b
PU		 824/*
825 * CGAIN volume control:
826 * 0 dB to 12 dB in 6 dB steps
827 * value 2 and 3 means 12 dB
828 */
d889a72c
PU		 829static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
830
831/*
832 * Analog playback gain
833 * -24 dB to 12 dB in 2 dB steps
834 */
835static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 836
4290239c
PU		 837/*
838 * Gain controls tied to outputs
839 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
840 */
841static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
842
381a22b5
PU		 843/*
844 * Capture gain after the ADCs
845 * from 0 dB to 31 dB in 1 dB steps
846 */
847static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
848
5920b453
GI		 849/*
850 * Gain control for input amplifiers
851 * 0 dB to 30 dB in 6 dB steps
852 */
853static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
854
89492be8
PU		 855static const char *twl4030_rampdelay_texts[] = {
856 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
857 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
858 "3495/2581/1748 ms"
859};
860
861static const struct soc_enum twl4030_rampdelay_enum =
862 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
863 ARRAY_SIZE(twl4030_rampdelay_texts),
864 twl4030_rampdelay_texts);
865
cc17557e 866static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 867 /* Common playback gain controls */
868 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
869 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
870 0, 0x3f, 0, digital_fine_tlv),
871 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
872 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
873 0, 0x3f, 0, digital_fine_tlv),
874
875 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
876 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
877 6, 0x2, 0, digital_coarse_tlv),
878 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
879 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
880 6, 0x2, 0, digital_coarse_tlv),
881
882 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
883 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
884 3, 0x12, 1, analog_tlv),
885 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
886 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
887 3, 0x12, 1, analog_tlv),
44c55870
PU		 888 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
889 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
890 1, 1, 0),
891 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
892 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
893 1, 1, 0),
381a22b5 894
4290239c
PU		 895 /* Separate output gain controls */
896 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
897 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
898 4, 3, 0, output_tvl),
899
900 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
901 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
902
903 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
904 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
905 4, 3, 0, output_tvl),
906
907 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
908 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
909
381a22b5 910 /* Common capture gain controls */
276c6222 911 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 912 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
913 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 914 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
915 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
916 0, 0x1f, 0, digital_capture_tlv),
5920b453 917
276c6222 918 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 919 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 920
921 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
cc17557e
SS		 922};
923
cc17557e 924static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 925 /* Left channel inputs */
926 SND_SOC_DAPM_INPUT("MAINMIC"),
927 SND_SOC_DAPM_INPUT("HSMIC"),
928 SND_SOC_DAPM_INPUT("AUXL"),
929 SND_SOC_DAPM_INPUT("CARKITMIC"),
930 /* Right channel inputs */
931 SND_SOC_DAPM_INPUT("SUBMIC"),
932 SND_SOC_DAPM_INPUT("AUXR"),
933 /* Digital microphones (Stereo) */
934 SND_SOC_DAPM_INPUT("DIGIMIC0"),
935 SND_SOC_DAPM_INPUT("DIGIMIC1"),
936
937 /* Outputs */
cc17557e
SS		 938 SND_SOC_DAPM_OUTPUT("OUTL"),
939 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 940 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 941 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
942 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 943 SND_SOC_DAPM_OUTPUT("HSOL"),
944 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 945 SND_SOC_DAPM_OUTPUT("CARKITL"),
946 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 947 SND_SOC_DAPM_OUTPUT("HFL"),
948 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 949
53b5047d 950 /* DACs */
1e5fa31f 951 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 952 SND_SOC_NOPM, 0, 0),
1e5fa31f 953 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 954 SND_SOC_NOPM, 0, 0),
1e5fa31f 955 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 956 SND_SOC_NOPM, 0, 0),
1e5fa31f 957 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 958 SND_SOC_NOPM, 0, 0),
cc17557e 959
44c55870
PU		 960 /* Analog PGAs */
961 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
962 0, 0, NULL, 0),
963 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
964 0, 0, NULL, 0),
965 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
966 0, 0, NULL, 0),
967 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
968 0, 0, NULL, 0),
969
7393958f
PU		 970 /* Analog bypasses */
971 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
972 &twl4030_dapm_abypassr1_control, bypass_event,
973 SND_SOC_DAPM_POST_REG),
974 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
975 &twl4030_dapm_abypassl1_control,
976 bypass_event, SND_SOC_DAPM_POST_REG),
977 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
978 &twl4030_dapm_abypassr2_control,
979 bypass_event, SND_SOC_DAPM_POST_REG),
980 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
981 &twl4030_dapm_abypassl2_control,
982 bypass_event, SND_SOC_DAPM_POST_REG),
983
6bab83fd
PU		 984 /* Digital bypasses */
985 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
986 &twl4030_dapm_dbypassl_control, bypass_event,
987 SND_SOC_DAPM_POST_REG),
988 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
989 &twl4030_dapm_dbypassr_control, bypass_event,
990 SND_SOC_DAPM_POST_REG),
991
7393958f
PU		 992 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
993 0, 0, NULL, 0),
994 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
995 1, 0, NULL, 0),
996 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
997 2, 0, NULL, 0),
998 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
999 3, 0, NULL, 0),
1000
5e98a464
PU		 1001 /* Output MUX controls */
1002 /* Earpiece */
2f423577
PU		 1003 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
1004 &twl4030_dapm_earpiece_control),
2a6f5c58 1005 /* PreDrivL/R */
2f423577
PU		 1006 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
1007 &twl4030_dapm_predrivel_control),
1008 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
1009 &twl4030_dapm_predriver_control),
dfad21a2 1010 /* HeadsetL/R */
aad749e5
PU		 1011 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
1012 &twl4030_dapm_hsol_control, headsetl_event,
1013 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2
PU		 1014 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
1015 &twl4030_dapm_hsor_control),
5152d8c2
PU		 1016 /* CarkitL/R */
1017 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
1018 &twl4030_dapm_carkitl_control),
1019 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
1020 &twl4030_dapm_carkitr_control),
df339804 1021 /* HandsfreeL/R */
49d92c7d
SM		 1022 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1023 &twl4030_dapm_handsfreel_control, handsfree_event,
1024 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1025 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1026 &twl4030_dapm_handsfreer_control, handsfree_event,
1027 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 1028
276c6222
PU		 1029 /* Introducing four virtual ADC, since TWL4030 have four channel for
1030 capture */
1031 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1032 SND_SOC_NOPM, 0, 0),
1033 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1034 SND_SOC_NOPM, 0, 0),
1035 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1036 SND_SOC_NOPM, 0, 0),
1037 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1038 SND_SOC_NOPM, 0, 0),
1039
1040 /* Analog/Digital mic path selection.
1041 TX1 Left/Right: either analog Left/Right or Digimic0
1042 TX2 Left/Right: either analog Left/Right or Digimic1 */
1043 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1044 &twl4030_dapm_micpathtx1_control, micpath_event,
1045 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1046 SND_SOC_DAPM_POST_REG),
1047 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1048 &twl4030_dapm_micpathtx2_control, micpath_event,
1049 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1050 SND_SOC_DAPM_POST_REG),
1051
fb2a2f84 1052 /* Analog input muxes with switch for the capture amplifiers */
2f423577 1053 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 1054 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1055 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1056 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1057
fb2a2f84
PU		 1058 SND_SOC_DAPM_PGA("ADC Physical Left",
1059 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1060 SND_SOC_DAPM_PGA("ADC Physical Right",
1061 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1062
1063 SND_SOC_DAPM_PGA("Digimic0 Enable",
1064 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1065 SND_SOC_DAPM_PGA("Digimic1 Enable",
1066 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1067
1068 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1069 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1070 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1071
cc17557e
SS		 1072};
1073
1074static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1075 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1076 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1077 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1078 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1079
1080 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1081 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1082 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1083 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
44c55870 1084
5e98a464
PU		 1085 /* Internal playback routings */
1086 /* Earpiece */
1087 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
1088 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
1089 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 1090 /* PreDrivL */
1091 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
1092 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
1093 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
1094 /* PreDrivR */
1095 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
1096 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
1097 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 1098 /* HeadsetL */
1099 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
1100 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
1101 /* HeadsetR */
1102 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
1103 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 1104 /* CarkitL */
1105 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
1106 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
1107 /* CarkitR */
1108 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
1109 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 1110 /* HandsfreeL */
1111 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
1112 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
1113 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
1114 /* HandsfreeR */
1115 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
1116 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
1117 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 1118
cc17557e 1119 /* outputs */
44c55870
PU		 1120 {"OUTL", NULL, "ARXL2_APGA"},
1121 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 1122 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 1123 {"PREDRIVEL", NULL, "PredriveL Mux"},
1124 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 1125 {"HSOL", NULL, "HeadsetL Mux"},
1126 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 1127 {"CARKITL", NULL, "CarkitL Mux"},
1128 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 1129 {"HFL", NULL, "HandsfreeL Mux"},
1130 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 1131
276c6222
PU		 1132 /* Capture path */
1133 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1134 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1135 {"Analog Left Capture Route", "AUXL", "AUXL"},
1136 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1137
1138 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1139 {"Analog Right Capture Route", "AUXR", "AUXR"},
1140
fb2a2f84
PU		 1141 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1142 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1143
1144 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1145 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1146
1147 /* TX1 Left capture path */
fb2a2f84 1148 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1149 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1150 /* TX1 Right capture path */
fb2a2f84 1151 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1152 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1153 /* TX2 Left capture path */
fb2a2f84 1154 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1155 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1156 /* TX2 Right capture path */
fb2a2f84 1157 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1158 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1159
1160 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1161 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1162 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1163 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1164
7393958f
PU		 1165 /* Analog bypass routes */
1166 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1167 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1168 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1169 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1170
1171 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1172 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1173 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1174 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1175
6bab83fd
PU		 1176 /* Digital bypass routes */
1177 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1178 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1179
1180 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1181 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
1182
cc17557e
SS		 1183};
1184
1185static int twl4030_add_widgets(struct snd_soc_codec *codec)
1186{
1187 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1188 ARRAY_SIZE(twl4030_dapm_widgets));
1189
1190 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1191
1192 snd_soc_dapm_new_widgets(codec);
1193 return 0;
1194}
1195
cc17557e
SS		 1196static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1197 enum snd_soc_bias_level level)
1198{
7393958f
PU		 1199 struct twl4030_priv *twl4030 = codec->private_data;
1200
cc17557e
SS		 1201 switch (level) {
1202 case SND_SOC_BIAS_ON:
7393958f 1203 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1204 break;
1205 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1206 twl4030_power_up(codec);
1207 if (twl4030->bypass_state)
1208 twl4030_codec_mute(codec, 0);
1209 else
1210 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1211 break;
1212 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1213 twl4030_power_up(codec);
1214 if (twl4030->bypass_state)
1215 twl4030_codec_mute(codec, 0);
1216 else
1217 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1218 break;
1219 case SND_SOC_BIAS_OFF:
1220 twl4030_power_down(codec);
1221 break;
1222 }
1223 codec->bias_level = level;
1224
1225 return 0;
1226}
1227
6b87a91f
PU		 1228static void twl4030_constraints(struct twl4030_priv *twl4030,
1229 struct snd_pcm_substream *mst_substream)
1230{
1231 struct snd_pcm_substream *slv_substream;
1232
1233 /* Pick the stream, which need to be constrained */
1234 if (mst_substream == twl4030->master_substream)
1235 slv_substream = twl4030->slave_substream;
1236 else if (mst_substream == twl4030->slave_substream)
1237 slv_substream = twl4030->master_substream;
1238 else /* This should not happen.. */
1239 return;
1240
1241 /* Set the constraints according to the already configured stream */
1242 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1243 SNDRV_PCM_HW_PARAM_RATE,
1244 twl4030->rate,
1245 twl4030->rate);
1246
1247 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1248 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1249 twl4030->sample_bits,
1250 twl4030->sample_bits);
1251
1252 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1253 SNDRV_PCM_HW_PARAM_CHANNELS,
1254 twl4030->channels,
1255 twl4030->channels);
1256}
1257
d6648da1
PU		 1258static int twl4030_startup(struct snd_pcm_substream *substream,
1259 struct snd_soc_dai *dai)
7220b9f4
PU		 1260{
1261 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1262 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1263 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1264 struct twl4030_priv *twl4030 = codec->private_data;
1265
7220b9f4 1266 if (twl4030->master_substream) {
7220b9f4 1267 twl4030->slave_substream = substream;
6b87a91f
PU		 1268 /* The DAI has one configuration for playback and capture, so
1269 * if the DAI has been already configured then constrain this
1270 * substream to match it. */
1271 if (twl4030->configured)
1272 twl4030_constraints(twl4030, twl4030->master_substream);
1273 } else {
7220b9f4 1274 twl4030->master_substream = substream;
6b87a91f 1275 }
7220b9f4
PU		 1276
1277 return 0;
1278}
1279
d6648da1
PU		 1280static void twl4030_shutdown(struct snd_pcm_substream *substream,
1281 struct snd_soc_dai *dai)
7220b9f4
PU		 1282{
1283 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1284 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1285 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1286 struct twl4030_priv *twl4030 = codec->private_data;
1287
1288 if (twl4030->master_substream == substream)
1289 twl4030->master_substream = twl4030->slave_substream;
1290
1291 twl4030->slave_substream = NULL;
6b87a91f
PU		 1292
1293 /* If all streams are closed, or the remaining stream has not yet
1294 * been configured than set the DAI as not configured. */
1295 if (!twl4030->master_substream)
1296 twl4030->configured = 0;
1297 else if (!twl4030->master_substream->runtime->channels)
1298 twl4030->configured = 0;
7220b9f4
PU		 1299}
1300
cc17557e 1301static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1302 struct snd_pcm_hw_params *params,
1303 struct snd_soc_dai *dai)
cc17557e
SS		 1304{
1305 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1306 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1307 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1308 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1309 u8 mode, old_mode, format, old_format;
1310
6b87a91f
PU		 1311 if (twl4030->configured)
1312 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1313 return 0;
1314
cc17557e
SS		 1315 /* bit rate */
1316 old_mode = twl4030_read_reg_cache(codec,
1317 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1318 mode = old_mode & ~TWL4030_APLL_RATE;
1319
1320 switch (params_rate(params)) {
1321 case 8000:
1322 mode |= TWL4030_APLL_RATE_8000;
1323 break;
1324 case 11025:
1325 mode |= TWL4030_APLL_RATE_11025;
1326 break;
1327 case 12000:
1328 mode |= TWL4030_APLL_RATE_12000;
1329 break;
1330 case 16000:
1331 mode |= TWL4030_APLL_RATE_16000;
1332 break;
1333 case 22050:
1334 mode |= TWL4030_APLL_RATE_22050;
1335 break;
1336 case 24000:
1337 mode |= TWL4030_APLL_RATE_24000;
1338 break;
1339 case 32000:
1340 mode |= TWL4030_APLL_RATE_32000;
1341 break;
1342 case 44100:
1343 mode |= TWL4030_APLL_RATE_44100;
1344 break;
1345 case 48000:
1346 mode |= TWL4030_APLL_RATE_48000;
1347 break;
103f211d
PU		 1348 case 96000:
1349 mode |= TWL4030_APLL_RATE_96000;
1350 break;
cc17557e
SS		 1351 default:
1352 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1353 params_rate(params));
1354 return -EINVAL;
1355 }
1356
1357 if (mode != old_mode) {
1358 /* change rate and set CODECPDZ */
7393958f 1359 twl4030_codec_enable(codec, 0);
cc17557e 1360 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1361 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1362 }
1363
1364 /* sample size */
1365 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1366 format = old_format;
1367 format &= ~TWL4030_DATA_WIDTH;
1368 switch (params_format(params)) {
1369 case SNDRV_PCM_FORMAT_S16_LE:
1370 format |= TWL4030_DATA_WIDTH_16S_16W;
1371 break;
1372 case SNDRV_PCM_FORMAT_S24_LE:
1373 format |= TWL4030_DATA_WIDTH_32S_24W;
1374 break;
1375 default:
1376 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1377 params_format(params));
1378 return -EINVAL;
1379 }
1380
1381 if (format != old_format) {
1382
1383 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1384 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1385
1386 /* change format */
1387 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1388
1389 /* set CODECPDZ afterwards */
db04e2c5 1390 twl4030_codec_enable(codec, 1);
cc17557e 1391 }
6b87a91f
PU		 1392
1393 /* Store the important parameters for the DAI configuration and set
1394 * the DAI as configured */
1395 twl4030->configured = 1;
1396 twl4030->rate = params_rate(params);
1397 twl4030->sample_bits = hw_param_interval(params,
1398 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1399 twl4030->channels = params_channels(params);
1400
1401 /* If both playback and capture streams are open, and one of them
1402 * is setting the hw parameters right now (since we are here), set
1403 * constraints to the other stream to match the current one. */
1404 if (twl4030->slave_substream)
1405 twl4030_constraints(twl4030, substream);
1406
cc17557e
SS		 1407 return 0;
1408}
1409
1410static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1411 int clk_id, unsigned int freq, int dir)
1412{
1413 struct snd_soc_codec *codec = codec_dai->codec;
1414 u8 infreq;
1415
1416 switch (freq) {
1417 case 19200000:
1418 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1419 break;
1420 case 26000000:
1421 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1422 break;
1423 case 38400000:
1424 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1425 break;
1426 default:
1427 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1428 freq);
1429 return -EINVAL;
1430 }
1431
1432 infreq |= TWL4030_APLL_EN;
1433 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1434
1435 return 0;
1436}
1437
1438static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1439 unsigned int fmt)
1440{
1441 struct snd_soc_codec *codec = codec_dai->codec;
1442 u8 old_format, format;
1443
1444 /* get format */
1445 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1446 format = old_format;
1447
1448 /* set master/slave audio interface */
1449 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1450 case SND_SOC_DAIFMT_CBM_CFM:
1451 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1452 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1453 break;
1454 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1455 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1456 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1457 break;
1458 default:
1459 return -EINVAL;
1460 }
1461
1462 /* interface format */
1463 format &= ~TWL4030_AIF_FORMAT;
1464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1465 case SND_SOC_DAIFMT_I2S:
1466 format |= TWL4030_AIF_FORMAT_CODEC;
1467 break;
1468 default:
1469 return -EINVAL;
1470 }
1471
1472 if (format != old_format) {
1473
1474 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1475 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1476
1477 /* change format */
1478 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1479
1480 /* set CODECPDZ afterwards */
db04e2c5 1481 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1482 }
1483
1484 return 0;
1485}
1486
7154b3e8
JS		 1487static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1488 struct snd_soc_dai *dai)
1489{
1490 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1491 struct snd_soc_device *socdev = rtd->socdev;
1492 struct snd_soc_codec *codec = socdev->card->codec;
1493 u8 infreq;
1494 u8 mode;
1495
1496 /* If the system master clock is not 26MHz, the voice PCM interface is
1497 * not avilable.
1498 */
1499 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1500 & TWL4030_APLL_INFREQ;
1501
1502 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1503 printk(KERN_ERR "TWL4030 voice startup: "
1504 "MCLK is not 26MHz, call set_sysclk() on init\n");
1505 return -EINVAL;
1506 }
1507
1508 /* If the codec mode is not option2, the voice PCM interface is not
1509 * avilable.
1510 */
1511 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1512 & TWL4030_OPT_MODE;
1513
1514 if (mode != TWL4030_OPTION_2) {
1515 printk(KERN_ERR "TWL4030 voice startup: "
1516 "the codec mode is not option2\n");
1517 return -EINVAL;
1518 }
1519
1520 return 0;
1521}
1522
1523static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1524 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1525{
1526 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1527 struct snd_soc_device *socdev = rtd->socdev;
1528 struct snd_soc_codec *codec = socdev->card->codec;
1529 u8 old_mode, mode;
1530
1531 /* bit rate */
1532 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1533 & ~(TWL4030_CODECPDZ);
1534 mode = old_mode;
1535
1536 switch (params_rate(params)) {
1537 case 8000:
1538 mode &= ~(TWL4030_SEL_16K);
1539 break;
1540 case 16000:
1541 mode |= TWL4030_SEL_16K;
1542 break;
1543 default:
1544 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1545 params_rate(params));
1546 return -EINVAL;
1547 }
1548
1549 if (mode != old_mode) {
1550 /* change rate and set CODECPDZ */
1551 twl4030_codec_enable(codec, 0);
1552 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1553 twl4030_codec_enable(codec, 1);
1554 }
1555
1556 return 0;
1557}
1558
1559static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1560 int clk_id, unsigned int freq, int dir)
1561{
1562 struct snd_soc_codec *codec = codec_dai->codec;
1563 u8 infreq;
1564
1565 switch (freq) {
1566 case 26000000:
1567 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1568 break;
1569 default:
1570 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1571 freq);
1572 return -EINVAL;
1573 }
1574
1575 infreq |= TWL4030_APLL_EN;
1576 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1577
1578 return 0;
1579}
1580
1581static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1582 unsigned int fmt)
1583{
1584 struct snd_soc_codec *codec = codec_dai->codec;
1585 u8 old_format, format;
1586
1587 /* get format */
1588 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1589 format = old_format;
1590
1591 /* set master/slave audio interface */
1592 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1593 case SND_SOC_DAIFMT_CBS_CFM:
1594 format &= ~(TWL4030_VIF_SLAVE_EN);
1595 break;
1596 case SND_SOC_DAIFMT_CBS_CFS:
1597 format |= TWL4030_VIF_SLAVE_EN;
1598 break;
1599 default:
1600 return -EINVAL;
1601 }
1602
1603 /* clock inversion */
1604 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1605 case SND_SOC_DAIFMT_IB_NF:
1606 format &= ~(TWL4030_VIF_FORMAT);
1607 break;
1608 case SND_SOC_DAIFMT_NB_IF:
1609 format |= TWL4030_VIF_FORMAT;
1610 break;
1611 default:
1612 return -EINVAL;
1613 }
1614
1615 if (format != old_format) {
1616 /* change format and set CODECPDZ */
1617 twl4030_codec_enable(codec, 0);
1618 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1619 twl4030_codec_enable(codec, 1);
1620 }
1621
1622 return 0;
1623}
1624
bbba9444 1625#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1626#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1627
10d9e3d9 1628static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1629 .startup = twl4030_startup,
1630 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1631 .hw_params = twl4030_hw_params,
1632 .set_sysclk = twl4030_set_dai_sysclk,
1633 .set_fmt = twl4030_set_dai_fmt,
1634};
1635
7154b3e8
JS		 1636static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1637 .startup = twl4030_voice_startup,
1638 .hw_params = twl4030_voice_hw_params,
1639 .set_sysclk = twl4030_voice_set_dai_sysclk,
1640 .set_fmt = twl4030_voice_set_dai_fmt,
1641};
1642
1643struct snd_soc_dai twl4030_dai[] = {
1644{
cc17557e
SS		 1645 .name = "twl4030",
1646 .playback = {
1647 .stream_name = "Playback",
1648 .channels_min = 2,
1649 .channels_max = 2,
31ad0f31 1650 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1651 .formats = TWL4030_FORMATS,},
1652 .capture = {
1653 .stream_name = "Capture",
1654 .channels_min = 2,
1655 .channels_max = 2,
1656 .rates = TWL4030_RATES,
1657 .formats = TWL4030_FORMATS,},
10d9e3d9 1658 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1659},
1660{
1661 .name = "twl4030 Voice",
1662 .playback = {
1663 .stream_name = "Playback",
1664 .channels_min = 1,
1665 .channels_max = 1,
1666 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1667 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1668 .capture = {
1669 .stream_name = "Capture",
1670 .channels_min = 1,
1671 .channels_max = 2,
1672 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1673 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1674 .ops = &twl4030_dai_voice_ops,
1675},
cc17557e
SS		 1676};
1677EXPORT_SYMBOL_GPL(twl4030_dai);
1678
1679static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1680{
1681 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1682 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1683
1684 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1685
1686 return 0;
1687}
1688
1689static int twl4030_resume(struct platform_device *pdev)
1690{
1691 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1692 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1693
1694 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1695 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1696 return 0;
1697}
1698
1699/*
1700 * initialize the driver
1701 * register the mixer and dsp interfaces with the kernel
1702 */
1703
1704static int twl4030_init(struct snd_soc_device *socdev)
1705{
6627a653 1706 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1707 int ret = 0;
1708
1709 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1710
1711 codec->name = "twl4030";
1712 codec->owner = THIS_MODULE;
1713 codec->read = twl4030_read_reg_cache;
1714 codec->write = twl4030_write;
1715 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 1716 codec->dai = twl4030_dai;
1717 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 1718 codec->reg_cache_size = sizeof(twl4030_reg);
1719 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1720 GFP_KERNEL);
1721 if (codec->reg_cache == NULL)
1722 return -ENOMEM;
1723
1724 /* register pcms */
1725 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1726 if (ret < 0) {
1727 printk(KERN_ERR "twl4030: failed to create pcms\n");
1728 goto pcm_err;
1729 }
1730
1731 twl4030_init_chip(codec);
1732
1733 /* power on device */
1734 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1735
3e8e1952
IM		 1736 snd_soc_add_controls(codec, twl4030_snd_controls,
1737 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1738 twl4030_add_widgets(codec);
1739
968a6025 1740 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1741 if (ret < 0) {
1742 printk(KERN_ERR "twl4030: failed to register card\n");
1743 goto card_err;
1744 }
1745
1746 return ret;
1747
1748card_err:
1749 snd_soc_free_pcms(socdev);
1750 snd_soc_dapm_free(socdev);
1751pcm_err:
1752 kfree(codec->reg_cache);
1753 return ret;
1754}
1755
1756static struct snd_soc_device *twl4030_socdev;
1757
1758static int twl4030_probe(struct platform_device *pdev)
1759{
1760 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1761 struct snd_soc_codec *codec;
7393958f 1762 struct twl4030_priv *twl4030;
cc17557e
SS		 1763
1764 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1765 if (codec == NULL)
1766 return -ENOMEM;
1767
7393958f
PU		 1768 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1769 if (twl4030 == NULL) {
1770 kfree(codec);
1771 return -ENOMEM;
1772 }
1773
1774 codec->private_data = twl4030;
6627a653 1775 socdev->card->codec = codec;
cc17557e
SS		 1776 mutex_init(&codec->mutex);
1777 INIT_LIST_HEAD(&codec->dapm_widgets);
1778 INIT_LIST_HEAD(&codec->dapm_paths);
1779
1780 twl4030_socdev = socdev;
1781 twl4030_init(socdev);
1782
1783 return 0;
1784}
1785
1786static int twl4030_remove(struct platform_device *pdev)
1787{
1788 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1789 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1790
1791 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1792 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1793 snd_soc_free_pcms(socdev);
1794 snd_soc_dapm_free(socdev);
7393958f 1795 kfree(codec->private_data);
cc17557e
SS		 1796 kfree(codec);
1797
1798 return 0;
1799}
1800
1801struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1802 .probe = twl4030_probe,
1803 .remove = twl4030_remove,
1804 .suspend = twl4030_suspend,
1805 .resume = twl4030_resume,
1806};
1807EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1808
24e07db8 1809static int __init twl4030_modinit(void)
64089b84 1810{
7154b3e8 1811 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 1812}
24e07db8 1813module_init(twl4030_modinit);
64089b84
MB		 1814
1815static void __exit twl4030_exit(void)
1816{
7154b3e8 1817 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 1818}
1819module_exit(twl4030_exit);
1820
cc17557e
SS		 1821MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1822MODULE_AUTHOR("Steve Sakoman");
1823MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.126503 seconds and 5 git commands to generate.