projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: TWL4030: DAPM mapping of the PreDriv outputs
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
5e98a464
PU		 193/* Earpiece */
194static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid",
196 "DACR1"};
197
198static const struct soc_enum twl4030_earpiece_enum =
199 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
200 ARRAY_SIZE(twl4030_earpiece_texts),
201 twl4030_earpiece_texts);
202
203static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
204SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
205
2a6f5c58
PU		 206/* PreDrive Left */
207static const char *twl4030_predrivel_texts[] =
208 {"Off", "DACL1", "DACL2", "Invalid",
209 "DACR2"};
210
211static const struct soc_enum twl4030_predrivel_enum =
212 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
213 ARRAY_SIZE(twl4030_predrivel_texts),
214 twl4030_predrivel_texts);
215
216static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
217SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
218
219/* PreDrive Right */
220static const char *twl4030_predriver_texts[] =
221 {"Off", "DACR1", "DACR2", "Invalid",
222 "DACL2"};
223
224static const struct soc_enum twl4030_predriver_enum =
225 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
226 ARRAY_SIZE(twl4030_predriver_texts),
227 twl4030_predriver_texts);
228
229static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
230SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
231
e8ff9c41
PU		 232static int outmixer_event(struct snd_soc_dapm_widget *w,
233 struct snd_kcontrol *kcontrol, int event)
234{
235 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
236 int ret = 0;
237 int val;
238
239 switch (e->reg) {
240 case TWL4030_REG_PREDL_CTL:
241 case TWL4030_REG_PREDR_CTL:
242 case TWL4030_REG_EAR_CTL:
243 val = w->value >> e->shift_l;
244 if (val == 3) {
245 printk(KERN_WARNING
246 "Invalid MUX setting for register 0x%02x (%d)\n",
247 e->reg, val);
248 ret = -1;
249 }
250 break;
251 }
252
253 return ret;
254}
255
b0bd53a7
PU		 256/*
257 * Some of the gain controls in TWL (mostly those which are associated with
258 * the outputs) are implemented in an interesting way:
259 * 0x0 : Power down (mute)
260 * 0x1 : 6dB
261 * 0x2 : 0 dB
262 * 0x3 : -6 dB
263 * Inverting not going to help with these.
264 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
265 */
266#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
267 xinvert, tlv_array) \
268{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
269 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
270 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
271 .tlv.p = (tlv_array), \
272 .info = snd_soc_info_volsw, \
273 .get = snd_soc_get_volsw_twl4030, \
274 .put = snd_soc_put_volsw_twl4030, \
275 .private_value = (unsigned long)&(struct soc_mixer_control) \
276 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
277 .max = xmax, .invert = xinvert} }
278#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
279 xinvert, tlv_array) \
280{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
281 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
282 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
283 .tlv.p = (tlv_array), \
284 .info = snd_soc_info_volsw_2r, \
285 .get = snd_soc_get_volsw_r2_twl4030,\
286 .put = snd_soc_put_volsw_r2_twl4030, \
287 .private_value = (unsigned long)&(struct soc_mixer_control) \
288 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
289 .max = xmax, .invert = xinvert} }
290#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
291 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
292 xinvert, tlv_array)
293
294static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_value *ucontrol)
296{
297 struct soc_mixer_control *mc =
298 (struct soc_mixer_control *)kcontrol->private_value;
299 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
300 unsigned int reg = mc->reg;
301 unsigned int shift = mc->shift;
302 unsigned int rshift = mc->rshift;
303 int max = mc->max;
304 int mask = (1 << fls(max)) - 1;
305
306 ucontrol->value.integer.value[0] =
307 (snd_soc_read(codec, reg) >> shift) & mask;
308 if (ucontrol->value.integer.value[0])
309 ucontrol->value.integer.value[0] =
310 max + 1 - ucontrol->value.integer.value[0];
311
312 if (shift != rshift) {
313 ucontrol->value.integer.value[1] =
314 (snd_soc_read(codec, reg) >> rshift) & mask;
315 if (ucontrol->value.integer.value[1])
316 ucontrol->value.integer.value[1] =
317 max + 1 - ucontrol->value.integer.value[1];
318 }
319
320 return 0;
321}
322
323static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
324 struct snd_ctl_elem_value *ucontrol)
325{
326 struct soc_mixer_control *mc =
327 (struct soc_mixer_control *)kcontrol->private_value;
328 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
329 unsigned int reg = mc->reg;
330 unsigned int shift = mc->shift;
331 unsigned int rshift = mc->rshift;
332 int max = mc->max;
333 int mask = (1 << fls(max)) - 1;
334 unsigned short val, val2, val_mask;
335
336 val = (ucontrol->value.integer.value[0] & mask);
337
338 val_mask = mask << shift;
339 if (val)
340 val = max + 1 - val;
341 val = val << shift;
342 if (shift != rshift) {
343 val2 = (ucontrol->value.integer.value[1] & mask);
344 val_mask |= mask << rshift;
345 if (val2)
346 val2 = max + 1 - val2;
347 val |= val2 << rshift;
348 }
349 return snd_soc_update_bits(codec, reg, val_mask, val);
350}
351
352static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
354{
355 struct soc_mixer_control *mc =
356 (struct soc_mixer_control *)kcontrol->private_value;
357 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
358 unsigned int reg = mc->reg;
359 unsigned int reg2 = mc->rreg;
360 unsigned int shift = mc->shift;
361 int max = mc->max;
362 int mask = (1<<fls(max))-1;
363
364 ucontrol->value.integer.value[0] =
365 (snd_soc_read(codec, reg) >> shift) & mask;
366 ucontrol->value.integer.value[1] =
367 (snd_soc_read(codec, reg2) >> shift) & mask;
368
369 if (ucontrol->value.integer.value[0])
370 ucontrol->value.integer.value[0] =
371 max + 1 - ucontrol->value.integer.value[0];
372 if (ucontrol->value.integer.value[1])
373 ucontrol->value.integer.value[1] =
374 max + 1 - ucontrol->value.integer.value[1];
375
376 return 0;
377}
378
379static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct soc_mixer_control *mc =
383 (struct soc_mixer_control *)kcontrol->private_value;
384 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
385 unsigned int reg = mc->reg;
386 unsigned int reg2 = mc->rreg;
387 unsigned int shift = mc->shift;
388 int max = mc->max;
389 int mask = (1 << fls(max)) - 1;
390 int err;
391 unsigned short val, val2, val_mask;
392
393 val_mask = mask << shift;
394 val = (ucontrol->value.integer.value[0] & mask);
395 val2 = (ucontrol->value.integer.value[1] & mask);
396
397 if (val)
398 val = max + 1 - val;
399 if (val2)
400 val2 = max + 1 - val2;
401
402 val = val << shift;
403 val2 = val2 << shift;
404
405 err = snd_soc_update_bits(codec, reg, val_mask, val);
406 if (err < 0)
407 return err;
408
409 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
410 return err;
411}
412
5920b453
GI		 413static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415{
416 struct snd_soc_codec *codec = kcontrol->private_data;
417 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
418 int result = 0;
419
420 /* one bit must be set a time */
421 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
422 | TWL4030_MAINMIC_EN;
423 if (reg != 0) {
424 result++;
425 while ((reg & 1) == 0) {
426 result++;
427 reg >>= 1;
428 }
429 }
430
431 ucontrol->value.integer.value[0] = result;
432 return 0;
433}
434
435static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437{
438 struct snd_soc_codec *codec = kcontrol->private_data;
439 int value = ucontrol->value.integer.value[0];
440 u8 anamicl, micbias, avadc_ctl;
441
442 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
443 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
444 | TWL4030_MAINMIC_EN);
445 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
446 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
447 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
448
449 switch (value) {
450 case 1:
451 anamicl |= TWL4030_MAINMIC_EN;
452 micbias |= TWL4030_MICBIAS1_EN;
453 break;
454 case 2:
455 anamicl |= TWL4030_HSMIC_EN;
456 micbias |= TWL4030_HSMICBIAS_EN;
457 break;
458 case 3:
459 anamicl |= TWL4030_AUXL_EN;
460 break;
461 case 4:
462 anamicl |= TWL4030_CKMIC_EN;
463 break;
464 default:
465 break;
466 }
467
468 /* If some input is selected, enable amp and ADC */
469 if (value != 0) {
470 anamicl |= TWL4030_MICAMPL_EN;
471 avadc_ctl |= TWL4030_ADCL_EN;
472 } else {
473 anamicl &= ~TWL4030_MICAMPL_EN;
474 avadc_ctl &= ~TWL4030_ADCL_EN;
475 }
476
477 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
478 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
479 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
480
481 return 1;
482}
483
484static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486{
487 struct snd_soc_codec *codec = kcontrol->private_data;
488 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
489 int value = 0;
490
491 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
492 switch (reg) {
493 case TWL4030_SUBMIC_EN:
494 value = 1;
495 break;
496 case TWL4030_AUXR_EN:
497 value = 2;
498 break;
499 default:
500 break;
501 }
502
503 ucontrol->value.integer.value[0] = value;
504 return 0;
505}
506
507static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
509{
510 struct snd_soc_codec *codec = kcontrol->private_data;
511 int value = ucontrol->value.integer.value[0];
512 u8 anamicr, micbias, avadc_ctl;
513
514 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
515 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
516 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
517 micbias &= ~TWL4030_MICBIAS2_EN;
518 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
519
520 switch (value) {
521 case 1:
522 anamicr |= TWL4030_SUBMIC_EN;
523 micbias |= TWL4030_MICBIAS2_EN;
524 break;
525 case 2:
526 anamicr |= TWL4030_AUXR_EN;
527 break;
528 default:
529 break;
530 }
531
532 if (value != 0) {
533 anamicr |= TWL4030_MICAMPR_EN;
534 avadc_ctl |= TWL4030_ADCR_EN;
535 } else {
536 anamicr &= ~TWL4030_MICAMPR_EN;
537 avadc_ctl &= ~TWL4030_ADCR_EN;
538 }
539
540 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
541 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
542 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
543
544 return 1;
545}
546
547static const char *twl4030_left_in_sel[] = {
548 "None",
549 "Main Mic",
550 "Headset Mic",
551 "Line In",
552 "Carkit Mic",
553};
554
555static const char *twl4030_right_in_sel[] = {
556 "None",
557 "Sub Mic",
558 "Line In",
559};
560
561static const struct soc_enum twl4030_left_input_mux =
562 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
563 twl4030_left_in_sel);
564
565static const struct soc_enum twl4030_right_input_mux =
566 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
567 twl4030_right_in_sel);
568
c10b82cf
PU		 569/*
570 * FGAIN volume control:
571 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
572 */
d889a72c 573static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 574
0d33ea0b
PU		 575/*
576 * CGAIN volume control:
577 * 0 dB to 12 dB in 6 dB steps
578 * value 2 and 3 means 12 dB
579 */
d889a72c
PU		 580static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
581
582/*
583 * Analog playback gain
584 * -24 dB to 12 dB in 2 dB steps
585 */
586static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 587
4290239c
PU		 588/*
589 * Gain controls tied to outputs
590 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
591 */
592static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
593
381a22b5
PU		 594/*
595 * Capture gain after the ADCs
596 * from 0 dB to 31 dB in 1 dB steps
597 */
598static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
599
5920b453
GI		 600/*
601 * Gain control for input amplifiers
602 * 0 dB to 30 dB in 6 dB steps
603 */
604static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
605
cc17557e 606static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 607 /* Common playback gain controls */
608 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
609 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
610 0, 0x3f, 0, digital_fine_tlv),
611 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
612 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
613 0, 0x3f, 0, digital_fine_tlv),
614
615 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
616 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
617 6, 0x2, 0, digital_coarse_tlv),
618 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
619 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
620 6, 0x2, 0, digital_coarse_tlv),
621
622 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
623 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
624 3, 0x12, 1, analog_tlv),
625 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
626 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
627 3, 0x12, 1, analog_tlv),
44c55870
PU		 628 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
629 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
630 1, 1, 0),
631 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
632 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
633 1, 1, 0),
381a22b5 634
4290239c
PU		 635 /* Separate output gain controls */
636 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
637 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
638 4, 3, 0, output_tvl),
639
640 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
641 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
642
643 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
644 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
645 4, 3, 0, output_tvl),
646
647 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
648 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
649
381a22b5
PU		 650 /* Common capture gain controls */
651 SOC_DOUBLE_R_TLV("Capture Volume",
652 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
653 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 654
655 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
656 0, 3, 5, 0, input_gain_tlv),
657
658 /* Input source controls */
659 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
660 twl4030_get_left_input, twl4030_put_left_input),
661 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
662 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 663};
664
665/* add non dapm controls */
666static int twl4030_add_controls(struct snd_soc_codec *codec)
667{
668 int err, i;
669
670 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
671 err = snd_ctl_add(codec->card,
672 snd_soc_cnew(&twl4030_snd_controls[i],
673 codec, NULL));
674 if (err < 0)
675 return err;
676 }
677
678 return 0;
679}
680
681static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
682 SND_SOC_DAPM_INPUT("INL"),
683 SND_SOC_DAPM_INPUT("INR"),
684
685 SND_SOC_DAPM_OUTPUT("OUTL"),
686 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 687 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 688 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
689 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
cc17557e 690
53b5047d
PU		 691 /* DACs */
692 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
693 TWL4030_REG_AVDAC_CTL, 0, 0),
694 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
695 TWL4030_REG_AVDAC_CTL, 1, 0),
696 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
697 TWL4030_REG_AVDAC_CTL, 2, 0),
698 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
699 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 700
44c55870
PU		 701 /* Analog PGAs */
702 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
703 0, 0, NULL, 0),
704 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
705 0, 0, NULL, 0),
706 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
707 0, 0, NULL, 0),
708 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
709 0, 0, NULL, 0),
710
5e98a464
PU		 711 /* Output MUX controls */
712 /* Earpiece */
713 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
714 &twl4030_dapm_earpiece_control, outmixer_event,
715 SND_SOC_DAPM_PRE_REG),
2a6f5c58
PU		 716 /* PreDrivL/R */
717 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
718 &twl4030_dapm_predrivel_control, outmixer_event,
719 SND_SOC_DAPM_PRE_REG),
720 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
721 &twl4030_dapm_predriver_control, outmixer_event,
722 SND_SOC_DAPM_PRE_REG),
5e98a464 723
cc17557e
SS		 724 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
725 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
726};
727
728static const struct snd_soc_dapm_route intercon[] = {
44c55870
PU		 729 {"ARXL1_APGA", NULL, "DACL1"},
730 {"ARXR1_APGA", NULL, "DACR1"},
731 {"ARXL2_APGA", NULL, "DACL2"},
732 {"ARXR2_APGA", NULL, "DACR2"},
733
5e98a464
PU		 734 /* Internal playback routings */
735 /* Earpiece */
736 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
737 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
738 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 739 /* PreDrivL */
740 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
741 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
742 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
743 /* PreDrivR */
744 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
745 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
746 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 747
cc17557e 748 /* outputs */
44c55870
PU		 749 {"OUTL", NULL, "ARXL2_APGA"},
750 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 751 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 752 {"PREDRIVEL", NULL, "PredriveL Mux"},
753 {"PREDRIVER", NULL, "PredriveR Mux"},
cc17557e
SS		 754
755 /* inputs */
756 {"ADCL", NULL, "INL"},
757 {"ADCR", NULL, "INR"},
758};
759
760static int twl4030_add_widgets(struct snd_soc_codec *codec)
761{
762 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
763 ARRAY_SIZE(twl4030_dapm_widgets));
764
765 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
766
767 snd_soc_dapm_new_widgets(codec);
768 return 0;
769}
770
771static void twl4030_power_up(struct snd_soc_codec *codec)
772{
773 u8 anamicl, regmisc1, byte, popn, hsgain;
774 int i = 0;
775
776 /* set CODECPDZ to turn on codec */
777 twl4030_set_codecpdz(codec);
778
779 /* initiate offset cancellation */
780 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
781 twl4030_write(codec, TWL4030_REG_ANAMICL,
782 anamicl | TWL4030_CNCL_OFFSET_START);
783
784 /* wait for offset cancellation to complete */
785 do {
786 /* this takes a little while, so don't slam i2c */
787 udelay(2000);
788 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
789 TWL4030_REG_ANAMICL);
790 } while ((i++ < 100) &&
791 ((byte & TWL4030_CNCL_OFFSET_START) ==
792 TWL4030_CNCL_OFFSET_START));
793
794 /* anti-pop when changing analog gain */
795 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
796 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
797 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
798
799 /* toggle CODECPDZ as per TRM */
800 twl4030_clear_codecpdz(codec);
801 twl4030_set_codecpdz(codec);
802
803 /* program anti-pop with bias ramp delay */
804 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
805 popn &= TWL4030_RAMP_DELAY;
806 popn |= TWL4030_RAMP_DELAY_645MS;
807 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
808 popn |= TWL4030_VMID_EN;
809 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
810
811 /* enable output stage and gain setting */
812 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
813 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
814
815 /* enable anti-pop ramp */
816 popn |= TWL4030_RAMP_EN;
817 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
818}
819
820static void twl4030_power_down(struct snd_soc_codec *codec)
821{
822 u8 popn, hsgain;
823
824 /* disable anti-pop ramp */
825 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
826 popn &= ~TWL4030_RAMP_EN;
827 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
828
829 /* disable output stage and gain setting */
830 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
831 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
832
833 /* disable bias out */
834 popn &= ~TWL4030_VMID_EN;
835 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
836
837 /* power down */
838 twl4030_clear_codecpdz(codec);
839}
840
841static int twl4030_set_bias_level(struct snd_soc_codec *codec,
842 enum snd_soc_bias_level level)
843{
844 switch (level) {
845 case SND_SOC_BIAS_ON:
846 twl4030_power_up(codec);
847 break;
848 case SND_SOC_BIAS_PREPARE:
849 /* TODO: develop a twl4030_prepare function */
850 break;
851 case SND_SOC_BIAS_STANDBY:
852 /* TODO: develop a twl4030_standby function */
853 twl4030_power_down(codec);
854 break;
855 case SND_SOC_BIAS_OFF:
856 twl4030_power_down(codec);
857 break;
858 }
859 codec->bias_level = level;
860
861 return 0;
862}
863
864static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 865 struct snd_pcm_hw_params *params,
866 struct snd_soc_dai *dai)
cc17557e
SS		 867{
868 struct snd_soc_pcm_runtime *rtd = substream->private_data;
869 struct snd_soc_device *socdev = rtd->socdev;
870 struct snd_soc_codec *codec = socdev->codec;
871 u8 mode, old_mode, format, old_format;
872
873
874 /* bit rate */
875 old_mode = twl4030_read_reg_cache(codec,
876 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
877 mode = old_mode & ~TWL4030_APLL_RATE;
878
879 switch (params_rate(params)) {
880 case 8000:
881 mode |= TWL4030_APLL_RATE_8000;
882 break;
883 case 11025:
884 mode |= TWL4030_APLL_RATE_11025;
885 break;
886 case 12000:
887 mode |= TWL4030_APLL_RATE_12000;
888 break;
889 case 16000:
890 mode |= TWL4030_APLL_RATE_16000;
891 break;
892 case 22050:
893 mode |= TWL4030_APLL_RATE_22050;
894 break;
895 case 24000:
896 mode |= TWL4030_APLL_RATE_24000;
897 break;
898 case 32000:
899 mode |= TWL4030_APLL_RATE_32000;
900 break;
901 case 44100:
902 mode |= TWL4030_APLL_RATE_44100;
903 break;
904 case 48000:
905 mode |= TWL4030_APLL_RATE_48000;
906 break;
907 default:
908 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
909 params_rate(params));
910 return -EINVAL;
911 }
912
913 if (mode != old_mode) {
914 /* change rate and set CODECPDZ */
915 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
916 twl4030_set_codecpdz(codec);
917 }
918
919 /* sample size */
920 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
921 format = old_format;
922 format &= ~TWL4030_DATA_WIDTH;
923 switch (params_format(params)) {
924 case SNDRV_PCM_FORMAT_S16_LE:
925 format |= TWL4030_DATA_WIDTH_16S_16W;
926 break;
927 case SNDRV_PCM_FORMAT_S24_LE:
928 format |= TWL4030_DATA_WIDTH_32S_24W;
929 break;
930 default:
931 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
932 params_format(params));
933 return -EINVAL;
934 }
935
936 if (format != old_format) {
937
938 /* clear CODECPDZ before changing format (codec requirement) */
939 twl4030_clear_codecpdz(codec);
940
941 /* change format */
942 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
943
944 /* set CODECPDZ afterwards */
945 twl4030_set_codecpdz(codec);
946 }
947 return 0;
948}
949
950static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
951 int clk_id, unsigned int freq, int dir)
952{
953 struct snd_soc_codec *codec = codec_dai->codec;
954 u8 infreq;
955
956 switch (freq) {
957 case 19200000:
958 infreq = TWL4030_APLL_INFREQ_19200KHZ;
959 break;
960 case 26000000:
961 infreq = TWL4030_APLL_INFREQ_26000KHZ;
962 break;
963 case 38400000:
964 infreq = TWL4030_APLL_INFREQ_38400KHZ;
965 break;
966 default:
967 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
968 freq);
969 return -EINVAL;
970 }
971
972 infreq |= TWL4030_APLL_EN;
973 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
974
975 return 0;
976}
977
978static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
979 unsigned int fmt)
980{
981 struct snd_soc_codec *codec = codec_dai->codec;
982 u8 old_format, format;
983
984 /* get format */
985 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
986 format = old_format;
987
988 /* set master/slave audio interface */
989 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
990 case SND_SOC_DAIFMT_CBM_CFM:
991 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 992 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 993 break;
994 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 995 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 996 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 997 break;
998 default:
999 return -EINVAL;
1000 }
1001
1002 /* interface format */
1003 format &= ~TWL4030_AIF_FORMAT;
1004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1005 case SND_SOC_DAIFMT_I2S:
1006 format |= TWL4030_AIF_FORMAT_CODEC;
1007 break;
1008 default:
1009 return -EINVAL;
1010 }
1011
1012 if (format != old_format) {
1013
1014 /* clear CODECPDZ before changing format (codec requirement) */
1015 twl4030_clear_codecpdz(codec);
1016
1017 /* change format */
1018 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1019
1020 /* set CODECPDZ afterwards */
1021 twl4030_set_codecpdz(codec);
1022 }
1023
1024 return 0;
1025}
1026
bbba9444 1027#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1028#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1029
1030struct snd_soc_dai twl4030_dai = {
1031 .name = "twl4030",
1032 .playback = {
1033 .stream_name = "Playback",
1034 .channels_min = 2,
1035 .channels_max = 2,
1036 .rates = TWL4030_RATES,
1037 .formats = TWL4030_FORMATS,},
1038 .capture = {
1039 .stream_name = "Capture",
1040 .channels_min = 2,
1041 .channels_max = 2,
1042 .rates = TWL4030_RATES,
1043 .formats = TWL4030_FORMATS,},
1044 .ops = {
1045 .hw_params = twl4030_hw_params,
cc17557e
SS		 1046 .set_sysclk = twl4030_set_dai_sysclk,
1047 .set_fmt = twl4030_set_dai_fmt,
1048 }
1049};
1050EXPORT_SYMBOL_GPL(twl4030_dai);
1051
1052static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1053{
1054 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1055 struct snd_soc_codec *codec = socdev->codec;
1056
1057 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1058
1059 return 0;
1060}
1061
1062static int twl4030_resume(struct platform_device *pdev)
1063{
1064 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1065 struct snd_soc_codec *codec = socdev->codec;
1066
1067 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1068 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1069 return 0;
1070}
1071
1072/*
1073 * initialize the driver
1074 * register the mixer and dsp interfaces with the kernel
1075 */
1076
1077static int twl4030_init(struct snd_soc_device *socdev)
1078{
1079 struct snd_soc_codec *codec = socdev->codec;
1080 int ret = 0;
1081
1082 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1083
1084 codec->name = "twl4030";
1085 codec->owner = THIS_MODULE;
1086 codec->read = twl4030_read_reg_cache;
1087 codec->write = twl4030_write;
1088 codec->set_bias_level = twl4030_set_bias_level;
1089 codec->dai = &twl4030_dai;
1090 codec->num_dai = 1;
1091 codec->reg_cache_size = sizeof(twl4030_reg);
1092 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1093 GFP_KERNEL);
1094 if (codec->reg_cache == NULL)
1095 return -ENOMEM;
1096
1097 /* register pcms */
1098 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1099 if (ret < 0) {
1100 printk(KERN_ERR "twl4030: failed to create pcms\n");
1101 goto pcm_err;
1102 }
1103
1104 twl4030_init_chip(codec);
1105
1106 /* power on device */
1107 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1108
1109 twl4030_add_controls(codec);
1110 twl4030_add_widgets(codec);
1111
968a6025 1112 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1113 if (ret < 0) {
1114 printk(KERN_ERR "twl4030: failed to register card\n");
1115 goto card_err;
1116 }
1117
1118 return ret;
1119
1120card_err:
1121 snd_soc_free_pcms(socdev);
1122 snd_soc_dapm_free(socdev);
1123pcm_err:
1124 kfree(codec->reg_cache);
1125 return ret;
1126}
1127
1128static struct snd_soc_device *twl4030_socdev;
1129
1130static int twl4030_probe(struct platform_device *pdev)
1131{
1132 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1133 struct snd_soc_codec *codec;
1134
1135 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1136 if (codec == NULL)
1137 return -ENOMEM;
1138
1139 socdev->codec = codec;
1140 mutex_init(&codec->mutex);
1141 INIT_LIST_HEAD(&codec->dapm_widgets);
1142 INIT_LIST_HEAD(&codec->dapm_paths);
1143
1144 twl4030_socdev = socdev;
1145 twl4030_init(socdev);
1146
1147 return 0;
1148}
1149
1150static int twl4030_remove(struct platform_device *pdev)
1151{
1152 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1153 struct snd_soc_codec *codec = socdev->codec;
1154
1155 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1156 kfree(codec);
1157
1158 return 0;
1159}
1160
1161struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1162 .probe = twl4030_probe,
1163 .remove = twl4030_remove,
1164 .suspend = twl4030_suspend,
1165 .resume = twl4030_resume,
1166};
1167EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1168
1169MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1170MODULE_AUTHOR("Steve Sakoman");
1171MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.084558 seconds and 5 git commands to generate.