projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: TWL4030: Add AVADC Clock Priority
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
d08664fd 148 u8 *cache = codec->reg_cache;
cc17557e 149
91432e97
IM		 150 if (reg >= TWL4030_CACHEREGNUM)
151 return -EIO;
152
cc17557e
SS		 153 return cache[reg];
154}
155
156/*
157 * write twl4030 register cache
158 */
159static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
160 u8 reg, u8 value)
161{
162 u8 *cache = codec->reg_cache;
163
164 if (reg >= TWL4030_CACHEREGNUM)
165 return;
166 cache[reg] = value;
167}
168
169/*
170 * write to the twl4030 register space
171 */
172static int twl4030_write(struct snd_soc_codec *codec,
173 unsigned int reg, unsigned int value)
174{
175 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
cc17557e
SS		 181}
182
db04e2c5 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 184{
7393958f 185 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 186 u8 mode;
187
7393958f
PU		 188 if (enable == twl4030->codec_powered)
189 return;
190
cc17557e 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 192 if (enable)
193 mode |= TWL4030_CODECPDZ;
194 else
195 mode &= ~TWL4030_CODECPDZ;
cc17557e 196
db04e2c5 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 198 twl4030->codec_powered = enable;
cc17557e
SS		 199
200 /* REVISIT: this delay is present in TI sample drivers */
201 /* but there seems to be no TRM requirement for it */
202 udelay(10);
203}
204
205static void twl4030_init_chip(struct snd_soc_codec *codec)
206{
16a30fbb 207 u8 *cache = codec->reg_cache;
cc17557e
SS		 208 int i;
209
210 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 211 twl4030_codec_enable(codec, 0);
cc17557e
SS		 212
213 /* set all audio section registers to reasonable defaults */
214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 215 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 216
217}
218
7393958f
PU		 219static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
220{
221 struct twl4030_priv *twl4030 = codec->private_data;
222 u8 reg_val;
223
224 if (mute == twl4030->codec_muted)
225 return;
226
227 if (mute) {
228 /* Bypass the reg_cache and mute the volumes
229 * Headset mute is done in it's own event handler
230 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
231 */
232 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
233 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
234 reg_val & (~TWL4030_EAR_GAIN),
235 TWL4030_REG_EAR_CTL);
236
237 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
238 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
239 reg_val & (~TWL4030_PREDL_GAIN),
240 TWL4030_REG_PREDL_CTL);
241 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
242 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
243 reg_val & (~TWL4030_PREDR_GAIN),
244 TWL4030_REG_PREDL_CTL);
245
246 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
247 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
248 reg_val & (~TWL4030_PRECKL_GAIN),
249 TWL4030_REG_PRECKL_CTL);
250 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
251 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 252 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 253 TWL4030_REG_PRECKR_CTL);
254
255 /* Disable PLL */
256 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
257 reg_val &= ~TWL4030_APLL_EN;
258 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
259 } else {
260 /* Restore the volumes
261 * Headset mute is done in it's own event handler
262 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
263 */
264 twl4030_write(codec, TWL4030_REG_EAR_CTL,
265 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
266
267 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
268 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
269 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
270 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
271
272 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
273 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
274 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
275 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
276
277 /* Enable PLL */
278 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
279 reg_val |= TWL4030_APLL_EN;
280 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
281 }
282
283 twl4030->codec_muted = mute;
284}
285
006f367e
PU		 286static void twl4030_power_up(struct snd_soc_codec *codec)
287{
7393958f 288 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 289 u8 anamicl, regmisc1, byte;
290 int i = 0;
291
7393958f
PU		 292 if (twl4030->codec_powered)
293 return;
294
006f367e
PU		 295 /* set CODECPDZ to turn on codec */
296 twl4030_codec_enable(codec, 1);
297
298 /* initiate offset cancellation */
299 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
300 twl4030_write(codec, TWL4030_REG_ANAMICL,
301 anamicl | TWL4030_CNCL_OFFSET_START);
302
303 /* wait for offset cancellation to complete */
304 do {
305 /* this takes a little while, so don't slam i2c */
306 udelay(2000);
307 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
308 TWL4030_REG_ANAMICL);
309 } while ((i++ < 100) &&
310 ((byte & TWL4030_CNCL_OFFSET_START) ==
311 TWL4030_CNCL_OFFSET_START));
312
313 /* Make sure that the reg_cache has the same value as the HW */
314 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
315
316 /* anti-pop when changing analog gain */
317 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
318 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
319 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
320
321 /* toggle CODECPDZ as per TRM */
322 twl4030_codec_enable(codec, 0);
323 twl4030_codec_enable(codec, 1);
324}
325
7393958f
PU		 326/*
327 * Unconditional power down
328 */
006f367e
PU		 329static void twl4030_power_down(struct snd_soc_codec *codec)
330{
331 /* power down */
332 twl4030_codec_enable(codec, 0);
333}
334
5e98a464 335/* Earpiece */
1a787e7a
JS		 336static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
337 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
338 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
339 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
341};
5e98a464 342
2a6f5c58 343/* PreDrive Left */
1a787e7a
JS		 344static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
345 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
346 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
347 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
348 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
349};
2a6f5c58
PU		 350
351/* PreDrive Right */
1a787e7a
JS		 352static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
353 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
354 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
355 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
356 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
357};
2a6f5c58 358
dfad21a2 359/* Headset Left */
1a787e7a
JS		 360static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
361 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
362 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
363 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
364};
dfad21a2
PU		 365
366/* Headset Right */
1a787e7a
JS		 367static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
368 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
369 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
370 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
371};
dfad21a2 372
5152d8c2 373/* Carkit Left */
1a787e7a
JS		 374static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
375 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
376 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
377 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
378};
5152d8c2
PU		 379
380/* Carkit Right */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
385};
5152d8c2 386
df339804
PU		 387/* Handsfree Left */
388static const char *twl4030_handsfreel_texts[] =
1a787e7a 389 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreel_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreel_texts),
394 twl4030_handsfreel_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
398
0f89bdca
PU		 399/* Handsfree Left virtual mute */
400static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
401 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
402
df339804
PU		 403/* Handsfree Right */
404static const char *twl4030_handsfreer_texts[] =
1a787e7a 405 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 406
407static const struct soc_enum twl4030_handsfreer_enum =
408 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
409 ARRAY_SIZE(twl4030_handsfreer_texts),
410 twl4030_handsfreer_texts);
411
412static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
413SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
414
0f89bdca
PU		 415/* Handsfree Right virtual mute */
416static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
417 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
418
376f7839
PU		 419/* Vibra */
420/* Vibra audio path selection */
421static const char *twl4030_vibra_texts[] =
422 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
423
424static const struct soc_enum twl4030_vibra_enum =
425 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
426 ARRAY_SIZE(twl4030_vibra_texts),
427 twl4030_vibra_texts);
428
429static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
430SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
431
432/* Vibra path selection: local vibrator (PWM) or audio driven */
433static const char *twl4030_vibrapath_texts[] =
434 {"Local vibrator", "Audio"};
435
436static const struct soc_enum twl4030_vibrapath_enum =
437 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
438 ARRAY_SIZE(twl4030_vibrapath_texts),
439 twl4030_vibrapath_texts);
440
441static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
442SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
443
276c6222 444/* Left analog microphone selection */
97b8096d
JS		 445static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
446 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
447 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
448 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
449 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
450};
276c6222
PU		 451
452/* Right analog microphone selection */
97b8096d
JS		 453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
454 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 455 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 456};
276c6222
PU		 457
458/* TX1 L/R Analog/Digital microphone selection */
459static const char *twl4030_micpathtx1_texts[] =
460 {"Analog", "Digimic0"};
461
462static const struct soc_enum twl4030_micpathtx1_enum =
463 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
464 ARRAY_SIZE(twl4030_micpathtx1_texts),
465 twl4030_micpathtx1_texts);
466
467static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
468SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
469
470/* TX2 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx2_texts[] =
472 {"Analog", "Digimic1"};
473
474static const struct soc_enum twl4030_micpathtx2_enum =
475 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
476 ARRAY_SIZE(twl4030_micpathtx2_texts),
477 twl4030_micpathtx2_texts);
478
479static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
480SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
481
7393958f
PU		 482/* Analog bypass for AudioR1 */
483static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
484 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
485
486/* Analog bypass for AudioL1 */
487static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
488 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
489
490/* Analog bypass for AudioR2 */
491static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
492 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
493
494/* Analog bypass for AudioL2 */
495static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
497
fcd274a3
LCM		 498/* Analog bypass for Voice */
499static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
501
6bab83fd
PU		 502/* Digital bypass gain, 0 mutes the bypass */
503static const unsigned int twl4030_dapm_dbypass_tlv[] = {
504 TLV_DB_RANGE_HEAD(2),
505 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
506 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
507};
508
509/* Digital bypass left (TX1L -> RX2L) */
510static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
511 SOC_DAPM_SINGLE_TLV("Volume",
512 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
513 twl4030_dapm_dbypass_tlv);
514
515/* Digital bypass right (TX1R -> RX2R) */
516static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
517 SOC_DAPM_SINGLE_TLV("Volume",
518 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
519 twl4030_dapm_dbypass_tlv);
520
ee8f6894
LCM		 521/*
522 * Voice Sidetone GAIN volume control:
523 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
524 */
525static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
526
527/* Digital bypass voice: sidetone (VUL -> VDL)*/
528static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
529 SOC_DAPM_SINGLE_TLV("Volume",
530 TWL4030_REG_VSTPGA, 0, 0x29, 0,
531 twl4030_dapm_dbypassv_tlv);
532
276c6222
PU		 533static int micpath_event(struct snd_soc_dapm_widget *w,
534 struct snd_kcontrol *kcontrol, int event)
535{
536 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
537 unsigned char adcmicsel, micbias_ctl;
538
539 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
540 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
541 /* Prepare the bits for the given TX path:
542 * shift_l == 0: TX1 microphone path
543 * shift_l == 2: TX2 microphone path */
544 if (e->shift_l) {
545 /* TX2 microphone path */
546 if (adcmicsel & TWL4030_TX2IN_SEL)
547 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
548 else
549 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
550 } else {
551 /* TX1 microphone path */
552 if (adcmicsel & TWL4030_TX1IN_SEL)
553 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
554 else
555 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
556 }
557
558 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
559
560 return 0;
561}
562
5a2e9a48 563static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 564{
49d92c7d
SM		 565 unsigned char hs_ctl;
566
5a2e9a48 567 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 568
5a2e9a48
PU		 569 if (ramp) {
570 /* HF ramp-up */
571 hs_ctl |= TWL4030_HF_CTL_REF_EN;
572 twl4030_write(codec, reg, hs_ctl);
573 udelay(10);
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 575 twl4030_write(codec, reg, hs_ctl);
576 udelay(40);
49d92c7d 577 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 578 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 579 twl4030_write(codec, reg, hs_ctl);
49d92c7d 580 } else {
5a2e9a48
PU		 581 /* HF ramp-down */
582 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
583 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
584 twl4030_write(codec, reg, hs_ctl);
585 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
586 twl4030_write(codec, reg, hs_ctl);
587 udelay(40);
588 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
589 twl4030_write(codec, reg, hs_ctl);
49d92c7d 590 }
5a2e9a48 591}
49d92c7d 592
5a2e9a48
PU		 593static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
594 struct snd_kcontrol *kcontrol, int event)
595{
596 switch (event) {
597 case SND_SOC_DAPM_POST_PMU:
598 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
599 break;
600 case SND_SOC_DAPM_POST_PMD:
601 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
602 break;
603 }
604 return 0;
605}
606
607static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
608 struct snd_kcontrol *kcontrol, int event)
609{
610 switch (event) {
611 case SND_SOC_DAPM_POST_PMU:
612 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
613 break;
614 case SND_SOC_DAPM_POST_PMD:
615 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
616 break;
617 }
49d92c7d
SM		 618 return 0;
619}
620
6943c92e 621static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 622{
623 unsigned char hs_gain, hs_pop;
6943c92e
PU		 624 struct twl4030_priv *twl4030 = codec->private_data;
625 /* Base values for ramp delay calculation: 2^19 - 2^26 */
626 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
627 8388608, 16777216, 33554432, 67108864};
aad749e5 628
6943c92e
PU		 629 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
630 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 631
6943c92e
PU		 632 if (ramp) {
633 /* Headset ramp-up according to the TRM */
aad749e5 634 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 635 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
636 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 637 hs_pop |= TWL4030_RAMP_EN;
6943c92e
PU		 638 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
639 } else {
640 /* Headset ramp-down _not_ according to
641 * the TRM, but in a way that it is working */
aad749e5 642 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 643 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
644 /* Wait ramp delay time + 1, so the VMID can settle */
645 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
646 twl4030->sysclk) + 1);
aad749e5
PU		 647 /* Bypass the reg_cache to mute the headset */
648 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
649 hs_gain & (~0x0f),
650 TWL4030_REG_HS_GAIN_SET);
6943c92e 651
aad749e5 652 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 653 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
654 }
655}
656
657static int headsetlpga_event(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *kcontrol, int event)
659{
660 struct twl4030_priv *twl4030 = w->codec->private_data;
661
662 switch (event) {
663 case SND_SOC_DAPM_POST_PMU:
664 /* Do the ramp-up only once */
665 if (!twl4030->hsr_enabled)
666 headset_ramp(w->codec, 1);
667
668 twl4030->hsl_enabled = 1;
669 break;
670 case SND_SOC_DAPM_POST_PMD:
671 /* Do the ramp-down only if both headsetL/R is disabled */
672 if (!twl4030->hsr_enabled)
673 headset_ramp(w->codec, 0);
674
675 twl4030->hsl_enabled = 0;
676 break;
677 }
678 return 0;
679}
680
681static int headsetrpga_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683{
684 struct twl4030_priv *twl4030 = w->codec->private_data;
685
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 /* Do the ramp-up only once */
689 if (!twl4030->hsl_enabled)
690 headset_ramp(w->codec, 1);
691
692 twl4030->hsr_enabled = 1;
693 break;
694 case SND_SOC_DAPM_POST_PMD:
695 /* Do the ramp-down only if both headsetL/R is disabled */
696 if (!twl4030->hsl_enabled)
697 headset_ramp(w->codec, 0);
698
699 twl4030->hsr_enabled = 0;
aad749e5
PU		 700 break;
701 }
702 return 0;
703}
704
7393958f
PU		 705static int bypass_event(struct snd_soc_dapm_widget *w,
706 struct snd_kcontrol *kcontrol, int event)
707{
708 struct soc_mixer_control *m =
709 (struct soc_mixer_control *)w->kcontrols->private_value;
710 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 711 unsigned char reg, misc;
7393958f
PU		 712
713 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 714
715 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
716 /* Analog bypass */
717 if (reg & (1 << m->shift))
718 twl4030->bypass_state |=
719 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
720 else
721 twl4030->bypass_state &=
722 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 723 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
724 /* Analog voice bypass */
725 if (reg & (1 << m->shift))
726 twl4030->bypass_state |= (1 << 4);
727 else
728 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 729 } else if (m->reg == TWL4030_REG_VSTPGA) {
730 /* Voice digital bypass */
731 if (reg)
732 twl4030->bypass_state |= (1 << 5);
733 else
734 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 735 } else {
736 /* Digital bypass */
737 if (reg & (0x7 << m->shift))
ee8f6894 738 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 739 else
ee8f6894 740 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 741 }
7393958f 742
fcd274a3
LCM		 743 /* Enable master analog loopback mode if any analog switch is enabled*/
744 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
745 if (twl4030->bypass_state & 0x1F)
746 misc |= TWL4030_FMLOOP_EN;
747 else
748 misc &= ~TWL4030_FMLOOP_EN;
749 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
750
7393958f
PU		 751 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
752 if (twl4030->bypass_state)
753 twl4030_codec_mute(w->codec, 0);
754 else
755 twl4030_codec_mute(w->codec, 1);
756 }
757 return 0;
758}
759
b0bd53a7
PU		 760/*
761 * Some of the gain controls in TWL (mostly those which are associated with
762 * the outputs) are implemented in an interesting way:
763 * 0x0 : Power down (mute)
764 * 0x1 : 6dB
765 * 0x2 : 0 dB
766 * 0x3 : -6 dB
767 * Inverting not going to help with these.
768 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
769 */
770#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
771 xinvert, tlv_array) \
772{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
773 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
774 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
775 .tlv.p = (tlv_array), \
776 .info = snd_soc_info_volsw, \
777 .get = snd_soc_get_volsw_twl4030, \
778 .put = snd_soc_put_volsw_twl4030, \
779 .private_value = (unsigned long)&(struct soc_mixer_control) \
780 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
781 .max = xmax, .invert = xinvert} }
782#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
783 xinvert, tlv_array) \
784{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
785 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
786 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
787 .tlv.p = (tlv_array), \
788 .info = snd_soc_info_volsw_2r, \
789 .get = snd_soc_get_volsw_r2_twl4030,\
790 .put = snd_soc_put_volsw_r2_twl4030, \
791 .private_value = (unsigned long)&(struct soc_mixer_control) \
792 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 793 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 794#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
795 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
796 xinvert, tlv_array)
797
798static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
800{
801 struct soc_mixer_control *mc =
802 (struct soc_mixer_control *)kcontrol->private_value;
803 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
804 unsigned int reg = mc->reg;
805 unsigned int shift = mc->shift;
806 unsigned int rshift = mc->rshift;
807 int max = mc->max;
808 int mask = (1 << fls(max)) - 1;
809
810 ucontrol->value.integer.value[0] =
811 (snd_soc_read(codec, reg) >> shift) & mask;
812 if (ucontrol->value.integer.value[0])
813 ucontrol->value.integer.value[0] =
814 max + 1 - ucontrol->value.integer.value[0];
815
816 if (shift != rshift) {
817 ucontrol->value.integer.value[1] =
818 (snd_soc_read(codec, reg) >> rshift) & mask;
819 if (ucontrol->value.integer.value[1])
820 ucontrol->value.integer.value[1] =
821 max + 1 - ucontrol->value.integer.value[1];
822 }
823
824 return 0;
825}
826
827static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
828 struct snd_ctl_elem_value *ucontrol)
829{
830 struct soc_mixer_control *mc =
831 (struct soc_mixer_control *)kcontrol->private_value;
832 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
833 unsigned int reg = mc->reg;
834 unsigned int shift = mc->shift;
835 unsigned int rshift = mc->rshift;
836 int max = mc->max;
837 int mask = (1 << fls(max)) - 1;
838 unsigned short val, val2, val_mask;
839
840 val = (ucontrol->value.integer.value[0] & mask);
841
842 val_mask = mask << shift;
843 if (val)
844 val = max + 1 - val;
845 val = val << shift;
846 if (shift != rshift) {
847 val2 = (ucontrol->value.integer.value[1] & mask);
848 val_mask |= mask << rshift;
849 if (val2)
850 val2 = max + 1 - val2;
851 val |= val2 << rshift;
852 }
853 return snd_soc_update_bits(codec, reg, val_mask, val);
854}
855
856static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
857 struct snd_ctl_elem_value *ucontrol)
858{
859 struct soc_mixer_control *mc =
860 (struct soc_mixer_control *)kcontrol->private_value;
861 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
862 unsigned int reg = mc->reg;
863 unsigned int reg2 = mc->rreg;
864 unsigned int shift = mc->shift;
865 int max = mc->max;
866 int mask = (1<<fls(max))-1;
867
868 ucontrol->value.integer.value[0] =
869 (snd_soc_read(codec, reg) >> shift) & mask;
870 ucontrol->value.integer.value[1] =
871 (snd_soc_read(codec, reg2) >> shift) & mask;
872
873 if (ucontrol->value.integer.value[0])
874 ucontrol->value.integer.value[0] =
875 max + 1 - ucontrol->value.integer.value[0];
876 if (ucontrol->value.integer.value[1])
877 ucontrol->value.integer.value[1] =
878 max + 1 - ucontrol->value.integer.value[1];
879
880 return 0;
881}
882
883static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
884 struct snd_ctl_elem_value *ucontrol)
885{
886 struct soc_mixer_control *mc =
887 (struct soc_mixer_control *)kcontrol->private_value;
888 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
889 unsigned int reg = mc->reg;
890 unsigned int reg2 = mc->rreg;
891 unsigned int shift = mc->shift;
892 int max = mc->max;
893 int mask = (1 << fls(max)) - 1;
894 int err;
895 unsigned short val, val2, val_mask;
896
897 val_mask = mask << shift;
898 val = (ucontrol->value.integer.value[0] & mask);
899 val2 = (ucontrol->value.integer.value[1] & mask);
900
901 if (val)
902 val = max + 1 - val;
903 if (val2)
904 val2 = max + 1 - val2;
905
906 val = val << shift;
907 val2 = val2 << shift;
908
909 err = snd_soc_update_bits(codec, reg, val_mask, val);
910 if (err < 0)
911 return err;
912
913 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
914 return err;
915}
916
b74bd40f
LCM		 917/* Codec operation modes */
918static const char *twl4030_op_modes_texts[] = {
919 "Option 2 (voice/audio)", "Option 1 (audio)"
920};
921
922static const struct soc_enum twl4030_op_modes_enum =
923 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
924 ARRAY_SIZE(twl4030_op_modes_texts),
925 twl4030_op_modes_texts);
926
423c238d 927static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 928 struct snd_ctl_elem_value *ucontrol)
929{
930 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
931 struct twl4030_priv *twl4030 = codec->private_data;
932 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
933 unsigned short val;
934 unsigned short mask, bitmask;
935
936 if (twl4030->configured) {
937 printk(KERN_ERR "twl4030 operation mode cannot be "
938 "changed on-the-fly\n");
939 return -EBUSY;
940 }
941
942 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
943 ;
944 if (ucontrol->value.enumerated.item[0] > e->max - 1)
945 return -EINVAL;
946
947 val = ucontrol->value.enumerated.item[0] << e->shift_l;
948 mask = (bitmask - 1) << e->shift_l;
949 if (e->shift_l != e->shift_r) {
950 if (ucontrol->value.enumerated.item[1] > e->max - 1)
951 return -EINVAL;
952 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
953 mask |= (bitmask - 1) << e->shift_r;
954 }
955
956 return snd_soc_update_bits(codec, e->reg, mask, val);
957}
958
c10b82cf
PU		 959/*
960 * FGAIN volume control:
961 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
962 */
d889a72c 963static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 964
0d33ea0b
PU		 965/*
966 * CGAIN volume control:
967 * 0 dB to 12 dB in 6 dB steps
968 * value 2 and 3 means 12 dB
969 */
d889a72c
PU		 970static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
971
1a787e7a
JS		 972/*
973 * Voice Downlink GAIN volume control:
974 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
975 */
976static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
977
d889a72c
PU		 978/*
979 * Analog playback gain
980 * -24 dB to 12 dB in 2 dB steps
981 */
982static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 983
4290239c
PU		 984/*
985 * Gain controls tied to outputs
986 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
987 */
988static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
989
18cc8d8d
JS		 990/*
991 * Gain control for earpiece amplifier
992 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
993 */
994static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
995
381a22b5
PU		 996/*
997 * Capture gain after the ADCs
998 * from 0 dB to 31 dB in 1 dB steps
999 */
1000static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1001
5920b453
GI		 1002/*
1003 * Gain control for input amplifiers
1004 * 0 dB to 30 dB in 6 dB steps
1005 */
1006static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1007
328d0a13
LCM		 1008/* AVADC clock priority */
1009static const char *twl4030_avadc_clk_priority_texts[] = {
1010 "Voice high priority", "HiFi high priority"
1011};
1012
1013static const struct soc_enum twl4030_avadc_clk_priority_enum =
1014 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1015 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1016 twl4030_avadc_clk_priority_texts);
1017
89492be8
PU		 1018static const char *twl4030_rampdelay_texts[] = {
1019 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1020 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1021 "3495/2581/1748 ms"
1022};
1023
1024static const struct soc_enum twl4030_rampdelay_enum =
1025 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1026 ARRAY_SIZE(twl4030_rampdelay_texts),
1027 twl4030_rampdelay_texts);
1028
376f7839
PU		 1029/* Vibra H-bridge direction mode */
1030static const char *twl4030_vibradirmode_texts[] = {
1031 "Vibra H-bridge direction", "Audio data MSB",
1032};
1033
1034static const struct soc_enum twl4030_vibradirmode_enum =
1035 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1036 ARRAY_SIZE(twl4030_vibradirmode_texts),
1037 twl4030_vibradirmode_texts);
1038
1039/* Vibra H-bridge direction */
1040static const char *twl4030_vibradir_texts[] = {
1041 "Positive polarity", "Negative polarity",
1042};
1043
1044static const struct soc_enum twl4030_vibradir_enum =
1045 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1046 ARRAY_SIZE(twl4030_vibradir_texts),
1047 twl4030_vibradir_texts);
1048
cc17557e 1049static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1050 /* Codec operation mode control */
1051 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1052 snd_soc_get_enum_double,
1053 snd_soc_put_twl4030_opmode_enum_double),
1054
d889a72c
PU		 1055 /* Common playback gain controls */
1056 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1057 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1058 0, 0x3f, 0, digital_fine_tlv),
1059 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1060 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1061 0, 0x3f, 0, digital_fine_tlv),
1062
1063 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1064 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1065 6, 0x2, 0, digital_coarse_tlv),
1066 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1067 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1068 6, 0x2, 0, digital_coarse_tlv),
1069
1070 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1071 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1072 3, 0x12, 1, analog_tlv),
1073 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1074 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1075 3, 0x12, 1, analog_tlv),
44c55870
PU		 1076 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1077 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1078 1, 1, 0),
1079 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1080 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1081 1, 1, 0),
381a22b5 1082
1a787e7a
JS		 1083 /* Common voice downlink gain controls */
1084 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1085 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1086
1087 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1088 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1089
1090 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1091 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1092
4290239c
PU		 1093 /* Separate output gain controls */
1094 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1095 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1096 4, 3, 0, output_tvl),
1097
1098 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1099 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1100
1101 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1102 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1103 4, 3, 0, output_tvl),
1104
1105 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1106 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1107
381a22b5 1108 /* Common capture gain controls */
276c6222 1109 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1110 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1111 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1112 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1113 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1114 0, 0x1f, 0, digital_capture_tlv),
5920b453 1115
276c6222 1116 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1117 0, 3, 5, 0, input_gain_tlv),
89492be8 1118
328d0a13
LCM		 1119 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1120
89492be8 1121 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1122
1123 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1124 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1125};
1126
cc17557e 1127static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1128 /* Left channel inputs */
1129 SND_SOC_DAPM_INPUT("MAINMIC"),
1130 SND_SOC_DAPM_INPUT("HSMIC"),
1131 SND_SOC_DAPM_INPUT("AUXL"),
1132 SND_SOC_DAPM_INPUT("CARKITMIC"),
1133 /* Right channel inputs */
1134 SND_SOC_DAPM_INPUT("SUBMIC"),
1135 SND_SOC_DAPM_INPUT("AUXR"),
1136 /* Digital microphones (Stereo) */
1137 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1138 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1139
1140 /* Outputs */
cc17557e
SS		 1141 SND_SOC_DAPM_OUTPUT("OUTL"),
1142 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1143 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1144 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1145 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1146 SND_SOC_DAPM_OUTPUT("HSOL"),
1147 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1148 SND_SOC_DAPM_OUTPUT("CARKITL"),
1149 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1150 SND_SOC_DAPM_OUTPUT("HFL"),
1151 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1152 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1153
53b5047d 1154 /* DACs */
b4852b79 1155 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1156 SND_SOC_NOPM, 0, 0),
b4852b79 1157 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1158 SND_SOC_NOPM, 0, 0),
b4852b79 1159 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1160 SND_SOC_NOPM, 0, 0),
b4852b79 1161 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1162 SND_SOC_NOPM, 0, 0),
1a787e7a 1163 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1164 SND_SOC_NOPM, 0, 0),
cc17557e 1165
7393958f
PU		 1166 /* Analog bypasses */
1167 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1168 &twl4030_dapm_abypassr1_control, bypass_event,
1169 SND_SOC_DAPM_POST_REG),
1170 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1171 &twl4030_dapm_abypassl1_control,
1172 bypass_event, SND_SOC_DAPM_POST_REG),
1173 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1174 &twl4030_dapm_abypassr2_control,
1175 bypass_event, SND_SOC_DAPM_POST_REG),
1176 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1177 &twl4030_dapm_abypassl2_control,
1178 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1179 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1180 &twl4030_dapm_abypassv_control,
1181 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1182
6bab83fd
PU		 1183 /* Digital bypasses */
1184 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1185 &twl4030_dapm_dbypassl_control, bypass_event,
1186 SND_SOC_DAPM_POST_REG),
1187 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1188 &twl4030_dapm_dbypassr_control, bypass_event,
1189 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1190 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1191 &twl4030_dapm_dbypassv_control, bypass_event,
1192 SND_SOC_DAPM_POST_REG),
6bab83fd 1193
4005d39a
PU		 1194 /* Digital mixers, power control for the physical DACs */
1195 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1196 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1197 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1198 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1199 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1200 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1201 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1202 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1203 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1204 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1205
1206 /* Analog mixers, power control for the physical PGAs */
1207 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1208 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1209 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1210 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1211 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1212 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1213 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1214 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1215 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1216 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1217
1a787e7a 1218 /* Output MIXER controls */
5e98a464 1219 /* Earpiece */
1a787e7a
JS		 1220 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1221 &twl4030_dapm_earpiece_controls[0],
1222 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1223 /* PreDrivL/R */
1a787e7a
JS		 1224 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1225 &twl4030_dapm_predrivel_controls[0],
1226 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1227 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1228 &twl4030_dapm_predriver_controls[0],
1229 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1230 /* HeadsetL/R */
6943c92e 1231 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1232 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1233 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1234 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1235 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1236 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1237 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1238 &twl4030_dapm_hsor_controls[0],
1239 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1240 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1241 0, 0, NULL, 0, headsetrpga_event,
1242 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1243 /* CarkitL/R */
1a787e7a
JS		 1244 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1245 &twl4030_dapm_carkitl_controls[0],
1246 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1247 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1248 &twl4030_dapm_carkitr_controls[0],
1249 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1250
1251 /* Output MUX controls */
df339804 1252 /* HandsfreeL/R */
5a2e9a48
PU		 1253 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1254 &twl4030_dapm_handsfreel_control),
0f89bdca
PU		 1255 SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
1256 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1257 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1258 0, 0, NULL, 0, handsfreelpga_event,
1259 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1260 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1261 &twl4030_dapm_handsfreer_control),
0f89bdca
PU		 1262 SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
1263 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1264 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1265 0, 0, NULL, 0, handsfreerpga_event,
1266 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1267 /* Vibra */
1268 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1269 &twl4030_dapm_vibra_control),
1270 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_vibrapath_control),
5e98a464 1272
276c6222
PU		 1273 /* Introducing four virtual ADC, since TWL4030 have four channel for
1274 capture */
1275 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1276 SND_SOC_NOPM, 0, 0),
1277 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1278 SND_SOC_NOPM, 0, 0),
1279 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1280 SND_SOC_NOPM, 0, 0),
1281 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1282 SND_SOC_NOPM, 0, 0),
1283
1284 /* Analog/Digital mic path selection.
1285 TX1 Left/Right: either analog Left/Right or Digimic0
1286 TX2 Left/Right: either analog Left/Right or Digimic1 */
1287 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1288 &twl4030_dapm_micpathtx1_control, micpath_event,
1289 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1290 SND_SOC_DAPM_POST_REG),
1291 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1292 &twl4030_dapm_micpathtx2_control, micpath_event,
1293 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1294 SND_SOC_DAPM_POST_REG),
1295
97b8096d
JS		 1296 /* Analog input mixers for the capture amplifiers */
1297 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1298 TWL4030_REG_ANAMICL, 4, 0,
1299 &twl4030_dapm_analoglmic_controls[0],
1300 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1301 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1302 TWL4030_REG_ANAMICR, 4, 0,
1303 &twl4030_dapm_analogrmic_controls[0],
1304 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1305
fb2a2f84
PU		 1306 SND_SOC_DAPM_PGA("ADC Physical Left",
1307 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1308 SND_SOC_DAPM_PGA("ADC Physical Right",
1309 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1310
1311 SND_SOC_DAPM_PGA("Digimic0 Enable",
1312 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1313 SND_SOC_DAPM_PGA("Digimic1 Enable",
1314 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1315
1316 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1317 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1318 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1319
cc17557e
SS		 1320};
1321
1322static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1323 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1324 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1325 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1326 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1327 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1328
1329 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1330 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1331 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1332 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1333 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1334
5e98a464
PU		 1335 /* Internal playback routings */
1336 /* Earpiece */
4005d39a
PU		 1337 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1338 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1339 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1340 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1341 /* PreDrivL */
4005d39a
PU		 1342 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1343 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1344 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1345 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1346 /* PreDrivR */
4005d39a
PU		 1347 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1348 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1349 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1350 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1351 /* HeadsetL */
4005d39a
PU		 1352 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1353 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1354 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1355 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1356 /* HeadsetR */
4005d39a
PU		 1357 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1358 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1359 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1360 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1361 /* CarkitL */
4005d39a
PU		 1362 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1363 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1364 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1365 /* CarkitR */
4005d39a
PU		 1366 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1367 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1368 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1369 /* HandsfreeL */
4005d39a
PU		 1370 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1371 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1372 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1373 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
0f89bdca
PU		 1374 {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
1375 {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
df339804 1376 /* HandsfreeR */
4005d39a
PU		 1377 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1378 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1379 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1380 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
0f89bdca
PU		 1381 {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
1382 {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
376f7839
PU		 1383 /* Vibra */
1384 {"Vibra Mux", "AudioL1", "DAC Left1"},
1385 {"Vibra Mux", "AudioR1", "DAC Right1"},
1386 {"Vibra Mux", "AudioL2", "DAC Left2"},
1387 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1388
cc17557e 1389 /* outputs */
4005d39a
PU		 1390 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1391 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1392 {"EARPIECE", NULL, "Earpiece Mixer"},
1393 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1394 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1395 {"HSOL", NULL, "HeadsetL PGA"},
1396 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1397 {"CARKITL", NULL, "CarkitL Mixer"},
1398 {"CARKITR", NULL, "CarkitR Mixer"},
5a2e9a48
PU		 1399 {"HFL", NULL, "HandsfreeL PGA"},
1400 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1401 {"Vibra Route", "Audio", "Vibra Mux"},
1402 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1403
276c6222
PU		 1404 /* Capture path */
1405 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1406 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1407 {"Analog Left Capture Route", "AUXL", "AUXL"},
1408 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1409
1410 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1411 {"Analog Right Capture Route", "AUXR", "AUXR"},
1412
fb2a2f84
PU		 1413 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1414 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1415
1416 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1417 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1418
1419 /* TX1 Left capture path */
fb2a2f84 1420 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1421 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1422 /* TX1 Right capture path */
fb2a2f84 1423 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1424 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1425 /* TX2 Left capture path */
fb2a2f84 1426 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1427 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1428 /* TX2 Right capture path */
fb2a2f84 1429 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1430 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1431
1432 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1433 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1434 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1435 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1436
7393958f
PU		 1437 /* Analog bypass routes */
1438 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1439 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1440 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1441 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1442 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1443
1444 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1445 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1446 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1447 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1448 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1449
6bab83fd
PU		 1450 /* Digital bypass routes */
1451 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1452 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1453 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1454
4005d39a
PU		 1455 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1456 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1457 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1458
cc17557e
SS		 1459};
1460
1461static int twl4030_add_widgets(struct snd_soc_codec *codec)
1462{
1463 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1464 ARRAY_SIZE(twl4030_dapm_widgets));
1465
1466 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1467
1468 snd_soc_dapm_new_widgets(codec);
1469 return 0;
1470}
1471
cc17557e
SS		 1472static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1473 enum snd_soc_bias_level level)
1474{
7393958f
PU		 1475 struct twl4030_priv *twl4030 = codec->private_data;
1476
cc17557e
SS		 1477 switch (level) {
1478 case SND_SOC_BIAS_ON:
7393958f 1479 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1480 break;
1481 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1482 twl4030_power_up(codec);
1483 if (twl4030->bypass_state)
1484 twl4030_codec_mute(codec, 0);
1485 else
1486 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1487 break;
1488 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1489 twl4030_power_up(codec);
1490 if (twl4030->bypass_state)
1491 twl4030_codec_mute(codec, 0);
1492 else
1493 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1494 break;
1495 case SND_SOC_BIAS_OFF:
1496 twl4030_power_down(codec);
1497 break;
1498 }
1499 codec->bias_level = level;
1500
1501 return 0;
1502}
1503
6b87a91f
PU		 1504static void twl4030_constraints(struct twl4030_priv *twl4030,
1505 struct snd_pcm_substream *mst_substream)
1506{
1507 struct snd_pcm_substream *slv_substream;
1508
1509 /* Pick the stream, which need to be constrained */
1510 if (mst_substream == twl4030->master_substream)
1511 slv_substream = twl4030->slave_substream;
1512 else if (mst_substream == twl4030->slave_substream)
1513 slv_substream = twl4030->master_substream;
1514 else /* This should not happen.. */
1515 return;
1516
1517 /* Set the constraints according to the already configured stream */
1518 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1519 SNDRV_PCM_HW_PARAM_RATE,
1520 twl4030->rate,
1521 twl4030->rate);
1522
1523 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1524 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1525 twl4030->sample_bits,
1526 twl4030->sample_bits);
1527
1528 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1529 SNDRV_PCM_HW_PARAM_CHANNELS,
1530 twl4030->channels,
1531 twl4030->channels);
1532}
1533
8a1f936a
PU		 1534/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1535 * capture has to be enabled/disabled. */
1536static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1537 int enable)
1538{
1539 u8 reg, mask;
1540
1541 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1542
1543 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1544 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1545 else
1546 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1547
1548 if (enable)
1549 reg |= mask;
1550 else
1551 reg &= ~mask;
1552
1553 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1554}
1555
d6648da1
PU		 1556static int twl4030_startup(struct snd_pcm_substream *substream,
1557 struct snd_soc_dai *dai)
7220b9f4
PU		 1558{
1559 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1560 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1561 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1562 struct twl4030_priv *twl4030 = codec->private_data;
1563
7220b9f4 1564 if (twl4030->master_substream) {
7220b9f4 1565 twl4030->slave_substream = substream;
6b87a91f
PU		 1566 /* The DAI has one configuration for playback and capture, so
1567 * if the DAI has been already configured then constrain this
1568 * substream to match it. */
1569 if (twl4030->configured)
1570 twl4030_constraints(twl4030, twl4030->master_substream);
1571 } else {
8a1f936a
PU		 1572 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1573 TWL4030_OPTION_1)) {
1574 /* In option2 4 channel is not supported, set the
1575 * constraint for the first stream for channels, the
1576 * second stream will 'inherit' this cosntraint */
1577 snd_pcm_hw_constraint_minmax(substream->runtime,
1578 SNDRV_PCM_HW_PARAM_CHANNELS,
1579 2, 2);
1580 }
7220b9f4 1581 twl4030->master_substream = substream;
6b87a91f 1582 }
7220b9f4
PU		 1583
1584 return 0;
1585}
1586
d6648da1
PU		 1587static void twl4030_shutdown(struct snd_pcm_substream *substream,
1588 struct snd_soc_dai *dai)
7220b9f4
PU		 1589{
1590 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1591 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1592 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1593 struct twl4030_priv *twl4030 = codec->private_data;
1594
1595 if (twl4030->master_substream == substream)
1596 twl4030->master_substream = twl4030->slave_substream;
1597
1598 twl4030->slave_substream = NULL;
6b87a91f
PU		 1599
1600 /* If all streams are closed, or the remaining stream has not yet
1601 * been configured than set the DAI as not configured. */
1602 if (!twl4030->master_substream)
1603 twl4030->configured = 0;
1604 else if (!twl4030->master_substream->runtime->channels)
1605 twl4030->configured = 0;
8a1f936a
PU		 1606
1607 /* If the closing substream had 4 channel, do the necessary cleanup */
1608 if (substream->runtime->channels == 4)
1609 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1610}
1611
cc17557e 1612static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1613 struct snd_pcm_hw_params *params,
1614 struct snd_soc_dai *dai)
cc17557e
SS		 1615{
1616 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1617 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1618 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1619 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1620 u8 mode, old_mode, format, old_format;
1621
8a1f936a
PU		 1622 /* If the substream has 4 channel, do the necessary setup */
1623 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1624 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1625 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1626
1627 /* Safety check: are we in the correct operating mode and
1628 * the interface is in TDM mode? */
1629 if ((mode & TWL4030_OPTION_1) &&
1630 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1631 twl4030_tdm_enable(codec, substream->stream, 1);
1632 else
1633 return -EINVAL;
1634 }
1635
6b87a91f
PU		 1636 if (twl4030->configured)
1637 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1638 return 0;
1639
cc17557e
SS		 1640 /* bit rate */
1641 old_mode = twl4030_read_reg_cache(codec,
1642 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1643 mode = old_mode & ~TWL4030_APLL_RATE;
1644
1645 switch (params_rate(params)) {
1646 case 8000:
1647 mode |= TWL4030_APLL_RATE_8000;
1648 break;
1649 case 11025:
1650 mode |= TWL4030_APLL_RATE_11025;
1651 break;
1652 case 12000:
1653 mode |= TWL4030_APLL_RATE_12000;
1654 break;
1655 case 16000:
1656 mode |= TWL4030_APLL_RATE_16000;
1657 break;
1658 case 22050:
1659 mode |= TWL4030_APLL_RATE_22050;
1660 break;
1661 case 24000:
1662 mode |= TWL4030_APLL_RATE_24000;
1663 break;
1664 case 32000:
1665 mode |= TWL4030_APLL_RATE_32000;
1666 break;
1667 case 44100:
1668 mode |= TWL4030_APLL_RATE_44100;
1669 break;
1670 case 48000:
1671 mode |= TWL4030_APLL_RATE_48000;
1672 break;
103f211d
PU		 1673 case 96000:
1674 mode |= TWL4030_APLL_RATE_96000;
1675 break;
cc17557e
SS		 1676 default:
1677 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1678 params_rate(params));
1679 return -EINVAL;
1680 }
1681
1682 if (mode != old_mode) {
1683 /* change rate and set CODECPDZ */
7393958f 1684 twl4030_codec_enable(codec, 0);
cc17557e 1685 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1686 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1687 }
1688
1689 /* sample size */
1690 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1691 format = old_format;
1692 format &= ~TWL4030_DATA_WIDTH;
1693 switch (params_format(params)) {
1694 case SNDRV_PCM_FORMAT_S16_LE:
1695 format |= TWL4030_DATA_WIDTH_16S_16W;
1696 break;
1697 case SNDRV_PCM_FORMAT_S24_LE:
1698 format |= TWL4030_DATA_WIDTH_32S_24W;
1699 break;
1700 default:
1701 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1702 params_format(params));
1703 return -EINVAL;
1704 }
1705
1706 if (format != old_format) {
1707
1708 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1709 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1710
1711 /* change format */
1712 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1713
1714 /* set CODECPDZ afterwards */
db04e2c5 1715 twl4030_codec_enable(codec, 1);
cc17557e 1716 }
6b87a91f
PU		 1717
1718 /* Store the important parameters for the DAI configuration and set
1719 * the DAI as configured */
1720 twl4030->configured = 1;
1721 twl4030->rate = params_rate(params);
1722 twl4030->sample_bits = hw_param_interval(params,
1723 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1724 twl4030->channels = params_channels(params);
1725
1726 /* If both playback and capture streams are open, and one of them
1727 * is setting the hw parameters right now (since we are here), set
1728 * constraints to the other stream to match the current one. */
1729 if (twl4030->slave_substream)
1730 twl4030_constraints(twl4030, substream);
1731
cc17557e
SS		 1732 return 0;
1733}
1734
1735static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1736 int clk_id, unsigned int freq, int dir)
1737{
1738 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1739 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1740 u8 infreq;
1741
1742 switch (freq) {
1743 case 19200000:
1744 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1745 twl4030->sysclk = 19200;
cc17557e
SS		 1746 break;
1747 case 26000000:
1748 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1749 twl4030->sysclk = 26000;
cc17557e
SS		 1750 break;
1751 case 38400000:
1752 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1753 twl4030->sysclk = 38400;
cc17557e
SS		 1754 break;
1755 default:
1756 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1757 freq);
1758 return -EINVAL;
1759 }
1760
1761 infreq |= TWL4030_APLL_EN;
1762 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1763
1764 return 0;
1765}
1766
1767static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1768 unsigned int fmt)
1769{
1770 struct snd_soc_codec *codec = codec_dai->codec;
1771 u8 old_format, format;
1772
1773 /* get format */
1774 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1775 format = old_format;
1776
1777 /* set master/slave audio interface */
1778 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1779 case SND_SOC_DAIFMT_CBM_CFM:
1780 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1781 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1782 break;
1783 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1784 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1785 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1786 break;
1787 default:
1788 return -EINVAL;
1789 }
1790
1791 /* interface format */
1792 format &= ~TWL4030_AIF_FORMAT;
1793 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1794 case SND_SOC_DAIFMT_I2S:
1795 format |= TWL4030_AIF_FORMAT_CODEC;
1796 break;
8a1f936a
PU		 1797 case SND_SOC_DAIFMT_DSP_A:
1798 format |= TWL4030_AIF_FORMAT_TDM;
1799 break;
cc17557e
SS		 1800 default:
1801 return -EINVAL;
1802 }
1803
1804 if (format != old_format) {
1805
1806 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1807 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1808
1809 /* change format */
1810 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1811
1812 /* set CODECPDZ afterwards */
db04e2c5 1813 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1814 }
1815
1816 return 0;
1817}
1818
b7a755a8
MLC		 1819/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1820 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1821static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1822 int enable)
1823{
1824 u8 reg, mask;
1825
1826 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1827
1828 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1829 mask = TWL4030_ARXL1_VRX_EN;
1830 else
1831 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1832
1833 if (enable)
1834 reg |= mask;
1835 else
1836 reg &= ~mask;
1837
1838 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1839}
1840
7154b3e8
JS		 1841static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1842 struct snd_soc_dai *dai)
1843{
1844 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1845 struct snd_soc_device *socdev = rtd->socdev;
1846 struct snd_soc_codec *codec = socdev->card->codec;
1847 u8 infreq;
1848 u8 mode;
1849
1850 /* If the system master clock is not 26MHz, the voice PCM interface is
1851 * not avilable.
1852 */
1853 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1854 & TWL4030_APLL_INFREQ;
1855
1856 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1857 printk(KERN_ERR "TWL4030 voice startup: "
1858 "MCLK is not 26MHz, call set_sysclk() on init\n");
1859 return -EINVAL;
1860 }
1861
1862 /* If the codec mode is not option2, the voice PCM interface is not
1863 * avilable.
1864 */
1865 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1866 & TWL4030_OPT_MODE;
1867
1868 if (mode != TWL4030_OPTION_2) {
1869 printk(KERN_ERR "TWL4030 voice startup: "
1870 "the codec mode is not option2\n");
1871 return -EINVAL;
1872 }
1873
1874 return 0;
1875}
1876
b7a755a8
MLC		 1877static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1878 struct snd_soc_dai *dai)
1879{
1880 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1881 struct snd_soc_device *socdev = rtd->socdev;
1882 struct snd_soc_codec *codec = socdev->card->codec;
1883
1884 /* Enable voice digital filters */
1885 twl4030_voice_enable(codec, substream->stream, 0);
1886}
1887
7154b3e8
JS		 1888static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1889 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1890{
1891 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1892 struct snd_soc_device *socdev = rtd->socdev;
1893 struct snd_soc_codec *codec = socdev->card->codec;
1894 u8 old_mode, mode;
1895
b7a755a8
MLC		 1896 /* Enable voice digital filters */
1897 twl4030_voice_enable(codec, substream->stream, 1);
1898
7154b3e8
JS		 1899 /* bit rate */
1900 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1901 & ~(TWL4030_CODECPDZ);
1902 mode = old_mode;
1903
1904 switch (params_rate(params)) {
1905 case 8000:
1906 mode &= ~(TWL4030_SEL_16K);
1907 break;
1908 case 16000:
1909 mode |= TWL4030_SEL_16K;
1910 break;
1911 default:
1912 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1913 params_rate(params));
1914 return -EINVAL;
1915 }
1916
1917 if (mode != old_mode) {
1918 /* change rate and set CODECPDZ */
1919 twl4030_codec_enable(codec, 0);
1920 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1921 twl4030_codec_enable(codec, 1);
1922 }
1923
1924 return 0;
1925}
1926
1927static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1928 int clk_id, unsigned int freq, int dir)
1929{
1930 struct snd_soc_codec *codec = codec_dai->codec;
1931 u8 infreq;
1932
1933 switch (freq) {
1934 case 26000000:
1935 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1936 break;
1937 default:
1938 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1939 freq);
1940 return -EINVAL;
1941 }
1942
1943 infreq |= TWL4030_APLL_EN;
1944 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1945
1946 return 0;
1947}
1948
1949static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1950 unsigned int fmt)
1951{
1952 struct snd_soc_codec *codec = codec_dai->codec;
1953 u8 old_format, format;
1954
1955 /* get format */
1956 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1957 format = old_format;
1958
1959 /* set master/slave audio interface */
1960 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 1961 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 1962 format &= ~(TWL4030_VIF_SLAVE_EN);
1963 break;
1964 case SND_SOC_DAIFMT_CBS_CFS:
1965 format |= TWL4030_VIF_SLAVE_EN;
1966 break;
1967 default:
1968 return -EINVAL;
1969 }
1970
1971 /* clock inversion */
1972 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1973 case SND_SOC_DAIFMT_IB_NF:
1974 format &= ~(TWL4030_VIF_FORMAT);
1975 break;
1976 case SND_SOC_DAIFMT_NB_IF:
1977 format |= TWL4030_VIF_FORMAT;
1978 break;
1979 default:
1980 return -EINVAL;
1981 }
1982
1983 if (format != old_format) {
1984 /* change format and set CODECPDZ */
1985 twl4030_codec_enable(codec, 0);
1986 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1987 twl4030_codec_enable(codec, 1);
1988 }
1989
1990 return 0;
1991}
1992
bbba9444 1993#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1994#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1995
10d9e3d9 1996static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1997 .startup = twl4030_startup,
1998 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1999 .hw_params = twl4030_hw_params,
2000 .set_sysclk = twl4030_set_dai_sysclk,
2001 .set_fmt = twl4030_set_dai_fmt,
2002};
2003
7154b3e8
JS		 2004static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2005 .startup = twl4030_voice_startup,
b7a755a8 2006 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2007 .hw_params = twl4030_voice_hw_params,
2008 .set_sysclk = twl4030_voice_set_dai_sysclk,
2009 .set_fmt = twl4030_voice_set_dai_fmt,
2010};
2011
2012struct snd_soc_dai twl4030_dai[] = {
2013{
cc17557e
SS		 2014 .name = "twl4030",
2015 .playback = {
b4852b79 2016 .stream_name = "HiFi Playback",
cc17557e 2017 .channels_min = 2,
8a1f936a 2018 .channels_max = 4,
31ad0f31 2019 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2020 .formats = TWL4030_FORMATS,},
2021 .capture = {
2022 .stream_name = "Capture",
2023 .channels_min = 2,
8a1f936a 2024 .channels_max = 4,
cc17557e
SS		 2025 .rates = TWL4030_RATES,
2026 .formats = TWL4030_FORMATS,},
10d9e3d9 2027 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2028},
2029{
2030 .name = "twl4030 Voice",
2031 .playback = {
b4852b79 2032 .stream_name = "Voice Playback",
7154b3e8
JS		 2033 .channels_min = 1,
2034 .channels_max = 1,
2035 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2036 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2037 .capture = {
2038 .stream_name = "Capture",
2039 .channels_min = 1,
2040 .channels_max = 2,
2041 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2042 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2043 .ops = &twl4030_dai_voice_ops,
2044},
cc17557e
SS		 2045};
2046EXPORT_SYMBOL_GPL(twl4030_dai);
2047
2048static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2049{
2050 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2051 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2052
2053 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2054
2055 return 0;
2056}
2057
2058static int twl4030_resume(struct platform_device *pdev)
2059{
2060 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2061 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2062
2063 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2064 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2065 return 0;
2066}
2067
2068/*
2069 * initialize the driver
2070 * register the mixer and dsp interfaces with the kernel
2071 */
2072
2073static int twl4030_init(struct snd_soc_device *socdev)
2074{
6627a653 2075 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2076 struct twl4030_setup_data *setup = socdev->codec_data;
2077 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2078 int ret = 0;
2079
2080 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2081
2082 codec->name = "twl4030";
2083 codec->owner = THIS_MODULE;
2084 codec->read = twl4030_read_reg_cache;
2085 codec->write = twl4030_write;
2086 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2087 codec->dai = twl4030_dai;
2088 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2089 codec->reg_cache_size = sizeof(twl4030_reg);
2090 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2091 GFP_KERNEL);
2092 if (codec->reg_cache == NULL)
2093 return -ENOMEM;
2094
9da28c7b
PU		 2095 /* Configuration for headset ramp delay from setup data */
2096 if (setup) {
2097 unsigned char hs_pop;
2098
2099 if (setup->sysclk)
2100 twl4030->sysclk = setup->sysclk;
2101 else
2102 twl4030->sysclk = 26000;
2103
2104 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2105 hs_pop &= ~TWL4030_RAMP_DELAY;
2106 hs_pop |= (setup->ramp_delay_value << 2);
2107 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2108 } else {
2109 twl4030->sysclk = 26000;
2110 }
2111
cc17557e
SS		 2112 /* register pcms */
2113 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2114 if (ret < 0) {
2115 printk(KERN_ERR "twl4030: failed to create pcms\n");
2116 goto pcm_err;
2117 }
2118
2119 twl4030_init_chip(codec);
2120
2121 /* power on device */
2122 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2123
3e8e1952
IM		 2124 snd_soc_add_controls(codec, twl4030_snd_controls,
2125 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2126 twl4030_add_widgets(codec);
2127
968a6025 2128 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2129 if (ret < 0) {
2130 printk(KERN_ERR "twl4030: failed to register card\n");
2131 goto card_err;
2132 }
2133
2134 return ret;
2135
2136card_err:
2137 snd_soc_free_pcms(socdev);
2138 snd_soc_dapm_free(socdev);
2139pcm_err:
2140 kfree(codec->reg_cache);
2141 return ret;
2142}
2143
2144static struct snd_soc_device *twl4030_socdev;
2145
2146static int twl4030_probe(struct platform_device *pdev)
2147{
2148 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2149 struct snd_soc_codec *codec;
7393958f 2150 struct twl4030_priv *twl4030;
cc17557e
SS		 2151
2152 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2153 if (codec == NULL)
2154 return -ENOMEM;
2155
7393958f
PU		 2156 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2157 if (twl4030 == NULL) {
2158 kfree(codec);
2159 return -ENOMEM;
2160 }
2161
2162 codec->private_data = twl4030;
6627a653 2163 socdev->card->codec = codec;
cc17557e
SS		 2164 mutex_init(&codec->mutex);
2165 INIT_LIST_HEAD(&codec->dapm_widgets);
2166 INIT_LIST_HEAD(&codec->dapm_paths);
2167
2168 twl4030_socdev = socdev;
2169 twl4030_init(socdev);
2170
2171 return 0;
2172}
2173
2174static int twl4030_remove(struct platform_device *pdev)
2175{
2176 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2177 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2178
2179 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2180 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2181 snd_soc_free_pcms(socdev);
2182 snd_soc_dapm_free(socdev);
7393958f 2183 kfree(codec->private_data);
cc17557e
SS		 2184 kfree(codec);
2185
2186 return 0;
2187}
2188
2189struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2190 .probe = twl4030_probe,
2191 .remove = twl4030_remove,
2192 .suspend = twl4030_suspend,
2193 .resume = twl4030_resume,
2194};
2195EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2196
24e07db8 2197static int __init twl4030_modinit(void)
64089b84 2198{
7154b3e8 2199 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2200}
24e07db8 2201module_init(twl4030_modinit);
64089b84
MB		 2202
2203static void __exit twl4030_exit(void)
2204{
7154b3e8 2205 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2206}
2207module_exit(twl4030_exit);
2208
cc17557e
SS		 2209MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2210MODULE_AUTHOR("Steve Sakoman");
2211MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.221469 seconds and 5 git commands to generate.