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ASoC: TWL4030: Revisit codec defaults
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
cc17557e
SS		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
33f92ed4 45 0x00, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 54 0x0f, /* REG_ATXL1PGA (0xA) */
55 0x0f, /* REG_ATXR1PGA (0xB) */
56 0x0f, /* REG_AVTXL2PGA (0xC) */
57 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 58 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 59 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 60 0x3f, /* REG_ARXR1PGA (0x10) */
61 0x3f, /* REG_ARXL1PGA (0x11) */
62 0x3f, /* REG_ARXR2PGA (0x12) */
63 0x3f, /* REG_ARXL2PGA (0x13) */
64 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 67 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 68 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 69 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 75 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 78 0x00, /* REG_HS_SEL (0x22) */
79 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 87 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 92 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 97 0x79, /* REG_DTMF_TONOFF (0x35) */
98 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 102 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 103 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 104 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 112 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
7a1fecf5
PU		 123 struct snd_soc_codec codec;
124
7393958f 125 unsigned int codec_powered;
7b4c734e
PU		 126
127 /* reference counts of AIF/APLL users */
2845fa13 128 unsigned int apll_enabled;
7220b9f4
PU		 129
130 struct snd_pcm_substream *master_substream;
131 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 132
133 unsigned int configured;
134 unsigned int rate;
135 unsigned int sample_bits;
136 unsigned int channels;
6943c92e
PU		 137
138 unsigned int sysclk;
139
c96907f2
PU		 140 /* Output (with associated amp) states */
141 u8 hsl_enabled, hsr_enabled;
142 u8 earpiece_enabled;
143 u8 predrivel_enabled, predriver_enabled;
144 u8 carkitl_enabled, carkitr_enabled;
7393958f
PU		 145};
146
cc17557e
SS		 147/*
148 * read twl4030 register cache
149 */
150static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned int reg)
152{
d08664fd 153 u8 *cache = codec->reg_cache;
cc17557e 154
91432e97
IM		 155 if (reg >= TWL4030_CACHEREGNUM)
156 return -EIO;
157
cc17557e
SS		 158 return cache[reg];
159}
160
161/*
162 * write twl4030 register cache
163 */
164static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
165 u8 reg, u8 value)
166{
167 u8 *cache = codec->reg_cache;
168
169 if (reg >= TWL4030_CACHEREGNUM)
170 return;
171 cache[reg] = value;
172}
173
174/*
175 * write to the twl4030 register space
176 */
177static int twl4030_write(struct snd_soc_codec *codec,
178 unsigned int reg, unsigned int value)
179{
b2c812e2 180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 181 int write_to_reg = 0;
182
cc17557e 183 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 184 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
185 /* Decide if the given register can be written */
186 switch (reg) {
187 case TWL4030_REG_EAR_CTL:
188 if (twl4030->earpiece_enabled)
189 write_to_reg = 1;
190 break;
191 case TWL4030_REG_PREDL_CTL:
192 if (twl4030->predrivel_enabled)
193 write_to_reg = 1;
194 break;
195 case TWL4030_REG_PREDR_CTL:
196 if (twl4030->predriver_enabled)
197 write_to_reg = 1;
198 break;
199 case TWL4030_REG_PRECKL_CTL:
200 if (twl4030->carkitl_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PRECKR_CTL:
204 if (twl4030->carkitr_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_HS_GAIN_SET:
208 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
209 write_to_reg = 1;
210 break;
211 default:
212 /* All other register can be written */
213 write_to_reg = 1;
214 break;
215 }
216 if (write_to_reg)
217 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
218 value, reg);
219 }
220 return 0;
cc17557e
SS		 221}
222
db04e2c5 223static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 224{
b2c812e2 225 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 226 int mode;
cc17557e 227
7393958f
PU		 228 if (enable == twl4030->codec_powered)
229 return;
230
db04e2c5 231 if (enable)
7a1fecf5 232 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 233 else
7a1fecf5 234 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 235
7a1fecf5
PU		 236 if (mode >= 0) {
237 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
238 twl4030->codec_powered = enable;
239 }
cc17557e
SS		 240
241 /* REVISIT: this delay is present in TI sample drivers */
242 /* but there seems to be no TRM requirement for it */
243 udelay(10);
244}
245
246static void twl4030_init_chip(struct snd_soc_codec *codec)
247{
16a30fbb 248 u8 *cache = codec->reg_cache;
cc17557e
SS		 249 int i;
250
251 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 252 twl4030_codec_enable(codec, 0);
cc17557e
SS		 253
254 /* set all audio section registers to reasonable defaults */
255 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955
PU		 256 if (i != TWL4030_REG_APLL_CTL)
257 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 258
259}
260
2845fa13 261static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
7393958f 262{
b2c812e2 263 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7b4c734e 264 int status = -1;
7393958f 265
7b4c734e
PU		 266 if (enable) {
267 twl4030->apll_enabled++;
268 if (twl4030->apll_enabled == 1)
269 status = twl4030_codec_enable_resource(
270 TWL4030_CODEC_RES_APLL);
271 } else {
272 twl4030->apll_enabled--;
273 if (!twl4030->apll_enabled)
274 status = twl4030_codec_disable_resource(
275 TWL4030_CODEC_RES_APLL);
276 }
7a1fecf5
PU		 277
278 if (status >= 0)
279 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
7393958f
PU		 280}
281
006f367e
PU		 282static void twl4030_power_up(struct snd_soc_codec *codec)
283{
b2c812e2 284 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
006f367e
PU		 285 u8 anamicl, regmisc1, byte;
286 int i = 0;
287
7393958f
PU		 288 if (twl4030->codec_powered)
289 return;
290
006f367e
PU		 291 /* set CODECPDZ to turn on codec */
292 twl4030_codec_enable(codec, 1);
293
294 /* initiate offset cancellation */
295 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
296 twl4030_write(codec, TWL4030_REG_ANAMICL,
297 anamicl | TWL4030_CNCL_OFFSET_START);
298
299 /* wait for offset cancellation to complete */
300 do {
301 /* this takes a little while, so don't slam i2c */
302 udelay(2000);
fc7b92fc 303 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 304 TWL4030_REG_ANAMICL);
305 } while ((i++ < 100) &&
306 ((byte & TWL4030_CNCL_OFFSET_START) ==
307 TWL4030_CNCL_OFFSET_START));
308
309 /* Make sure that the reg_cache has the same value as the HW */
310 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
311
312 /* anti-pop when changing analog gain */
313 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
314 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
315 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
316
317 /* toggle CODECPDZ as per TRM */
318 twl4030_codec_enable(codec, 0);
319 twl4030_codec_enable(codec, 1);
320}
321
7393958f
PU		 322/*
323 * Unconditional power down
324 */
006f367e
PU		 325static void twl4030_power_down(struct snd_soc_codec *codec)
326{
327 /* power down */
328 twl4030_codec_enable(codec, 0);
329}
330
5e98a464 331/* Earpiece */
1a787e7a
JS		 332static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
337};
5e98a464 338
2a6f5c58 339/* PreDrive Left */
1a787e7a
JS		 340static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
345};
2a6f5c58
PU		 346
347/* PreDrive Right */
1a787e7a
JS		 348static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
352 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
353};
2a6f5c58 354
dfad21a2 355/* Headset Left */
1a787e7a
JS		 356static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
357 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
358 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
359 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
360};
dfad21a2
PU		 361
362/* Headset Right */
1a787e7a
JS		 363static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
364 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
365 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
366 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
367};
dfad21a2 368
5152d8c2 369/* Carkit Left */
1a787e7a
JS		 370static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
371 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
372 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
373 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
374};
5152d8c2
PU		 375
376/* Carkit Right */
1a787e7a
JS		 377static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
378 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
379 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
380 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
381};
5152d8c2 382
df339804
PU		 383/* Handsfree Left */
384static const char *twl4030_handsfreel_texts[] =
1a787e7a 385 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 386
387static const struct soc_enum twl4030_handsfreel_enum =
388 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
389 ARRAY_SIZE(twl4030_handsfreel_texts),
390 twl4030_handsfreel_texts);
391
392static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
393SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
394
0f89bdca
PU		 395/* Handsfree Left virtual mute */
396static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
397 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
398
df339804
PU		 399/* Handsfree Right */
400static const char *twl4030_handsfreer_texts[] =
1a787e7a 401 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 402
403static const struct soc_enum twl4030_handsfreer_enum =
404 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
405 ARRAY_SIZE(twl4030_handsfreer_texts),
406 twl4030_handsfreer_texts);
407
408static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
409SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
410
0f89bdca
PU		 411/* Handsfree Right virtual mute */
412static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
413 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
414
376f7839
PU		 415/* Vibra */
416/* Vibra audio path selection */
417static const char *twl4030_vibra_texts[] =
418 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
419
420static const struct soc_enum twl4030_vibra_enum =
421 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
422 ARRAY_SIZE(twl4030_vibra_texts),
423 twl4030_vibra_texts);
424
425static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
426SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
427
428/* Vibra path selection: local vibrator (PWM) or audio driven */
429static const char *twl4030_vibrapath_texts[] =
430 {"Local vibrator", "Audio"};
431
432static const struct soc_enum twl4030_vibrapath_enum =
433 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
434 ARRAY_SIZE(twl4030_vibrapath_texts),
435 twl4030_vibrapath_texts);
436
437static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
438SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
439
276c6222 440/* Left analog microphone selection */
97b8096d 441static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 442 SOC_DAPM_SINGLE("Main Mic Capture Switch",
443 TWL4030_REG_ANAMICL, 0, 1, 0),
444 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
445 TWL4030_REG_ANAMICL, 1, 1, 0),
446 SOC_DAPM_SINGLE("AUXL Capture Switch",
447 TWL4030_REG_ANAMICL, 2, 1, 0),
448 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
449 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 450};
276c6222
PU		 451
452/* Right analog microphone selection */
97b8096d 453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 454 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
455 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 456};
276c6222
PU		 457
458/* TX1 L/R Analog/Digital microphone selection */
459static const char *twl4030_micpathtx1_texts[] =
460 {"Analog", "Digimic0"};
461
462static const struct soc_enum twl4030_micpathtx1_enum =
463 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
464 ARRAY_SIZE(twl4030_micpathtx1_texts),
465 twl4030_micpathtx1_texts);
466
467static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
468SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
469
470/* TX2 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx2_texts[] =
472 {"Analog", "Digimic1"};
473
474static const struct soc_enum twl4030_micpathtx2_enum =
475 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
476 ARRAY_SIZE(twl4030_micpathtx2_texts),
477 twl4030_micpathtx2_texts);
478
479static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
480SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
481
7393958f
PU		 482/* Analog bypass for AudioR1 */
483static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
484 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
485
486/* Analog bypass for AudioL1 */
487static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
488 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
489
490/* Analog bypass for AudioR2 */
491static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
492 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
493
494/* Analog bypass for AudioL2 */
495static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
497
fcd274a3
LCM		 498/* Analog bypass for Voice */
499static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
501
6bab83fd
PU		 502/* Digital bypass gain, 0 mutes the bypass */
503static const unsigned int twl4030_dapm_dbypass_tlv[] = {
504 TLV_DB_RANGE_HEAD(2),
505 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
506 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
507};
508
509/* Digital bypass left (TX1L -> RX2L) */
510static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
511 SOC_DAPM_SINGLE_TLV("Volume",
512 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
513 twl4030_dapm_dbypass_tlv);
514
515/* Digital bypass right (TX1R -> RX2R) */
516static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
517 SOC_DAPM_SINGLE_TLV("Volume",
518 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
519 twl4030_dapm_dbypass_tlv);
520
ee8f6894
LCM		 521/*
522 * Voice Sidetone GAIN volume control:
523 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
524 */
525static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
526
527/* Digital bypass voice: sidetone (VUL -> VDL)*/
528static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
529 SOC_DAPM_SINGLE_TLV("Volume",
530 TWL4030_REG_VSTPGA, 0, 0x29, 0,
531 twl4030_dapm_dbypassv_tlv);
532
276c6222
PU		 533static int micpath_event(struct snd_soc_dapm_widget *w,
534 struct snd_kcontrol *kcontrol, int event)
535{
536 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
537 unsigned char adcmicsel, micbias_ctl;
538
539 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
540 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
541 /* Prepare the bits for the given TX path:
542 * shift_l == 0: TX1 microphone path
543 * shift_l == 2: TX2 microphone path */
544 if (e->shift_l) {
545 /* TX2 microphone path */
546 if (adcmicsel & TWL4030_TX2IN_SEL)
547 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
548 else
549 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
550 } else {
551 /* TX1 microphone path */
552 if (adcmicsel & TWL4030_TX1IN_SEL)
553 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
554 else
555 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
556 }
557
558 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
559
560 return 0;
561}
562
9008adf9
PU		 563/*
564 * Output PGA builder:
565 * Handle the muting and unmuting of the given output (turning off the
566 * amplifier associated with the output pin)
c96907f2
PU		 567 * On mute bypass the reg_cache and write 0 to the register
568 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 569 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
570 */
571#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
572static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
573 struct snd_kcontrol *kcontrol, int event) \
574{ \
b2c812e2 575 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 576 \
577 switch (event) { \
578 case SND_SOC_DAPM_POST_PMU: \
c96907f2 579 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 580 twl4030_write(w->codec, reg, \
581 twl4030_read_reg_cache(w->codec, reg)); \
582 break; \
583 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 584 twl4030->pin_name##_enabled = 0; \
585 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
586 0, reg); \
9008adf9
PU		 587 break; \
588 } \
589 return 0; \
590}
591
592TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
593TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
594TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
595TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
596TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
597
5a2e9a48 598static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 599{
49d92c7d
SM		 600 unsigned char hs_ctl;
601
5a2e9a48 602 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 603
5a2e9a48
PU		 604 if (ramp) {
605 /* HF ramp-up */
606 hs_ctl |= TWL4030_HF_CTL_REF_EN;
607 twl4030_write(codec, reg, hs_ctl);
608 udelay(10);
49d92c7d 609 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 610 twl4030_write(codec, reg, hs_ctl);
611 udelay(40);
49d92c7d 612 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 613 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 614 twl4030_write(codec, reg, hs_ctl);
49d92c7d 615 } else {
5a2e9a48
PU		 616 /* HF ramp-down */
617 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
618 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
619 twl4030_write(codec, reg, hs_ctl);
620 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
621 twl4030_write(codec, reg, hs_ctl);
622 udelay(40);
623 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
624 twl4030_write(codec, reg, hs_ctl);
49d92c7d 625 }
5a2e9a48 626}
49d92c7d 627
5a2e9a48
PU		 628static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
629 struct snd_kcontrol *kcontrol, int event)
630{
631 switch (event) {
632 case SND_SOC_DAPM_POST_PMU:
633 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
634 break;
635 case SND_SOC_DAPM_POST_PMD:
636 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
637 break;
638 }
639 return 0;
640}
641
642static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
643 struct snd_kcontrol *kcontrol, int event)
644{
645 switch (event) {
646 case SND_SOC_DAPM_POST_PMU:
647 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
648 break;
649 case SND_SOC_DAPM_POST_PMD:
650 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
651 break;
652 }
49d92c7d
SM		 653 return 0;
654}
655
86139a13
JV		 656static int vibramux_event(struct snd_soc_dapm_widget *w,
657 struct snd_kcontrol *kcontrol, int event)
658{
659 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
660 return 0;
661}
662
7729cf74
PU		 663static int apll_event(struct snd_soc_dapm_widget *w,
664 struct snd_kcontrol *kcontrol, int event)
665{
666 switch (event) {
667 case SND_SOC_DAPM_PRE_PMU:
668 twl4030_apll_enable(w->codec, 1);
669 break;
670 case SND_SOC_DAPM_POST_PMD:
671 twl4030_apll_enable(w->codec, 0);
672 break;
673 }
674 return 0;
675}
676
7b4c734e
PU		 677static int aif_event(struct snd_soc_dapm_widget *w,
678 struct snd_kcontrol *kcontrol, int event)
679{
680 u8 audio_if;
681
682 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
683 switch (event) {
684 case SND_SOC_DAPM_PRE_PMU:
685 /* Enable AIF */
686 /* enable the PLL before we use it to clock the DAI */
687 twl4030_apll_enable(w->codec, 1);
688
689 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
690 audio_if | TWL4030_AIF_EN);
691 break;
692 case SND_SOC_DAPM_POST_PMD:
693 /* disable the DAI before we stop it's source PLL */
694 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
695 audio_if & ~TWL4030_AIF_EN);
696 twl4030_apll_enable(w->codec, 0);
697 break;
698 }
699 return 0;
700}
701
6943c92e 702static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 703{
4e49ffd1
CVJ		 704 struct snd_soc_device *socdev = codec->socdev;
705 struct twl4030_setup_data *setup = socdev->codec_data;
706
aad749e5 707 unsigned char hs_gain, hs_pop;
b2c812e2 708 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 709 /* Base values for ramp delay calculation: 2^19 - 2^26 */
710 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
711 8388608, 16777216, 33554432, 67108864};
aad749e5 712
6943c92e
PU		 713 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
714 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 715
4e49ffd1
CVJ		 716 /* Enable external mute control, this dramatically reduces
717 * the pop-noise */
718 if (setup && setup->hs_extmute) {
719 if (setup->set_hs_extmute) {
720 setup->set_hs_extmute(1);
721 } else {
722 hs_pop |= TWL4030_EXTMUTE;
723 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
724 }
725 }
726
6943c92e
PU		 727 if (ramp) {
728 /* Headset ramp-up according to the TRM */
aad749e5 729 hs_pop |= TWL4030_VMID_EN;
6943c92e 730 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 731 /* Actually write to the register */
732 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
733 hs_gain,
734 TWL4030_REG_HS_GAIN_SET);
aad749e5 735 hs_pop |= TWL4030_RAMP_EN;
6943c92e 736 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 737 /* Wait ramp delay time + 1, so the VMID can settle */
738 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
739 twl4030->sysclk) + 1);
6943c92e
PU		 740 } else {
741 /* Headset ramp-down _not_ according to
742 * the TRM, but in a way that it is working */
aad749e5 743 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 744 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
745 /* Wait ramp delay time + 1, so the VMID can settle */
746 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
747 twl4030->sysclk) + 1);
aad749e5 748 /* Bypass the reg_cache to mute the headset */
fc7b92fc 749 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 750 hs_gain & (~0x0f),
751 TWL4030_REG_HS_GAIN_SET);
6943c92e 752
aad749e5 753 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 754 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
755 }
4e49ffd1
CVJ		 756
757 /* Disable external mute */
758 if (setup && setup->hs_extmute) {
759 if (setup->set_hs_extmute) {
760 setup->set_hs_extmute(0);
761 } else {
762 hs_pop &= ~TWL4030_EXTMUTE;
763 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
764 }
765 }
6943c92e
PU		 766}
767
768static int headsetlpga_event(struct snd_soc_dapm_widget *w,
769 struct snd_kcontrol *kcontrol, int event)
770{
b2c812e2 771 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 772
773 switch (event) {
774 case SND_SOC_DAPM_POST_PMU:
775 /* Do the ramp-up only once */
776 if (!twl4030->hsr_enabled)
777 headset_ramp(w->codec, 1);
778
779 twl4030->hsl_enabled = 1;
780 break;
781 case SND_SOC_DAPM_POST_PMD:
782 /* Do the ramp-down only if both headsetL/R is disabled */
783 if (!twl4030->hsr_enabled)
784 headset_ramp(w->codec, 0);
785
786 twl4030->hsl_enabled = 0;
787 break;
788 }
789 return 0;
790}
791
792static int headsetrpga_event(struct snd_soc_dapm_widget *w,
793 struct snd_kcontrol *kcontrol, int event)
794{
b2c812e2 795 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 796
797 switch (event) {
798 case SND_SOC_DAPM_POST_PMU:
799 /* Do the ramp-up only once */
800 if (!twl4030->hsl_enabled)
801 headset_ramp(w->codec, 1);
802
803 twl4030->hsr_enabled = 1;
804 break;
805 case SND_SOC_DAPM_POST_PMD:
806 /* Do the ramp-down only if both headsetL/R is disabled */
807 if (!twl4030->hsl_enabled)
808 headset_ramp(w->codec, 0);
809
810 twl4030->hsr_enabled = 0;
aad749e5
PU		 811 break;
812 }
813 return 0;
814}
815
b0bd53a7
PU		 816/*
817 * Some of the gain controls in TWL (mostly those which are associated with
818 * the outputs) are implemented in an interesting way:
819 * 0x0 : Power down (mute)
820 * 0x1 : 6dB
821 * 0x2 : 0 dB
822 * 0x3 : -6 dB
823 * Inverting not going to help with these.
824 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
825 */
826#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
827 xinvert, tlv_array) \
828{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
829 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
830 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
831 .tlv.p = (tlv_array), \
832 .info = snd_soc_info_volsw, \
833 .get = snd_soc_get_volsw_twl4030, \
834 .put = snd_soc_put_volsw_twl4030, \
835 .private_value = (unsigned long)&(struct soc_mixer_control) \
836 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
837 .max = xmax, .invert = xinvert} }
838#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
839 xinvert, tlv_array) \
840{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
841 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
842 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
843 .tlv.p = (tlv_array), \
844 .info = snd_soc_info_volsw_2r, \
845 .get = snd_soc_get_volsw_r2_twl4030,\
846 .put = snd_soc_put_volsw_r2_twl4030, \
847 .private_value = (unsigned long)&(struct soc_mixer_control) \
848 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 849 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 850#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
851 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
852 xinvert, tlv_array)
853
854static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
855 struct snd_ctl_elem_value *ucontrol)
856{
857 struct soc_mixer_control *mc =
858 (struct soc_mixer_control *)kcontrol->private_value;
859 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
860 unsigned int reg = mc->reg;
861 unsigned int shift = mc->shift;
862 unsigned int rshift = mc->rshift;
863 int max = mc->max;
864 int mask = (1 << fls(max)) - 1;
865
866 ucontrol->value.integer.value[0] =
867 (snd_soc_read(codec, reg) >> shift) & mask;
868 if (ucontrol->value.integer.value[0])
869 ucontrol->value.integer.value[0] =
870 max + 1 - ucontrol->value.integer.value[0];
871
872 if (shift != rshift) {
873 ucontrol->value.integer.value[1] =
874 (snd_soc_read(codec, reg) >> rshift) & mask;
875 if (ucontrol->value.integer.value[1])
876 ucontrol->value.integer.value[1] =
877 max + 1 - ucontrol->value.integer.value[1];
878 }
879
880 return 0;
881}
882
883static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
884 struct snd_ctl_elem_value *ucontrol)
885{
886 struct soc_mixer_control *mc =
887 (struct soc_mixer_control *)kcontrol->private_value;
888 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
889 unsigned int reg = mc->reg;
890 unsigned int shift = mc->shift;
891 unsigned int rshift = mc->rshift;
892 int max = mc->max;
893 int mask = (1 << fls(max)) - 1;
894 unsigned short val, val2, val_mask;
895
896 val = (ucontrol->value.integer.value[0] & mask);
897
898 val_mask = mask << shift;
899 if (val)
900 val = max + 1 - val;
901 val = val << shift;
902 if (shift != rshift) {
903 val2 = (ucontrol->value.integer.value[1] & mask);
904 val_mask |= mask << rshift;
905 if (val2)
906 val2 = max + 1 - val2;
907 val |= val2 << rshift;
908 }
909 return snd_soc_update_bits(codec, reg, val_mask, val);
910}
911
912static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
913 struct snd_ctl_elem_value *ucontrol)
914{
915 struct soc_mixer_control *mc =
916 (struct soc_mixer_control *)kcontrol->private_value;
917 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
918 unsigned int reg = mc->reg;
919 unsigned int reg2 = mc->rreg;
920 unsigned int shift = mc->shift;
921 int max = mc->max;
922 int mask = (1<<fls(max))-1;
923
924 ucontrol->value.integer.value[0] =
925 (snd_soc_read(codec, reg) >> shift) & mask;
926 ucontrol->value.integer.value[1] =
927 (snd_soc_read(codec, reg2) >> shift) & mask;
928
929 if (ucontrol->value.integer.value[0])
930 ucontrol->value.integer.value[0] =
931 max + 1 - ucontrol->value.integer.value[0];
932 if (ucontrol->value.integer.value[1])
933 ucontrol->value.integer.value[1] =
934 max + 1 - ucontrol->value.integer.value[1];
935
936 return 0;
937}
938
939static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
940 struct snd_ctl_elem_value *ucontrol)
941{
942 struct soc_mixer_control *mc =
943 (struct soc_mixer_control *)kcontrol->private_value;
944 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
945 unsigned int reg = mc->reg;
946 unsigned int reg2 = mc->rreg;
947 unsigned int shift = mc->shift;
948 int max = mc->max;
949 int mask = (1 << fls(max)) - 1;
950 int err;
951 unsigned short val, val2, val_mask;
952
953 val_mask = mask << shift;
954 val = (ucontrol->value.integer.value[0] & mask);
955 val2 = (ucontrol->value.integer.value[1] & mask);
956
957 if (val)
958 val = max + 1 - val;
959 if (val2)
960 val2 = max + 1 - val2;
961
962 val = val << shift;
963 val2 = val2 << shift;
964
965 err = snd_soc_update_bits(codec, reg, val_mask, val);
966 if (err < 0)
967 return err;
968
969 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
970 return err;
971}
972
b74bd40f
LCM		 973/* Codec operation modes */
974static const char *twl4030_op_modes_texts[] = {
975 "Option 2 (voice/audio)", "Option 1 (audio)"
976};
977
978static const struct soc_enum twl4030_op_modes_enum =
979 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
980 ARRAY_SIZE(twl4030_op_modes_texts),
981 twl4030_op_modes_texts);
982
423c238d 983static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 984 struct snd_ctl_elem_value *ucontrol)
985{
986 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 987 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 988 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
989 unsigned short val;
990 unsigned short mask, bitmask;
991
992 if (twl4030->configured) {
993 printk(KERN_ERR "twl4030 operation mode cannot be "
994 "changed on-the-fly\n");
995 return -EBUSY;
996 }
997
998 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
999 ;
1000 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1001 return -EINVAL;
1002
1003 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1004 mask = (bitmask - 1) << e->shift_l;
1005 if (e->shift_l != e->shift_r) {
1006 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1007 return -EINVAL;
1008 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1009 mask |= (bitmask - 1) << e->shift_r;
1010 }
1011
1012 return snd_soc_update_bits(codec, e->reg, mask, val);
1013}
1014
c10b82cf
PU		 1015/*
1016 * FGAIN volume control:
1017 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1018 */
d889a72c 1019static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1020
0d33ea0b
PU		 1021/*
1022 * CGAIN volume control:
1023 * 0 dB to 12 dB in 6 dB steps
1024 * value 2 and 3 means 12 dB
1025 */
d889a72c
PU		 1026static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1027
1a787e7a
JS		 1028/*
1029 * Voice Downlink GAIN volume control:
1030 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1031 */
1032static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1033
d889a72c
PU		 1034/*
1035 * Analog playback gain
1036 * -24 dB to 12 dB in 2 dB steps
1037 */
1038static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1039
4290239c
PU		 1040/*
1041 * Gain controls tied to outputs
1042 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1043 */
1044static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1045
18cc8d8d
JS		 1046/*
1047 * Gain control for earpiece amplifier
1048 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1049 */
1050static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1051
381a22b5
PU		 1052/*
1053 * Capture gain after the ADCs
1054 * from 0 dB to 31 dB in 1 dB steps
1055 */
1056static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1057
5920b453
GI		 1058/*
1059 * Gain control for input amplifiers
1060 * 0 dB to 30 dB in 6 dB steps
1061 */
1062static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1063
328d0a13
LCM		 1064/* AVADC clock priority */
1065static const char *twl4030_avadc_clk_priority_texts[] = {
1066 "Voice high priority", "HiFi high priority"
1067};
1068
1069static const struct soc_enum twl4030_avadc_clk_priority_enum =
1070 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1071 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1072 twl4030_avadc_clk_priority_texts);
1073
89492be8
PU		 1074static const char *twl4030_rampdelay_texts[] = {
1075 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1076 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1077 "3495/2581/1748 ms"
1078};
1079
1080static const struct soc_enum twl4030_rampdelay_enum =
1081 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1082 ARRAY_SIZE(twl4030_rampdelay_texts),
1083 twl4030_rampdelay_texts);
1084
376f7839
PU		 1085/* Vibra H-bridge direction mode */
1086static const char *twl4030_vibradirmode_texts[] = {
1087 "Vibra H-bridge direction", "Audio data MSB",
1088};
1089
1090static const struct soc_enum twl4030_vibradirmode_enum =
1091 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1092 ARRAY_SIZE(twl4030_vibradirmode_texts),
1093 twl4030_vibradirmode_texts);
1094
1095/* Vibra H-bridge direction */
1096static const char *twl4030_vibradir_texts[] = {
1097 "Positive polarity", "Negative polarity",
1098};
1099
1100static const struct soc_enum twl4030_vibradir_enum =
1101 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1102 ARRAY_SIZE(twl4030_vibradir_texts),
1103 twl4030_vibradir_texts);
1104
36aeff61
PU		 1105/* Digimic Left and right swapping */
1106static const char *twl4030_digimicswap_texts[] = {
1107 "Not swapped", "Swapped",
1108};
1109
1110static const struct soc_enum twl4030_digimicswap_enum =
1111 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1112 ARRAY_SIZE(twl4030_digimicswap_texts),
1113 twl4030_digimicswap_texts);
1114
cc17557e 1115static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1116 /* Codec operation mode control */
1117 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1118 snd_soc_get_enum_double,
1119 snd_soc_put_twl4030_opmode_enum_double),
1120
d889a72c
PU		 1121 /* Common playback gain controls */
1122 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1123 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1124 0, 0x3f, 0, digital_fine_tlv),
1125 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1126 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1127 0, 0x3f, 0, digital_fine_tlv),
1128
1129 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1130 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1131 6, 0x2, 0, digital_coarse_tlv),
1132 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1133 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1134 6, 0x2, 0, digital_coarse_tlv),
1135
1136 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1137 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1138 3, 0x12, 1, analog_tlv),
1139 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1140 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1141 3, 0x12, 1, analog_tlv),
44c55870
PU		 1142 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1143 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1144 1, 1, 0),
1145 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1146 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1147 1, 1, 0),
381a22b5 1148
1a787e7a
JS		 1149 /* Common voice downlink gain controls */
1150 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1151 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1152
1153 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1154 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1155
1156 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1157 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1158
4290239c
PU		 1159 /* Separate output gain controls */
1160 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1161 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1162 4, 3, 0, output_tvl),
1163
1164 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1165 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1166
1167 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1168 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1169 4, 3, 0, output_tvl),
1170
1171 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1172 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1173
381a22b5 1174 /* Common capture gain controls */
276c6222 1175 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1176 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1177 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1178 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1179 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1180 0, 0x1f, 0, digital_capture_tlv),
5920b453 1181
276c6222 1182 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1183 0, 3, 5, 0, input_gain_tlv),
89492be8 1184
328d0a13
LCM		 1185 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1186
89492be8 1187 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1188
1189 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1190 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1191
1192 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1193};
1194
cc17557e 1195static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1196 /* Left channel inputs */
1197 SND_SOC_DAPM_INPUT("MAINMIC"),
1198 SND_SOC_DAPM_INPUT("HSMIC"),
1199 SND_SOC_DAPM_INPUT("AUXL"),
1200 SND_SOC_DAPM_INPUT("CARKITMIC"),
1201 /* Right channel inputs */
1202 SND_SOC_DAPM_INPUT("SUBMIC"),
1203 SND_SOC_DAPM_INPUT("AUXR"),
1204 /* Digital microphones (Stereo) */
1205 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1206 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1207
1208 /* Outputs */
5e98a464 1209 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1210 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1211 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1212 SND_SOC_DAPM_OUTPUT("HSOL"),
1213 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1214 SND_SOC_DAPM_OUTPUT("CARKITL"),
1215 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1216 SND_SOC_DAPM_OUTPUT("HFL"),
1217 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1218 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1219
7b4c734e
PU		 1220 /* AIF and APLL clocks for running DAIs (including loopback) */
1221 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1222 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1223 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1224
53b5047d 1225 /* DACs */
b4852b79 1226 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1227 SND_SOC_NOPM, 0, 0),
b4852b79 1228 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1229 SND_SOC_NOPM, 0, 0),
b4852b79 1230 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1231 SND_SOC_NOPM, 0, 0),
b4852b79 1232 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1233 SND_SOC_NOPM, 0, 0),
1a787e7a 1234 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1235 SND_SOC_NOPM, 0, 0),
cc17557e 1236
7393958f 1237 /* Analog bypasses */
78e08e2f
PU		 1238 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1239 &twl4030_dapm_abypassr1_control),
1240 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1241 &twl4030_dapm_abypassl1_control),
1242 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1243 &twl4030_dapm_abypassr2_control),
1244 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1245 &twl4030_dapm_abypassl2_control),
1246 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1247 &twl4030_dapm_abypassv_control),
1248
1249 /* Master analog loopback switch */
1250 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1251 NULL, 0),
7393958f 1252
6bab83fd 1253 /* Digital bypasses */
78e08e2f
PU		 1254 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1255 &twl4030_dapm_dbypassl_control),
1256 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1257 &twl4030_dapm_dbypassr_control),
1258 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1259 &twl4030_dapm_dbypassv_control),
6bab83fd 1260
4005d39a
PU		 1261 /* Digital mixers, power control for the physical DACs */
1262 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1263 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1264 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1265 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1266 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1267 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1268 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1269 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1270 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1271 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1272
1273 /* Analog mixers, power control for the physical PGAs */
1274 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1275 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1276 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1277 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1278 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1279 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1280 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1281 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1282 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1283 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1284
7729cf74
PU		 1285 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1286 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1287
7b4c734e
PU		 1288 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1289 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1290
1a787e7a 1291 /* Output MIXER controls */
5e98a464 1292 /* Earpiece */
1a787e7a
JS		 1293 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1294 &twl4030_dapm_earpiece_controls[0],
1295 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1296 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1297 0, 0, NULL, 0, earpiecepga_event,
1298 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1299 /* PreDrivL/R */
1a787e7a
JS		 1300 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1301 &twl4030_dapm_predrivel_controls[0],
1302 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1303 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1304 0, 0, NULL, 0, predrivelpga_event,
1305 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1306 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1307 &twl4030_dapm_predriver_controls[0],
1308 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1309 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1310 0, 0, NULL, 0, predriverpga_event,
1311 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1312 /* HeadsetL/R */
6943c92e 1313 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1314 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1315 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1316 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1317 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1318 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1319 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1320 &twl4030_dapm_hsor_controls[0],
1321 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1322 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1323 0, 0, NULL, 0, headsetrpga_event,
1324 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1325 /* CarkitL/R */
1a787e7a
JS		 1326 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1327 &twl4030_dapm_carkitl_controls[0],
1328 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1329 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1330 0, 0, NULL, 0, carkitlpga_event,
1331 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1332 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1333 &twl4030_dapm_carkitr_controls[0],
1334 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1335 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1336 0, 0, NULL, 0, carkitrpga_event,
1337 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1338
1339 /* Output MUX controls */
df339804 1340 /* HandsfreeL/R */
5a2e9a48
PU		 1341 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1343 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1344 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1345 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1346 0, 0, NULL, 0, handsfreelpga_event,
1347 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1348 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1349 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1350 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1351 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1352 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1353 0, 0, NULL, 0, handsfreerpga_event,
1354 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1355 /* Vibra */
86139a13
JV		 1356 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1357 &twl4030_dapm_vibra_control, vibramux_event,
1358 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1359 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1360 &twl4030_dapm_vibrapath_control),
5e98a464 1361
276c6222
PU		 1362 /* Introducing four virtual ADC, since TWL4030 have four channel for
1363 capture */
1364 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1365 SND_SOC_NOPM, 0, 0),
1366 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1367 SND_SOC_NOPM, 0, 0),
1368 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1369 SND_SOC_NOPM, 0, 0),
1370 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1371 SND_SOC_NOPM, 0, 0),
1372
1373 /* Analog/Digital mic path selection.
1374 TX1 Left/Right: either analog Left/Right or Digimic0
1375 TX2 Left/Right: either analog Left/Right or Digimic1 */
1376 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1377 &twl4030_dapm_micpathtx1_control, micpath_event,
1378 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1379 SND_SOC_DAPM_POST_REG),
1380 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1381 &twl4030_dapm_micpathtx2_control, micpath_event,
1382 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1383 SND_SOC_DAPM_POST_REG),
1384
97b8096d 1385 /* Analog input mixers for the capture amplifiers */
9028935d 1386 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1387 TWL4030_REG_ANAMICL, 4, 0,
1388 &twl4030_dapm_analoglmic_controls[0],
1389 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1390 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1391 TWL4030_REG_ANAMICR, 4, 0,
1392 &twl4030_dapm_analogrmic_controls[0],
1393 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1394
fb2a2f84
PU		 1395 SND_SOC_DAPM_PGA("ADC Physical Left",
1396 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1397 SND_SOC_DAPM_PGA("ADC Physical Right",
1398 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1399
1400 SND_SOC_DAPM_PGA("Digimic0 Enable",
1401 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1402 SND_SOC_DAPM_PGA("Digimic1 Enable",
1403 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1404
1405 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1406 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1407 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1408
cc17557e
SS		 1409};
1410
1411static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1412 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1413 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1414 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1415 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1416 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1417
7729cf74 1418 /* Supply for the digital part (APLL) */
7729cf74
PU		 1419 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1420
c42a59ea
PU		 1421 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1422 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1423 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1424 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1425
4005d39a
PU		 1426 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1427 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1428 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1429 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1430 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1431
5e98a464
PU		 1432 /* Internal playback routings */
1433 /* Earpiece */
4005d39a
PU		 1434 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1435 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1436 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1437 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1438 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1439 /* PreDrivL */
4005d39a
PU		 1440 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1441 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1442 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1443 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1444 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1445 /* PreDrivR */
4005d39a
PU		 1446 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1447 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1448 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1449 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1450 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1451 /* HeadsetL */
4005d39a
PU		 1452 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1453 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1454 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1455 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1456 /* HeadsetR */
4005d39a
PU		 1457 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1458 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1459 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1460 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1461 /* CarkitL */
4005d39a
PU		 1462 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1463 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1464 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1465 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1466 /* CarkitR */
4005d39a
PU		 1467 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1468 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1469 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1470 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1471 /* HandsfreeL */
4005d39a
PU		 1472 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1473 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1474 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1475 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1476 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1477 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1478 /* HandsfreeR */
4005d39a
PU		 1479 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1480 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1481 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1482 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1483 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1484 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1485 /* Vibra */
1486 {"Vibra Mux", "AudioL1", "DAC Left1"},
1487 {"Vibra Mux", "AudioR1", "DAC Right1"},
1488 {"Vibra Mux", "AudioL2", "DAC Left2"},
1489 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1490
cc17557e 1491 /* outputs */
7b4c734e
PU		 1492 /* Must be always connected (for AIF and APLL) */
1493 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1494 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1495 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1496 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1497 /* Must be always connected (for APLL) */
1498 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1499 /* Physical outputs */
9008adf9
PU		 1500 {"EARPIECE", NULL, "Earpiece PGA"},
1501 {"PREDRIVEL", NULL, "PredriveL PGA"},
1502 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1503 {"HSOL", NULL, "HeadsetL PGA"},
1504 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1505 {"CARKITL", NULL, "CarkitL PGA"},
1506 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1507 {"HFL", NULL, "HandsfreeL PGA"},
1508 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1509 {"Vibra Route", "Audio", "Vibra Mux"},
1510 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1511
276c6222 1512 /* Capture path */
7b4c734e
PU		 1513 /* Must be always connected (for AIF and APLL) */
1514 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1515 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1516 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1517 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1518 /* Physical inputs */
9028935d
PU		 1519 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1520 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1521 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1522 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1523
9028935d
PU		 1524 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1525 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1526
9028935d
PU		 1527 {"ADC Physical Left", NULL, "Analog Left"},
1528 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1529
1530 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1531 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1532
1533 /* TX1 Left capture path */
fb2a2f84 1534 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1535 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1536 /* TX1 Right capture path */
fb2a2f84 1537 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1538 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1539 /* TX2 Left capture path */
fb2a2f84 1540 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1541 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1542 /* TX2 Right capture path */
fb2a2f84 1543 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1544 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1545
1546 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1547 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1548 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1549 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1550
c42a59ea
PU		 1551 {"ADC Virtual Left1", NULL, "AIF Enable"},
1552 {"ADC Virtual Right1", NULL, "AIF Enable"},
1553 {"ADC Virtual Left2", NULL, "AIF Enable"},
1554 {"ADC Virtual Right2", NULL, "AIF Enable"},
1555
7393958f 1556 /* Analog bypass routes */
9028935d
PU		 1557 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1558 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1559 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1560 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1561 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1562
78e08e2f
PU		 1563 /* Supply for the Analog loopbacks */
1564 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1565 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1566 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1567 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1568 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1569
7393958f
PU		 1570 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1571 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1572 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1573 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1574 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1575
6bab83fd
PU		 1576 /* Digital bypass routes */
1577 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1578 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1579 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1580
4005d39a
PU		 1581 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1582 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1583 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1584
cc17557e
SS		 1585};
1586
1587static int twl4030_add_widgets(struct snd_soc_codec *codec)
1588{
1589 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1590 ARRAY_SIZE(twl4030_dapm_widgets));
1591
1592 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1593
cc17557e
SS		 1594 return 0;
1595}
1596
cc17557e
SS		 1597static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1598 enum snd_soc_bias_level level)
1599{
1600 switch (level) {
1601 case SND_SOC_BIAS_ON:
cc17557e
SS		 1602 break;
1603 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1604 break;
1605 case SND_SOC_BIAS_STANDBY:
78e08e2f
PU		 1606 if (codec->bias_level == SND_SOC_BIAS_OFF)
1607 twl4030_power_up(codec);
cc17557e
SS		 1608 break;
1609 case SND_SOC_BIAS_OFF:
1610 twl4030_power_down(codec);
1611 break;
1612 }
1613 codec->bias_level = level;
1614
1615 return 0;
1616}
1617
6b87a91f
PU		 1618static void twl4030_constraints(struct twl4030_priv *twl4030,
1619 struct snd_pcm_substream *mst_substream)
1620{
1621 struct snd_pcm_substream *slv_substream;
1622
1623 /* Pick the stream, which need to be constrained */
1624 if (mst_substream == twl4030->master_substream)
1625 slv_substream = twl4030->slave_substream;
1626 else if (mst_substream == twl4030->slave_substream)
1627 slv_substream = twl4030->master_substream;
1628 else /* This should not happen.. */
1629 return;
1630
1631 /* Set the constraints according to the already configured stream */
1632 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1633 SNDRV_PCM_HW_PARAM_RATE,
1634 twl4030->rate,
1635 twl4030->rate);
1636
1637 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1638 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1639 twl4030->sample_bits,
1640 twl4030->sample_bits);
1641
1642 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1643 SNDRV_PCM_HW_PARAM_CHANNELS,
1644 twl4030->channels,
1645 twl4030->channels);
1646}
1647
8a1f936a
PU		 1648/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1649 * capture has to be enabled/disabled. */
1650static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1651 int enable)
1652{
1653 u8 reg, mask;
1654
1655 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1656
1657 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1658 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1659 else
1660 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1661
1662 if (enable)
1663 reg |= mask;
1664 else
1665 reg &= ~mask;
1666
1667 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1668}
1669
d6648da1
PU		 1670static int twl4030_startup(struct snd_pcm_substream *substream,
1671 struct snd_soc_dai *dai)
7220b9f4
PU		 1672{
1673 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1674 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1675 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1676 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1677
7220b9f4 1678 if (twl4030->master_substream) {
7220b9f4 1679 twl4030->slave_substream = substream;
6b87a91f
PU		 1680 /* The DAI has one configuration for playback and capture, so
1681 * if the DAI has been already configured then constrain this
1682 * substream to match it. */
1683 if (twl4030->configured)
1684 twl4030_constraints(twl4030, twl4030->master_substream);
1685 } else {
8a1f936a
PU		 1686 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1687 TWL4030_OPTION_1)) {
1688 /* In option2 4 channel is not supported, set the
1689 * constraint for the first stream for channels, the
1690 * second stream will 'inherit' this cosntraint */
1691 snd_pcm_hw_constraint_minmax(substream->runtime,
1692 SNDRV_PCM_HW_PARAM_CHANNELS,
1693 2, 2);
1694 }
7220b9f4 1695 twl4030->master_substream = substream;
6b87a91f 1696 }
7220b9f4
PU		 1697
1698 return 0;
1699}
1700
d6648da1
PU		 1701static void twl4030_shutdown(struct snd_pcm_substream *substream,
1702 struct snd_soc_dai *dai)
7220b9f4
PU		 1703{
1704 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1705 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1706 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1707 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1708
1709 if (twl4030->master_substream == substream)
1710 twl4030->master_substream = twl4030->slave_substream;
1711
1712 twl4030->slave_substream = NULL;
6b87a91f
PU		 1713
1714 /* If all streams are closed, or the remaining stream has not yet
1715 * been configured than set the DAI as not configured. */
1716 if (!twl4030->master_substream)
1717 twl4030->configured = 0;
1718 else if (!twl4030->master_substream->runtime->channels)
1719 twl4030->configured = 0;
8a1f936a
PU		 1720
1721 /* If the closing substream had 4 channel, do the necessary cleanup */
1722 if (substream->runtime->channels == 4)
1723 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1724}
1725
cc17557e 1726static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1727 struct snd_pcm_hw_params *params,
1728 struct snd_soc_dai *dai)
cc17557e
SS		 1729{
1730 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1731 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1732 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1733 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1734 u8 mode, old_mode, format, old_format;
1735
8a1f936a
PU		 1736 /* If the substream has 4 channel, do the necessary setup */
1737 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1738 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1739 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1740
1741 /* Safety check: are we in the correct operating mode and
1742 * the interface is in TDM mode? */
1743 if ((mode & TWL4030_OPTION_1) &&
1744 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1745 twl4030_tdm_enable(codec, substream->stream, 1);
1746 else
1747 return -EINVAL;
1748 }
1749
6b87a91f
PU		 1750 if (twl4030->configured)
1751 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1752 return 0;
1753
cc17557e
SS		 1754 /* bit rate */
1755 old_mode = twl4030_read_reg_cache(codec,
1756 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1757 mode = old_mode & ~TWL4030_APLL_RATE;
1758
1759 switch (params_rate(params)) {
1760 case 8000:
1761 mode |= TWL4030_APLL_RATE_8000;
1762 break;
1763 case 11025:
1764 mode |= TWL4030_APLL_RATE_11025;
1765 break;
1766 case 12000:
1767 mode |= TWL4030_APLL_RATE_12000;
1768 break;
1769 case 16000:
1770 mode |= TWL4030_APLL_RATE_16000;
1771 break;
1772 case 22050:
1773 mode |= TWL4030_APLL_RATE_22050;
1774 break;
1775 case 24000:
1776 mode |= TWL4030_APLL_RATE_24000;
1777 break;
1778 case 32000:
1779 mode |= TWL4030_APLL_RATE_32000;
1780 break;
1781 case 44100:
1782 mode |= TWL4030_APLL_RATE_44100;
1783 break;
1784 case 48000:
1785 mode |= TWL4030_APLL_RATE_48000;
1786 break;
103f211d
PU		 1787 case 96000:
1788 mode |= TWL4030_APLL_RATE_96000;
1789 break;
cc17557e
SS		 1790 default:
1791 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1792 params_rate(params));
1793 return -EINVAL;
1794 }
1795
1796 if (mode != old_mode) {
1797 /* change rate and set CODECPDZ */
7393958f 1798 twl4030_codec_enable(codec, 0);
cc17557e 1799 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1800 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1801 }
1802
1803 /* sample size */
1804 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1805 format = old_format;
1806 format &= ~TWL4030_DATA_WIDTH;
1807 switch (params_format(params)) {
1808 case SNDRV_PCM_FORMAT_S16_LE:
1809 format |= TWL4030_DATA_WIDTH_16S_16W;
1810 break;
1811 case SNDRV_PCM_FORMAT_S24_LE:
1812 format |= TWL4030_DATA_WIDTH_32S_24W;
1813 break;
1814 default:
1815 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1816 params_format(params));
1817 return -EINVAL;
1818 }
1819
1820 if (format != old_format) {
1821
1822 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1823 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1824
1825 /* change format */
1826 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1827
1828 /* set CODECPDZ afterwards */
db04e2c5 1829 twl4030_codec_enable(codec, 1);
cc17557e 1830 }
6b87a91f
PU		 1831
1832 /* Store the important parameters for the DAI configuration and set
1833 * the DAI as configured */
1834 twl4030->configured = 1;
1835 twl4030->rate = params_rate(params);
1836 twl4030->sample_bits = hw_param_interval(params,
1837 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1838 twl4030->channels = params_channels(params);
1839
1840 /* If both playback and capture streams are open, and one of them
1841 * is setting the hw parameters right now (since we are here), set
1842 * constraints to the other stream to match the current one. */
1843 if (twl4030->slave_substream)
1844 twl4030_constraints(twl4030, substream);
1845
cc17557e
SS		 1846 return 0;
1847}
1848
1849static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1850 int clk_id, unsigned int freq, int dir)
1851{
1852 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1853 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1854
1855 switch (freq) {
1856 case 19200000:
cc17557e 1857 case 26000000:
cc17557e 1858 case 38400000:
cc17557e
SS		 1859 break;
1860 default:
68d01955 1861 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1862 return -EINVAL;
1863 }
1864
68d01955
PU		 1865 if ((freq / 1000) != twl4030->sysclk) {
1866 dev_err(codec->dev,
1867 "Mismatch in APLL mclk: %u (configured: %u)\n",
1868 freq, twl4030->sysclk * 1000);
1869 return -EINVAL;
1870 }
cc17557e
SS		 1871
1872 return 0;
1873}
1874
1875static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1876 unsigned int fmt)
1877{
1878 struct snd_soc_codec *codec = codec_dai->codec;
1879 u8 old_format, format;
1880
1881 /* get format */
1882 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1883 format = old_format;
1884
1885 /* set master/slave audio interface */
1886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1887 case SND_SOC_DAIFMT_CBM_CFM:
1888 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1889 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1890 break;
1891 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1892 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1893 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1894 break;
1895 default:
1896 return -EINVAL;
1897 }
1898
1899 /* interface format */
1900 format &= ~TWL4030_AIF_FORMAT;
1901 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1902 case SND_SOC_DAIFMT_I2S:
1903 format |= TWL4030_AIF_FORMAT_CODEC;
1904 break;
8a1f936a
PU		 1905 case SND_SOC_DAIFMT_DSP_A:
1906 format |= TWL4030_AIF_FORMAT_TDM;
1907 break;
cc17557e
SS		 1908 default:
1909 return -EINVAL;
1910 }
1911
1912 if (format != old_format) {
1913
1914 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1915 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1916
1917 /* change format */
1918 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1919
1920 /* set CODECPDZ afterwards */
db04e2c5 1921 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1922 }
1923
1924 return 0;
1925}
1926
68140443
LCM		 1927static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1928{
1929 struct snd_soc_codec *codec = dai->codec;
1930 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1931
1932 if (tristate)
1933 reg |= TWL4030_AIF_TRI_EN;
1934 else
1935 reg &= ~TWL4030_AIF_TRI_EN;
1936
1937 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1938}
1939
b7a755a8
MLC		 1940/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1941 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1942static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1943 int enable)
1944{
1945 u8 reg, mask;
1946
1947 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1948
1949 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1950 mask = TWL4030_ARXL1_VRX_EN;
1951 else
1952 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1953
1954 if (enable)
1955 reg |= mask;
1956 else
1957 reg &= ~mask;
1958
1959 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1960}
1961
7154b3e8
JS		 1962static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1963 struct snd_soc_dai *dai)
1964{
1965 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1966 struct snd_soc_device *socdev = rtd->socdev;
1967 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1968 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1969 u8 mode;
1970
1971 /* If the system master clock is not 26MHz, the voice PCM interface is
1972 * not avilable.
1973 */
68d01955
PU		 1974 if (twl4030->sysclk != 26000) {
1975 dev_err(codec->dev, "The board is configured for %u Hz, while"
1976 "the Voice interface needs 26MHz APLL mclk\n",
1977 twl4030->sysclk * 1000);
7154b3e8
JS		 1978 return -EINVAL;
1979 }
1980
1981 /* If the codec mode is not option2, the voice PCM interface is not
1982 * avilable.
1983 */
1984 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1985 & TWL4030_OPT_MODE;
1986
1987 if (mode != TWL4030_OPTION_2) {
1988 printk(KERN_ERR "TWL4030 voice startup: "
1989 "the codec mode is not option2\n");
1990 return -EINVAL;
1991 }
1992
1993 return 0;
1994}
1995
b7a755a8
MLC		 1996static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1997 struct snd_soc_dai *dai)
1998{
1999 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2000 struct snd_soc_device *socdev = rtd->socdev;
2001 struct snd_soc_codec *codec = socdev->card->codec;
2002
2003 /* Enable voice digital filters */
2004 twl4030_voice_enable(codec, substream->stream, 0);
2005}
2006
7154b3e8
JS		 2007static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2008 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2009{
2010 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2011 struct snd_soc_device *socdev = rtd->socdev;
2012 struct snd_soc_codec *codec = socdev->card->codec;
2013 u8 old_mode, mode;
2014
b7a755a8
MLC		 2015 /* Enable voice digital filters */
2016 twl4030_voice_enable(codec, substream->stream, 1);
2017
7154b3e8
JS		 2018 /* bit rate */
2019 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2020 & ~(TWL4030_CODECPDZ);
2021 mode = old_mode;
2022
2023 switch (params_rate(params)) {
2024 case 8000:
2025 mode &= ~(TWL4030_SEL_16K);
2026 break;
2027 case 16000:
2028 mode |= TWL4030_SEL_16K;
2029 break;
2030 default:
2031 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2032 params_rate(params));
2033 return -EINVAL;
2034 }
2035
2036 if (mode != old_mode) {
2037 /* change rate and set CODECPDZ */
2038 twl4030_codec_enable(codec, 0);
2039 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2040 twl4030_codec_enable(codec, 1);
2041 }
2042
2043 return 0;
2044}
2045
2046static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2047 int clk_id, unsigned int freq, int dir)
2048{
2049 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2050 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2051
68d01955
PU		 2052 if (freq != 26000000) {
2053 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2054 "interface needs 26MHz APLL mclk\n", freq);
2055 return -EINVAL;
2056 }
2057 if ((freq / 1000) != twl4030->sysclk) {
2058 dev_err(codec->dev,
2059 "Mismatch in APLL mclk: %u (configured: %u)\n",
2060 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2061 return -EINVAL;
2062 }
7154b3e8
JS		 2063 return 0;
2064}
2065
2066static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2067 unsigned int fmt)
2068{
2069 struct snd_soc_codec *codec = codec_dai->codec;
2070 u8 old_format, format;
2071
2072 /* get format */
2073 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2074 format = old_format;
2075
2076 /* set master/slave audio interface */
2077 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2078 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2079 format &= ~(TWL4030_VIF_SLAVE_EN);
2080 break;
2081 case SND_SOC_DAIFMT_CBS_CFS:
2082 format |= TWL4030_VIF_SLAVE_EN;
2083 break;
2084 default:
2085 return -EINVAL;
2086 }
2087
2088 /* clock inversion */
2089 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2090 case SND_SOC_DAIFMT_IB_NF:
2091 format &= ~(TWL4030_VIF_FORMAT);
2092 break;
2093 case SND_SOC_DAIFMT_NB_IF:
2094 format |= TWL4030_VIF_FORMAT;
2095 break;
2096 default:
2097 return -EINVAL;
2098 }
2099
2100 if (format != old_format) {
2101 /* change format and set CODECPDZ */
2102 twl4030_codec_enable(codec, 0);
2103 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2104 twl4030_codec_enable(codec, 1);
2105 }
2106
2107 return 0;
2108}
2109
68140443
LCM		 2110static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2111{
2112 struct snd_soc_codec *codec = dai->codec;
2113 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2114
2115 if (tristate)
2116 reg |= TWL4030_VIF_TRI_EN;
2117 else
2118 reg &= ~TWL4030_VIF_TRI_EN;
2119
2120 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2121}
2122
bbba9444 2123#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2124#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2125
10d9e3d9 2126static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2127 .startup = twl4030_startup,
2128 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2129 .hw_params = twl4030_hw_params,
2130 .set_sysclk = twl4030_set_dai_sysclk,
2131 .set_fmt = twl4030_set_dai_fmt,
68140443 2132 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2133};
2134
7154b3e8
JS		 2135static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2136 .startup = twl4030_voice_startup,
b7a755a8 2137 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2138 .hw_params = twl4030_voice_hw_params,
2139 .set_sysclk = twl4030_voice_set_dai_sysclk,
2140 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2141 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2142};
2143
2144struct snd_soc_dai twl4030_dai[] = {
2145{
cc17557e
SS		 2146 .name = "twl4030",
2147 .playback = {
b4852b79 2148 .stream_name = "HiFi Playback",
cc17557e 2149 .channels_min = 2,
8a1f936a 2150 .channels_max = 4,
31ad0f31 2151 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2152 .formats = TWL4030_FORMATS,},
2153 .capture = {
2154 .stream_name = "Capture",
2155 .channels_min = 2,
8a1f936a 2156 .channels_max = 4,
cc17557e
SS		 2157 .rates = TWL4030_RATES,
2158 .formats = TWL4030_FORMATS,},
10d9e3d9 2159 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2160},
2161{
2162 .name = "twl4030 Voice",
2163 .playback = {
b4852b79 2164 .stream_name = "Voice Playback",
7154b3e8
JS		 2165 .channels_min = 1,
2166 .channels_max = 1,
2167 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2168 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2169 .capture = {
2170 .stream_name = "Capture",
2171 .channels_min = 1,
2172 .channels_max = 2,
2173 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2174 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2175 .ops = &twl4030_dai_voice_ops,
2176},
cc17557e
SS		 2177};
2178EXPORT_SYMBOL_GPL(twl4030_dai);
2179
7a1fecf5 2180static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2181{
2182 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2183 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2184
2185 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2186
2187 return 0;
2188}
2189
7a1fecf5 2190static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2191{
2192 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2193 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2194
2195 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2196 return 0;
2197}
2198
7a1fecf5 2199static struct snd_soc_codec *twl4030_codec;
cc17557e 2200
7a1fecf5 2201static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2202{
7a1fecf5 2203 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
9da28c7b 2204 struct twl4030_setup_data *setup = socdev->codec_data;
7a1fecf5
PU		 2205 struct snd_soc_codec *codec;
2206 struct twl4030_priv *twl4030;
2207 int ret;
cc17557e 2208
7a1fecf5 2209 BUG_ON(!twl4030_codec);
cc17557e 2210
7a1fecf5 2211 codec = twl4030_codec;
b2c812e2 2212 twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 2213 socdev->card->codec = codec;
cc17557e 2214
9da28c7b
PU		 2215 /* Configuration for headset ramp delay from setup data */
2216 if (setup) {
2217 unsigned char hs_pop;
2218
68d01955
PU		 2219 if (setup->sysclk != twl4030->sysclk)
2220 dev_warn(&pdev->dev,
2221 "Mismatch in APLL mclk: %u (configured: %u)\n",
2222 setup->sysclk, twl4030->sysclk);
9da28c7b
PU		 2223
2224 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2225 hs_pop &= ~TWL4030_RAMP_DELAY;
2226 hs_pop |= (setup->ramp_delay_value << 2);
2227 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
9da28c7b
PU		 2228 }
2229
cc17557e
SS		 2230 /* register pcms */
2231 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2232 if (ret < 0) {
7a1fecf5
PU		 2233 dev_err(&pdev->dev, "failed to create pcms\n");
2234 return ret;
cc17557e
SS		 2235 }
2236
3e8e1952
IM		 2237 snd_soc_add_controls(codec, twl4030_snd_controls,
2238 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2239 twl4030_add_widgets(codec);
2240
7a1fecf5 2241 return 0;
cc17557e
SS		 2242}
2243
7a1fecf5 2244static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2245{
2246 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2247 struct snd_soc_codec *codec = socdev->card->codec;
2248
2249 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2250 snd_soc_free_pcms(socdev);
2251 snd_soc_dapm_free(socdev);
7a1fecf5
PU		 2252
2253 return 0;
2254}
2255
2256static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2257{
2258 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2259 struct snd_soc_codec *codec;
7393958f 2260 struct twl4030_priv *twl4030;
7a1fecf5 2261 int ret;
cc17557e 2262
68d01955
PU		 2263 if (!pdata) {
2264 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2265 return -EINVAL;
2266 }
cc17557e 2267
7393958f
PU		 2268 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2269 if (twl4030 == NULL) {
7a1fecf5 2270 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2271 return -ENOMEM;
2272 }
2273
7a1fecf5 2274 codec = &twl4030->codec;
b2c812e2 2275 snd_soc_codec_set_drvdata(codec, twl4030);
7a1fecf5
PU		 2276 codec->dev = &pdev->dev;
2277 twl4030_dai[0].dev = &pdev->dev;
2278 twl4030_dai[1].dev = &pdev->dev;
2279
cc17557e
SS		 2280 mutex_init(&codec->mutex);
2281 INIT_LIST_HEAD(&codec->dapm_widgets);
2282 INIT_LIST_HEAD(&codec->dapm_paths);
2283
7a1fecf5
PU		 2284 codec->name = "twl4030";
2285 codec->owner = THIS_MODULE;
2286 codec->read = twl4030_read_reg_cache;
2287 codec->write = twl4030_write;
2288 codec->set_bias_level = twl4030_set_bias_level;
2289 codec->dai = twl4030_dai;
fd63df22 2290 codec->num_dai = ARRAY_SIZE(twl4030_dai);
7a1fecf5
PU		 2291 codec->reg_cache_size = sizeof(twl4030_reg);
2292 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2293 GFP_KERNEL);
2294 if (codec->reg_cache == NULL) {
2295 ret = -ENOMEM;
2296 goto error_cache;
2297 }
2298
2299 platform_set_drvdata(pdev, twl4030);
2300 twl4030_codec = codec;
2301
2302 /* Set the defaults, and power up the codec */
68d01955 2303 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
7a1fecf5 2304 twl4030_init_chip(codec);
b3f5a272 2305 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2306 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2307
2308 ret = snd_soc_register_codec(codec);
2309 if (ret != 0) {
2310 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2311 goto error_codec;
2312 }
2313
2314 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2315 if (ret != 0) {
2316 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2317 snd_soc_unregister_codec(codec);
2318 goto error_codec;
2319 }
cc17557e
SS		 2320
2321 return 0;
7a1fecf5
PU		 2322
2323error_codec:
2324 twl4030_power_down(codec);
2325 kfree(codec->reg_cache);
2326error_cache:
2327 kfree(twl4030);
2328 return ret;
cc17557e
SS		 2329}
2330
7a1fecf5 2331static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2332{
7a1fecf5 2333 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2334
cb67286d
PU		 2335 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2336 snd_soc_unregister_codec(&twl4030->codec);
2337 kfree(twl4030->codec.reg_cache);
7a1fecf5 2338 kfree(twl4030);
cc17557e 2339
7a1fecf5 2340 twl4030_codec = NULL;
cc17557e
SS		 2341 return 0;
2342}
2343
7a1fecf5
PU		 2344MODULE_ALIAS("platform:twl4030_codec_audio");
2345
2346static struct platform_driver twl4030_codec_driver = {
2347 .probe = twl4030_codec_probe,
2348 .remove = __devexit_p(twl4030_codec_remove),
2349 .driver = {
2350 .name = "twl4030_codec_audio",
2351 .owner = THIS_MODULE,
2352 },
cc17557e 2353};
cc17557e 2354
24e07db8 2355static int __init twl4030_modinit(void)
64089b84 2356{
7a1fecf5 2357 return platform_driver_register(&twl4030_codec_driver);
64089b84 2358}
24e07db8 2359module_init(twl4030_modinit);
64089b84
MB		 2360
2361static void __exit twl4030_exit(void)
2362{
7a1fecf5 2363 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2364}
2365module_exit(twl4030_exit);
2366
7a1fecf5
PU		 2367struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2368 .probe = twl4030_soc_probe,
2369 .remove = twl4030_soc_remove,
2370 .suspend = twl4030_soc_suspend,
2371 .resume = twl4030_soc_resume,
2372};
2373EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2374
cc17557e
SS		 2375MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2376MODULE_AUTHOR("Steve Sakoman");
2377MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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