projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
cc17557e
SS		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
33f92ed4 45 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 46 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 49 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 54 0x0f, /* REG_ATXL1PGA (0xA) */
55 0x0f, /* REG_ATXR1PGA (0xB) */
56 0x0f, /* REG_AVTXL2PGA (0xC) */
57 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 58 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 59 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 60 0x3f, /* REG_ARXR1PGA (0x10) */
61 0x3f, /* REG_ARXL1PGA (0x11) */
62 0x3f, /* REG_ARXR2PGA (0x12) */
63 0x3f, /* REG_ARXL2PGA (0x13) */
64 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 67 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 68 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 69 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 75 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 78 0x00, /* REG_HS_SEL (0x22) */
79 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 87 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 92 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 97 0x79, /* REG_DTMF_TONOFF (0x35) */
98 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 102 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 103 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 104 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 112 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
7a1fecf5
PU		 123 struct snd_soc_codec codec;
124
7393958f 125 unsigned int codec_powered;
7b4c734e
PU		 126
127 /* reference counts of AIF/APLL users */
2845fa13 128 unsigned int apll_enabled;
7220b9f4
PU		 129
130 struct snd_pcm_substream *master_substream;
131 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 132
133 unsigned int configured;
134 unsigned int rate;
135 unsigned int sample_bits;
136 unsigned int channels;
6943c92e
PU		 137
138 unsigned int sysclk;
139
c96907f2
PU		 140 /* Output (with associated amp) states */
141 u8 hsl_enabled, hsr_enabled;
142 u8 earpiece_enabled;
143 u8 predrivel_enabled, predriver_enabled;
144 u8 carkitl_enabled, carkitr_enabled;
7393958f
PU		 145};
146
cc17557e
SS		 147/*
148 * read twl4030 register cache
149 */
150static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned int reg)
152{
d08664fd 153 u8 *cache = codec->reg_cache;
cc17557e 154
91432e97
IM		 155 if (reg >= TWL4030_CACHEREGNUM)
156 return -EIO;
157
cc17557e
SS		 158 return cache[reg];
159}
160
161/*
162 * write twl4030 register cache
163 */
164static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
165 u8 reg, u8 value)
166{
167 u8 *cache = codec->reg_cache;
168
169 if (reg >= TWL4030_CACHEREGNUM)
170 return;
171 cache[reg] = value;
172}
173
174/*
175 * write to the twl4030 register space
176 */
177static int twl4030_write(struct snd_soc_codec *codec,
178 unsigned int reg, unsigned int value)
179{
b2c812e2 180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 181 int write_to_reg = 0;
182
cc17557e 183 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 184 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
185 /* Decide if the given register can be written */
186 switch (reg) {
187 case TWL4030_REG_EAR_CTL:
188 if (twl4030->earpiece_enabled)
189 write_to_reg = 1;
190 break;
191 case TWL4030_REG_PREDL_CTL:
192 if (twl4030->predrivel_enabled)
193 write_to_reg = 1;
194 break;
195 case TWL4030_REG_PREDR_CTL:
196 if (twl4030->predriver_enabled)
197 write_to_reg = 1;
198 break;
199 case TWL4030_REG_PRECKL_CTL:
200 if (twl4030->carkitl_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PRECKR_CTL:
204 if (twl4030->carkitr_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_HS_GAIN_SET:
208 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
209 write_to_reg = 1;
210 break;
211 default:
212 /* All other register can be written */
213 write_to_reg = 1;
214 break;
215 }
216 if (write_to_reg)
217 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
218 value, reg);
219 }
220 return 0;
cc17557e
SS		 221}
222
db04e2c5 223static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 224{
b2c812e2 225 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 226 int mode;
cc17557e 227
7393958f
PU		 228 if (enable == twl4030->codec_powered)
229 return;
230
db04e2c5 231 if (enable)
7a1fecf5 232 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 233 else
7a1fecf5 234 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 235
7a1fecf5
PU		 236 if (mode >= 0) {
237 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
238 twl4030->codec_powered = enable;
239 }
cc17557e
SS		 240
241 /* REVISIT: this delay is present in TI sample drivers */
242 /* but there seems to be no TRM requirement for it */
243 udelay(10);
244}
245
9fdcc0f7
PU		 246static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
247{
248 int i, difference = 0;
249 u8 val;
250
251 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
252 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
253 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
254 if (val != twl4030_reg[i]) {
255 difference++;
256 dev_dbg(codec->dev,
257 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
258 i, val, twl4030_reg[i]);
259 }
260 }
261 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
262 difference, difference ? "Not OK" : "OK");
263}
264
ee4ccac7 265static void twl4030_init_chip(struct platform_device *pdev)
7393958f 266{
ee4ccac7
PU		 267 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
268 struct twl4030_setup_data *setup = socdev->codec_data;
269 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 270 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 271 u8 reg, byte;
272 int i = 0;
7393958f 273
9fdcc0f7
PU		 274 /* Check defaults, if instructed before anything else */
275 if (setup && setup->check_defaults)
276 twl4030_check_defaults(codec);
277
ee4ccac7 278 /* Refresh APLL_CTL register from HW */
9fdcc0f7 279 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 280 TWL4030_REG_APLL_CTL);
281 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
7a1fecf5 282
ee4ccac7
PU		 283 /* anti-pop when changing analog gain */
284 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
285 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
286 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 287
ee4ccac7
PU		 288 twl4030_write(codec, TWL4030_REG_OPTION,
289 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
290 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 291
3c36cc68
PU		 292 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
293 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
294
ee4ccac7
PU		 295 /* Machine dependent setup */
296 if (!setup)
7393958f
PU		 297 return;
298
ee4ccac7
PU		 299 /* Configuration for headset ramp delay from setup data */
300 if (setup->sysclk != twl4030->sysclk)
301 dev_warn(codec->dev,
302 "Mismatch in APLL mclk: %u (configured: %u)\n",
303 setup->sysclk, twl4030->sysclk);
304
305 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
306 reg &= ~TWL4030_RAMP_DELAY;
307 reg |= (setup->ramp_delay_value << 2);
308 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 309
310 /* initiate offset cancellation */
ee4ccac7
PU		 311 twl4030_codec_enable(codec, 1);
312
313 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
314 reg &= ~TWL4030_OFFSET_CNCL_SEL;
315 reg |= setup->offset_cncl_path;
006f367e 316 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 317 reg | TWL4030_CNCL_OFFSET_START);
006f367e
PU		 318
319 /* wait for offset cancellation to complete */
320 do {
321 /* this takes a little while, so don't slam i2c */
322 udelay(2000);
fc7b92fc 323 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 324 TWL4030_REG_ANAMICL);
325 } while ((i++ < 100) &&
326 ((byte & TWL4030_CNCL_OFFSET_START) ==
327 TWL4030_CNCL_OFFSET_START));
328
329 /* Make sure that the reg_cache has the same value as the HW */
330 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
331
006f367e 332 twl4030_codec_enable(codec, 0);
ee4ccac7
PU		 333}
334
335static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
336{
337 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
338 int status = -1;
339
340 if (enable) {
341 twl4030->apll_enabled++;
342 if (twl4030->apll_enabled == 1)
343 status = twl4030_codec_enable_resource(
344 TWL4030_CODEC_RES_APLL);
345 } else {
346 twl4030->apll_enabled--;
347 if (!twl4030->apll_enabled)
348 status = twl4030_codec_disable_resource(
349 TWL4030_CODEC_RES_APLL);
350 }
351
352 if (status >= 0)
353 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 354}
355
5e98a464 356/* Earpiece */
1a787e7a
JS		 357static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
358 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
359 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
360 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
361 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
362};
5e98a464 363
2a6f5c58 364/* PreDrive Left */
1a787e7a
JS		 365static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
366 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
367 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
368 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
369 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
370};
2a6f5c58
PU		 371
372/* PreDrive Right */
1a787e7a
JS		 373static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
377 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
378};
2a6f5c58 379
dfad21a2 380/* Headset Left */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
385};
dfad21a2
PU		 386
387/* Headset Right */
1a787e7a
JS		 388static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
389 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
390 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
391 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
392};
dfad21a2 393
5152d8c2 394/* Carkit Left */
1a787e7a
JS		 395static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
396 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
397 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
398 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
399};
5152d8c2
PU		 400
401/* Carkit Right */
1a787e7a
JS		 402static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
403 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
404 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
405 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
406};
5152d8c2 407
df339804
PU		 408/* Handsfree Left */
409static const char *twl4030_handsfreel_texts[] =
1a787e7a 410 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 411
412static const struct soc_enum twl4030_handsfreel_enum =
413 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
414 ARRAY_SIZE(twl4030_handsfreel_texts),
415 twl4030_handsfreel_texts);
416
417static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
418SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
419
0f89bdca
PU		 420/* Handsfree Left virtual mute */
421static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
422 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
423
df339804
PU		 424/* Handsfree Right */
425static const char *twl4030_handsfreer_texts[] =
1a787e7a 426 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 427
428static const struct soc_enum twl4030_handsfreer_enum =
429 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
430 ARRAY_SIZE(twl4030_handsfreer_texts),
431 twl4030_handsfreer_texts);
432
433static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
434SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
435
0f89bdca
PU		 436/* Handsfree Right virtual mute */
437static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
438 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
439
376f7839
PU		 440/* Vibra */
441/* Vibra audio path selection */
442static const char *twl4030_vibra_texts[] =
443 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
444
445static const struct soc_enum twl4030_vibra_enum =
446 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
447 ARRAY_SIZE(twl4030_vibra_texts),
448 twl4030_vibra_texts);
449
450static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
451SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
452
453/* Vibra path selection: local vibrator (PWM) or audio driven */
454static const char *twl4030_vibrapath_texts[] =
455 {"Local vibrator", "Audio"};
456
457static const struct soc_enum twl4030_vibrapath_enum =
458 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
459 ARRAY_SIZE(twl4030_vibrapath_texts),
460 twl4030_vibrapath_texts);
461
462static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
463SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
464
276c6222 465/* Left analog microphone selection */
97b8096d 466static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 467 SOC_DAPM_SINGLE("Main Mic Capture Switch",
468 TWL4030_REG_ANAMICL, 0, 1, 0),
469 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
470 TWL4030_REG_ANAMICL, 1, 1, 0),
471 SOC_DAPM_SINGLE("AUXL Capture Switch",
472 TWL4030_REG_ANAMICL, 2, 1, 0),
473 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
474 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 475};
276c6222
PU		 476
477/* Right analog microphone selection */
97b8096d 478static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 479 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
480 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 481};
276c6222
PU		 482
483/* TX1 L/R Analog/Digital microphone selection */
484static const char *twl4030_micpathtx1_texts[] =
485 {"Analog", "Digimic0"};
486
487static const struct soc_enum twl4030_micpathtx1_enum =
488 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
489 ARRAY_SIZE(twl4030_micpathtx1_texts),
490 twl4030_micpathtx1_texts);
491
492static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
493SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
494
495/* TX2 L/R Analog/Digital microphone selection */
496static const char *twl4030_micpathtx2_texts[] =
497 {"Analog", "Digimic1"};
498
499static const struct soc_enum twl4030_micpathtx2_enum =
500 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
501 ARRAY_SIZE(twl4030_micpathtx2_texts),
502 twl4030_micpathtx2_texts);
503
504static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
505SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
506
7393958f
PU		 507/* Analog bypass for AudioR1 */
508static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
509 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
510
511/* Analog bypass for AudioL1 */
512static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
513 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
514
515/* Analog bypass for AudioR2 */
516static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
517 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
518
519/* Analog bypass for AudioL2 */
520static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
521 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
522
fcd274a3
LCM		 523/* Analog bypass for Voice */
524static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
525 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
526
6bab83fd
PU		 527/* Digital bypass gain, 0 mutes the bypass */
528static const unsigned int twl4030_dapm_dbypass_tlv[] = {
529 TLV_DB_RANGE_HEAD(2),
530 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
531 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
532};
533
534/* Digital bypass left (TX1L -> RX2L) */
535static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
536 SOC_DAPM_SINGLE_TLV("Volume",
537 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
538 twl4030_dapm_dbypass_tlv);
539
540/* Digital bypass right (TX1R -> RX2R) */
541static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
542 SOC_DAPM_SINGLE_TLV("Volume",
543 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
544 twl4030_dapm_dbypass_tlv);
545
ee8f6894
LCM		 546/*
547 * Voice Sidetone GAIN volume control:
548 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
549 */
550static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
551
552/* Digital bypass voice: sidetone (VUL -> VDL)*/
553static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
554 SOC_DAPM_SINGLE_TLV("Volume",
555 TWL4030_REG_VSTPGA, 0, 0x29, 0,
556 twl4030_dapm_dbypassv_tlv);
557
276c6222
PU		 558static int micpath_event(struct snd_soc_dapm_widget *w,
559 struct snd_kcontrol *kcontrol, int event)
560{
561 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
562 unsigned char adcmicsel, micbias_ctl;
563
564 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
565 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
566 /* Prepare the bits for the given TX path:
567 * shift_l == 0: TX1 microphone path
568 * shift_l == 2: TX2 microphone path */
569 if (e->shift_l) {
570 /* TX2 microphone path */
571 if (adcmicsel & TWL4030_TX2IN_SEL)
572 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
573 else
574 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
575 } else {
576 /* TX1 microphone path */
577 if (adcmicsel & TWL4030_TX1IN_SEL)
578 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
579 else
580 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
581 }
582
583 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
584
585 return 0;
586}
587
9008adf9
PU		 588/*
589 * Output PGA builder:
590 * Handle the muting and unmuting of the given output (turning off the
591 * amplifier associated with the output pin)
c96907f2
PU		 592 * On mute bypass the reg_cache and write 0 to the register
593 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 594 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
595 */
596#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
597static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
598 struct snd_kcontrol *kcontrol, int event) \
599{ \
b2c812e2 600 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 601 \
602 switch (event) { \
603 case SND_SOC_DAPM_POST_PMU: \
c96907f2 604 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 605 twl4030_write(w->codec, reg, \
606 twl4030_read_reg_cache(w->codec, reg)); \
607 break; \
608 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 609 twl4030->pin_name##_enabled = 0; \
610 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
611 0, reg); \
9008adf9
PU		 612 break; \
613 } \
614 return 0; \
615}
616
617TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
618TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
619TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
620TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
621TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
622
5a2e9a48 623static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 624{
49d92c7d
SM		 625 unsigned char hs_ctl;
626
5a2e9a48 627 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 628
5a2e9a48
PU		 629 if (ramp) {
630 /* HF ramp-up */
631 hs_ctl |= TWL4030_HF_CTL_REF_EN;
632 twl4030_write(codec, reg, hs_ctl);
633 udelay(10);
49d92c7d 634 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 635 twl4030_write(codec, reg, hs_ctl);
636 udelay(40);
49d92c7d 637 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 638 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 639 twl4030_write(codec, reg, hs_ctl);
49d92c7d 640 } else {
5a2e9a48
PU		 641 /* HF ramp-down */
642 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
643 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
644 twl4030_write(codec, reg, hs_ctl);
645 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
646 twl4030_write(codec, reg, hs_ctl);
647 udelay(40);
648 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
649 twl4030_write(codec, reg, hs_ctl);
49d92c7d 650 }
5a2e9a48 651}
49d92c7d 652
5a2e9a48
PU		 653static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
654 struct snd_kcontrol *kcontrol, int event)
655{
656 switch (event) {
657 case SND_SOC_DAPM_POST_PMU:
658 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
659 break;
660 case SND_SOC_DAPM_POST_PMD:
661 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
662 break;
663 }
664 return 0;
665}
666
667static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
668 struct snd_kcontrol *kcontrol, int event)
669{
670 switch (event) {
671 case SND_SOC_DAPM_POST_PMU:
672 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
673 break;
674 case SND_SOC_DAPM_POST_PMD:
675 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
676 break;
677 }
49d92c7d
SM		 678 return 0;
679}
680
86139a13
JV		 681static int vibramux_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683{
684 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
685 return 0;
686}
687
7729cf74
PU		 688static int apll_event(struct snd_soc_dapm_widget *w,
689 struct snd_kcontrol *kcontrol, int event)
690{
691 switch (event) {
692 case SND_SOC_DAPM_PRE_PMU:
693 twl4030_apll_enable(w->codec, 1);
694 break;
695 case SND_SOC_DAPM_POST_PMD:
696 twl4030_apll_enable(w->codec, 0);
697 break;
698 }
699 return 0;
700}
701
7b4c734e
PU		 702static int aif_event(struct snd_soc_dapm_widget *w,
703 struct snd_kcontrol *kcontrol, int event)
704{
705 u8 audio_if;
706
707 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
708 switch (event) {
709 case SND_SOC_DAPM_PRE_PMU:
710 /* Enable AIF */
711 /* enable the PLL before we use it to clock the DAI */
712 twl4030_apll_enable(w->codec, 1);
713
714 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
715 audio_if | TWL4030_AIF_EN);
716 break;
717 case SND_SOC_DAPM_POST_PMD:
718 /* disable the DAI before we stop it's source PLL */
719 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
720 audio_if & ~TWL4030_AIF_EN);
721 twl4030_apll_enable(w->codec, 0);
722 break;
723 }
724 return 0;
725}
726
6943c92e 727static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 728{
4e49ffd1
CVJ		 729 struct snd_soc_device *socdev = codec->socdev;
730 struct twl4030_setup_data *setup = socdev->codec_data;
731
aad749e5 732 unsigned char hs_gain, hs_pop;
b2c812e2 733 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 734 /* Base values for ramp delay calculation: 2^19 - 2^26 */
735 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
736 8388608, 16777216, 33554432, 67108864};
aad749e5 737
6943c92e
PU		 738 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
739 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 740
4e49ffd1
CVJ		 741 /* Enable external mute control, this dramatically reduces
742 * the pop-noise */
743 if (setup && setup->hs_extmute) {
744 if (setup->set_hs_extmute) {
745 setup->set_hs_extmute(1);
746 } else {
747 hs_pop |= TWL4030_EXTMUTE;
748 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
749 }
750 }
751
6943c92e
PU		 752 if (ramp) {
753 /* Headset ramp-up according to the TRM */
aad749e5 754 hs_pop |= TWL4030_VMID_EN;
6943c92e 755 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 756 /* Actually write to the register */
757 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
758 hs_gain,
759 TWL4030_REG_HS_GAIN_SET);
aad749e5 760 hs_pop |= TWL4030_RAMP_EN;
6943c92e 761 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 762 /* Wait ramp delay time + 1, so the VMID can settle */
763 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
764 twl4030->sysclk) + 1);
6943c92e
PU		 765 } else {
766 /* Headset ramp-down _not_ according to
767 * the TRM, but in a way that it is working */
aad749e5 768 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 769 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
770 /* Wait ramp delay time + 1, so the VMID can settle */
771 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
772 twl4030->sysclk) + 1);
aad749e5 773 /* Bypass the reg_cache to mute the headset */
fc7b92fc 774 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 775 hs_gain & (~0x0f),
776 TWL4030_REG_HS_GAIN_SET);
6943c92e 777
aad749e5 778 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 779 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
780 }
4e49ffd1
CVJ		 781
782 /* Disable external mute */
783 if (setup && setup->hs_extmute) {
784 if (setup->set_hs_extmute) {
785 setup->set_hs_extmute(0);
786 } else {
787 hs_pop &= ~TWL4030_EXTMUTE;
788 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
789 }
790 }
6943c92e
PU		 791}
792
793static int headsetlpga_event(struct snd_soc_dapm_widget *w,
794 struct snd_kcontrol *kcontrol, int event)
795{
b2c812e2 796 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 797
798 switch (event) {
799 case SND_SOC_DAPM_POST_PMU:
800 /* Do the ramp-up only once */
801 if (!twl4030->hsr_enabled)
802 headset_ramp(w->codec, 1);
803
804 twl4030->hsl_enabled = 1;
805 break;
806 case SND_SOC_DAPM_POST_PMD:
807 /* Do the ramp-down only if both headsetL/R is disabled */
808 if (!twl4030->hsr_enabled)
809 headset_ramp(w->codec, 0);
810
811 twl4030->hsl_enabled = 0;
812 break;
813 }
814 return 0;
815}
816
817static int headsetrpga_event(struct snd_soc_dapm_widget *w,
818 struct snd_kcontrol *kcontrol, int event)
819{
b2c812e2 820 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 821
822 switch (event) {
823 case SND_SOC_DAPM_POST_PMU:
824 /* Do the ramp-up only once */
825 if (!twl4030->hsl_enabled)
826 headset_ramp(w->codec, 1);
827
828 twl4030->hsr_enabled = 1;
829 break;
830 case SND_SOC_DAPM_POST_PMD:
831 /* Do the ramp-down only if both headsetL/R is disabled */
832 if (!twl4030->hsl_enabled)
833 headset_ramp(w->codec, 0);
834
835 twl4030->hsr_enabled = 0;
aad749e5
PU		 836 break;
837 }
838 return 0;
839}
840
b0bd53a7
PU		 841/*
842 * Some of the gain controls in TWL (mostly those which are associated with
843 * the outputs) are implemented in an interesting way:
844 * 0x0 : Power down (mute)
845 * 0x1 : 6dB
846 * 0x2 : 0 dB
847 * 0x3 : -6 dB
848 * Inverting not going to help with these.
849 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
850 */
851#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
852 xinvert, tlv_array) \
853{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
854 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
855 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
856 .tlv.p = (tlv_array), \
857 .info = snd_soc_info_volsw, \
858 .get = snd_soc_get_volsw_twl4030, \
859 .put = snd_soc_put_volsw_twl4030, \
860 .private_value = (unsigned long)&(struct soc_mixer_control) \
861 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
862 .max = xmax, .invert = xinvert} }
863#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
864 xinvert, tlv_array) \
865{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
866 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
867 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
868 .tlv.p = (tlv_array), \
869 .info = snd_soc_info_volsw_2r, \
870 .get = snd_soc_get_volsw_r2_twl4030,\
871 .put = snd_soc_put_volsw_r2_twl4030, \
872 .private_value = (unsigned long)&(struct soc_mixer_control) \
873 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 874 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 875#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
876 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
877 xinvert, tlv_array)
878
879static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_value *ucontrol)
881{
882 struct soc_mixer_control *mc =
883 (struct soc_mixer_control *)kcontrol->private_value;
884 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
885 unsigned int reg = mc->reg;
886 unsigned int shift = mc->shift;
887 unsigned int rshift = mc->rshift;
888 int max = mc->max;
889 int mask = (1 << fls(max)) - 1;
890
891 ucontrol->value.integer.value[0] =
892 (snd_soc_read(codec, reg) >> shift) & mask;
893 if (ucontrol->value.integer.value[0])
894 ucontrol->value.integer.value[0] =
895 max + 1 - ucontrol->value.integer.value[0];
896
897 if (shift != rshift) {
898 ucontrol->value.integer.value[1] =
899 (snd_soc_read(codec, reg) >> rshift) & mask;
900 if (ucontrol->value.integer.value[1])
901 ucontrol->value.integer.value[1] =
902 max + 1 - ucontrol->value.integer.value[1];
903 }
904
905 return 0;
906}
907
908static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
909 struct snd_ctl_elem_value *ucontrol)
910{
911 struct soc_mixer_control *mc =
912 (struct soc_mixer_control *)kcontrol->private_value;
913 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
914 unsigned int reg = mc->reg;
915 unsigned int shift = mc->shift;
916 unsigned int rshift = mc->rshift;
917 int max = mc->max;
918 int mask = (1 << fls(max)) - 1;
919 unsigned short val, val2, val_mask;
920
921 val = (ucontrol->value.integer.value[0] & mask);
922
923 val_mask = mask << shift;
924 if (val)
925 val = max + 1 - val;
926 val = val << shift;
927 if (shift != rshift) {
928 val2 = (ucontrol->value.integer.value[1] & mask);
929 val_mask |= mask << rshift;
930 if (val2)
931 val2 = max + 1 - val2;
932 val |= val2 << rshift;
933 }
934 return snd_soc_update_bits(codec, reg, val_mask, val);
935}
936
937static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
938 struct snd_ctl_elem_value *ucontrol)
939{
940 struct soc_mixer_control *mc =
941 (struct soc_mixer_control *)kcontrol->private_value;
942 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
943 unsigned int reg = mc->reg;
944 unsigned int reg2 = mc->rreg;
945 unsigned int shift = mc->shift;
946 int max = mc->max;
947 int mask = (1<<fls(max))-1;
948
949 ucontrol->value.integer.value[0] =
950 (snd_soc_read(codec, reg) >> shift) & mask;
951 ucontrol->value.integer.value[1] =
952 (snd_soc_read(codec, reg2) >> shift) & mask;
953
954 if (ucontrol->value.integer.value[0])
955 ucontrol->value.integer.value[0] =
956 max + 1 - ucontrol->value.integer.value[0];
957 if (ucontrol->value.integer.value[1])
958 ucontrol->value.integer.value[1] =
959 max + 1 - ucontrol->value.integer.value[1];
960
961 return 0;
962}
963
964static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
965 struct snd_ctl_elem_value *ucontrol)
966{
967 struct soc_mixer_control *mc =
968 (struct soc_mixer_control *)kcontrol->private_value;
969 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
970 unsigned int reg = mc->reg;
971 unsigned int reg2 = mc->rreg;
972 unsigned int shift = mc->shift;
973 int max = mc->max;
974 int mask = (1 << fls(max)) - 1;
975 int err;
976 unsigned short val, val2, val_mask;
977
978 val_mask = mask << shift;
979 val = (ucontrol->value.integer.value[0] & mask);
980 val2 = (ucontrol->value.integer.value[1] & mask);
981
982 if (val)
983 val = max + 1 - val;
984 if (val2)
985 val2 = max + 1 - val2;
986
987 val = val << shift;
988 val2 = val2 << shift;
989
990 err = snd_soc_update_bits(codec, reg, val_mask, val);
991 if (err < 0)
992 return err;
993
994 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
995 return err;
996}
997
b74bd40f
LCM		 998/* Codec operation modes */
999static const char *twl4030_op_modes_texts[] = {
1000 "Option 2 (voice/audio)", "Option 1 (audio)"
1001};
1002
1003static const struct soc_enum twl4030_op_modes_enum =
1004 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1005 ARRAY_SIZE(twl4030_op_modes_texts),
1006 twl4030_op_modes_texts);
1007
423c238d 1008static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1009 struct snd_ctl_elem_value *ucontrol)
1010{
1011 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1012 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1013 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1014 unsigned short val;
1015 unsigned short mask, bitmask;
1016
1017 if (twl4030->configured) {
1018 printk(KERN_ERR "twl4030 operation mode cannot be "
1019 "changed on-the-fly\n");
1020 return -EBUSY;
1021 }
1022
1023 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1024 ;
1025 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1026 return -EINVAL;
1027
1028 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1029 mask = (bitmask - 1) << e->shift_l;
1030 if (e->shift_l != e->shift_r) {
1031 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1032 return -EINVAL;
1033 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1034 mask |= (bitmask - 1) << e->shift_r;
1035 }
1036
1037 return snd_soc_update_bits(codec, e->reg, mask, val);
1038}
1039
c10b82cf
PU		 1040/*
1041 * FGAIN volume control:
1042 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1043 */
d889a72c 1044static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1045
0d33ea0b
PU		 1046/*
1047 * CGAIN volume control:
1048 * 0 dB to 12 dB in 6 dB steps
1049 * value 2 and 3 means 12 dB
1050 */
d889a72c
PU		 1051static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1052
1a787e7a
JS		 1053/*
1054 * Voice Downlink GAIN volume control:
1055 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1056 */
1057static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1058
d889a72c
PU		 1059/*
1060 * Analog playback gain
1061 * -24 dB to 12 dB in 2 dB steps
1062 */
1063static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1064
4290239c
PU		 1065/*
1066 * Gain controls tied to outputs
1067 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1068 */
1069static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1070
18cc8d8d
JS		 1071/*
1072 * Gain control for earpiece amplifier
1073 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1074 */
1075static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1076
381a22b5
PU		 1077/*
1078 * Capture gain after the ADCs
1079 * from 0 dB to 31 dB in 1 dB steps
1080 */
1081static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1082
5920b453
GI		 1083/*
1084 * Gain control for input amplifiers
1085 * 0 dB to 30 dB in 6 dB steps
1086 */
1087static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1088
328d0a13
LCM		 1089/* AVADC clock priority */
1090static const char *twl4030_avadc_clk_priority_texts[] = {
1091 "Voice high priority", "HiFi high priority"
1092};
1093
1094static const struct soc_enum twl4030_avadc_clk_priority_enum =
1095 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1096 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1097 twl4030_avadc_clk_priority_texts);
1098
89492be8
PU		 1099static const char *twl4030_rampdelay_texts[] = {
1100 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1101 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1102 "3495/2581/1748 ms"
1103};
1104
1105static const struct soc_enum twl4030_rampdelay_enum =
1106 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1107 ARRAY_SIZE(twl4030_rampdelay_texts),
1108 twl4030_rampdelay_texts);
1109
376f7839
PU		 1110/* Vibra H-bridge direction mode */
1111static const char *twl4030_vibradirmode_texts[] = {
1112 "Vibra H-bridge direction", "Audio data MSB",
1113};
1114
1115static const struct soc_enum twl4030_vibradirmode_enum =
1116 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1117 ARRAY_SIZE(twl4030_vibradirmode_texts),
1118 twl4030_vibradirmode_texts);
1119
1120/* Vibra H-bridge direction */
1121static const char *twl4030_vibradir_texts[] = {
1122 "Positive polarity", "Negative polarity",
1123};
1124
1125static const struct soc_enum twl4030_vibradir_enum =
1126 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1127 ARRAY_SIZE(twl4030_vibradir_texts),
1128 twl4030_vibradir_texts);
1129
36aeff61
PU		 1130/* Digimic Left and right swapping */
1131static const char *twl4030_digimicswap_texts[] = {
1132 "Not swapped", "Swapped",
1133};
1134
1135static const struct soc_enum twl4030_digimicswap_enum =
1136 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1137 ARRAY_SIZE(twl4030_digimicswap_texts),
1138 twl4030_digimicswap_texts);
1139
cc17557e 1140static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1141 /* Codec operation mode control */
1142 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1143 snd_soc_get_enum_double,
1144 snd_soc_put_twl4030_opmode_enum_double),
1145
d889a72c
PU		 1146 /* Common playback gain controls */
1147 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1148 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1149 0, 0x3f, 0, digital_fine_tlv),
1150 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1151 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1152 0, 0x3f, 0, digital_fine_tlv),
1153
1154 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1155 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1156 6, 0x2, 0, digital_coarse_tlv),
1157 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1158 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1159 6, 0x2, 0, digital_coarse_tlv),
1160
1161 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1162 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1163 3, 0x12, 1, analog_tlv),
1164 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1165 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1166 3, 0x12, 1, analog_tlv),
44c55870
PU		 1167 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1168 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1169 1, 1, 0),
1170 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1171 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1172 1, 1, 0),
381a22b5 1173
1a787e7a
JS		 1174 /* Common voice downlink gain controls */
1175 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1176 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1177
1178 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1179 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1180
1181 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1182 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1183
4290239c
PU		 1184 /* Separate output gain controls */
1185 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1186 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1187 4, 3, 0, output_tvl),
1188
1189 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1190 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1191
1192 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1193 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1194 4, 3, 0, output_tvl),
1195
1196 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1197 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1198
381a22b5 1199 /* Common capture gain controls */
276c6222 1200 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1201 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1202 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1203 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1204 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1205 0, 0x1f, 0, digital_capture_tlv),
5920b453 1206
276c6222 1207 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1208 0, 3, 5, 0, input_gain_tlv),
89492be8 1209
328d0a13
LCM		 1210 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1211
89492be8 1212 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1213
1214 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1215 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1216
1217 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1218};
1219
cc17557e 1220static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1221 /* Left channel inputs */
1222 SND_SOC_DAPM_INPUT("MAINMIC"),
1223 SND_SOC_DAPM_INPUT("HSMIC"),
1224 SND_SOC_DAPM_INPUT("AUXL"),
1225 SND_SOC_DAPM_INPUT("CARKITMIC"),
1226 /* Right channel inputs */
1227 SND_SOC_DAPM_INPUT("SUBMIC"),
1228 SND_SOC_DAPM_INPUT("AUXR"),
1229 /* Digital microphones (Stereo) */
1230 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1231 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1232
1233 /* Outputs */
5e98a464 1234 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1235 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1236 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1237 SND_SOC_DAPM_OUTPUT("HSOL"),
1238 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1239 SND_SOC_DAPM_OUTPUT("CARKITL"),
1240 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1241 SND_SOC_DAPM_OUTPUT("HFL"),
1242 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1243 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1244
7b4c734e
PU		 1245 /* AIF and APLL clocks for running DAIs (including loopback) */
1246 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1247 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1248 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1249
53b5047d 1250 /* DACs */
b4852b79 1251 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1252 SND_SOC_NOPM, 0, 0),
b4852b79 1253 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1254 SND_SOC_NOPM, 0, 0),
b4852b79 1255 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1256 SND_SOC_NOPM, 0, 0),
b4852b79 1257 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1258 SND_SOC_NOPM, 0, 0),
1a787e7a 1259 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1260 SND_SOC_NOPM, 0, 0),
cc17557e 1261
7393958f 1262 /* Analog bypasses */
78e08e2f
PU		 1263 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1264 &twl4030_dapm_abypassr1_control),
1265 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1266 &twl4030_dapm_abypassl1_control),
1267 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1268 &twl4030_dapm_abypassr2_control),
1269 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1270 &twl4030_dapm_abypassl2_control),
1271 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1272 &twl4030_dapm_abypassv_control),
1273
1274 /* Master analog loopback switch */
1275 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1276 NULL, 0),
7393958f 1277
6bab83fd 1278 /* Digital bypasses */
78e08e2f
PU		 1279 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1280 &twl4030_dapm_dbypassl_control),
1281 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1282 &twl4030_dapm_dbypassr_control),
1283 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1284 &twl4030_dapm_dbypassv_control),
6bab83fd 1285
4005d39a
PU		 1286 /* Digital mixers, power control for the physical DACs */
1287 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1288 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1289 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1290 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1291 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1292 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1293 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1294 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1295 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1296 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1297
1298 /* Analog mixers, power control for the physical PGAs */
1299 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1300 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1301 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1302 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1303 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1304 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1305 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1306 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1307 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1308 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1309
7729cf74
PU		 1310 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1311 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1312
7b4c734e
PU		 1313 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1314 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1315
1a787e7a 1316 /* Output MIXER controls */
5e98a464 1317 /* Earpiece */
1a787e7a
JS		 1318 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1319 &twl4030_dapm_earpiece_controls[0],
1320 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1321 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1322 0, 0, NULL, 0, earpiecepga_event,
1323 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1324 /* PreDrivL/R */
1a787e7a
JS		 1325 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1326 &twl4030_dapm_predrivel_controls[0],
1327 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1328 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1329 0, 0, NULL, 0, predrivelpga_event,
1330 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1331 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1332 &twl4030_dapm_predriver_controls[0],
1333 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1334 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1335 0, 0, NULL, 0, predriverpga_event,
1336 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1337 /* HeadsetL/R */
6943c92e 1338 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1339 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1340 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1341 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1342 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1343 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1344 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1345 &twl4030_dapm_hsor_controls[0],
1346 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1347 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1348 0, 0, NULL, 0, headsetrpga_event,
1349 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1350 /* CarkitL/R */
1a787e7a
JS		 1351 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1352 &twl4030_dapm_carkitl_controls[0],
1353 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1354 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1355 0, 0, NULL, 0, carkitlpga_event,
1356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1357 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1358 &twl4030_dapm_carkitr_controls[0],
1359 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1360 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1361 0, 0, NULL, 0, carkitrpga_event,
1362 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1363
1364 /* Output MUX controls */
df339804 1365 /* HandsfreeL/R */
5a2e9a48
PU		 1366 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1367 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1368 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1369 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1370 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1371 0, 0, NULL, 0, handsfreelpga_event,
1372 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1373 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1374 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1375 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1376 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1377 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1378 0, 0, NULL, 0, handsfreerpga_event,
1379 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1380 /* Vibra */
86139a13
JV		 1381 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1382 &twl4030_dapm_vibra_control, vibramux_event,
1383 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1384 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1385 &twl4030_dapm_vibrapath_control),
5e98a464 1386
276c6222
PU		 1387 /* Introducing four virtual ADC, since TWL4030 have four channel for
1388 capture */
1389 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1390 SND_SOC_NOPM, 0, 0),
1391 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1392 SND_SOC_NOPM, 0, 0),
1393 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1394 SND_SOC_NOPM, 0, 0),
1395 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1396 SND_SOC_NOPM, 0, 0),
1397
1398 /* Analog/Digital mic path selection.
1399 TX1 Left/Right: either analog Left/Right or Digimic0
1400 TX2 Left/Right: either analog Left/Right or Digimic1 */
1401 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1402 &twl4030_dapm_micpathtx1_control, micpath_event,
1403 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1404 SND_SOC_DAPM_POST_REG),
1405 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1406 &twl4030_dapm_micpathtx2_control, micpath_event,
1407 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1408 SND_SOC_DAPM_POST_REG),
1409
97b8096d 1410 /* Analog input mixers for the capture amplifiers */
9028935d 1411 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1412 TWL4030_REG_ANAMICL, 4, 0,
1413 &twl4030_dapm_analoglmic_controls[0],
1414 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1415 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1416 TWL4030_REG_ANAMICR, 4, 0,
1417 &twl4030_dapm_analogrmic_controls[0],
1418 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1419
fb2a2f84
PU		 1420 SND_SOC_DAPM_PGA("ADC Physical Left",
1421 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1422 SND_SOC_DAPM_PGA("ADC Physical Right",
1423 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1424
1425 SND_SOC_DAPM_PGA("Digimic0 Enable",
1426 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1427 SND_SOC_DAPM_PGA("Digimic1 Enable",
1428 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1429
1430 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1431 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1432 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1433
cc17557e
SS		 1434};
1435
1436static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1437 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1438 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1439 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1440 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1441 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1442
7729cf74 1443 /* Supply for the digital part (APLL) */
7729cf74
PU		 1444 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1445
c42a59ea
PU		 1446 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1447 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1448 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1449 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1450
4005d39a
PU		 1451 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1452 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1453 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1454 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1455 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1456
5e98a464
PU		 1457 /* Internal playback routings */
1458 /* Earpiece */
4005d39a
PU		 1459 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1460 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1461 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1462 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1463 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1464 /* PreDrivL */
4005d39a
PU		 1465 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1466 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1467 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1468 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1469 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1470 /* PreDrivR */
4005d39a
PU		 1471 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1472 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1473 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1474 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1475 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1476 /* HeadsetL */
4005d39a
PU		 1477 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1478 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1479 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1480 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1481 /* HeadsetR */
4005d39a
PU		 1482 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1483 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1484 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1485 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1486 /* CarkitL */
4005d39a
PU		 1487 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1488 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1489 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1490 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1491 /* CarkitR */
4005d39a
PU		 1492 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1493 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1494 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1495 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1496 /* HandsfreeL */
4005d39a
PU		 1497 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1498 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1499 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1500 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1501 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1502 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1503 /* HandsfreeR */
4005d39a
PU		 1504 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1505 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1506 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1507 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1508 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1509 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1510 /* Vibra */
1511 {"Vibra Mux", "AudioL1", "DAC Left1"},
1512 {"Vibra Mux", "AudioR1", "DAC Right1"},
1513 {"Vibra Mux", "AudioL2", "DAC Left2"},
1514 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1515
cc17557e 1516 /* outputs */
7b4c734e
PU		 1517 /* Must be always connected (for AIF and APLL) */
1518 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1519 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1520 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1521 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1522 /* Must be always connected (for APLL) */
1523 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1524 /* Physical outputs */
9008adf9
PU		 1525 {"EARPIECE", NULL, "Earpiece PGA"},
1526 {"PREDRIVEL", NULL, "PredriveL PGA"},
1527 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1528 {"HSOL", NULL, "HeadsetL PGA"},
1529 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1530 {"CARKITL", NULL, "CarkitL PGA"},
1531 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1532 {"HFL", NULL, "HandsfreeL PGA"},
1533 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1534 {"Vibra Route", "Audio", "Vibra Mux"},
1535 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1536
276c6222 1537 /* Capture path */
7b4c734e
PU		 1538 /* Must be always connected (for AIF and APLL) */
1539 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1540 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1541 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1542 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1543 /* Physical inputs */
9028935d
PU		 1544 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1545 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1546 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1547 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1548
9028935d
PU		 1549 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1550 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1551
9028935d
PU		 1552 {"ADC Physical Left", NULL, "Analog Left"},
1553 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1554
1555 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1556 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1557
1558 /* TX1 Left capture path */
fb2a2f84 1559 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1560 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1561 /* TX1 Right capture path */
fb2a2f84 1562 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1563 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1564 /* TX2 Left capture path */
fb2a2f84 1565 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1566 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1567 /* TX2 Right capture path */
fb2a2f84 1568 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1569 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1570
1571 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1572 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1573 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1574 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1575
c42a59ea
PU		 1576 {"ADC Virtual Left1", NULL, "AIF Enable"},
1577 {"ADC Virtual Right1", NULL, "AIF Enable"},
1578 {"ADC Virtual Left2", NULL, "AIF Enable"},
1579 {"ADC Virtual Right2", NULL, "AIF Enable"},
1580
7393958f 1581 /* Analog bypass routes */
9028935d
PU		 1582 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1583 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1584 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1585 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1586 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1587
78e08e2f
PU		 1588 /* Supply for the Analog loopbacks */
1589 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1590 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1591 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1592 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1593 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1594
7393958f
PU		 1595 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1596 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1597 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1598 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1599 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1600
6bab83fd
PU		 1601 /* Digital bypass routes */
1602 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1603 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1604 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1605
4005d39a
PU		 1606 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1607 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1608 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1609
cc17557e
SS		 1610};
1611
1612static int twl4030_add_widgets(struct snd_soc_codec *codec)
1613{
1614 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1615 ARRAY_SIZE(twl4030_dapm_widgets));
1616
1617 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1618
cc17557e
SS		 1619 return 0;
1620}
1621
cc17557e
SS		 1622static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1623 enum snd_soc_bias_level level)
1624{
1625 switch (level) {
1626 case SND_SOC_BIAS_ON:
cc17557e
SS		 1627 break;
1628 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1629 break;
1630 case SND_SOC_BIAS_STANDBY:
78e08e2f 1631 if (codec->bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1632 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1633 break;
1634 case SND_SOC_BIAS_OFF:
cbd2db12 1635 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1636 break;
1637 }
1638 codec->bias_level = level;
1639
1640 return 0;
1641}
1642
6b87a91f
PU		 1643static void twl4030_constraints(struct twl4030_priv *twl4030,
1644 struct snd_pcm_substream *mst_substream)
1645{
1646 struct snd_pcm_substream *slv_substream;
1647
1648 /* Pick the stream, which need to be constrained */
1649 if (mst_substream == twl4030->master_substream)
1650 slv_substream = twl4030->slave_substream;
1651 else if (mst_substream == twl4030->slave_substream)
1652 slv_substream = twl4030->master_substream;
1653 else /* This should not happen.. */
1654 return;
1655
1656 /* Set the constraints according to the already configured stream */
1657 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1658 SNDRV_PCM_HW_PARAM_RATE,
1659 twl4030->rate,
1660 twl4030->rate);
1661
1662 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1663 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1664 twl4030->sample_bits,
1665 twl4030->sample_bits);
1666
1667 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1668 SNDRV_PCM_HW_PARAM_CHANNELS,
1669 twl4030->channels,
1670 twl4030->channels);
1671}
1672
8a1f936a
PU		 1673/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1674 * capture has to be enabled/disabled. */
1675static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1676 int enable)
1677{
1678 u8 reg, mask;
1679
1680 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1681
1682 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1683 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1684 else
1685 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1686
1687 if (enable)
1688 reg |= mask;
1689 else
1690 reg &= ~mask;
1691
1692 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1693}
1694
d6648da1
PU		 1695static int twl4030_startup(struct snd_pcm_substream *substream,
1696 struct snd_soc_dai *dai)
7220b9f4
PU		 1697{
1698 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1699 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1700 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1701 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1702
7220b9f4 1703 if (twl4030->master_substream) {
7220b9f4 1704 twl4030->slave_substream = substream;
6b87a91f
PU		 1705 /* The DAI has one configuration for playback and capture, so
1706 * if the DAI has been already configured then constrain this
1707 * substream to match it. */
1708 if (twl4030->configured)
1709 twl4030_constraints(twl4030, twl4030->master_substream);
1710 } else {
8a1f936a
PU		 1711 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1712 TWL4030_OPTION_1)) {
1713 /* In option2 4 channel is not supported, set the
1714 * constraint for the first stream for channels, the
1715 * second stream will 'inherit' this cosntraint */
1716 snd_pcm_hw_constraint_minmax(substream->runtime,
1717 SNDRV_PCM_HW_PARAM_CHANNELS,
1718 2, 2);
1719 }
7220b9f4 1720 twl4030->master_substream = substream;
6b87a91f 1721 }
7220b9f4
PU		 1722
1723 return 0;
1724}
1725
d6648da1
PU		 1726static void twl4030_shutdown(struct snd_pcm_substream *substream,
1727 struct snd_soc_dai *dai)
7220b9f4
PU		 1728{
1729 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1730 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1731 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1732 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1733
1734 if (twl4030->master_substream == substream)
1735 twl4030->master_substream = twl4030->slave_substream;
1736
1737 twl4030->slave_substream = NULL;
6b87a91f
PU		 1738
1739 /* If all streams are closed, or the remaining stream has not yet
1740 * been configured than set the DAI as not configured. */
1741 if (!twl4030->master_substream)
1742 twl4030->configured = 0;
1743 else if (!twl4030->master_substream->runtime->channels)
1744 twl4030->configured = 0;
8a1f936a
PU		 1745
1746 /* If the closing substream had 4 channel, do the necessary cleanup */
1747 if (substream->runtime->channels == 4)
1748 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1749}
1750
cc17557e 1751static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1752 struct snd_pcm_hw_params *params,
1753 struct snd_soc_dai *dai)
cc17557e
SS		 1754{
1755 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1756 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1757 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1758 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1759 u8 mode, old_mode, format, old_format;
1760
8a1f936a
PU		 1761 /* If the substream has 4 channel, do the necessary setup */
1762 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1763 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1764 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1765
1766 /* Safety check: are we in the correct operating mode and
1767 * the interface is in TDM mode? */
1768 if ((mode & TWL4030_OPTION_1) &&
1769 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1770 twl4030_tdm_enable(codec, substream->stream, 1);
1771 else
1772 return -EINVAL;
1773 }
1774
6b87a91f
PU		 1775 if (twl4030->configured)
1776 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1777 return 0;
1778
cc17557e
SS		 1779 /* bit rate */
1780 old_mode = twl4030_read_reg_cache(codec,
1781 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1782 mode = old_mode & ~TWL4030_APLL_RATE;
1783
1784 switch (params_rate(params)) {
1785 case 8000:
1786 mode |= TWL4030_APLL_RATE_8000;
1787 break;
1788 case 11025:
1789 mode |= TWL4030_APLL_RATE_11025;
1790 break;
1791 case 12000:
1792 mode |= TWL4030_APLL_RATE_12000;
1793 break;
1794 case 16000:
1795 mode |= TWL4030_APLL_RATE_16000;
1796 break;
1797 case 22050:
1798 mode |= TWL4030_APLL_RATE_22050;
1799 break;
1800 case 24000:
1801 mode |= TWL4030_APLL_RATE_24000;
1802 break;
1803 case 32000:
1804 mode |= TWL4030_APLL_RATE_32000;
1805 break;
1806 case 44100:
1807 mode |= TWL4030_APLL_RATE_44100;
1808 break;
1809 case 48000:
1810 mode |= TWL4030_APLL_RATE_48000;
1811 break;
103f211d
PU		 1812 case 96000:
1813 mode |= TWL4030_APLL_RATE_96000;
1814 break;
cc17557e
SS		 1815 default:
1816 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1817 params_rate(params));
1818 return -EINVAL;
1819 }
1820
1821 if (mode != old_mode) {
1822 /* change rate and set CODECPDZ */
7393958f 1823 twl4030_codec_enable(codec, 0);
cc17557e 1824 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1825 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1826 }
1827
1828 /* sample size */
1829 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1830 format = old_format;
1831 format &= ~TWL4030_DATA_WIDTH;
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 format |= TWL4030_DATA_WIDTH_16S_16W;
1835 break;
1836 case SNDRV_PCM_FORMAT_S24_LE:
1837 format |= TWL4030_DATA_WIDTH_32S_24W;
1838 break;
1839 default:
1840 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1841 params_format(params));
1842 return -EINVAL;
1843 }
1844
1845 if (format != old_format) {
1846
1847 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1848 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1849
1850 /* change format */
1851 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1852
1853 /* set CODECPDZ afterwards */
db04e2c5 1854 twl4030_codec_enable(codec, 1);
cc17557e 1855 }
6b87a91f
PU		 1856
1857 /* Store the important parameters for the DAI configuration and set
1858 * the DAI as configured */
1859 twl4030->configured = 1;
1860 twl4030->rate = params_rate(params);
1861 twl4030->sample_bits = hw_param_interval(params,
1862 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1863 twl4030->channels = params_channels(params);
1864
1865 /* If both playback and capture streams are open, and one of them
1866 * is setting the hw parameters right now (since we are here), set
1867 * constraints to the other stream to match the current one. */
1868 if (twl4030->slave_substream)
1869 twl4030_constraints(twl4030, substream);
1870
cc17557e
SS		 1871 return 0;
1872}
1873
1874static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1875 int clk_id, unsigned int freq, int dir)
1876{
1877 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1878 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1879
1880 switch (freq) {
1881 case 19200000:
cc17557e 1882 case 26000000:
cc17557e 1883 case 38400000:
cc17557e
SS		 1884 break;
1885 default:
68d01955 1886 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1887 return -EINVAL;
1888 }
1889
68d01955
PU		 1890 if ((freq / 1000) != twl4030->sysclk) {
1891 dev_err(codec->dev,
1892 "Mismatch in APLL mclk: %u (configured: %u)\n",
1893 freq, twl4030->sysclk * 1000);
1894 return -EINVAL;
1895 }
cc17557e
SS		 1896
1897 return 0;
1898}
1899
1900static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1901 unsigned int fmt)
1902{
1903 struct snd_soc_codec *codec = codec_dai->codec;
1904 u8 old_format, format;
1905
1906 /* get format */
1907 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1908 format = old_format;
1909
1910 /* set master/slave audio interface */
1911 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1912 case SND_SOC_DAIFMT_CBM_CFM:
1913 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1914 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1915 break;
1916 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1917 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1918 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1919 break;
1920 default:
1921 return -EINVAL;
1922 }
1923
1924 /* interface format */
1925 format &= ~TWL4030_AIF_FORMAT;
1926 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1927 case SND_SOC_DAIFMT_I2S:
1928 format |= TWL4030_AIF_FORMAT_CODEC;
1929 break;
8a1f936a
PU		 1930 case SND_SOC_DAIFMT_DSP_A:
1931 format |= TWL4030_AIF_FORMAT_TDM;
1932 break;
cc17557e
SS		 1933 default:
1934 return -EINVAL;
1935 }
1936
1937 if (format != old_format) {
1938
1939 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1940 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1941
1942 /* change format */
1943 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1944
1945 /* set CODECPDZ afterwards */
db04e2c5 1946 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1947 }
1948
1949 return 0;
1950}
1951
68140443
LCM		 1952static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1953{
1954 struct snd_soc_codec *codec = dai->codec;
1955 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1956
1957 if (tristate)
1958 reg |= TWL4030_AIF_TRI_EN;
1959 else
1960 reg &= ~TWL4030_AIF_TRI_EN;
1961
1962 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1963}
1964
b7a755a8
MLC		 1965/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1966 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1967static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1968 int enable)
1969{
1970 u8 reg, mask;
1971
1972 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1973
1974 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1975 mask = TWL4030_ARXL1_VRX_EN;
1976 else
1977 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1978
1979 if (enable)
1980 reg |= mask;
1981 else
1982 reg &= ~mask;
1983
1984 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1985}
1986
7154b3e8
JS		 1987static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1988 struct snd_soc_dai *dai)
1989{
1990 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1991 struct snd_soc_device *socdev = rtd->socdev;
1992 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1993 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1994 u8 mode;
1995
1996 /* If the system master clock is not 26MHz, the voice PCM interface is
1997 * not avilable.
1998 */
68d01955
PU		 1999 if (twl4030->sysclk != 26000) {
2000 dev_err(codec->dev, "The board is configured for %u Hz, while"
2001 "the Voice interface needs 26MHz APLL mclk\n",
2002 twl4030->sysclk * 1000);
7154b3e8
JS		 2003 return -EINVAL;
2004 }
2005
2006 /* If the codec mode is not option2, the voice PCM interface is not
2007 * avilable.
2008 */
2009 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2010 & TWL4030_OPT_MODE;
2011
2012 if (mode != TWL4030_OPTION_2) {
2013 printk(KERN_ERR "TWL4030 voice startup: "
2014 "the codec mode is not option2\n");
2015 return -EINVAL;
2016 }
2017
2018 return 0;
2019}
2020
b7a755a8
MLC		 2021static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2022 struct snd_soc_dai *dai)
2023{
2024 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2025 struct snd_soc_device *socdev = rtd->socdev;
2026 struct snd_soc_codec *codec = socdev->card->codec;
2027
2028 /* Enable voice digital filters */
2029 twl4030_voice_enable(codec, substream->stream, 0);
2030}
2031
7154b3e8
JS		 2032static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2033 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2034{
2035 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2036 struct snd_soc_device *socdev = rtd->socdev;
2037 struct snd_soc_codec *codec = socdev->card->codec;
2038 u8 old_mode, mode;
2039
b7a755a8
MLC		 2040 /* Enable voice digital filters */
2041 twl4030_voice_enable(codec, substream->stream, 1);
2042
7154b3e8
JS		 2043 /* bit rate */
2044 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2045 & ~(TWL4030_CODECPDZ);
2046 mode = old_mode;
2047
2048 switch (params_rate(params)) {
2049 case 8000:
2050 mode &= ~(TWL4030_SEL_16K);
2051 break;
2052 case 16000:
2053 mode |= TWL4030_SEL_16K;
2054 break;
2055 default:
2056 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2057 params_rate(params));
2058 return -EINVAL;
2059 }
2060
2061 if (mode != old_mode) {
2062 /* change rate and set CODECPDZ */
2063 twl4030_codec_enable(codec, 0);
2064 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2065 twl4030_codec_enable(codec, 1);
2066 }
2067
2068 return 0;
2069}
2070
2071static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2072 int clk_id, unsigned int freq, int dir)
2073{
2074 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2075 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2076
68d01955
PU		 2077 if (freq != 26000000) {
2078 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2079 "interface needs 26MHz APLL mclk\n", freq);
2080 return -EINVAL;
2081 }
2082 if ((freq / 1000) != twl4030->sysclk) {
2083 dev_err(codec->dev,
2084 "Mismatch in APLL mclk: %u (configured: %u)\n",
2085 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2086 return -EINVAL;
2087 }
7154b3e8
JS		 2088 return 0;
2089}
2090
2091static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2092 unsigned int fmt)
2093{
2094 struct snd_soc_codec *codec = codec_dai->codec;
2095 u8 old_format, format;
2096
2097 /* get format */
2098 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2099 format = old_format;
2100
2101 /* set master/slave audio interface */
2102 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2103 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2104 format &= ~(TWL4030_VIF_SLAVE_EN);
2105 break;
2106 case SND_SOC_DAIFMT_CBS_CFS:
2107 format |= TWL4030_VIF_SLAVE_EN;
2108 break;
2109 default:
2110 return -EINVAL;
2111 }
2112
2113 /* clock inversion */
2114 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2115 case SND_SOC_DAIFMT_IB_NF:
2116 format &= ~(TWL4030_VIF_FORMAT);
2117 break;
2118 case SND_SOC_DAIFMT_NB_IF:
2119 format |= TWL4030_VIF_FORMAT;
2120 break;
2121 default:
2122 return -EINVAL;
2123 }
2124
2125 if (format != old_format) {
2126 /* change format and set CODECPDZ */
2127 twl4030_codec_enable(codec, 0);
2128 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2129 twl4030_codec_enable(codec, 1);
2130 }
2131
2132 return 0;
2133}
2134
68140443
LCM		 2135static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2136{
2137 struct snd_soc_codec *codec = dai->codec;
2138 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2139
2140 if (tristate)
2141 reg |= TWL4030_VIF_TRI_EN;
2142 else
2143 reg &= ~TWL4030_VIF_TRI_EN;
2144
2145 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2146}
2147
bbba9444 2148#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2149#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2150
10d9e3d9 2151static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2152 .startup = twl4030_startup,
2153 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2154 .hw_params = twl4030_hw_params,
2155 .set_sysclk = twl4030_set_dai_sysclk,
2156 .set_fmt = twl4030_set_dai_fmt,
68140443 2157 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2158};
2159
7154b3e8
JS		 2160static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2161 .startup = twl4030_voice_startup,
b7a755a8 2162 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2163 .hw_params = twl4030_voice_hw_params,
2164 .set_sysclk = twl4030_voice_set_dai_sysclk,
2165 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2166 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2167};
2168
2169struct snd_soc_dai twl4030_dai[] = {
2170{
cc17557e
SS		 2171 .name = "twl4030",
2172 .playback = {
b4852b79 2173 .stream_name = "HiFi Playback",
cc17557e 2174 .channels_min = 2,
8a1f936a 2175 .channels_max = 4,
31ad0f31 2176 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2177 .formats = TWL4030_FORMATS,},
2178 .capture = {
2179 .stream_name = "Capture",
2180 .channels_min = 2,
8a1f936a 2181 .channels_max = 4,
cc17557e
SS		 2182 .rates = TWL4030_RATES,
2183 .formats = TWL4030_FORMATS,},
10d9e3d9 2184 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2185},
2186{
2187 .name = "twl4030 Voice",
2188 .playback = {
b4852b79 2189 .stream_name = "Voice Playback",
7154b3e8
JS		 2190 .channels_min = 1,
2191 .channels_max = 1,
2192 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2193 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2194 .capture = {
2195 .stream_name = "Capture",
2196 .channels_min = 1,
2197 .channels_max = 2,
2198 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2199 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2200 .ops = &twl4030_dai_voice_ops,
2201},
cc17557e
SS		 2202};
2203EXPORT_SYMBOL_GPL(twl4030_dai);
2204
7a1fecf5 2205static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2206{
2207 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2208 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2209
2210 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2211
2212 return 0;
2213}
2214
7a1fecf5 2215static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2216{
2217 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2218 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2219
2220 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2221 return 0;
2222}
2223
7a1fecf5 2224static struct snd_soc_codec *twl4030_codec;
cc17557e 2225
7a1fecf5 2226static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2227{
7a1fecf5 2228 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5 2229 struct snd_soc_codec *codec;
7a1fecf5 2230 int ret;
cc17557e 2231
7a1fecf5 2232 BUG_ON(!twl4030_codec);
cc17557e 2233
7a1fecf5 2234 codec = twl4030_codec;
7a1fecf5 2235 socdev->card->codec = codec;
cc17557e 2236
ee4ccac7
PU		 2237 twl4030_init_chip(pdev);
2238 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
9da28c7b 2239
cc17557e
SS		 2240 /* register pcms */
2241 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2242 if (ret < 0) {
7a1fecf5
PU		 2243 dev_err(&pdev->dev, "failed to create pcms\n");
2244 return ret;
cc17557e
SS		 2245 }
2246
3e8e1952
IM		 2247 snd_soc_add_controls(codec, twl4030_snd_controls,
2248 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2249 twl4030_add_widgets(codec);
2250
7a1fecf5 2251 return 0;
cc17557e
SS		 2252}
2253
7a1fecf5 2254static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2255{
2256 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2257 struct snd_soc_codec *codec = socdev->card->codec;
2258
2259 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2260 snd_soc_free_pcms(socdev);
2261 snd_soc_dapm_free(socdev);
7a1fecf5
PU		 2262
2263 return 0;
2264}
2265
2266static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2267{
2268 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2269 struct snd_soc_codec *codec;
7393958f 2270 struct twl4030_priv *twl4030;
7a1fecf5 2271 int ret;
cc17557e 2272
68d01955
PU		 2273 if (!pdata) {
2274 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2275 return -EINVAL;
2276 }
cc17557e 2277
7393958f
PU		 2278 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2279 if (twl4030 == NULL) {
7a1fecf5 2280 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2281 return -ENOMEM;
2282 }
2283
7a1fecf5 2284 codec = &twl4030->codec;
b2c812e2 2285 snd_soc_codec_set_drvdata(codec, twl4030);
7a1fecf5
PU		 2286 codec->dev = &pdev->dev;
2287 twl4030_dai[0].dev = &pdev->dev;
2288 twl4030_dai[1].dev = &pdev->dev;
2289
cc17557e
SS		 2290 mutex_init(&codec->mutex);
2291 INIT_LIST_HEAD(&codec->dapm_widgets);
2292 INIT_LIST_HEAD(&codec->dapm_paths);
2293
7a1fecf5
PU		 2294 codec->name = "twl4030";
2295 codec->owner = THIS_MODULE;
2296 codec->read = twl4030_read_reg_cache;
2297 codec->write = twl4030_write;
2298 codec->set_bias_level = twl4030_set_bias_level;
2299 codec->dai = twl4030_dai;
fd63df22 2300 codec->num_dai = ARRAY_SIZE(twl4030_dai);
7a1fecf5
PU		 2301 codec->reg_cache_size = sizeof(twl4030_reg);
2302 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2303 GFP_KERNEL);
2304 if (codec->reg_cache == NULL) {
2305 ret = -ENOMEM;
2306 goto error_cache;
2307 }
2308
2309 platform_set_drvdata(pdev, twl4030);
2310 twl4030_codec = codec;
2311
2312 /* Set the defaults, and power up the codec */
68d01955 2313 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
b3f5a272 2314 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2315
2316 ret = snd_soc_register_codec(codec);
2317 if (ret != 0) {
2318 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2319 goto error_codec;
2320 }
2321
2322 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2323 if (ret != 0) {
2324 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2325 snd_soc_unregister_codec(codec);
2326 goto error_codec;
2327 }
cc17557e
SS		 2328
2329 return 0;
7a1fecf5
PU		 2330
2331error_codec:
cbd2db12 2332 twl4030_codec_enable(codec, 0);
7a1fecf5
PU		 2333 kfree(codec->reg_cache);
2334error_cache:
2335 kfree(twl4030);
2336 return ret;
cc17557e
SS		 2337}
2338
7a1fecf5 2339static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2340{
7a1fecf5 2341 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2342
cb67286d
PU		 2343 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2344 snd_soc_unregister_codec(&twl4030->codec);
2345 kfree(twl4030->codec.reg_cache);
7a1fecf5 2346 kfree(twl4030);
cc17557e 2347
7a1fecf5 2348 twl4030_codec = NULL;
cc17557e
SS		 2349 return 0;
2350}
2351
7a1fecf5
PU		 2352MODULE_ALIAS("platform:twl4030_codec_audio");
2353
2354static struct platform_driver twl4030_codec_driver = {
2355 .probe = twl4030_codec_probe,
2356 .remove = __devexit_p(twl4030_codec_remove),
2357 .driver = {
2358 .name = "twl4030_codec_audio",
2359 .owner = THIS_MODULE,
2360 },
cc17557e 2361};
cc17557e 2362
24e07db8 2363static int __init twl4030_modinit(void)
64089b84 2364{
7a1fecf5 2365 return platform_driver_register(&twl4030_codec_driver);
64089b84 2366}
24e07db8 2367module_init(twl4030_modinit);
64089b84
MB		 2368
2369static void __exit twl4030_exit(void)
2370{
7a1fecf5 2371 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2372}
2373module_exit(twl4030_exit);
2374
7a1fecf5
PU		 2375struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2376 .probe = twl4030_soc_probe,
2377 .remove = twl4030_soc_remove,
2378 .suspend = twl4030_soc_suspend,
2379 .resume = twl4030_soc_resume,
2380};
2381EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2382
cc17557e
SS		 2383MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2384MODULE_AUTHOR("Steve Sakoman");
2385MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.181267 seconds and 5 git commands to generate.