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ASoC: TWL4030: Syncronize the reg_cache for ANAMICL after the offset cancelation
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
91432e97
IM		 128 if (reg >= TWL4030_CACHEREGNUM)
129 return -EIO;
130
cc17557e
SS		 131 return cache[reg];
132}
133
134/*
135 * write twl4030 register cache
136 */
137static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
138 u8 reg, u8 value)
139{
140 u8 *cache = codec->reg_cache;
141
142 if (reg >= TWL4030_CACHEREGNUM)
143 return;
144 cache[reg] = value;
145}
146
147/*
148 * write to the twl4030 register space
149 */
150static int twl4030_write(struct snd_soc_codec *codec,
151 unsigned int reg, unsigned int value)
152{
153 twl4030_write_reg_cache(codec, reg, value);
154 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
155}
156
157static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
158{
159 u8 mode;
160
161 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
162 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
163 mode & ~TWL4030_CODECPDZ);
164
165 /* REVISIT: this delay is present in TI sample drivers */
166 /* but there seems to be no TRM requirement for it */
167 udelay(10);
168}
169
170static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
171{
172 u8 mode;
173
174 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
175 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
176 mode | TWL4030_CODECPDZ);
177
178 /* REVISIT: this delay is present in TI sample drivers */
179 /* but there seems to be no TRM requirement for it */
180 udelay(10);
181}
182
183static void twl4030_init_chip(struct snd_soc_codec *codec)
184{
185 int i;
186
187 /* clear CODECPDZ prior to setting register defaults */
188 twl4030_clear_codecpdz(codec);
189
190 /* set all audio section registers to reasonable defaults */
191 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
192 twl4030_write(codec, i, twl4030_reg[i]);
193
194}
195
5e98a464
PU		 196/* Earpiece */
197static const char *twl4030_earpiece_texts[] =
2f423577 198 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 199
2f423577
PU		 200static const unsigned int twl4030_earpiece_values[] =
201 {0x0, 0x1, 0x2, 0x4};
202
cb1ace04 203static const struct soc_enum twl4030_earpiece_enum =
2f423577 204 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 205 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 206 twl4030_earpiece_texts,
207 twl4030_earpiece_values);
5e98a464
PU		 208
209static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 210SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 211
2a6f5c58
PU		 212/* PreDrive Left */
213static const char *twl4030_predrivel_texts[] =
2f423577
PU		 214 {"Off", "DACL1", "DACL2", "DACR2"};
215
216static const unsigned int twl4030_predrivel_values[] =
217 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 218
cb1ace04 219static const struct soc_enum twl4030_predrivel_enum =
2f423577 220 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 221 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 222 twl4030_predrivel_texts,
223 twl4030_predrivel_values);
2a6f5c58
PU		 224
225static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 226SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 227
228/* PreDrive Right */
229static const char *twl4030_predriver_texts[] =
2f423577 230 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 231
2f423577
PU		 232static const unsigned int twl4030_predriver_values[] =
233 {0x0, 0x1, 0x2, 0x4};
234
cb1ace04 235static const struct soc_enum twl4030_predriver_enum =
2f423577 236 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 237 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 238 twl4030_predriver_texts,
239 twl4030_predriver_values);
2a6f5c58
PU		 240
241static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 242SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 243
dfad21a2
PU		 244/* Headset Left */
245static const char *twl4030_hsol_texts[] =
246 {"Off", "DACL1", "DACL2"};
247
248static const struct soc_enum twl4030_hsol_enum =
249 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
250 ARRAY_SIZE(twl4030_hsol_texts),
251 twl4030_hsol_texts);
252
253static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
254SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
255
256/* Headset Right */
257static const char *twl4030_hsor_texts[] =
258 {"Off", "DACR1", "DACR2"};
259
260static const struct soc_enum twl4030_hsor_enum =
261 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
262 ARRAY_SIZE(twl4030_hsor_texts),
263 twl4030_hsor_texts);
264
265static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
266SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
267
5152d8c2
PU		 268/* Carkit Left */
269static const char *twl4030_carkitl_texts[] =
270 {"Off", "DACL1", "DACL2"};
271
272static const struct soc_enum twl4030_carkitl_enum =
273 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
274 ARRAY_SIZE(twl4030_carkitl_texts),
275 twl4030_carkitl_texts);
276
277static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
278SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
279
280/* Carkit Right */
281static const char *twl4030_carkitr_texts[] =
282 {"Off", "DACR1", "DACR2"};
283
284static const struct soc_enum twl4030_carkitr_enum =
285 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
286 ARRAY_SIZE(twl4030_carkitr_texts),
287 twl4030_carkitr_texts);
288
289static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
290SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
291
df339804
PU		 292/* Handsfree Left */
293static const char *twl4030_handsfreel_texts[] =
294 {"Voice", "DACL1", "DACL2", "DACR2"};
295
296static const struct soc_enum twl4030_handsfreel_enum =
297 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
298 ARRAY_SIZE(twl4030_handsfreel_texts),
299 twl4030_handsfreel_texts);
300
301static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
302SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
303
304/* Handsfree Right */
305static const char *twl4030_handsfreer_texts[] =
306 {"Voice", "DACR1", "DACR2", "DACL2"};
307
308static const struct soc_enum twl4030_handsfreer_enum =
309 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
310 ARRAY_SIZE(twl4030_handsfreer_texts),
311 twl4030_handsfreer_texts);
312
313static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
314SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
315
276c6222
PU		 316/* Left analog microphone selection */
317static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 318 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
319
320static const unsigned int twl4030_analoglmic_values[] =
321 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 322
cb1ace04 323static const struct soc_enum twl4030_analoglmic_enum =
2f423577 324 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 325 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 326 twl4030_analoglmic_texts,
327 twl4030_analoglmic_values);
276c6222
PU		 328
329static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 330SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 331
332/* Right analog microphone selection */
333static const char *twl4030_analogrmic_texts[] =
2f423577 334 {"Off", "Sub mic", "AUXR"};
276c6222 335
2f423577
PU		 336static const unsigned int twl4030_analogrmic_values[] =
337 {0x0, 0x1, 0x4};
338
cb1ace04 339static const struct soc_enum twl4030_analogrmic_enum =
2f423577 340 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 341 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 342 twl4030_analogrmic_texts,
343 twl4030_analogrmic_values);
276c6222
PU		 344
345static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 346SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 347
348/* TX1 L/R Analog/Digital microphone selection */
349static const char *twl4030_micpathtx1_texts[] =
350 {"Analog", "Digimic0"};
351
352static const struct soc_enum twl4030_micpathtx1_enum =
353 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
354 ARRAY_SIZE(twl4030_micpathtx1_texts),
355 twl4030_micpathtx1_texts);
356
357static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
358SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
359
360/* TX2 L/R Analog/Digital microphone selection */
361static const char *twl4030_micpathtx2_texts[] =
362 {"Analog", "Digimic1"};
363
364static const struct soc_enum twl4030_micpathtx2_enum =
365 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
366 ARRAY_SIZE(twl4030_micpathtx2_texts),
367 twl4030_micpathtx2_texts);
368
369static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
370SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
371
276c6222
PU		 372static int micpath_event(struct snd_soc_dapm_widget *w,
373 struct snd_kcontrol *kcontrol, int event)
374{
375 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
376 unsigned char adcmicsel, micbias_ctl;
377
378 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
379 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
380 /* Prepare the bits for the given TX path:
381 * shift_l == 0: TX1 microphone path
382 * shift_l == 2: TX2 microphone path */
383 if (e->shift_l) {
384 /* TX2 microphone path */
385 if (adcmicsel & TWL4030_TX2IN_SEL)
386 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
387 else
388 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
389 } else {
390 /* TX1 microphone path */
391 if (adcmicsel & TWL4030_TX1IN_SEL)
392 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
393 else
394 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
395 }
396
397 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
398
399 return 0;
400}
401
49d92c7d
SM		 402static int handsfree_event(struct snd_soc_dapm_widget *w,
403 struct snd_kcontrol *kcontrol, int event)
404{
405 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
406 unsigned char hs_ctl;
407
408 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
409
410 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
411 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
412 twl4030_write(w->codec, e->reg, hs_ctl);
413 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
414 twl4030_write(w->codec, e->reg, hs_ctl);
415 hs_ctl |= TWL4030_HF_CTL_HB_EN;
416 twl4030_write(w->codec, e->reg, hs_ctl);
417 } else {
418 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
419 | TWL4030_HF_CTL_HB_EN);
420 twl4030_write(w->codec, e->reg, hs_ctl);
421 }
422
423 return 0;
424}
425
b0bd53a7
PU		 426/*
427 * Some of the gain controls in TWL (mostly those which are associated with
428 * the outputs) are implemented in an interesting way:
429 * 0x0 : Power down (mute)
430 * 0x1 : 6dB
431 * 0x2 : 0 dB
432 * 0x3 : -6 dB
433 * Inverting not going to help with these.
434 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
435 */
436#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
437 xinvert, tlv_array) \
438{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
439 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
440 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
441 .tlv.p = (tlv_array), \
442 .info = snd_soc_info_volsw, \
443 .get = snd_soc_get_volsw_twl4030, \
444 .put = snd_soc_put_volsw_twl4030, \
445 .private_value = (unsigned long)&(struct soc_mixer_control) \
446 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
447 .max = xmax, .invert = xinvert} }
448#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
449 xinvert, tlv_array) \
450{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
451 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
452 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
453 .tlv.p = (tlv_array), \
454 .info = snd_soc_info_volsw_2r, \
455 .get = snd_soc_get_volsw_r2_twl4030,\
456 .put = snd_soc_put_volsw_r2_twl4030, \
457 .private_value = (unsigned long)&(struct soc_mixer_control) \
458 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 459 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 460#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
461 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
462 xinvert, tlv_array)
463
464static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
465 struct snd_ctl_elem_value *ucontrol)
466{
467 struct soc_mixer_control *mc =
468 (struct soc_mixer_control *)kcontrol->private_value;
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
470 unsigned int reg = mc->reg;
471 unsigned int shift = mc->shift;
472 unsigned int rshift = mc->rshift;
473 int max = mc->max;
474 int mask = (1 << fls(max)) - 1;
475
476 ucontrol->value.integer.value[0] =
477 (snd_soc_read(codec, reg) >> shift) & mask;
478 if (ucontrol->value.integer.value[0])
479 ucontrol->value.integer.value[0] =
480 max + 1 - ucontrol->value.integer.value[0];
481
482 if (shift != rshift) {
483 ucontrol->value.integer.value[1] =
484 (snd_soc_read(codec, reg) >> rshift) & mask;
485 if (ucontrol->value.integer.value[1])
486 ucontrol->value.integer.value[1] =
487 max + 1 - ucontrol->value.integer.value[1];
488 }
489
490 return 0;
491}
492
493static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495{
496 struct soc_mixer_control *mc =
497 (struct soc_mixer_control *)kcontrol->private_value;
498 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
499 unsigned int reg = mc->reg;
500 unsigned int shift = mc->shift;
501 unsigned int rshift = mc->rshift;
502 int max = mc->max;
503 int mask = (1 << fls(max)) - 1;
504 unsigned short val, val2, val_mask;
505
506 val = (ucontrol->value.integer.value[0] & mask);
507
508 val_mask = mask << shift;
509 if (val)
510 val = max + 1 - val;
511 val = val << shift;
512 if (shift != rshift) {
513 val2 = (ucontrol->value.integer.value[1] & mask);
514 val_mask |= mask << rshift;
515 if (val2)
516 val2 = max + 1 - val2;
517 val |= val2 << rshift;
518 }
519 return snd_soc_update_bits(codec, reg, val_mask, val);
520}
521
522static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524{
525 struct soc_mixer_control *mc =
526 (struct soc_mixer_control *)kcontrol->private_value;
527 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
528 unsigned int reg = mc->reg;
529 unsigned int reg2 = mc->rreg;
530 unsigned int shift = mc->shift;
531 int max = mc->max;
532 int mask = (1<<fls(max))-1;
533
534 ucontrol->value.integer.value[0] =
535 (snd_soc_read(codec, reg) >> shift) & mask;
536 ucontrol->value.integer.value[1] =
537 (snd_soc_read(codec, reg2) >> shift) & mask;
538
539 if (ucontrol->value.integer.value[0])
540 ucontrol->value.integer.value[0] =
541 max + 1 - ucontrol->value.integer.value[0];
542 if (ucontrol->value.integer.value[1])
543 ucontrol->value.integer.value[1] =
544 max + 1 - ucontrol->value.integer.value[1];
545
546 return 0;
547}
548
549static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
550 struct snd_ctl_elem_value *ucontrol)
551{
552 struct soc_mixer_control *mc =
553 (struct soc_mixer_control *)kcontrol->private_value;
554 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
555 unsigned int reg = mc->reg;
556 unsigned int reg2 = mc->rreg;
557 unsigned int shift = mc->shift;
558 int max = mc->max;
559 int mask = (1 << fls(max)) - 1;
560 int err;
561 unsigned short val, val2, val_mask;
562
563 val_mask = mask << shift;
564 val = (ucontrol->value.integer.value[0] & mask);
565 val2 = (ucontrol->value.integer.value[1] & mask);
566
567 if (val)
568 val = max + 1 - val;
569 if (val2)
570 val2 = max + 1 - val2;
571
572 val = val << shift;
573 val2 = val2 << shift;
574
575 err = snd_soc_update_bits(codec, reg, val_mask, val);
576 if (err < 0)
577 return err;
578
579 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
580 return err;
581}
582
c10b82cf
PU		 583/*
584 * FGAIN volume control:
585 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
586 */
d889a72c 587static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 588
0d33ea0b
PU		 589/*
590 * CGAIN volume control:
591 * 0 dB to 12 dB in 6 dB steps
592 * value 2 and 3 means 12 dB
593 */
d889a72c
PU		 594static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
595
596/*
597 * Analog playback gain
598 * -24 dB to 12 dB in 2 dB steps
599 */
600static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 601
4290239c
PU		 602/*
603 * Gain controls tied to outputs
604 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
605 */
606static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
607
381a22b5
PU		 608/*
609 * Capture gain after the ADCs
610 * from 0 dB to 31 dB in 1 dB steps
611 */
612static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
613
5920b453
GI		 614/*
615 * Gain control for input amplifiers
616 * 0 dB to 30 dB in 6 dB steps
617 */
618static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
619
cc17557e 620static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 621 /* Common playback gain controls */
622 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
623 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
624 0, 0x3f, 0, digital_fine_tlv),
625 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
626 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
627 0, 0x3f, 0, digital_fine_tlv),
628
629 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
630 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
631 6, 0x2, 0, digital_coarse_tlv),
632 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
633 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
634 6, 0x2, 0, digital_coarse_tlv),
635
636 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
637 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
638 3, 0x12, 1, analog_tlv),
639 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
640 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
641 3, 0x12, 1, analog_tlv),
44c55870
PU		 642 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
643 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
644 1, 1, 0),
645 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
646 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
647 1, 1, 0),
381a22b5 648
4290239c
PU		 649 /* Separate output gain controls */
650 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
651 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
652 4, 3, 0, output_tvl),
653
654 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
655 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
656
657 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
658 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
659 4, 3, 0, output_tvl),
660
661 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
662 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
663
381a22b5 664 /* Common capture gain controls */
276c6222 665 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 666 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
667 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 668 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
669 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
670 0, 0x1f, 0, digital_capture_tlv),
5920b453 671
276c6222 672 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 673 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 674};
675
cc17557e 676static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 677 /* Left channel inputs */
678 SND_SOC_DAPM_INPUT("MAINMIC"),
679 SND_SOC_DAPM_INPUT("HSMIC"),
680 SND_SOC_DAPM_INPUT("AUXL"),
681 SND_SOC_DAPM_INPUT("CARKITMIC"),
682 /* Right channel inputs */
683 SND_SOC_DAPM_INPUT("SUBMIC"),
684 SND_SOC_DAPM_INPUT("AUXR"),
685 /* Digital microphones (Stereo) */
686 SND_SOC_DAPM_INPUT("DIGIMIC0"),
687 SND_SOC_DAPM_INPUT("DIGIMIC1"),
688
689 /* Outputs */
cc17557e
SS		 690 SND_SOC_DAPM_OUTPUT("OUTL"),
691 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 692 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 693 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
694 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 695 SND_SOC_DAPM_OUTPUT("HSOL"),
696 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 697 SND_SOC_DAPM_OUTPUT("CARKITL"),
698 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 699 SND_SOC_DAPM_OUTPUT("HFL"),
700 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 701
53b5047d 702 /* DACs */
1e5fa31f 703 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
53b5047d 704 TWL4030_REG_AVDAC_CTL, 0, 0),
1e5fa31f 705 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
53b5047d 706 TWL4030_REG_AVDAC_CTL, 1, 0),
1e5fa31f 707 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
53b5047d 708 TWL4030_REG_AVDAC_CTL, 2, 0),
1e5fa31f 709 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
53b5047d 710 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 711
44c55870
PU		 712 /* Analog PGAs */
713 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
714 0, 0, NULL, 0),
715 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
716 0, 0, NULL, 0),
717 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
718 0, 0, NULL, 0),
719 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
720 0, 0, NULL, 0),
721
5e98a464
PU		 722 /* Output MUX controls */
723 /* Earpiece */
2f423577
PU		 724 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
725 &twl4030_dapm_earpiece_control),
2a6f5c58 726 /* PreDrivL/R */
2f423577
PU		 727 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
728 &twl4030_dapm_predrivel_control),
729 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
730 &twl4030_dapm_predriver_control),
dfad21a2
PU		 731 /* HeadsetL/R */
732 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
733 &twl4030_dapm_hsol_control),
734 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
735 &twl4030_dapm_hsor_control),
5152d8c2
PU		 736 /* CarkitL/R */
737 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
738 &twl4030_dapm_carkitl_control),
739 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
740 &twl4030_dapm_carkitr_control),
df339804 741 /* HandsfreeL/R */
49d92c7d
SM		 742 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
743 &twl4030_dapm_handsfreel_control, handsfree_event,
744 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
745 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
746 &twl4030_dapm_handsfreer_control, handsfree_event,
747 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 748
276c6222
PU		 749 /* Introducing four virtual ADC, since TWL4030 have four channel for
750 capture */
751 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
752 SND_SOC_NOPM, 0, 0),
753 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
754 SND_SOC_NOPM, 0, 0),
755 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
756 SND_SOC_NOPM, 0, 0),
757 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
758 SND_SOC_NOPM, 0, 0),
759
760 /* Analog/Digital mic path selection.
761 TX1 Left/Right: either analog Left/Right or Digimic0
762 TX2 Left/Right: either analog Left/Right or Digimic1 */
763 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
764 &twl4030_dapm_micpathtx1_control, micpath_event,
765 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
766 SND_SOC_DAPM_POST_REG),
767 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
768 &twl4030_dapm_micpathtx2_control, micpath_event,
769 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
770 SND_SOC_DAPM_POST_REG),
771
772 /* Analog input muxes with power switch for the physical ADCL/R */
2f423577
PU		 773 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
774 TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
775 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
776 TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
276c6222
PU		 777
778 SND_SOC_DAPM_PGA("Analog Left Amplifier",
779 TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
780 SND_SOC_DAPM_PGA("Analog Right Amplifier",
781 TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
782
783 SND_SOC_DAPM_PGA("Digimic0 Enable",
784 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
785 SND_SOC_DAPM_PGA("Digimic1 Enable",
786 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
787
788 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
789 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
790 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
cc17557e
SS		 791};
792
793static const struct snd_soc_dapm_route intercon[] = {
1e5fa31f
PU		 794 {"ARXL1_APGA", NULL, "DAC Left1"},
795 {"ARXR1_APGA", NULL, "DAC Right1"},
796 {"ARXL2_APGA", NULL, "DAC Left2"},
797 {"ARXR2_APGA", NULL, "DAC Right2"},
44c55870 798
5e98a464
PU		 799 /* Internal playback routings */
800 /* Earpiece */
801 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
802 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
803 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 804 /* PreDrivL */
805 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
806 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
807 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
808 /* PreDrivR */
809 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
810 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
811 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 812 /* HeadsetL */
813 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
814 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
815 /* HeadsetR */
816 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
817 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 818 /* CarkitL */
819 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
820 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
821 /* CarkitR */
822 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
823 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 824 /* HandsfreeL */
825 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
826 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
827 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
828 /* HandsfreeR */
829 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
830 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
831 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 832
cc17557e 833 /* outputs */
44c55870
PU		 834 {"OUTL", NULL, "ARXL2_APGA"},
835 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 836 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 837 {"PREDRIVEL", NULL, "PredriveL Mux"},
838 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 839 {"HSOL", NULL, "HeadsetL Mux"},
840 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 841 {"CARKITL", NULL, "CarkitL Mux"},
842 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 843 {"HFL", NULL, "HandsfreeL Mux"},
844 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 845
276c6222
PU		 846 /* Capture path */
847 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
848 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
849 {"Analog Left Capture Route", "AUXL", "AUXL"},
850 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
851
852 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
853 {"Analog Right Capture Route", "AUXR", "AUXR"},
854
855 {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
856 {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
857
858 {"Digimic0 Enable", NULL, "DIGIMIC0"},
859 {"Digimic1 Enable", NULL, "DIGIMIC1"},
860
861 /* TX1 Left capture path */
862 {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
863 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
864 /* TX1 Right capture path */
865 {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
866 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
867 /* TX2 Left capture path */
868 {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
869 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
870 /* TX2 Right capture path */
871 {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
872 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
873
874 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
875 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
876 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
877 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
878
cc17557e
SS		 879};
880
881static int twl4030_add_widgets(struct snd_soc_codec *codec)
882{
883 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
884 ARRAY_SIZE(twl4030_dapm_widgets));
885
886 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
887
888 snd_soc_dapm_new_widgets(codec);
889 return 0;
890}
891
892static void twl4030_power_up(struct snd_soc_codec *codec)
893{
ca4513fe 894 u8 anamicl, regmisc1, byte, popn;
cc17557e
SS		 895 int i = 0;
896
897 /* set CODECPDZ to turn on codec */
898 twl4030_set_codecpdz(codec);
899
900 /* initiate offset cancellation */
901 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
902 twl4030_write(codec, TWL4030_REG_ANAMICL,
903 anamicl | TWL4030_CNCL_OFFSET_START);
904
276c6222 905
cc17557e
SS		 906 /* wait for offset cancellation to complete */
907 do {
908 /* this takes a little while, so don't slam i2c */
909 udelay(2000);
910 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
911 TWL4030_REG_ANAMICL);
912 } while ((i++ < 100) &&
913 ((byte & TWL4030_CNCL_OFFSET_START) ==
914 TWL4030_CNCL_OFFSET_START));
915
3fc93030
PU		 916 /* Make sure that the reg_cache has the same value as the HW */
917 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
918
cc17557e
SS		 919 /* anti-pop when changing analog gain */
920 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
921 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
922 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
923
924 /* toggle CODECPDZ as per TRM */
925 twl4030_clear_codecpdz(codec);
926 twl4030_set_codecpdz(codec);
927
928 /* program anti-pop with bias ramp delay */
929 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
930 popn &= TWL4030_RAMP_DELAY;
931 popn |= TWL4030_RAMP_DELAY_645MS;
932 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
933 popn |= TWL4030_VMID_EN;
934 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
935
cc17557e
SS		 936 /* enable anti-pop ramp */
937 popn |= TWL4030_RAMP_EN;
938 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
939}
940
941static void twl4030_power_down(struct snd_soc_codec *codec)
942{
ca4513fe 943 u8 popn;
cc17557e
SS		 944
945 /* disable anti-pop ramp */
946 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
947 popn &= ~TWL4030_RAMP_EN;
948 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
949
cc17557e
SS		 950 /* disable bias out */
951 popn &= ~TWL4030_VMID_EN;
952 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
953
954 /* power down */
955 twl4030_clear_codecpdz(codec);
956}
957
958static int twl4030_set_bias_level(struct snd_soc_codec *codec,
959 enum snd_soc_bias_level level)
960{
961 switch (level) {
962 case SND_SOC_BIAS_ON:
963 twl4030_power_up(codec);
964 break;
965 case SND_SOC_BIAS_PREPARE:
966 /* TODO: develop a twl4030_prepare function */
967 break;
968 case SND_SOC_BIAS_STANDBY:
969 /* TODO: develop a twl4030_standby function */
970 twl4030_power_down(codec);
971 break;
972 case SND_SOC_BIAS_OFF:
973 twl4030_power_down(codec);
974 break;
975 }
976 codec->bias_level = level;
977
978 return 0;
979}
980
981static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 982 struct snd_pcm_hw_params *params,
983 struct snd_soc_dai *dai)
cc17557e
SS		 984{
985 struct snd_soc_pcm_runtime *rtd = substream->private_data;
986 struct snd_soc_device *socdev = rtd->socdev;
6627a653 987 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 988 u8 mode, old_mode, format, old_format;
989
990
991 /* bit rate */
992 old_mode = twl4030_read_reg_cache(codec,
993 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
994 mode = old_mode & ~TWL4030_APLL_RATE;
995
996 switch (params_rate(params)) {
997 case 8000:
998 mode |= TWL4030_APLL_RATE_8000;
999 break;
1000 case 11025:
1001 mode |= TWL4030_APLL_RATE_11025;
1002 break;
1003 case 12000:
1004 mode |= TWL4030_APLL_RATE_12000;
1005 break;
1006 case 16000:
1007 mode |= TWL4030_APLL_RATE_16000;
1008 break;
1009 case 22050:
1010 mode |= TWL4030_APLL_RATE_22050;
1011 break;
1012 case 24000:
1013 mode |= TWL4030_APLL_RATE_24000;
1014 break;
1015 case 32000:
1016 mode |= TWL4030_APLL_RATE_32000;
1017 break;
1018 case 44100:
1019 mode |= TWL4030_APLL_RATE_44100;
1020 break;
1021 case 48000:
1022 mode |= TWL4030_APLL_RATE_48000;
1023 break;
1024 default:
1025 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1026 params_rate(params));
1027 return -EINVAL;
1028 }
1029
1030 if (mode != old_mode) {
1031 /* change rate and set CODECPDZ */
1032 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1033 twl4030_set_codecpdz(codec);
1034 }
1035
1036 /* sample size */
1037 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1038 format = old_format;
1039 format &= ~TWL4030_DATA_WIDTH;
1040 switch (params_format(params)) {
1041 case SNDRV_PCM_FORMAT_S16_LE:
1042 format |= TWL4030_DATA_WIDTH_16S_16W;
1043 break;
1044 case SNDRV_PCM_FORMAT_S24_LE:
1045 format |= TWL4030_DATA_WIDTH_32S_24W;
1046 break;
1047 default:
1048 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1049 params_format(params));
1050 return -EINVAL;
1051 }
1052
1053 if (format != old_format) {
1054
1055 /* clear CODECPDZ before changing format (codec requirement) */
1056 twl4030_clear_codecpdz(codec);
1057
1058 /* change format */
1059 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1060
1061 /* set CODECPDZ afterwards */
1062 twl4030_set_codecpdz(codec);
1063 }
1064 return 0;
1065}
1066
1067static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1068 int clk_id, unsigned int freq, int dir)
1069{
1070 struct snd_soc_codec *codec = codec_dai->codec;
1071 u8 infreq;
1072
1073 switch (freq) {
1074 case 19200000:
1075 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1076 break;
1077 case 26000000:
1078 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1079 break;
1080 case 38400000:
1081 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1082 break;
1083 default:
1084 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1085 freq);
1086 return -EINVAL;
1087 }
1088
1089 infreq |= TWL4030_APLL_EN;
1090 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1091
1092 return 0;
1093}
1094
1095static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1096 unsigned int fmt)
1097{
1098 struct snd_soc_codec *codec = codec_dai->codec;
1099 u8 old_format, format;
1100
1101 /* get format */
1102 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1103 format = old_format;
1104
1105 /* set master/slave audio interface */
1106 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1107 case SND_SOC_DAIFMT_CBM_CFM:
1108 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1109 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1110 break;
1111 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1112 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1113 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1114 break;
1115 default:
1116 return -EINVAL;
1117 }
1118
1119 /* interface format */
1120 format &= ~TWL4030_AIF_FORMAT;
1121 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1122 case SND_SOC_DAIFMT_I2S:
1123 format |= TWL4030_AIF_FORMAT_CODEC;
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 if (format != old_format) {
1130
1131 /* clear CODECPDZ before changing format (codec requirement) */
1132 twl4030_clear_codecpdz(codec);
1133
1134 /* change format */
1135 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1136
1137 /* set CODECPDZ afterwards */
1138 twl4030_set_codecpdz(codec);
1139 }
1140
1141 return 0;
1142}
1143
bbba9444 1144#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1145#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1146
1147struct snd_soc_dai twl4030_dai = {
1148 .name = "twl4030",
1149 .playback = {
1150 .stream_name = "Playback",
1151 .channels_min = 2,
1152 .channels_max = 2,
1153 .rates = TWL4030_RATES,
1154 .formats = TWL4030_FORMATS,},
1155 .capture = {
1156 .stream_name = "Capture",
1157 .channels_min = 2,
1158 .channels_max = 2,
1159 .rates = TWL4030_RATES,
1160 .formats = TWL4030_FORMATS,},
1161 .ops = {
1162 .hw_params = twl4030_hw_params,
cc17557e
SS		 1163 .set_sysclk = twl4030_set_dai_sysclk,
1164 .set_fmt = twl4030_set_dai_fmt,
1165 }
1166};
1167EXPORT_SYMBOL_GPL(twl4030_dai);
1168
1169static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1170{
1171 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1172 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1173
1174 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1175
1176 return 0;
1177}
1178
1179static int twl4030_resume(struct platform_device *pdev)
1180{
1181 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1182 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1183
1184 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1185 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1186 return 0;
1187}
1188
1189/*
1190 * initialize the driver
1191 * register the mixer and dsp interfaces with the kernel
1192 */
1193
1194static int twl4030_init(struct snd_soc_device *socdev)
1195{
6627a653 1196 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1197 int ret = 0;
1198
1199 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1200
1201 codec->name = "twl4030";
1202 codec->owner = THIS_MODULE;
1203 codec->read = twl4030_read_reg_cache;
1204 codec->write = twl4030_write;
1205 codec->set_bias_level = twl4030_set_bias_level;
1206 codec->dai = &twl4030_dai;
1207 codec->num_dai = 1;
1208 codec->reg_cache_size = sizeof(twl4030_reg);
1209 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1210 GFP_KERNEL);
1211 if (codec->reg_cache == NULL)
1212 return -ENOMEM;
1213
1214 /* register pcms */
1215 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1216 if (ret < 0) {
1217 printk(KERN_ERR "twl4030: failed to create pcms\n");
1218 goto pcm_err;
1219 }
1220
1221 twl4030_init_chip(codec);
1222
1223 /* power on device */
1224 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1225
3e8e1952
IM		 1226 snd_soc_add_controls(codec, twl4030_snd_controls,
1227 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1228 twl4030_add_widgets(codec);
1229
968a6025 1230 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1231 if (ret < 0) {
1232 printk(KERN_ERR "twl4030: failed to register card\n");
1233 goto card_err;
1234 }
1235
1236 return ret;
1237
1238card_err:
1239 snd_soc_free_pcms(socdev);
1240 snd_soc_dapm_free(socdev);
1241pcm_err:
1242 kfree(codec->reg_cache);
1243 return ret;
1244}
1245
1246static struct snd_soc_device *twl4030_socdev;
1247
1248static int twl4030_probe(struct platform_device *pdev)
1249{
1250 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1251 struct snd_soc_codec *codec;
1252
1253 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1254 if (codec == NULL)
1255 return -ENOMEM;
1256
6627a653 1257 socdev->card->codec = codec;
cc17557e
SS		 1258 mutex_init(&codec->mutex);
1259 INIT_LIST_HEAD(&codec->dapm_widgets);
1260 INIT_LIST_HEAD(&codec->dapm_paths);
1261
1262 twl4030_socdev = socdev;
1263 twl4030_init(socdev);
1264
1265 return 0;
1266}
1267
1268static int twl4030_remove(struct platform_device *pdev)
1269{
1270 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1271 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1272
1273 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
c6d1662b
PU		 1274 snd_soc_free_pcms(socdev);
1275 snd_soc_dapm_free(socdev);
cc17557e
SS		 1276 kfree(codec);
1277
1278 return 0;
1279}
1280
1281struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1282 .probe = twl4030_probe,
1283 .remove = twl4030_remove,
1284 .suspend = twl4030_suspend,
1285 .resume = twl4030_resume,
1286};
1287EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1288
24e07db8 1289static int __init twl4030_modinit(void)
64089b84
MB		 1290{
1291 return snd_soc_register_dai(&twl4030_dai);
1292}
24e07db8 1293module_init(twl4030_modinit);
64089b84
MB		 1294
1295static void __exit twl4030_exit(void)
1296{
1297 snd_soc_unregister_dai(&twl4030_dai);
1298}
1299module_exit(twl4030_exit);
1300
cc17557e
SS		 1301MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1302MODULE_AUTHOR("Steve Sakoman");
1303MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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