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ASoC: Remove unused DAI format defines
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
7393958f
PU		 133};
134
cc17557e
SS		 135/*
136 * read twl4030 register cache
137 */
138static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140{
141 u8 *cache = codec->reg_cache;
142
91432e97
IM		 143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
cc17557e
SS		 146 return cache[reg];
147}
148
149/*
150 * write twl4030 register cache
151 */
152static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154{
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160}
161
162/*
163 * write to the twl4030 register space
164 */
165static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167{
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170}
171
db04e2c5 172static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 173{
7393958f 174 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 175 u8 mode;
176
7393958f
PU		 177 if (enable == twl4030->codec_powered)
178 return;
179
cc17557e 180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
cc17557e 185
db04e2c5 186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 187 twl4030->codec_powered = enable;
cc17557e
SS		 188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192}
193
194static void twl4030_init_chip(struct snd_soc_codec *codec)
195{
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 199 twl4030_codec_enable(codec, 0);
cc17557e
SS		 200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205}
206
7393958f
PU		 207static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208{
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
240 reg_val & (~TWL4030_PRECKL_GAIN),
241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272}
273
006f367e
PU		 274static void twl4030_power_up(struct snd_soc_codec *codec)
275{
7393958f 276 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
7393958f
PU		 280 if (twl4030->codec_powered)
281 return;
282
006f367e
PU		 283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312}
313
7393958f
PU		 314/*
315 * Unconditional power down
316 */
006f367e
PU		 317static void twl4030_power_down(struct snd_soc_codec *codec)
318{
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321}
322
5e98a464 323/* Earpiece */
1a787e7a
JS		 324static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
326 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
327 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
328 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
329};
5e98a464 330
2a6f5c58 331/* PreDrive Left */
1a787e7a
JS		 332static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
337};
2a6f5c58
PU		 338
339/* PreDrive Right */
1a787e7a
JS		 340static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
345};
2a6f5c58 346
dfad21a2 347/* Headset Left */
1a787e7a
JS		 348static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
352};
dfad21a2
PU		 353
354/* Headset Right */
1a787e7a
JS		 355static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
357 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
358 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
359};
dfad21a2 360
5152d8c2 361/* Carkit Left */
1a787e7a
JS		 362static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
366};
5152d8c2
PU		 367
368/* Carkit Right */
1a787e7a
JS		 369static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
370 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
371 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
372 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
373};
5152d8c2 374
df339804
PU		 375/* Handsfree Left */
376static const char *twl4030_handsfreel_texts[] =
1a787e7a 377 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 378
379static const struct soc_enum twl4030_handsfreel_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
381 ARRAY_SIZE(twl4030_handsfreel_texts),
382 twl4030_handsfreel_texts);
383
384static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
385SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
386
387/* Handsfree Right */
388static const char *twl4030_handsfreer_texts[] =
1a787e7a 389 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreer_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreer_texts),
394 twl4030_handsfreer_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
398
276c6222
PU		 399/* Left analog microphone selection */
400static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 401 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
402
403static const unsigned int twl4030_analoglmic_values[] =
404 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 405
cb1ace04 406static const struct soc_enum twl4030_analoglmic_enum =
2f423577 407 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 408 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 409 twl4030_analoglmic_texts,
410 twl4030_analoglmic_values);
276c6222
PU		 411
412static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 413SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 414
415/* Right analog microphone selection */
416static const char *twl4030_analogrmic_texts[] =
2f423577 417 {"Off", "Sub mic", "AUXR"};
276c6222 418
2f423577
PU		 419static const unsigned int twl4030_analogrmic_values[] =
420 {0x0, 0x1, 0x4};
421
cb1ace04 422static const struct soc_enum twl4030_analogrmic_enum =
2f423577 423 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 424 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 425 twl4030_analogrmic_texts,
426 twl4030_analogrmic_values);
276c6222
PU		 427
428static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 429SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 430
431/* TX1 L/R Analog/Digital microphone selection */
432static const char *twl4030_micpathtx1_texts[] =
433 {"Analog", "Digimic0"};
434
435static const struct soc_enum twl4030_micpathtx1_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
437 ARRAY_SIZE(twl4030_micpathtx1_texts),
438 twl4030_micpathtx1_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
441SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
442
443/* TX2 L/R Analog/Digital microphone selection */
444static const char *twl4030_micpathtx2_texts[] =
445 {"Analog", "Digimic1"};
446
447static const struct soc_enum twl4030_micpathtx2_enum =
448 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
449 ARRAY_SIZE(twl4030_micpathtx2_texts),
450 twl4030_micpathtx2_texts);
451
452static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
453SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
454
7393958f
PU		 455/* Analog bypass for AudioR1 */
456static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
457 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
458
459/* Analog bypass for AudioL1 */
460static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
461 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
462
463/* Analog bypass for AudioR2 */
464static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
465 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
466
467/* Analog bypass for AudioL2 */
468static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
469 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
470
6bab83fd
PU		 471/* Digital bypass gain, 0 mutes the bypass */
472static const unsigned int twl4030_dapm_dbypass_tlv[] = {
473 TLV_DB_RANGE_HEAD(2),
474 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
475 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
476};
477
478/* Digital bypass left (TX1L -> RX2L) */
479static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
480 SOC_DAPM_SINGLE_TLV("Volume",
481 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
482 twl4030_dapm_dbypass_tlv);
483
484/* Digital bypass right (TX1R -> RX2R) */
485static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
486 SOC_DAPM_SINGLE_TLV("Volume",
487 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
488 twl4030_dapm_dbypass_tlv);
489
276c6222
PU		 490static int micpath_event(struct snd_soc_dapm_widget *w,
491 struct snd_kcontrol *kcontrol, int event)
492{
493 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
494 unsigned char adcmicsel, micbias_ctl;
495
496 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
497 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
498 /* Prepare the bits for the given TX path:
499 * shift_l == 0: TX1 microphone path
500 * shift_l == 2: TX2 microphone path */
501 if (e->shift_l) {
502 /* TX2 microphone path */
503 if (adcmicsel & TWL4030_TX2IN_SEL)
504 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
505 else
506 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
507 } else {
508 /* TX1 microphone path */
509 if (adcmicsel & TWL4030_TX1IN_SEL)
510 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
511 else
512 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
513 }
514
515 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
516
517 return 0;
518}
519
49d92c7d
SM		 520static int handsfree_event(struct snd_soc_dapm_widget *w,
521 struct snd_kcontrol *kcontrol, int event)
522{
523 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
524 unsigned char hs_ctl;
525
526 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
527
528 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
529 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
530 twl4030_write(w->codec, e->reg, hs_ctl);
531 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
532 twl4030_write(w->codec, e->reg, hs_ctl);
533 hs_ctl |= TWL4030_HF_CTL_HB_EN;
534 twl4030_write(w->codec, e->reg, hs_ctl);
535 } else {
536 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
537 | TWL4030_HF_CTL_HB_EN);
538 twl4030_write(w->codec, e->reg, hs_ctl);
539 }
540
541 return 0;
542}
543
aad749e5
PU		 544static int headsetl_event(struct snd_soc_dapm_widget *w,
545 struct snd_kcontrol *kcontrol, int event)
546{
547 unsigned char hs_gain, hs_pop;
548
549 /* Save the current volume */
550 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
89492be8 551 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
aad749e5
PU		 552
553 switch (event) {
554 case SND_SOC_DAPM_POST_PMU:
555 /* Do the anti-pop/bias ramp enable according to the TRM */
aad749e5
PU		 556 hs_pop |= TWL4030_VMID_EN;
557 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
558 /* Is this needed? Can we just use whatever gain here? */
559 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
560 (hs_gain & (~0x0f)) | 0x0a);
561 hs_pop |= TWL4030_RAMP_EN;
562 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
563
564 /* Restore the original volume */
565 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
566 break;
567 case SND_SOC_DAPM_POST_PMD:
568 /* Do the anti-pop/bias ramp disable according to the TRM */
aad749e5
PU		 569 hs_pop &= ~TWL4030_RAMP_EN;
570 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
571 /* Bypass the reg_cache to mute the headset */
572 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
573 hs_gain & (~0x0f),
574 TWL4030_REG_HS_GAIN_SET);
575 hs_pop &= ~TWL4030_VMID_EN;
576 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
577 break;
578 }
579 return 0;
580}
581
7393958f
PU		 582static int bypass_event(struct snd_soc_dapm_widget *w,
583 struct snd_kcontrol *kcontrol, int event)
584{
585 struct soc_mixer_control *m =
586 (struct soc_mixer_control *)w->kcontrols->private_value;
587 struct twl4030_priv *twl4030 = w->codec->private_data;
588 unsigned char reg;
589
590 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 591
592 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
593 /* Analog bypass */
594 if (reg & (1 << m->shift))
595 twl4030->bypass_state |=
596 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
597 else
598 twl4030->bypass_state &=
599 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
600 } else {
601 /* Digital bypass */
602 if (reg & (0x7 << m->shift))
603 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
604 else
605 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
606 }
7393958f
PU		 607
608 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
609 if (twl4030->bypass_state)
610 twl4030_codec_mute(w->codec, 0);
611 else
612 twl4030_codec_mute(w->codec, 1);
613 }
614 return 0;
615}
616
b0bd53a7
PU		 617/*
618 * Some of the gain controls in TWL (mostly those which are associated with
619 * the outputs) are implemented in an interesting way:
620 * 0x0 : Power down (mute)
621 * 0x1 : 6dB
622 * 0x2 : 0 dB
623 * 0x3 : -6 dB
624 * Inverting not going to help with these.
625 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
626 */
627#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
628 xinvert, tlv_array) \
629{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
630 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
631 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
632 .tlv.p = (tlv_array), \
633 .info = snd_soc_info_volsw, \
634 .get = snd_soc_get_volsw_twl4030, \
635 .put = snd_soc_put_volsw_twl4030, \
636 .private_value = (unsigned long)&(struct soc_mixer_control) \
637 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
638 .max = xmax, .invert = xinvert} }
639#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
640 xinvert, tlv_array) \
641{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
642 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
643 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
644 .tlv.p = (tlv_array), \
645 .info = snd_soc_info_volsw_2r, \
646 .get = snd_soc_get_volsw_r2_twl4030,\
647 .put = snd_soc_put_volsw_r2_twl4030, \
648 .private_value = (unsigned long)&(struct soc_mixer_control) \
649 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 650 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 651#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
652 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
653 xinvert, tlv_array)
654
655static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_value *ucontrol)
657{
658 struct soc_mixer_control *mc =
659 (struct soc_mixer_control *)kcontrol->private_value;
660 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
661 unsigned int reg = mc->reg;
662 unsigned int shift = mc->shift;
663 unsigned int rshift = mc->rshift;
664 int max = mc->max;
665 int mask = (1 << fls(max)) - 1;
666
667 ucontrol->value.integer.value[0] =
668 (snd_soc_read(codec, reg) >> shift) & mask;
669 if (ucontrol->value.integer.value[0])
670 ucontrol->value.integer.value[0] =
671 max + 1 - ucontrol->value.integer.value[0];
672
673 if (shift != rshift) {
674 ucontrol->value.integer.value[1] =
675 (snd_soc_read(codec, reg) >> rshift) & mask;
676 if (ucontrol->value.integer.value[1])
677 ucontrol->value.integer.value[1] =
678 max + 1 - ucontrol->value.integer.value[1];
679 }
680
681 return 0;
682}
683
684static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
685 struct snd_ctl_elem_value *ucontrol)
686{
687 struct soc_mixer_control *mc =
688 (struct soc_mixer_control *)kcontrol->private_value;
689 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
690 unsigned int reg = mc->reg;
691 unsigned int shift = mc->shift;
692 unsigned int rshift = mc->rshift;
693 int max = mc->max;
694 int mask = (1 << fls(max)) - 1;
695 unsigned short val, val2, val_mask;
696
697 val = (ucontrol->value.integer.value[0] & mask);
698
699 val_mask = mask << shift;
700 if (val)
701 val = max + 1 - val;
702 val = val << shift;
703 if (shift != rshift) {
704 val2 = (ucontrol->value.integer.value[1] & mask);
705 val_mask |= mask << rshift;
706 if (val2)
707 val2 = max + 1 - val2;
708 val |= val2 << rshift;
709 }
710 return snd_soc_update_bits(codec, reg, val_mask, val);
711}
712
713static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
714 struct snd_ctl_elem_value *ucontrol)
715{
716 struct soc_mixer_control *mc =
717 (struct soc_mixer_control *)kcontrol->private_value;
718 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
719 unsigned int reg = mc->reg;
720 unsigned int reg2 = mc->rreg;
721 unsigned int shift = mc->shift;
722 int max = mc->max;
723 int mask = (1<<fls(max))-1;
724
725 ucontrol->value.integer.value[0] =
726 (snd_soc_read(codec, reg) >> shift) & mask;
727 ucontrol->value.integer.value[1] =
728 (snd_soc_read(codec, reg2) >> shift) & mask;
729
730 if (ucontrol->value.integer.value[0])
731 ucontrol->value.integer.value[0] =
732 max + 1 - ucontrol->value.integer.value[0];
733 if (ucontrol->value.integer.value[1])
734 ucontrol->value.integer.value[1] =
735 max + 1 - ucontrol->value.integer.value[1];
736
737 return 0;
738}
739
740static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
741 struct snd_ctl_elem_value *ucontrol)
742{
743 struct soc_mixer_control *mc =
744 (struct soc_mixer_control *)kcontrol->private_value;
745 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
746 unsigned int reg = mc->reg;
747 unsigned int reg2 = mc->rreg;
748 unsigned int shift = mc->shift;
749 int max = mc->max;
750 int mask = (1 << fls(max)) - 1;
751 int err;
752 unsigned short val, val2, val_mask;
753
754 val_mask = mask << shift;
755 val = (ucontrol->value.integer.value[0] & mask);
756 val2 = (ucontrol->value.integer.value[1] & mask);
757
758 if (val)
759 val = max + 1 - val;
760 if (val2)
761 val2 = max + 1 - val2;
762
763 val = val << shift;
764 val2 = val2 << shift;
765
766 err = snd_soc_update_bits(codec, reg, val_mask, val);
767 if (err < 0)
768 return err;
769
770 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
771 return err;
772}
773
c10b82cf
PU		 774/*
775 * FGAIN volume control:
776 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
777 */
d889a72c 778static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 779
0d33ea0b
PU		 780/*
781 * CGAIN volume control:
782 * 0 dB to 12 dB in 6 dB steps
783 * value 2 and 3 means 12 dB
784 */
d889a72c
PU		 785static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
786
1a787e7a
JS		 787/*
788 * Voice Downlink GAIN volume control:
789 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
790 */
791static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
792
d889a72c
PU		 793/*
794 * Analog playback gain
795 * -24 dB to 12 dB in 2 dB steps
796 */
797static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 798
4290239c
PU		 799/*
800 * Gain controls tied to outputs
801 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
802 */
803static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
804
18cc8d8d
JS		 805/*
806 * Gain control for earpiece amplifier
807 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
808 */
809static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
810
381a22b5
PU		 811/*
812 * Capture gain after the ADCs
813 * from 0 dB to 31 dB in 1 dB steps
814 */
815static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
816
5920b453
GI		 817/*
818 * Gain control for input amplifiers
819 * 0 dB to 30 dB in 6 dB steps
820 */
821static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
822
89492be8
PU		 823static const char *twl4030_rampdelay_texts[] = {
824 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
825 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
826 "3495/2581/1748 ms"
827};
828
829static const struct soc_enum twl4030_rampdelay_enum =
830 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
831 ARRAY_SIZE(twl4030_rampdelay_texts),
832 twl4030_rampdelay_texts);
833
cc17557e 834static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 835 /* Common playback gain controls */
836 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
837 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
838 0, 0x3f, 0, digital_fine_tlv),
839 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
840 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
841 0, 0x3f, 0, digital_fine_tlv),
842
843 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
844 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
845 6, 0x2, 0, digital_coarse_tlv),
846 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
847 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
848 6, 0x2, 0, digital_coarse_tlv),
849
850 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
851 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
852 3, 0x12, 1, analog_tlv),
853 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
854 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
855 3, 0x12, 1, analog_tlv),
44c55870
PU		 856 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
857 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
858 1, 1, 0),
859 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
860 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
861 1, 1, 0),
381a22b5 862
1a787e7a
JS		 863 /* Common voice downlink gain controls */
864 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
865 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
866
867 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
868 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
869
870 SOC_SINGLE("DAC Voice Analog Downlink Switch",
871 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
872
4290239c
PU		 873 /* Separate output gain controls */
874 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
875 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
876 4, 3, 0, output_tvl),
877
878 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
879 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
880
881 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
882 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
883 4, 3, 0, output_tvl),
884
885 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 886 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 887
381a22b5 888 /* Common capture gain controls */
276c6222 889 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 890 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
891 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 892 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
893 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
894 0, 0x1f, 0, digital_capture_tlv),
5920b453 895
276c6222 896 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 897 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 898
899 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
cc17557e
SS		 900};
901
cc17557e 902static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 903 /* Left channel inputs */
904 SND_SOC_DAPM_INPUT("MAINMIC"),
905 SND_SOC_DAPM_INPUT("HSMIC"),
906 SND_SOC_DAPM_INPUT("AUXL"),
907 SND_SOC_DAPM_INPUT("CARKITMIC"),
908 /* Right channel inputs */
909 SND_SOC_DAPM_INPUT("SUBMIC"),
910 SND_SOC_DAPM_INPUT("AUXR"),
911 /* Digital microphones (Stereo) */
912 SND_SOC_DAPM_INPUT("DIGIMIC0"),
913 SND_SOC_DAPM_INPUT("DIGIMIC1"),
914
915 /* Outputs */
cc17557e
SS		 916 SND_SOC_DAPM_OUTPUT("OUTL"),
917 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 918 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 919 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
920 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 921 SND_SOC_DAPM_OUTPUT("HSOL"),
922 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 923 SND_SOC_DAPM_OUTPUT("CARKITL"),
924 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 925 SND_SOC_DAPM_OUTPUT("HFL"),
926 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 927
53b5047d 928 /* DACs */
1e5fa31f 929 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 930 SND_SOC_NOPM, 0, 0),
1e5fa31f 931 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 932 SND_SOC_NOPM, 0, 0),
1e5fa31f 933 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 934 SND_SOC_NOPM, 0, 0),
1e5fa31f 935 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 936 SND_SOC_NOPM, 0, 0),
1a787e7a
JS		 937 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
938 TWL4030_REG_AVDAC_CTL, 4, 0),
cc17557e 939
44c55870
PU		 940 /* Analog PGAs */
941 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
942 0, 0, NULL, 0),
943 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
944 0, 0, NULL, 0),
945 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
946 0, 0, NULL, 0),
947 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
948 0, 0, NULL, 0),
1a787e7a
JS		 949 SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
950 0, 0, NULL, 0),
44c55870 951
7393958f
PU		 952 /* Analog bypasses */
953 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
954 &twl4030_dapm_abypassr1_control, bypass_event,
955 SND_SOC_DAPM_POST_REG),
956 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
957 &twl4030_dapm_abypassl1_control,
958 bypass_event, SND_SOC_DAPM_POST_REG),
959 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
960 &twl4030_dapm_abypassr2_control,
961 bypass_event, SND_SOC_DAPM_POST_REG),
962 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
963 &twl4030_dapm_abypassl2_control,
964 bypass_event, SND_SOC_DAPM_POST_REG),
965
6bab83fd
PU		 966 /* Digital bypasses */
967 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
968 &twl4030_dapm_dbypassl_control, bypass_event,
969 SND_SOC_DAPM_POST_REG),
970 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
971 &twl4030_dapm_dbypassr_control, bypass_event,
972 SND_SOC_DAPM_POST_REG),
973
7393958f
PU		 974 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
975 0, 0, NULL, 0),
976 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
977 1, 0, NULL, 0),
978 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
979 2, 0, NULL, 0),
980 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
981 3, 0, NULL, 0),
982
1a787e7a 983 /* Output MIXER controls */
5e98a464 984 /* Earpiece */
1a787e7a
JS		 985 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
986 &twl4030_dapm_earpiece_controls[0],
987 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 988 /* PreDrivL/R */
1a787e7a
JS		 989 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
990 &twl4030_dapm_predrivel_controls[0],
991 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
992 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
993 &twl4030_dapm_predriver_controls[0],
994 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 995 /* HeadsetL/R */
1a787e7a
JS		 996 SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
997 &twl4030_dapm_hsol_controls[0],
998 ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
999 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1000 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1001 &twl4030_dapm_hsor_controls[0],
1002 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
5152d8c2 1003 /* CarkitL/R */
1a787e7a
JS		 1004 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1005 &twl4030_dapm_carkitl_controls[0],
1006 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1007 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1008 &twl4030_dapm_carkitr_controls[0],
1009 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1010
1011 /* Output MUX controls */
df339804 1012 /* HandsfreeL/R */
49d92c7d
SM		 1013 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1014 &twl4030_dapm_handsfreel_control, handsfree_event,
1015 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1016 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1017 &twl4030_dapm_handsfreer_control, handsfree_event,
1018 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 1019
276c6222
PU		 1020 /* Introducing four virtual ADC, since TWL4030 have four channel for
1021 capture */
1022 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1023 SND_SOC_NOPM, 0, 0),
1024 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1025 SND_SOC_NOPM, 0, 0),
1026 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1027 SND_SOC_NOPM, 0, 0),
1028 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1029 SND_SOC_NOPM, 0, 0),
1030
1031 /* Analog/Digital mic path selection.
1032 TX1 Left/Right: either analog Left/Right or Digimic0
1033 TX2 Left/Right: either analog Left/Right or Digimic1 */
1034 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1035 &twl4030_dapm_micpathtx1_control, micpath_event,
1036 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1037 SND_SOC_DAPM_POST_REG),
1038 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1039 &twl4030_dapm_micpathtx2_control, micpath_event,
1040 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1041 SND_SOC_DAPM_POST_REG),
1042
fb2a2f84 1043 /* Analog input muxes with switch for the capture amplifiers */
2f423577 1044 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 1045 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1046 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1047 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1048
fb2a2f84
PU		 1049 SND_SOC_DAPM_PGA("ADC Physical Left",
1050 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1051 SND_SOC_DAPM_PGA("ADC Physical Right",
1052 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1053
1054 SND_SOC_DAPM_PGA("Digimic0 Enable",
1055 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1056 SND_SOC_DAPM_PGA("Digimic1 Enable",
1057 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1058
1059 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1060 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1061 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1062
cc17557e
SS		 1063};
1064
1065static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1066 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1067 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1068 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1069 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1070
1071 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1072 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1073 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1074 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
44c55870 1075
1a787e7a
JS		 1076 {"VDL_APGA", NULL, "DAC Voice"},
1077
5e98a464
PU		 1078 /* Internal playback routings */
1079 /* Earpiece */
1a787e7a
JS		 1080 {"Earpiece Mixer", "Voice", "VDL_APGA"},
1081 {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
1082 {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
1083 {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
2a6f5c58 1084 /* PreDrivL */
1a787e7a
JS		 1085 {"PredriveL Mixer", "Voice", "VDL_APGA"},
1086 {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
1087 {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
1088 {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
2a6f5c58 1089 /* PreDrivR */
1a787e7a
JS		 1090 {"PredriveR Mixer", "Voice", "VDL_APGA"},
1091 {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
1092 {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
1093 {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1094 /* HeadsetL */
1a787e7a
JS		 1095 {"HeadsetL Mixer", "Voice", "VDL_APGA"},
1096 {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
1097 {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1098 /* HeadsetR */
1a787e7a
JS		 1099 {"HeadsetR Mixer", "Voice", "VDL_APGA"},
1100 {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
1101 {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
5152d8c2 1102 /* CarkitL */
1a787e7a
JS		 1103 {"CarkitL Mixer", "Voice", "VDL_APGA"},
1104 {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
1105 {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
5152d8c2 1106 /* CarkitR */
1a787e7a
JS		 1107 {"CarkitR Mixer", "Voice", "VDL_APGA"},
1108 {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
1109 {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
df339804 1110 /* HandsfreeL */
1a787e7a
JS		 1111 {"HandsfreeL Mux", "Voice", "VDL_APGA"},
1112 {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
1113 {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
1114 {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
df339804 1115 /* HandsfreeR */
1a787e7a
JS		 1116 {"HandsfreeR Mux", "Voice", "VDL_APGA"},
1117 {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
1118 {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
1119 {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
5e98a464 1120
cc17557e 1121 /* outputs */
44c55870
PU		 1122 {"OUTL", NULL, "ARXL2_APGA"},
1123 {"OUTR", NULL, "ARXR2_APGA"},
1a787e7a
JS		 1124 {"EARPIECE", NULL, "Earpiece Mixer"},
1125 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1126 {"PREDRIVER", NULL, "PredriveR Mixer"},
1127 {"HSOL", NULL, "HeadsetL Mixer"},
1128 {"HSOR", NULL, "HeadsetR Mixer"},
1129 {"CARKITL", NULL, "CarkitL Mixer"},
1130 {"CARKITR", NULL, "CarkitR Mixer"},
df339804
PU		 1131 {"HFL", NULL, "HandsfreeL Mux"},
1132 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 1133
276c6222
PU		 1134 /* Capture path */
1135 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1136 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1137 {"Analog Left Capture Route", "AUXL", "AUXL"},
1138 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1139
1140 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1141 {"Analog Right Capture Route", "AUXR", "AUXR"},
1142
fb2a2f84
PU		 1143 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1144 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1145
1146 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1147 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1148
1149 /* TX1 Left capture path */
fb2a2f84 1150 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1151 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1152 /* TX1 Right capture path */
fb2a2f84 1153 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1154 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1155 /* TX2 Left capture path */
fb2a2f84 1156 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1157 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1158 /* TX2 Right capture path */
fb2a2f84 1159 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1160 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1161
1162 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1163 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1164 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1165 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1166
7393958f
PU		 1167 /* Analog bypass routes */
1168 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1169 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1170 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1171 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1172
1173 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1174 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1175 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1176 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1177
6bab83fd
PU		 1178 /* Digital bypass routes */
1179 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1180 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1181
1182 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1183 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
1184
cc17557e
SS		 1185};
1186
1187static int twl4030_add_widgets(struct snd_soc_codec *codec)
1188{
1189 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1190 ARRAY_SIZE(twl4030_dapm_widgets));
1191
1192 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1193
1194 snd_soc_dapm_new_widgets(codec);
1195 return 0;
1196}
1197
cc17557e
SS		 1198static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1199 enum snd_soc_bias_level level)
1200{
7393958f
PU		 1201 struct twl4030_priv *twl4030 = codec->private_data;
1202
cc17557e
SS		 1203 switch (level) {
1204 case SND_SOC_BIAS_ON:
7393958f 1205 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1206 break;
1207 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1208 twl4030_power_up(codec);
1209 if (twl4030->bypass_state)
1210 twl4030_codec_mute(codec, 0);
1211 else
1212 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1213 break;
1214 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1215 twl4030_power_up(codec);
1216 if (twl4030->bypass_state)
1217 twl4030_codec_mute(codec, 0);
1218 else
1219 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1220 break;
1221 case SND_SOC_BIAS_OFF:
1222 twl4030_power_down(codec);
1223 break;
1224 }
1225 codec->bias_level = level;
1226
1227 return 0;
1228}
1229
6b87a91f
PU		 1230static void twl4030_constraints(struct twl4030_priv *twl4030,
1231 struct snd_pcm_substream *mst_substream)
1232{
1233 struct snd_pcm_substream *slv_substream;
1234
1235 /* Pick the stream, which need to be constrained */
1236 if (mst_substream == twl4030->master_substream)
1237 slv_substream = twl4030->slave_substream;
1238 else if (mst_substream == twl4030->slave_substream)
1239 slv_substream = twl4030->master_substream;
1240 else /* This should not happen.. */
1241 return;
1242
1243 /* Set the constraints according to the already configured stream */
1244 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1245 SNDRV_PCM_HW_PARAM_RATE,
1246 twl4030->rate,
1247 twl4030->rate);
1248
1249 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1250 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1251 twl4030->sample_bits,
1252 twl4030->sample_bits);
1253
1254 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1255 SNDRV_PCM_HW_PARAM_CHANNELS,
1256 twl4030->channels,
1257 twl4030->channels);
1258}
1259
8a1f936a
PU		 1260/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1261 * capture has to be enabled/disabled. */
1262static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1263 int enable)
1264{
1265 u8 reg, mask;
1266
1267 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1268
1269 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1270 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1271 else
1272 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1273
1274 if (enable)
1275 reg |= mask;
1276 else
1277 reg &= ~mask;
1278
1279 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1280}
1281
d6648da1
PU		 1282static int twl4030_startup(struct snd_pcm_substream *substream,
1283 struct snd_soc_dai *dai)
7220b9f4
PU		 1284{
1285 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1286 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1287 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1288 struct twl4030_priv *twl4030 = codec->private_data;
1289
7220b9f4 1290 if (twl4030->master_substream) {
7220b9f4 1291 twl4030->slave_substream = substream;
6b87a91f
PU		 1292 /* The DAI has one configuration for playback and capture, so
1293 * if the DAI has been already configured then constrain this
1294 * substream to match it. */
1295 if (twl4030->configured)
1296 twl4030_constraints(twl4030, twl4030->master_substream);
1297 } else {
8a1f936a
PU		 1298 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1299 TWL4030_OPTION_1)) {
1300 /* In option2 4 channel is not supported, set the
1301 * constraint for the first stream for channels, the
1302 * second stream will 'inherit' this cosntraint */
1303 snd_pcm_hw_constraint_minmax(substream->runtime,
1304 SNDRV_PCM_HW_PARAM_CHANNELS,
1305 2, 2);
1306 }
7220b9f4 1307 twl4030->master_substream = substream;
6b87a91f 1308 }
7220b9f4
PU		 1309
1310 return 0;
1311}
1312
d6648da1
PU		 1313static void twl4030_shutdown(struct snd_pcm_substream *substream,
1314 struct snd_soc_dai *dai)
7220b9f4
PU		 1315{
1316 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1317 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1318 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1319 struct twl4030_priv *twl4030 = codec->private_data;
1320
1321 if (twl4030->master_substream == substream)
1322 twl4030->master_substream = twl4030->slave_substream;
1323
1324 twl4030->slave_substream = NULL;
6b87a91f
PU		 1325
1326 /* If all streams are closed, or the remaining stream has not yet
1327 * been configured than set the DAI as not configured. */
1328 if (!twl4030->master_substream)
1329 twl4030->configured = 0;
1330 else if (!twl4030->master_substream->runtime->channels)
1331 twl4030->configured = 0;
8a1f936a
PU		 1332
1333 /* If the closing substream had 4 channel, do the necessary cleanup */
1334 if (substream->runtime->channels == 4)
1335 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1336}
1337
cc17557e 1338static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1339 struct snd_pcm_hw_params *params,
1340 struct snd_soc_dai *dai)
cc17557e
SS		 1341{
1342 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1343 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1344 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1345 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1346 u8 mode, old_mode, format, old_format;
1347
8a1f936a
PU		 1348 /* If the substream has 4 channel, do the necessary setup */
1349 if (params_channels(params) == 4) {
1350 /* Safety check: are we in the correct operating mode? */
1351 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1352 TWL4030_OPTION_1))
1353 twl4030_tdm_enable(codec, substream->stream, 1);
1354 else
1355 return -EINVAL;
1356 }
1357
6b87a91f
PU		 1358 if (twl4030->configured)
1359 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1360 return 0;
1361
cc17557e
SS		 1362 /* bit rate */
1363 old_mode = twl4030_read_reg_cache(codec,
1364 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1365 mode = old_mode & ~TWL4030_APLL_RATE;
1366
1367 switch (params_rate(params)) {
1368 case 8000:
1369 mode |= TWL4030_APLL_RATE_8000;
1370 break;
1371 case 11025:
1372 mode |= TWL4030_APLL_RATE_11025;
1373 break;
1374 case 12000:
1375 mode |= TWL4030_APLL_RATE_12000;
1376 break;
1377 case 16000:
1378 mode |= TWL4030_APLL_RATE_16000;
1379 break;
1380 case 22050:
1381 mode |= TWL4030_APLL_RATE_22050;
1382 break;
1383 case 24000:
1384 mode |= TWL4030_APLL_RATE_24000;
1385 break;
1386 case 32000:
1387 mode |= TWL4030_APLL_RATE_32000;
1388 break;
1389 case 44100:
1390 mode |= TWL4030_APLL_RATE_44100;
1391 break;
1392 case 48000:
1393 mode |= TWL4030_APLL_RATE_48000;
1394 break;
103f211d
PU		 1395 case 96000:
1396 mode |= TWL4030_APLL_RATE_96000;
1397 break;
cc17557e
SS		 1398 default:
1399 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1400 params_rate(params));
1401 return -EINVAL;
1402 }
1403
1404 if (mode != old_mode) {
1405 /* change rate and set CODECPDZ */
7393958f 1406 twl4030_codec_enable(codec, 0);
cc17557e 1407 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1408 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1409 }
1410
1411 /* sample size */
1412 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1413 format = old_format;
1414 format &= ~TWL4030_DATA_WIDTH;
1415 switch (params_format(params)) {
1416 case SNDRV_PCM_FORMAT_S16_LE:
1417 format |= TWL4030_DATA_WIDTH_16S_16W;
1418 break;
1419 case SNDRV_PCM_FORMAT_S24_LE:
1420 format |= TWL4030_DATA_WIDTH_32S_24W;
1421 break;
1422 default:
1423 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1424 params_format(params));
1425 return -EINVAL;
1426 }
1427
1428 if (format != old_format) {
1429
1430 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1431 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1432
1433 /* change format */
1434 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1435
1436 /* set CODECPDZ afterwards */
db04e2c5 1437 twl4030_codec_enable(codec, 1);
cc17557e 1438 }
6b87a91f
PU		 1439
1440 /* Store the important parameters for the DAI configuration and set
1441 * the DAI as configured */
1442 twl4030->configured = 1;
1443 twl4030->rate = params_rate(params);
1444 twl4030->sample_bits = hw_param_interval(params,
1445 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1446 twl4030->channels = params_channels(params);
1447
1448 /* If both playback and capture streams are open, and one of them
1449 * is setting the hw parameters right now (since we are here), set
1450 * constraints to the other stream to match the current one. */
1451 if (twl4030->slave_substream)
1452 twl4030_constraints(twl4030, substream);
1453
cc17557e
SS		 1454 return 0;
1455}
1456
1457static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1458 int clk_id, unsigned int freq, int dir)
1459{
1460 struct snd_soc_codec *codec = codec_dai->codec;
1461 u8 infreq;
1462
1463 switch (freq) {
1464 case 19200000:
1465 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1466 break;
1467 case 26000000:
1468 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1469 break;
1470 case 38400000:
1471 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1472 break;
1473 default:
1474 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1475 freq);
1476 return -EINVAL;
1477 }
1478
1479 infreq |= TWL4030_APLL_EN;
1480 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1481
1482 return 0;
1483}
1484
1485static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1486 unsigned int fmt)
1487{
1488 struct snd_soc_codec *codec = codec_dai->codec;
1489 u8 old_format, format;
1490
1491 /* get format */
1492 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1493 format = old_format;
1494
1495 /* set master/slave audio interface */
1496 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1497 case SND_SOC_DAIFMT_CBM_CFM:
1498 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1499 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1500 break;
1501 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1502 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1503 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1504 break;
1505 default:
1506 return -EINVAL;
1507 }
1508
1509 /* interface format */
1510 format &= ~TWL4030_AIF_FORMAT;
1511 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1512 case SND_SOC_DAIFMT_I2S:
1513 format |= TWL4030_AIF_FORMAT_CODEC;
1514 break;
8a1f936a
PU		 1515 case SND_SOC_DAIFMT_DSP_A:
1516 format |= TWL4030_AIF_FORMAT_TDM;
1517 break;
cc17557e
SS		 1518 default:
1519 return -EINVAL;
1520 }
1521
1522 if (format != old_format) {
1523
1524 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1525 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1526
1527 /* change format */
1528 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1529
1530 /* set CODECPDZ afterwards */
db04e2c5 1531 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1532 }
1533
1534 return 0;
1535}
1536
7154b3e8
JS		 1537static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1538 struct snd_soc_dai *dai)
1539{
1540 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1541 struct snd_soc_device *socdev = rtd->socdev;
1542 struct snd_soc_codec *codec = socdev->card->codec;
1543 u8 infreq;
1544 u8 mode;
1545
1546 /* If the system master clock is not 26MHz, the voice PCM interface is
1547 * not avilable.
1548 */
1549 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1550 & TWL4030_APLL_INFREQ;
1551
1552 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1553 printk(KERN_ERR "TWL4030 voice startup: "
1554 "MCLK is not 26MHz, call set_sysclk() on init\n");
1555 return -EINVAL;
1556 }
1557
1558 /* If the codec mode is not option2, the voice PCM interface is not
1559 * avilable.
1560 */
1561 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1562 & TWL4030_OPT_MODE;
1563
1564 if (mode != TWL4030_OPTION_2) {
1565 printk(KERN_ERR "TWL4030 voice startup: "
1566 "the codec mode is not option2\n");
1567 return -EINVAL;
1568 }
1569
1570 return 0;
1571}
1572
1573static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1574 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1575{
1576 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1577 struct snd_soc_device *socdev = rtd->socdev;
1578 struct snd_soc_codec *codec = socdev->card->codec;
1579 u8 old_mode, mode;
1580
1581 /* bit rate */
1582 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1583 & ~(TWL4030_CODECPDZ);
1584 mode = old_mode;
1585
1586 switch (params_rate(params)) {
1587 case 8000:
1588 mode &= ~(TWL4030_SEL_16K);
1589 break;
1590 case 16000:
1591 mode |= TWL4030_SEL_16K;
1592 break;
1593 default:
1594 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1595 params_rate(params));
1596 return -EINVAL;
1597 }
1598
1599 if (mode != old_mode) {
1600 /* change rate and set CODECPDZ */
1601 twl4030_codec_enable(codec, 0);
1602 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1603 twl4030_codec_enable(codec, 1);
1604 }
1605
1606 return 0;
1607}
1608
1609static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1610 int clk_id, unsigned int freq, int dir)
1611{
1612 struct snd_soc_codec *codec = codec_dai->codec;
1613 u8 infreq;
1614
1615 switch (freq) {
1616 case 26000000:
1617 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1618 break;
1619 default:
1620 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1621 freq);
1622 return -EINVAL;
1623 }
1624
1625 infreq |= TWL4030_APLL_EN;
1626 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1627
1628 return 0;
1629}
1630
1631static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1632 unsigned int fmt)
1633{
1634 struct snd_soc_codec *codec = codec_dai->codec;
1635 u8 old_format, format;
1636
1637 /* get format */
1638 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1639 format = old_format;
1640
1641 /* set master/slave audio interface */
1642 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1643 case SND_SOC_DAIFMT_CBS_CFM:
1644 format &= ~(TWL4030_VIF_SLAVE_EN);
1645 break;
1646 case SND_SOC_DAIFMT_CBS_CFS:
1647 format |= TWL4030_VIF_SLAVE_EN;
1648 break;
1649 default:
1650 return -EINVAL;
1651 }
1652
1653 /* clock inversion */
1654 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1655 case SND_SOC_DAIFMT_IB_NF:
1656 format &= ~(TWL4030_VIF_FORMAT);
1657 break;
1658 case SND_SOC_DAIFMT_NB_IF:
1659 format |= TWL4030_VIF_FORMAT;
1660 break;
1661 default:
1662 return -EINVAL;
1663 }
1664
1665 if (format != old_format) {
1666 /* change format and set CODECPDZ */
1667 twl4030_codec_enable(codec, 0);
1668 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1669 twl4030_codec_enable(codec, 1);
1670 }
1671
1672 return 0;
1673}
1674
bbba9444 1675#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1676#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1677
10d9e3d9 1678static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1679 .startup = twl4030_startup,
1680 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1681 .hw_params = twl4030_hw_params,
1682 .set_sysclk = twl4030_set_dai_sysclk,
1683 .set_fmt = twl4030_set_dai_fmt,
1684};
1685
7154b3e8
JS		 1686static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1687 .startup = twl4030_voice_startup,
1688 .hw_params = twl4030_voice_hw_params,
1689 .set_sysclk = twl4030_voice_set_dai_sysclk,
1690 .set_fmt = twl4030_voice_set_dai_fmt,
1691};
1692
1693struct snd_soc_dai twl4030_dai[] = {
1694{
cc17557e
SS		 1695 .name = "twl4030",
1696 .playback = {
1697 .stream_name = "Playback",
1698 .channels_min = 2,
8a1f936a 1699 .channels_max = 4,
31ad0f31 1700 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1701 .formats = TWL4030_FORMATS,},
1702 .capture = {
1703 .stream_name = "Capture",
1704 .channels_min = 2,
8a1f936a 1705 .channels_max = 4,
cc17557e
SS		 1706 .rates = TWL4030_RATES,
1707 .formats = TWL4030_FORMATS,},
10d9e3d9 1708 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1709},
1710{
1711 .name = "twl4030 Voice",
1712 .playback = {
1713 .stream_name = "Playback",
1714 .channels_min = 1,
1715 .channels_max = 1,
1716 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1717 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1718 .capture = {
1719 .stream_name = "Capture",
1720 .channels_min = 1,
1721 .channels_max = 2,
1722 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1723 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1724 .ops = &twl4030_dai_voice_ops,
1725},
cc17557e
SS		 1726};
1727EXPORT_SYMBOL_GPL(twl4030_dai);
1728
1729static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1730{
1731 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1732 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1733
1734 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1735
1736 return 0;
1737}
1738
1739static int twl4030_resume(struct platform_device *pdev)
1740{
1741 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1742 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1743
1744 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1745 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1746 return 0;
1747}
1748
1749/*
1750 * initialize the driver
1751 * register the mixer and dsp interfaces with the kernel
1752 */
1753
1754static int twl4030_init(struct snd_soc_device *socdev)
1755{
6627a653 1756 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1757 int ret = 0;
1758
1759 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1760
1761 codec->name = "twl4030";
1762 codec->owner = THIS_MODULE;
1763 codec->read = twl4030_read_reg_cache;
1764 codec->write = twl4030_write;
1765 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 1766 codec->dai = twl4030_dai;
1767 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 1768 codec->reg_cache_size = sizeof(twl4030_reg);
1769 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1770 GFP_KERNEL);
1771 if (codec->reg_cache == NULL)
1772 return -ENOMEM;
1773
1774 /* register pcms */
1775 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1776 if (ret < 0) {
1777 printk(KERN_ERR "twl4030: failed to create pcms\n");
1778 goto pcm_err;
1779 }
1780
1781 twl4030_init_chip(codec);
1782
1783 /* power on device */
1784 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1785
3e8e1952
IM		 1786 snd_soc_add_controls(codec, twl4030_snd_controls,
1787 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1788 twl4030_add_widgets(codec);
1789
968a6025 1790 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1791 if (ret < 0) {
1792 printk(KERN_ERR "twl4030: failed to register card\n");
1793 goto card_err;
1794 }
1795
1796 return ret;
1797
1798card_err:
1799 snd_soc_free_pcms(socdev);
1800 snd_soc_dapm_free(socdev);
1801pcm_err:
1802 kfree(codec->reg_cache);
1803 return ret;
1804}
1805
1806static struct snd_soc_device *twl4030_socdev;
1807
1808static int twl4030_probe(struct platform_device *pdev)
1809{
1810 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1811 struct snd_soc_codec *codec;
7393958f 1812 struct twl4030_priv *twl4030;
cc17557e
SS		 1813
1814 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1815 if (codec == NULL)
1816 return -ENOMEM;
1817
7393958f
PU		 1818 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1819 if (twl4030 == NULL) {
1820 kfree(codec);
1821 return -ENOMEM;
1822 }
1823
1824 codec->private_data = twl4030;
6627a653 1825 socdev->card->codec = codec;
cc17557e
SS		 1826 mutex_init(&codec->mutex);
1827 INIT_LIST_HEAD(&codec->dapm_widgets);
1828 INIT_LIST_HEAD(&codec->dapm_paths);
1829
1830 twl4030_socdev = socdev;
1831 twl4030_init(socdev);
1832
1833 return 0;
1834}
1835
1836static int twl4030_remove(struct platform_device *pdev)
1837{
1838 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1839 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1840
1841 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1842 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1843 snd_soc_free_pcms(socdev);
1844 snd_soc_dapm_free(socdev);
7393958f 1845 kfree(codec->private_data);
cc17557e
SS		 1846 kfree(codec);
1847
1848 return 0;
1849}
1850
1851struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1852 .probe = twl4030_probe,
1853 .remove = twl4030_remove,
1854 .suspend = twl4030_suspend,
1855 .resume = twl4030_resume,
1856};
1857EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1858
24e07db8 1859static int __init twl4030_modinit(void)
64089b84 1860{
7154b3e8 1861 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 1862}
24e07db8 1863module_init(twl4030_modinit);
64089b84
MB		 1864
1865static void __exit twl4030_exit(void)
1866{
7154b3e8 1867 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 1868}
1869module_exit(twl4030_exit);
1870
cc17557e
SS		 1871MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1872MODULE_AUTHOR("Steve Sakoman");
1873MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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