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ALSA: Allow passing platform_data for pxa2xx-ac97
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
d08664fd 148 u8 *cache = codec->reg_cache;
cc17557e 149
91432e97
IM		 150 if (reg >= TWL4030_CACHEREGNUM)
151 return -EIO;
152
cc17557e
SS		 153 return cache[reg];
154}
155
156/*
157 * write twl4030 register cache
158 */
159static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
160 u8 reg, u8 value)
161{
162 u8 *cache = codec->reg_cache;
163
164 if (reg >= TWL4030_CACHEREGNUM)
165 return;
166 cache[reg] = value;
167}
168
169/*
170 * write to the twl4030 register space
171 */
172static int twl4030_write(struct snd_soc_codec *codec,
173 unsigned int reg, unsigned int value)
174{
175 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
cc17557e
SS		 181}
182
db04e2c5 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 184{
7393958f 185 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 186 u8 mode;
187
7393958f
PU		 188 if (enable == twl4030->codec_powered)
189 return;
190
cc17557e 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 192 if (enable)
193 mode |= TWL4030_CODECPDZ;
194 else
195 mode &= ~TWL4030_CODECPDZ;
cc17557e 196
db04e2c5 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 198 twl4030->codec_powered = enable;
cc17557e
SS		 199
200 /* REVISIT: this delay is present in TI sample drivers */
201 /* but there seems to be no TRM requirement for it */
202 udelay(10);
203}
204
205static void twl4030_init_chip(struct snd_soc_codec *codec)
206{
16a30fbb 207 u8 *cache = codec->reg_cache;
cc17557e
SS		 208 int i;
209
210 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 211 twl4030_codec_enable(codec, 0);
cc17557e
SS		 212
213 /* set all audio section registers to reasonable defaults */
214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 215 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 216
217}
218
7393958f
PU		 219static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
220{
221 struct twl4030_priv *twl4030 = codec->private_data;
222 u8 reg_val;
223
224 if (mute == twl4030->codec_muted)
225 return;
226
227 if (mute) {
7393958f
PU		 228 /* Disable PLL */
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
230 reg_val &= ~TWL4030_APLL_EN;
231 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
232 } else {
7393958f
PU		 233 /* Enable PLL */
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
235 reg_val |= TWL4030_APLL_EN;
236 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
237 }
238
239 twl4030->codec_muted = mute;
240}
241
006f367e
PU		 242static void twl4030_power_up(struct snd_soc_codec *codec)
243{
7393958f 244 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 245 u8 anamicl, regmisc1, byte;
246 int i = 0;
247
7393958f
PU		 248 if (twl4030->codec_powered)
249 return;
250
006f367e
PU		 251 /* set CODECPDZ to turn on codec */
252 twl4030_codec_enable(codec, 1);
253
254 /* initiate offset cancellation */
255 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
256 twl4030_write(codec, TWL4030_REG_ANAMICL,
257 anamicl | TWL4030_CNCL_OFFSET_START);
258
259 /* wait for offset cancellation to complete */
260 do {
261 /* this takes a little while, so don't slam i2c */
262 udelay(2000);
263 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
264 TWL4030_REG_ANAMICL);
265 } while ((i++ < 100) &&
266 ((byte & TWL4030_CNCL_OFFSET_START) ==
267 TWL4030_CNCL_OFFSET_START));
268
269 /* Make sure that the reg_cache has the same value as the HW */
270 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
271
272 /* anti-pop when changing analog gain */
273 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
274 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
275 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
276
277 /* toggle CODECPDZ as per TRM */
278 twl4030_codec_enable(codec, 0);
279 twl4030_codec_enable(codec, 1);
280}
281
7393958f
PU		 282/*
283 * Unconditional power down
284 */
006f367e
PU		 285static void twl4030_power_down(struct snd_soc_codec *codec)
286{
287 /* power down */
288 twl4030_codec_enable(codec, 0);
289}
290
5e98a464 291/* Earpiece */
1a787e7a
JS		 292static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
293 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
294 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
295 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
296 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
297};
5e98a464 298
2a6f5c58 299/* PreDrive Left */
1a787e7a
JS		 300static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
301 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
302 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
303 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
304 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
305};
2a6f5c58
PU		 306
307/* PreDrive Right */
1a787e7a
JS		 308static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
309 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
310 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
311 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
312 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
313};
2a6f5c58 314
dfad21a2 315/* Headset Left */
1a787e7a
JS		 316static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
317 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
318 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
319 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
320};
dfad21a2
PU		 321
322/* Headset Right */
1a787e7a
JS		 323static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
324 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
325 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
326 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
327};
dfad21a2 328
5152d8c2 329/* Carkit Left */
1a787e7a
JS		 330static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
331 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
332 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
333 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
334};
5152d8c2
PU		 335
336/* Carkit Right */
1a787e7a
JS		 337static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
338 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
340 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
341};
5152d8c2 342
df339804
PU		 343/* Handsfree Left */
344static const char *twl4030_handsfreel_texts[] =
1a787e7a 345 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 346
347static const struct soc_enum twl4030_handsfreel_enum =
348 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
349 ARRAY_SIZE(twl4030_handsfreel_texts),
350 twl4030_handsfreel_texts);
351
352static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
353SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
354
0f89bdca
PU		 355/* Handsfree Left virtual mute */
356static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
357 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
358
df339804
PU		 359/* Handsfree Right */
360static const char *twl4030_handsfreer_texts[] =
1a787e7a 361 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 362
363static const struct soc_enum twl4030_handsfreer_enum =
364 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
365 ARRAY_SIZE(twl4030_handsfreer_texts),
366 twl4030_handsfreer_texts);
367
368static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
369SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
370
0f89bdca
PU		 371/* Handsfree Right virtual mute */
372static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
373 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
374
376f7839
PU		 375/* Vibra */
376/* Vibra audio path selection */
377static const char *twl4030_vibra_texts[] =
378 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
379
380static const struct soc_enum twl4030_vibra_enum =
381 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
382 ARRAY_SIZE(twl4030_vibra_texts),
383 twl4030_vibra_texts);
384
385static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
386SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
387
388/* Vibra path selection: local vibrator (PWM) or audio driven */
389static const char *twl4030_vibrapath_texts[] =
390 {"Local vibrator", "Audio"};
391
392static const struct soc_enum twl4030_vibrapath_enum =
393 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
394 ARRAY_SIZE(twl4030_vibrapath_texts),
395 twl4030_vibrapath_texts);
396
397static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
398SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
399
276c6222 400/* Left analog microphone selection */
97b8096d
JS		 401static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
402 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
403 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
404 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
405 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
406};
276c6222
PU		 407
408/* Right analog microphone selection */
97b8096d
JS		 409static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
410 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 411 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 412};
276c6222
PU		 413
414/* TX1 L/R Analog/Digital microphone selection */
415static const char *twl4030_micpathtx1_texts[] =
416 {"Analog", "Digimic0"};
417
418static const struct soc_enum twl4030_micpathtx1_enum =
419 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
420 ARRAY_SIZE(twl4030_micpathtx1_texts),
421 twl4030_micpathtx1_texts);
422
423static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
424SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
425
426/* TX2 L/R Analog/Digital microphone selection */
427static const char *twl4030_micpathtx2_texts[] =
428 {"Analog", "Digimic1"};
429
430static const struct soc_enum twl4030_micpathtx2_enum =
431 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
432 ARRAY_SIZE(twl4030_micpathtx2_texts),
433 twl4030_micpathtx2_texts);
434
435static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
436SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
437
7393958f
PU		 438/* Analog bypass for AudioR1 */
439static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
440 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
441
442/* Analog bypass for AudioL1 */
443static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
444 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
445
446/* Analog bypass for AudioR2 */
447static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
448 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
449
450/* Analog bypass for AudioL2 */
451static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
452 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
453
fcd274a3
LCM		 454/* Analog bypass for Voice */
455static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
456 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
457
6bab83fd
PU		 458/* Digital bypass gain, 0 mutes the bypass */
459static const unsigned int twl4030_dapm_dbypass_tlv[] = {
460 TLV_DB_RANGE_HEAD(2),
461 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
462 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
463};
464
465/* Digital bypass left (TX1L -> RX2L) */
466static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
467 SOC_DAPM_SINGLE_TLV("Volume",
468 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
469 twl4030_dapm_dbypass_tlv);
470
471/* Digital bypass right (TX1R -> RX2R) */
472static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
473 SOC_DAPM_SINGLE_TLV("Volume",
474 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
475 twl4030_dapm_dbypass_tlv);
476
ee8f6894
LCM		 477/*
478 * Voice Sidetone GAIN volume control:
479 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
480 */
481static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
482
483/* Digital bypass voice: sidetone (VUL -> VDL)*/
484static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
485 SOC_DAPM_SINGLE_TLV("Volume",
486 TWL4030_REG_VSTPGA, 0, 0x29, 0,
487 twl4030_dapm_dbypassv_tlv);
488
276c6222
PU		 489static int micpath_event(struct snd_soc_dapm_widget *w,
490 struct snd_kcontrol *kcontrol, int event)
491{
492 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
493 unsigned char adcmicsel, micbias_ctl;
494
495 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
496 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
497 /* Prepare the bits for the given TX path:
498 * shift_l == 0: TX1 microphone path
499 * shift_l == 2: TX2 microphone path */
500 if (e->shift_l) {
501 /* TX2 microphone path */
502 if (adcmicsel & TWL4030_TX2IN_SEL)
503 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
504 else
505 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
506 } else {
507 /* TX1 microphone path */
508 if (adcmicsel & TWL4030_TX1IN_SEL)
509 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
510 else
511 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
512 }
513
514 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
515
516 return 0;
517}
518
9008adf9
PU		 519/*
520 * Output PGA builder:
521 * Handle the muting and unmuting of the given output (turning off the
522 * amplifier associated with the output pin)
523 * On mute bypass the reg_cache and mute the volume
524 * On unmute: restore the register content
525 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
526 */
527#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
528static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
529 struct snd_kcontrol *kcontrol, int event) \
530{ \
531 u8 reg_val; \
532 \
533 switch (event) { \
534 case SND_SOC_DAPM_POST_PMU: \
535 twl4030_write(w->codec, reg, \
536 twl4030_read_reg_cache(w->codec, reg)); \
537 break; \
538 case SND_SOC_DAPM_POST_PMD: \
539 reg_val = twl4030_read_reg_cache(w->codec, reg); \
540 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
541 reg_val & (~mask), \
542 reg); \
543 break; \
544 } \
545 return 0; \
546}
547
548TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
549TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
550TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
551TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
552TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
553
5a2e9a48 554static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 555{
49d92c7d
SM		 556 unsigned char hs_ctl;
557
5a2e9a48 558 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 559
5a2e9a48
PU		 560 if (ramp) {
561 /* HF ramp-up */
562 hs_ctl |= TWL4030_HF_CTL_REF_EN;
563 twl4030_write(codec, reg, hs_ctl);
564 udelay(10);
49d92c7d 565 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 566 twl4030_write(codec, reg, hs_ctl);
567 udelay(40);
49d92c7d 568 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 569 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 570 twl4030_write(codec, reg, hs_ctl);
49d92c7d 571 } else {
5a2e9a48
PU		 572 /* HF ramp-down */
573 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
574 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
575 twl4030_write(codec, reg, hs_ctl);
576 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
577 twl4030_write(codec, reg, hs_ctl);
578 udelay(40);
579 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
580 twl4030_write(codec, reg, hs_ctl);
49d92c7d 581 }
5a2e9a48 582}
49d92c7d 583
5a2e9a48
PU		 584static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
585 struct snd_kcontrol *kcontrol, int event)
586{
587 switch (event) {
588 case SND_SOC_DAPM_POST_PMU:
589 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
590 break;
591 case SND_SOC_DAPM_POST_PMD:
592 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
593 break;
594 }
595 return 0;
596}
597
598static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
599 struct snd_kcontrol *kcontrol, int event)
600{
601 switch (event) {
602 case SND_SOC_DAPM_POST_PMU:
603 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
604 break;
605 case SND_SOC_DAPM_POST_PMD:
606 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
607 break;
608 }
49d92c7d
SM		 609 return 0;
610}
611
6943c92e 612static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 613{
4e49ffd1
CVJ		 614 struct snd_soc_device *socdev = codec->socdev;
615 struct twl4030_setup_data *setup = socdev->codec_data;
616
aad749e5 617 unsigned char hs_gain, hs_pop;
6943c92e
PU		 618 struct twl4030_priv *twl4030 = codec->private_data;
619 /* Base values for ramp delay calculation: 2^19 - 2^26 */
620 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
621 8388608, 16777216, 33554432, 67108864};
aad749e5 622
6943c92e
PU		 623 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
624 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 625
4e49ffd1
CVJ		 626 /* Enable external mute control, this dramatically reduces
627 * the pop-noise */
628 if (setup && setup->hs_extmute) {
629 if (setup->set_hs_extmute) {
630 setup->set_hs_extmute(1);
631 } else {
632 hs_pop |= TWL4030_EXTMUTE;
633 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
634 }
635 }
636
6943c92e
PU		 637 if (ramp) {
638 /* Headset ramp-up according to the TRM */
aad749e5 639 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 640 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
641 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 642 hs_pop |= TWL4030_RAMP_EN;
6943c92e 643 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 644 /* Wait ramp delay time + 1, so the VMID can settle */
645 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
646 twl4030->sysclk) + 1);
6943c92e
PU		 647 } else {
648 /* Headset ramp-down _not_ according to
649 * the TRM, but in a way that it is working */
aad749e5 650 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 651 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
652 /* Wait ramp delay time + 1, so the VMID can settle */
653 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
654 twl4030->sysclk) + 1);
aad749e5
PU		 655 /* Bypass the reg_cache to mute the headset */
656 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
657 hs_gain & (~0x0f),
658 TWL4030_REG_HS_GAIN_SET);
6943c92e 659
aad749e5 660 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 661 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
662 }
4e49ffd1
CVJ		 663
664 /* Disable external mute */
665 if (setup && setup->hs_extmute) {
666 if (setup->set_hs_extmute) {
667 setup->set_hs_extmute(0);
668 } else {
669 hs_pop &= ~TWL4030_EXTMUTE;
670 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
671 }
672 }
6943c92e
PU		 673}
674
675static int headsetlpga_event(struct snd_soc_dapm_widget *w,
676 struct snd_kcontrol *kcontrol, int event)
677{
678 struct twl4030_priv *twl4030 = w->codec->private_data;
679
680 switch (event) {
681 case SND_SOC_DAPM_POST_PMU:
682 /* Do the ramp-up only once */
683 if (!twl4030->hsr_enabled)
684 headset_ramp(w->codec, 1);
685
686 twl4030->hsl_enabled = 1;
687 break;
688 case SND_SOC_DAPM_POST_PMD:
689 /* Do the ramp-down only if both headsetL/R is disabled */
690 if (!twl4030->hsr_enabled)
691 headset_ramp(w->codec, 0);
692
693 twl4030->hsl_enabled = 0;
694 break;
695 }
696 return 0;
697}
698
699static int headsetrpga_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
701{
702 struct twl4030_priv *twl4030 = w->codec->private_data;
703
704 switch (event) {
705 case SND_SOC_DAPM_POST_PMU:
706 /* Do the ramp-up only once */
707 if (!twl4030->hsl_enabled)
708 headset_ramp(w->codec, 1);
709
710 twl4030->hsr_enabled = 1;
711 break;
712 case SND_SOC_DAPM_POST_PMD:
713 /* Do the ramp-down only if both headsetL/R is disabled */
714 if (!twl4030->hsl_enabled)
715 headset_ramp(w->codec, 0);
716
717 twl4030->hsr_enabled = 0;
aad749e5
PU		 718 break;
719 }
720 return 0;
721}
722
7393958f
PU		 723static int bypass_event(struct snd_soc_dapm_widget *w,
724 struct snd_kcontrol *kcontrol, int event)
725{
726 struct soc_mixer_control *m =
727 (struct soc_mixer_control *)w->kcontrols->private_value;
728 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 729 unsigned char reg, misc;
7393958f
PU		 730
731 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd 732
30808ca7
LCM		 733 /*
734 * bypass_state[0:3] - analog HiFi bypass
735 * bypass_state[4] - analog voice bypass
736 * bypass_state[5] - digital voice bypass
737 * bypass_state[6:7] - digital HiFi bypass
738 */
739 if (m->reg == TWL4030_REG_VSTPGA) {
740 /* Voice digital bypass */
741 if (reg)
742 twl4030->bypass_state |= (1 << 5);
743 else
744 twl4030->bypass_state &= ~(1 << 5);
745 } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
6bab83fd
PU		 746 /* Analog bypass */
747 if (reg & (1 << m->shift))
748 twl4030->bypass_state |=
749 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
750 else
751 twl4030->bypass_state &=
752 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 753 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
754 /* Analog voice bypass */
755 if (reg & (1 << m->shift))
756 twl4030->bypass_state |= (1 << 4);
757 else
758 twl4030->bypass_state &= ~(1 << 4);
6bab83fd
PU		 759 } else {
760 /* Digital bypass */
761 if (reg & (0x7 << m->shift))
ee8f6894 762 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 763 else
ee8f6894 764 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 765 }
7393958f 766
fcd274a3
LCM		 767 /* Enable master analog loopback mode if any analog switch is enabled*/
768 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
769 if (twl4030->bypass_state & 0x1F)
770 misc |= TWL4030_FMLOOP_EN;
771 else
772 misc &= ~TWL4030_FMLOOP_EN;
773 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
774
7393958f
PU		 775 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
776 if (twl4030->bypass_state)
777 twl4030_codec_mute(w->codec, 0);
778 else
779 twl4030_codec_mute(w->codec, 1);
780 }
781 return 0;
782}
783
b0bd53a7
PU		 784/*
785 * Some of the gain controls in TWL (mostly those which are associated with
786 * the outputs) are implemented in an interesting way:
787 * 0x0 : Power down (mute)
788 * 0x1 : 6dB
789 * 0x2 : 0 dB
790 * 0x3 : -6 dB
791 * Inverting not going to help with these.
792 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
793 */
794#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
795 xinvert, tlv_array) \
796{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
797 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
798 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
799 .tlv.p = (tlv_array), \
800 .info = snd_soc_info_volsw, \
801 .get = snd_soc_get_volsw_twl4030, \
802 .put = snd_soc_put_volsw_twl4030, \
803 .private_value = (unsigned long)&(struct soc_mixer_control) \
804 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
805 .max = xmax, .invert = xinvert} }
806#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
807 xinvert, tlv_array) \
808{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
809 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
810 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
811 .tlv.p = (tlv_array), \
812 .info = snd_soc_info_volsw_2r, \
813 .get = snd_soc_get_volsw_r2_twl4030,\
814 .put = snd_soc_put_volsw_r2_twl4030, \
815 .private_value = (unsigned long)&(struct soc_mixer_control) \
816 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 817 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 818#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
819 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
820 xinvert, tlv_array)
821
822static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
823 struct snd_ctl_elem_value *ucontrol)
824{
825 struct soc_mixer_control *mc =
826 (struct soc_mixer_control *)kcontrol->private_value;
827 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
828 unsigned int reg = mc->reg;
829 unsigned int shift = mc->shift;
830 unsigned int rshift = mc->rshift;
831 int max = mc->max;
832 int mask = (1 << fls(max)) - 1;
833
834 ucontrol->value.integer.value[0] =
835 (snd_soc_read(codec, reg) >> shift) & mask;
836 if (ucontrol->value.integer.value[0])
837 ucontrol->value.integer.value[0] =
838 max + 1 - ucontrol->value.integer.value[0];
839
840 if (shift != rshift) {
841 ucontrol->value.integer.value[1] =
842 (snd_soc_read(codec, reg) >> rshift) & mask;
843 if (ucontrol->value.integer.value[1])
844 ucontrol->value.integer.value[1] =
845 max + 1 - ucontrol->value.integer.value[1];
846 }
847
848 return 0;
849}
850
851static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
852 struct snd_ctl_elem_value *ucontrol)
853{
854 struct soc_mixer_control *mc =
855 (struct soc_mixer_control *)kcontrol->private_value;
856 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
857 unsigned int reg = mc->reg;
858 unsigned int shift = mc->shift;
859 unsigned int rshift = mc->rshift;
860 int max = mc->max;
861 int mask = (1 << fls(max)) - 1;
862 unsigned short val, val2, val_mask;
863
864 val = (ucontrol->value.integer.value[0] & mask);
865
866 val_mask = mask << shift;
867 if (val)
868 val = max + 1 - val;
869 val = val << shift;
870 if (shift != rshift) {
871 val2 = (ucontrol->value.integer.value[1] & mask);
872 val_mask |= mask << rshift;
873 if (val2)
874 val2 = max + 1 - val2;
875 val |= val2 << rshift;
876 }
877 return snd_soc_update_bits(codec, reg, val_mask, val);
878}
879
880static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
881 struct snd_ctl_elem_value *ucontrol)
882{
883 struct soc_mixer_control *mc =
884 (struct soc_mixer_control *)kcontrol->private_value;
885 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
886 unsigned int reg = mc->reg;
887 unsigned int reg2 = mc->rreg;
888 unsigned int shift = mc->shift;
889 int max = mc->max;
890 int mask = (1<<fls(max))-1;
891
892 ucontrol->value.integer.value[0] =
893 (snd_soc_read(codec, reg) >> shift) & mask;
894 ucontrol->value.integer.value[1] =
895 (snd_soc_read(codec, reg2) >> shift) & mask;
896
897 if (ucontrol->value.integer.value[0])
898 ucontrol->value.integer.value[0] =
899 max + 1 - ucontrol->value.integer.value[0];
900 if (ucontrol->value.integer.value[1])
901 ucontrol->value.integer.value[1] =
902 max + 1 - ucontrol->value.integer.value[1];
903
904 return 0;
905}
906
907static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
908 struct snd_ctl_elem_value *ucontrol)
909{
910 struct soc_mixer_control *mc =
911 (struct soc_mixer_control *)kcontrol->private_value;
912 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
913 unsigned int reg = mc->reg;
914 unsigned int reg2 = mc->rreg;
915 unsigned int shift = mc->shift;
916 int max = mc->max;
917 int mask = (1 << fls(max)) - 1;
918 int err;
919 unsigned short val, val2, val_mask;
920
921 val_mask = mask << shift;
922 val = (ucontrol->value.integer.value[0] & mask);
923 val2 = (ucontrol->value.integer.value[1] & mask);
924
925 if (val)
926 val = max + 1 - val;
927 if (val2)
928 val2 = max + 1 - val2;
929
930 val = val << shift;
931 val2 = val2 << shift;
932
933 err = snd_soc_update_bits(codec, reg, val_mask, val);
934 if (err < 0)
935 return err;
936
937 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
938 return err;
939}
940
b74bd40f
LCM		 941/* Codec operation modes */
942static const char *twl4030_op_modes_texts[] = {
943 "Option 2 (voice/audio)", "Option 1 (audio)"
944};
945
946static const struct soc_enum twl4030_op_modes_enum =
947 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
948 ARRAY_SIZE(twl4030_op_modes_texts),
949 twl4030_op_modes_texts);
950
423c238d 951static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 952 struct snd_ctl_elem_value *ucontrol)
953{
954 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
955 struct twl4030_priv *twl4030 = codec->private_data;
956 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
957 unsigned short val;
958 unsigned short mask, bitmask;
959
960 if (twl4030->configured) {
961 printk(KERN_ERR "twl4030 operation mode cannot be "
962 "changed on-the-fly\n");
963 return -EBUSY;
964 }
965
966 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
967 ;
968 if (ucontrol->value.enumerated.item[0] > e->max - 1)
969 return -EINVAL;
970
971 val = ucontrol->value.enumerated.item[0] << e->shift_l;
972 mask = (bitmask - 1) << e->shift_l;
973 if (e->shift_l != e->shift_r) {
974 if (ucontrol->value.enumerated.item[1] > e->max - 1)
975 return -EINVAL;
976 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
977 mask |= (bitmask - 1) << e->shift_r;
978 }
979
980 return snd_soc_update_bits(codec, e->reg, mask, val);
981}
982
c10b82cf
PU		 983/*
984 * FGAIN volume control:
985 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
986 */
d889a72c 987static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 988
0d33ea0b
PU		 989/*
990 * CGAIN volume control:
991 * 0 dB to 12 dB in 6 dB steps
992 * value 2 and 3 means 12 dB
993 */
d889a72c
PU		 994static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
995
1a787e7a
JS		 996/*
997 * Voice Downlink GAIN volume control:
998 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
999 */
1000static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1001
d889a72c
PU		 1002/*
1003 * Analog playback gain
1004 * -24 dB to 12 dB in 2 dB steps
1005 */
1006static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1007
4290239c
PU		 1008/*
1009 * Gain controls tied to outputs
1010 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1011 */
1012static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1013
18cc8d8d
JS		 1014/*
1015 * Gain control for earpiece amplifier
1016 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1017 */
1018static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1019
381a22b5
PU		 1020/*
1021 * Capture gain after the ADCs
1022 * from 0 dB to 31 dB in 1 dB steps
1023 */
1024static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1025
5920b453
GI		 1026/*
1027 * Gain control for input amplifiers
1028 * 0 dB to 30 dB in 6 dB steps
1029 */
1030static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1031
328d0a13
LCM		 1032/* AVADC clock priority */
1033static const char *twl4030_avadc_clk_priority_texts[] = {
1034 "Voice high priority", "HiFi high priority"
1035};
1036
1037static const struct soc_enum twl4030_avadc_clk_priority_enum =
1038 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1039 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1040 twl4030_avadc_clk_priority_texts);
1041
89492be8
PU		 1042static const char *twl4030_rampdelay_texts[] = {
1043 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1044 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1045 "3495/2581/1748 ms"
1046};
1047
1048static const struct soc_enum twl4030_rampdelay_enum =
1049 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1050 ARRAY_SIZE(twl4030_rampdelay_texts),
1051 twl4030_rampdelay_texts);
1052
376f7839
PU		 1053/* Vibra H-bridge direction mode */
1054static const char *twl4030_vibradirmode_texts[] = {
1055 "Vibra H-bridge direction", "Audio data MSB",
1056};
1057
1058static const struct soc_enum twl4030_vibradirmode_enum =
1059 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1060 ARRAY_SIZE(twl4030_vibradirmode_texts),
1061 twl4030_vibradirmode_texts);
1062
1063/* Vibra H-bridge direction */
1064static const char *twl4030_vibradir_texts[] = {
1065 "Positive polarity", "Negative polarity",
1066};
1067
1068static const struct soc_enum twl4030_vibradir_enum =
1069 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1070 ARRAY_SIZE(twl4030_vibradir_texts),
1071 twl4030_vibradir_texts);
1072
cc17557e 1073static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1074 /* Codec operation mode control */
1075 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1076 snd_soc_get_enum_double,
1077 snd_soc_put_twl4030_opmode_enum_double),
1078
d889a72c
PU		 1079 /* Common playback gain controls */
1080 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1081 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1082 0, 0x3f, 0, digital_fine_tlv),
1083 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1084 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1085 0, 0x3f, 0, digital_fine_tlv),
1086
1087 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1088 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1089 6, 0x2, 0, digital_coarse_tlv),
1090 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1091 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1092 6, 0x2, 0, digital_coarse_tlv),
1093
1094 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1095 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1096 3, 0x12, 1, analog_tlv),
1097 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1098 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1099 3, 0x12, 1, analog_tlv),
44c55870
PU		 1100 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1101 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1102 1, 1, 0),
1103 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1104 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1105 1, 1, 0),
381a22b5 1106
1a787e7a
JS		 1107 /* Common voice downlink gain controls */
1108 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1109 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1110
1111 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1112 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1113
1114 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1115 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1116
4290239c
PU		 1117 /* Separate output gain controls */
1118 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1119 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1120 4, 3, 0, output_tvl),
1121
1122 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1123 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1124
1125 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1126 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1127 4, 3, 0, output_tvl),
1128
1129 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1130 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1131
381a22b5 1132 /* Common capture gain controls */
276c6222 1133 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1134 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1135 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1136 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1137 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1138 0, 0x1f, 0, digital_capture_tlv),
5920b453 1139
276c6222 1140 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1141 0, 3, 5, 0, input_gain_tlv),
89492be8 1142
328d0a13
LCM		 1143 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1144
89492be8 1145 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1146
1147 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1148 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1149};
1150
cc17557e 1151static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1152 /* Left channel inputs */
1153 SND_SOC_DAPM_INPUT("MAINMIC"),
1154 SND_SOC_DAPM_INPUT("HSMIC"),
1155 SND_SOC_DAPM_INPUT("AUXL"),
1156 SND_SOC_DAPM_INPUT("CARKITMIC"),
1157 /* Right channel inputs */
1158 SND_SOC_DAPM_INPUT("SUBMIC"),
1159 SND_SOC_DAPM_INPUT("AUXR"),
1160 /* Digital microphones (Stereo) */
1161 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1162 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1163
1164 /* Outputs */
cc17557e
SS		 1165 SND_SOC_DAPM_OUTPUT("OUTL"),
1166 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1167 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1168 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1169 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1170 SND_SOC_DAPM_OUTPUT("HSOL"),
1171 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1172 SND_SOC_DAPM_OUTPUT("CARKITL"),
1173 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1174 SND_SOC_DAPM_OUTPUT("HFL"),
1175 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1176 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1177
53b5047d 1178 /* DACs */
b4852b79 1179 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1180 SND_SOC_NOPM, 0, 0),
b4852b79 1181 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1182 SND_SOC_NOPM, 0, 0),
b4852b79 1183 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1184 SND_SOC_NOPM, 0, 0),
b4852b79 1185 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1186 SND_SOC_NOPM, 0, 0),
1a787e7a 1187 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1188 SND_SOC_NOPM, 0, 0),
cc17557e 1189
7393958f
PU		 1190 /* Analog bypasses */
1191 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1192 &twl4030_dapm_abypassr1_control, bypass_event,
1193 SND_SOC_DAPM_POST_REG),
1194 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1195 &twl4030_dapm_abypassl1_control,
1196 bypass_event, SND_SOC_DAPM_POST_REG),
1197 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1198 &twl4030_dapm_abypassr2_control,
1199 bypass_event, SND_SOC_DAPM_POST_REG),
1200 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1201 &twl4030_dapm_abypassl2_control,
1202 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1203 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1204 &twl4030_dapm_abypassv_control,
1205 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1206
6bab83fd
PU		 1207 /* Digital bypasses */
1208 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1209 &twl4030_dapm_dbypassl_control, bypass_event,
1210 SND_SOC_DAPM_POST_REG),
1211 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1212 &twl4030_dapm_dbypassr_control, bypass_event,
1213 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1214 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1215 &twl4030_dapm_dbypassv_control, bypass_event,
1216 SND_SOC_DAPM_POST_REG),
6bab83fd 1217
4005d39a
PU		 1218 /* Digital mixers, power control for the physical DACs */
1219 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1220 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1221 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1222 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1223 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1224 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1225 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1226 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1227 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1228 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1229
1230 /* Analog mixers, power control for the physical PGAs */
1231 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1232 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1233 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1234 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1235 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1236 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1237 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1238 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1239 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1240 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1241
1a787e7a 1242 /* Output MIXER controls */
5e98a464 1243 /* Earpiece */
1a787e7a
JS		 1244 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1245 &twl4030_dapm_earpiece_controls[0],
1246 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1247 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1248 0, 0, NULL, 0, earpiecepga_event,
1249 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1250 /* PreDrivL/R */
1a787e7a
JS		 1251 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1252 &twl4030_dapm_predrivel_controls[0],
1253 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1254 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1255 0, 0, NULL, 0, predrivelpga_event,
1256 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1257 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_predriver_controls[0],
1259 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1260 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1261 0, 0, NULL, 0, predriverpga_event,
1262 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1263 /* HeadsetL/R */
6943c92e 1264 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1265 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1266 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1267 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1268 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1269 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1270 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_hsor_controls[0],
1272 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1273 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1274 0, 0, NULL, 0, headsetrpga_event,
1275 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1276 /* CarkitL/R */
1a787e7a
JS		 1277 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1278 &twl4030_dapm_carkitl_controls[0],
1279 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1280 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1281 0, 0, NULL, 0, carkitlpga_event,
1282 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1283 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1284 &twl4030_dapm_carkitr_controls[0],
1285 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1286 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1287 0, 0, NULL, 0, carkitrpga_event,
1288 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1289
1290 /* Output MUX controls */
df339804 1291 /* HandsfreeL/R */
5a2e9a48
PU		 1292 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1293 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1294 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1295 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1296 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1297 0, 0, NULL, 0, handsfreelpga_event,
1298 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1299 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1300 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1301 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1302 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1303 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1304 0, 0, NULL, 0, handsfreerpga_event,
1305 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1306 /* Vibra */
1307 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1308 &twl4030_dapm_vibra_control),
1309 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1310 &twl4030_dapm_vibrapath_control),
5e98a464 1311
276c6222
PU		 1312 /* Introducing four virtual ADC, since TWL4030 have four channel for
1313 capture */
1314 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1315 SND_SOC_NOPM, 0, 0),
1316 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1317 SND_SOC_NOPM, 0, 0),
1318 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1319 SND_SOC_NOPM, 0, 0),
1320 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1321 SND_SOC_NOPM, 0, 0),
1322
1323 /* Analog/Digital mic path selection.
1324 TX1 Left/Right: either analog Left/Right or Digimic0
1325 TX2 Left/Right: either analog Left/Right or Digimic1 */
1326 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1327 &twl4030_dapm_micpathtx1_control, micpath_event,
1328 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1329 SND_SOC_DAPM_POST_REG),
1330 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1331 &twl4030_dapm_micpathtx2_control, micpath_event,
1332 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1333 SND_SOC_DAPM_POST_REG),
1334
97b8096d
JS		 1335 /* Analog input mixers for the capture amplifiers */
1336 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1337 TWL4030_REG_ANAMICL, 4, 0,
1338 &twl4030_dapm_analoglmic_controls[0],
1339 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1340 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1341 TWL4030_REG_ANAMICR, 4, 0,
1342 &twl4030_dapm_analogrmic_controls[0],
1343 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1344
fb2a2f84
PU		 1345 SND_SOC_DAPM_PGA("ADC Physical Left",
1346 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1347 SND_SOC_DAPM_PGA("ADC Physical Right",
1348 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1349
1350 SND_SOC_DAPM_PGA("Digimic0 Enable",
1351 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1352 SND_SOC_DAPM_PGA("Digimic1 Enable",
1353 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1354
1355 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1356 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1357 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1358
cc17557e
SS		 1359};
1360
1361static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1362 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1363 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1364 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1365 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1366 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1367
1368 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1369 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1370 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1371 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1372 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1373
5e98a464
PU		 1374 /* Internal playback routings */
1375 /* Earpiece */
4005d39a
PU		 1376 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1377 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1378 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1379 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1380 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1381 /* PreDrivL */
4005d39a
PU		 1382 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1383 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1384 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1385 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1386 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1387 /* PreDrivR */
4005d39a
PU		 1388 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1389 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1390 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1391 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1392 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1393 /* HeadsetL */
4005d39a
PU		 1394 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1395 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1396 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1397 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1398 /* HeadsetR */
4005d39a
PU		 1399 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1400 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1401 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1402 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1403 /* CarkitL */
4005d39a
PU		 1404 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1405 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1406 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1407 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1408 /* CarkitR */
4005d39a
PU		 1409 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1410 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1411 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1412 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1413 /* HandsfreeL */
4005d39a
PU		 1414 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1415 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1416 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1417 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1418 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1419 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1420 /* HandsfreeR */
4005d39a
PU		 1421 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1422 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1423 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1424 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1425 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1426 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1427 /* Vibra */
1428 {"Vibra Mux", "AudioL1", "DAC Left1"},
1429 {"Vibra Mux", "AudioR1", "DAC Right1"},
1430 {"Vibra Mux", "AudioL2", "DAC Left2"},
1431 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1432
cc17557e 1433 /* outputs */
4005d39a
PU		 1434 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1435 {"OUTR", NULL, "Analog R2 Playback Mixer"},
9008adf9
PU		 1436 {"EARPIECE", NULL, "Earpiece PGA"},
1437 {"PREDRIVEL", NULL, "PredriveL PGA"},
1438 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1439 {"HSOL", NULL, "HeadsetL PGA"},
1440 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1441 {"CARKITL", NULL, "CarkitL PGA"},
1442 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1443 {"HFL", NULL, "HandsfreeL PGA"},
1444 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1445 {"Vibra Route", "Audio", "Vibra Mux"},
1446 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1447
276c6222
PU		 1448 /* Capture path */
1449 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1450 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1451 {"Analog Left Capture Route", "AUXL", "AUXL"},
1452 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1453
1454 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1455 {"Analog Right Capture Route", "AUXR", "AUXR"},
1456
fb2a2f84
PU		 1457 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1458 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1459
1460 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1461 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1462
1463 /* TX1 Left capture path */
fb2a2f84 1464 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1465 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1466 /* TX1 Right capture path */
fb2a2f84 1467 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1468 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1469 /* TX2 Left capture path */
fb2a2f84 1470 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1471 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1472 /* TX2 Right capture path */
fb2a2f84 1473 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1474 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1475
1476 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1477 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1478 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1479 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1480
7393958f
PU		 1481 /* Analog bypass routes */
1482 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1483 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1484 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1485 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1486 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1487
1488 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1489 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1490 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1491 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1492 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1493
6bab83fd
PU		 1494 /* Digital bypass routes */
1495 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1496 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1497 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1498
4005d39a
PU		 1499 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1500 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1501 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1502
cc17557e
SS		 1503};
1504
1505static int twl4030_add_widgets(struct snd_soc_codec *codec)
1506{
1507 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1508 ARRAY_SIZE(twl4030_dapm_widgets));
1509
1510 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1511
1512 snd_soc_dapm_new_widgets(codec);
1513 return 0;
1514}
1515
cc17557e
SS		 1516static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1517 enum snd_soc_bias_level level)
1518{
7393958f
PU		 1519 struct twl4030_priv *twl4030 = codec->private_data;
1520
cc17557e
SS		 1521 switch (level) {
1522 case SND_SOC_BIAS_ON:
7393958f 1523 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1524 break;
1525 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1526 twl4030_power_up(codec);
1527 if (twl4030->bypass_state)
1528 twl4030_codec_mute(codec, 0);
1529 else
1530 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1531 break;
1532 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1533 twl4030_power_up(codec);
1534 if (twl4030->bypass_state)
1535 twl4030_codec_mute(codec, 0);
1536 else
1537 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1538 break;
1539 case SND_SOC_BIAS_OFF:
1540 twl4030_power_down(codec);
1541 break;
1542 }
1543 codec->bias_level = level;
1544
1545 return 0;
1546}
1547
6b87a91f
PU		 1548static void twl4030_constraints(struct twl4030_priv *twl4030,
1549 struct snd_pcm_substream *mst_substream)
1550{
1551 struct snd_pcm_substream *slv_substream;
1552
1553 /* Pick the stream, which need to be constrained */
1554 if (mst_substream == twl4030->master_substream)
1555 slv_substream = twl4030->slave_substream;
1556 else if (mst_substream == twl4030->slave_substream)
1557 slv_substream = twl4030->master_substream;
1558 else /* This should not happen.. */
1559 return;
1560
1561 /* Set the constraints according to the already configured stream */
1562 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1563 SNDRV_PCM_HW_PARAM_RATE,
1564 twl4030->rate,
1565 twl4030->rate);
1566
1567 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1568 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1569 twl4030->sample_bits,
1570 twl4030->sample_bits);
1571
1572 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1573 SNDRV_PCM_HW_PARAM_CHANNELS,
1574 twl4030->channels,
1575 twl4030->channels);
1576}
1577
8a1f936a
PU		 1578/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1579 * capture has to be enabled/disabled. */
1580static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1581 int enable)
1582{
1583 u8 reg, mask;
1584
1585 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1586
1587 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1588 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1589 else
1590 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1591
1592 if (enable)
1593 reg |= mask;
1594 else
1595 reg &= ~mask;
1596
1597 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1598}
1599
d6648da1
PU		 1600static int twl4030_startup(struct snd_pcm_substream *substream,
1601 struct snd_soc_dai *dai)
7220b9f4
PU		 1602{
1603 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1604 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1605 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1606 struct twl4030_priv *twl4030 = codec->private_data;
1607
7220b9f4 1608 if (twl4030->master_substream) {
7220b9f4 1609 twl4030->slave_substream = substream;
6b87a91f
PU		 1610 /* The DAI has one configuration for playback and capture, so
1611 * if the DAI has been already configured then constrain this
1612 * substream to match it. */
1613 if (twl4030->configured)
1614 twl4030_constraints(twl4030, twl4030->master_substream);
1615 } else {
8a1f936a
PU		 1616 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1617 TWL4030_OPTION_1)) {
1618 /* In option2 4 channel is not supported, set the
1619 * constraint for the first stream for channels, the
1620 * second stream will 'inherit' this cosntraint */
1621 snd_pcm_hw_constraint_minmax(substream->runtime,
1622 SNDRV_PCM_HW_PARAM_CHANNELS,
1623 2, 2);
1624 }
7220b9f4 1625 twl4030->master_substream = substream;
6b87a91f 1626 }
7220b9f4
PU		 1627
1628 return 0;
1629}
1630
d6648da1
PU		 1631static void twl4030_shutdown(struct snd_pcm_substream *substream,
1632 struct snd_soc_dai *dai)
7220b9f4
PU		 1633{
1634 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1635 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1636 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1637 struct twl4030_priv *twl4030 = codec->private_data;
1638
1639 if (twl4030->master_substream == substream)
1640 twl4030->master_substream = twl4030->slave_substream;
1641
1642 twl4030->slave_substream = NULL;
6b87a91f
PU		 1643
1644 /* If all streams are closed, or the remaining stream has not yet
1645 * been configured than set the DAI as not configured. */
1646 if (!twl4030->master_substream)
1647 twl4030->configured = 0;
1648 else if (!twl4030->master_substream->runtime->channels)
1649 twl4030->configured = 0;
8a1f936a
PU		 1650
1651 /* If the closing substream had 4 channel, do the necessary cleanup */
1652 if (substream->runtime->channels == 4)
1653 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1654}
1655
cc17557e 1656static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1657 struct snd_pcm_hw_params *params,
1658 struct snd_soc_dai *dai)
cc17557e
SS		 1659{
1660 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1661 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1662 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1663 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1664 u8 mode, old_mode, format, old_format;
1665
8a1f936a
PU		 1666 /* If the substream has 4 channel, do the necessary setup */
1667 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1668 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1669 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1670
1671 /* Safety check: are we in the correct operating mode and
1672 * the interface is in TDM mode? */
1673 if ((mode & TWL4030_OPTION_1) &&
1674 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1675 twl4030_tdm_enable(codec, substream->stream, 1);
1676 else
1677 return -EINVAL;
1678 }
1679
6b87a91f
PU		 1680 if (twl4030->configured)
1681 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1682 return 0;
1683
cc17557e
SS		 1684 /* bit rate */
1685 old_mode = twl4030_read_reg_cache(codec,
1686 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1687 mode = old_mode & ~TWL4030_APLL_RATE;
1688
1689 switch (params_rate(params)) {
1690 case 8000:
1691 mode |= TWL4030_APLL_RATE_8000;
1692 break;
1693 case 11025:
1694 mode |= TWL4030_APLL_RATE_11025;
1695 break;
1696 case 12000:
1697 mode |= TWL4030_APLL_RATE_12000;
1698 break;
1699 case 16000:
1700 mode |= TWL4030_APLL_RATE_16000;
1701 break;
1702 case 22050:
1703 mode |= TWL4030_APLL_RATE_22050;
1704 break;
1705 case 24000:
1706 mode |= TWL4030_APLL_RATE_24000;
1707 break;
1708 case 32000:
1709 mode |= TWL4030_APLL_RATE_32000;
1710 break;
1711 case 44100:
1712 mode |= TWL4030_APLL_RATE_44100;
1713 break;
1714 case 48000:
1715 mode |= TWL4030_APLL_RATE_48000;
1716 break;
103f211d
PU		 1717 case 96000:
1718 mode |= TWL4030_APLL_RATE_96000;
1719 break;
cc17557e
SS		 1720 default:
1721 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1722 params_rate(params));
1723 return -EINVAL;
1724 }
1725
1726 if (mode != old_mode) {
1727 /* change rate and set CODECPDZ */
7393958f 1728 twl4030_codec_enable(codec, 0);
cc17557e 1729 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1730 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1731 }
1732
1733 /* sample size */
1734 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1735 format = old_format;
1736 format &= ~TWL4030_DATA_WIDTH;
1737 switch (params_format(params)) {
1738 case SNDRV_PCM_FORMAT_S16_LE:
1739 format |= TWL4030_DATA_WIDTH_16S_16W;
1740 break;
1741 case SNDRV_PCM_FORMAT_S24_LE:
1742 format |= TWL4030_DATA_WIDTH_32S_24W;
1743 break;
1744 default:
1745 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1746 params_format(params));
1747 return -EINVAL;
1748 }
1749
1750 if (format != old_format) {
1751
1752 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1753 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1754
1755 /* change format */
1756 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1757
1758 /* set CODECPDZ afterwards */
db04e2c5 1759 twl4030_codec_enable(codec, 1);
cc17557e 1760 }
6b87a91f
PU		 1761
1762 /* Store the important parameters for the DAI configuration and set
1763 * the DAI as configured */
1764 twl4030->configured = 1;
1765 twl4030->rate = params_rate(params);
1766 twl4030->sample_bits = hw_param_interval(params,
1767 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1768 twl4030->channels = params_channels(params);
1769
1770 /* If both playback and capture streams are open, and one of them
1771 * is setting the hw parameters right now (since we are here), set
1772 * constraints to the other stream to match the current one. */
1773 if (twl4030->slave_substream)
1774 twl4030_constraints(twl4030, substream);
1775
cc17557e
SS		 1776 return 0;
1777}
1778
1779static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1780 int clk_id, unsigned int freq, int dir)
1781{
1782 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1783 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1784 u8 infreq;
1785
1786 switch (freq) {
1787 case 19200000:
1788 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1789 twl4030->sysclk = 19200;
cc17557e
SS		 1790 break;
1791 case 26000000:
1792 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1793 twl4030->sysclk = 26000;
cc17557e
SS		 1794 break;
1795 case 38400000:
1796 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1797 twl4030->sysclk = 38400;
cc17557e
SS		 1798 break;
1799 default:
1800 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1801 freq);
1802 return -EINVAL;
1803 }
1804
1805 infreq |= TWL4030_APLL_EN;
1806 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1807
1808 return 0;
1809}
1810
1811static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1812 unsigned int fmt)
1813{
1814 struct snd_soc_codec *codec = codec_dai->codec;
1815 u8 old_format, format;
1816
1817 /* get format */
1818 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1819 format = old_format;
1820
1821 /* set master/slave audio interface */
1822 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1823 case SND_SOC_DAIFMT_CBM_CFM:
1824 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1825 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1826 break;
1827 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1828 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1829 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1830 break;
1831 default:
1832 return -EINVAL;
1833 }
1834
1835 /* interface format */
1836 format &= ~TWL4030_AIF_FORMAT;
1837 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1838 case SND_SOC_DAIFMT_I2S:
1839 format |= TWL4030_AIF_FORMAT_CODEC;
1840 break;
8a1f936a
PU		 1841 case SND_SOC_DAIFMT_DSP_A:
1842 format |= TWL4030_AIF_FORMAT_TDM;
1843 break;
cc17557e
SS		 1844 default:
1845 return -EINVAL;
1846 }
1847
1848 if (format != old_format) {
1849
1850 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1851 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1852
1853 /* change format */
1854 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1855
1856 /* set CODECPDZ afterwards */
db04e2c5 1857 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1858 }
1859
1860 return 0;
1861}
1862
68140443
LCM		 1863static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1864{
1865 struct snd_soc_codec *codec = dai->codec;
1866 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1867
1868 if (tristate)
1869 reg |= TWL4030_AIF_TRI_EN;
1870 else
1871 reg &= ~TWL4030_AIF_TRI_EN;
1872
1873 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1874}
1875
b7a755a8
MLC		 1876/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1877 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1878static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1879 int enable)
1880{
1881 u8 reg, mask;
1882
1883 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1884
1885 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1886 mask = TWL4030_ARXL1_VRX_EN;
1887 else
1888 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1889
1890 if (enable)
1891 reg |= mask;
1892 else
1893 reg &= ~mask;
1894
1895 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1896}
1897
7154b3e8
JS		 1898static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1899 struct snd_soc_dai *dai)
1900{
1901 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1902 struct snd_soc_device *socdev = rtd->socdev;
1903 struct snd_soc_codec *codec = socdev->card->codec;
1904 u8 infreq;
1905 u8 mode;
1906
1907 /* If the system master clock is not 26MHz, the voice PCM interface is
1908 * not avilable.
1909 */
1910 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1911 & TWL4030_APLL_INFREQ;
1912
1913 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1914 printk(KERN_ERR "TWL4030 voice startup: "
1915 "MCLK is not 26MHz, call set_sysclk() on init\n");
1916 return -EINVAL;
1917 }
1918
1919 /* If the codec mode is not option2, the voice PCM interface is not
1920 * avilable.
1921 */
1922 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1923 & TWL4030_OPT_MODE;
1924
1925 if (mode != TWL4030_OPTION_2) {
1926 printk(KERN_ERR "TWL4030 voice startup: "
1927 "the codec mode is not option2\n");
1928 return -EINVAL;
1929 }
1930
1931 return 0;
1932}
1933
b7a755a8
MLC		 1934static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1935 struct snd_soc_dai *dai)
1936{
1937 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1938 struct snd_soc_device *socdev = rtd->socdev;
1939 struct snd_soc_codec *codec = socdev->card->codec;
1940
1941 /* Enable voice digital filters */
1942 twl4030_voice_enable(codec, substream->stream, 0);
1943}
1944
7154b3e8
JS		 1945static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1946 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1947{
1948 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1949 struct snd_soc_device *socdev = rtd->socdev;
1950 struct snd_soc_codec *codec = socdev->card->codec;
1951 u8 old_mode, mode;
1952
b7a755a8
MLC		 1953 /* Enable voice digital filters */
1954 twl4030_voice_enable(codec, substream->stream, 1);
1955
7154b3e8
JS		 1956 /* bit rate */
1957 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1958 & ~(TWL4030_CODECPDZ);
1959 mode = old_mode;
1960
1961 switch (params_rate(params)) {
1962 case 8000:
1963 mode &= ~(TWL4030_SEL_16K);
1964 break;
1965 case 16000:
1966 mode |= TWL4030_SEL_16K;
1967 break;
1968 default:
1969 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1970 params_rate(params));
1971 return -EINVAL;
1972 }
1973
1974 if (mode != old_mode) {
1975 /* change rate and set CODECPDZ */
1976 twl4030_codec_enable(codec, 0);
1977 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1978 twl4030_codec_enable(codec, 1);
1979 }
1980
1981 return 0;
1982}
1983
1984static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1985 int clk_id, unsigned int freq, int dir)
1986{
1987 struct snd_soc_codec *codec = codec_dai->codec;
1988 u8 infreq;
1989
1990 switch (freq) {
1991 case 26000000:
1992 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1993 break;
1994 default:
1995 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1996 freq);
1997 return -EINVAL;
1998 }
1999
2000 infreq |= TWL4030_APLL_EN;
2001 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
2002
2003 return 0;
2004}
2005
2006static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2007 unsigned int fmt)
2008{
2009 struct snd_soc_codec *codec = codec_dai->codec;
2010 u8 old_format, format;
2011
2012 /* get format */
2013 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2014 format = old_format;
2015
2016 /* set master/slave audio interface */
2017 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2018 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2019 format &= ~(TWL4030_VIF_SLAVE_EN);
2020 break;
2021 case SND_SOC_DAIFMT_CBS_CFS:
2022 format |= TWL4030_VIF_SLAVE_EN;
2023 break;
2024 default:
2025 return -EINVAL;
2026 }
2027
2028 /* clock inversion */
2029 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2030 case SND_SOC_DAIFMT_IB_NF:
2031 format &= ~(TWL4030_VIF_FORMAT);
2032 break;
2033 case SND_SOC_DAIFMT_NB_IF:
2034 format |= TWL4030_VIF_FORMAT;
2035 break;
2036 default:
2037 return -EINVAL;
2038 }
2039
2040 if (format != old_format) {
2041 /* change format and set CODECPDZ */
2042 twl4030_codec_enable(codec, 0);
2043 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2044 twl4030_codec_enable(codec, 1);
2045 }
2046
2047 return 0;
2048}
2049
68140443
LCM		 2050static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2051{
2052 struct snd_soc_codec *codec = dai->codec;
2053 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2054
2055 if (tristate)
2056 reg |= TWL4030_VIF_TRI_EN;
2057 else
2058 reg &= ~TWL4030_VIF_TRI_EN;
2059
2060 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2061}
2062
bbba9444 2063#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2064#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2065
10d9e3d9 2066static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2067 .startup = twl4030_startup,
2068 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2069 .hw_params = twl4030_hw_params,
2070 .set_sysclk = twl4030_set_dai_sysclk,
2071 .set_fmt = twl4030_set_dai_fmt,
68140443 2072 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2073};
2074
7154b3e8
JS		 2075static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2076 .startup = twl4030_voice_startup,
b7a755a8 2077 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2078 .hw_params = twl4030_voice_hw_params,
2079 .set_sysclk = twl4030_voice_set_dai_sysclk,
2080 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2081 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2082};
2083
2084struct snd_soc_dai twl4030_dai[] = {
2085{
cc17557e
SS		 2086 .name = "twl4030",
2087 .playback = {
b4852b79 2088 .stream_name = "HiFi Playback",
cc17557e 2089 .channels_min = 2,
8a1f936a 2090 .channels_max = 4,
31ad0f31 2091 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2092 .formats = TWL4030_FORMATS,},
2093 .capture = {
2094 .stream_name = "Capture",
2095 .channels_min = 2,
8a1f936a 2096 .channels_max = 4,
cc17557e
SS		 2097 .rates = TWL4030_RATES,
2098 .formats = TWL4030_FORMATS,},
10d9e3d9 2099 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2100},
2101{
2102 .name = "twl4030 Voice",
2103 .playback = {
b4852b79 2104 .stream_name = "Voice Playback",
7154b3e8
JS		 2105 .channels_min = 1,
2106 .channels_max = 1,
2107 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2108 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2109 .capture = {
2110 .stream_name = "Capture",
2111 .channels_min = 1,
2112 .channels_max = 2,
2113 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2114 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2115 .ops = &twl4030_dai_voice_ops,
2116},
cc17557e
SS		 2117};
2118EXPORT_SYMBOL_GPL(twl4030_dai);
2119
2120static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2121{
2122 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2123 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2124
2125 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2126
2127 return 0;
2128}
2129
2130static int twl4030_resume(struct platform_device *pdev)
2131{
2132 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2133 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2134
2135 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2136 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2137 return 0;
2138}
2139
2140/*
2141 * initialize the driver
2142 * register the mixer and dsp interfaces with the kernel
2143 */
2144
2145static int twl4030_init(struct snd_soc_device *socdev)
2146{
6627a653 2147 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2148 struct twl4030_setup_data *setup = socdev->codec_data;
2149 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2150 int ret = 0;
2151
2152 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2153
2154 codec->name = "twl4030";
2155 codec->owner = THIS_MODULE;
2156 codec->read = twl4030_read_reg_cache;
2157 codec->write = twl4030_write;
2158 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2159 codec->dai = twl4030_dai;
2160 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2161 codec->reg_cache_size = sizeof(twl4030_reg);
2162 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2163 GFP_KERNEL);
2164 if (codec->reg_cache == NULL)
2165 return -ENOMEM;
2166
9da28c7b
PU		 2167 /* Configuration for headset ramp delay from setup data */
2168 if (setup) {
2169 unsigned char hs_pop;
2170
2171 if (setup->sysclk)
2172 twl4030->sysclk = setup->sysclk;
2173 else
2174 twl4030->sysclk = 26000;
2175
2176 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2177 hs_pop &= ~TWL4030_RAMP_DELAY;
2178 hs_pop |= (setup->ramp_delay_value << 2);
2179 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2180 } else {
2181 twl4030->sysclk = 26000;
2182 }
2183
cc17557e
SS		 2184 /* register pcms */
2185 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2186 if (ret < 0) {
2187 printk(KERN_ERR "twl4030: failed to create pcms\n");
2188 goto pcm_err;
2189 }
2190
2191 twl4030_init_chip(codec);
2192
2193 /* power on device */
2194 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2195
3e8e1952
IM		 2196 snd_soc_add_controls(codec, twl4030_snd_controls,
2197 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2198 twl4030_add_widgets(codec);
2199
968a6025 2200 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2201 if (ret < 0) {
2202 printk(KERN_ERR "twl4030: failed to register card\n");
2203 goto card_err;
2204 }
2205
2206 return ret;
2207
2208card_err:
2209 snd_soc_free_pcms(socdev);
2210 snd_soc_dapm_free(socdev);
2211pcm_err:
2212 kfree(codec->reg_cache);
2213 return ret;
2214}
2215
2216static struct snd_soc_device *twl4030_socdev;
2217
2218static int twl4030_probe(struct platform_device *pdev)
2219{
2220 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2221 struct snd_soc_codec *codec;
7393958f 2222 struct twl4030_priv *twl4030;
cc17557e
SS		 2223
2224 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2225 if (codec == NULL)
2226 return -ENOMEM;
2227
7393958f
PU		 2228 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2229 if (twl4030 == NULL) {
2230 kfree(codec);
2231 return -ENOMEM;
2232 }
2233
2234 codec->private_data = twl4030;
6627a653 2235 socdev->card->codec = codec;
cc17557e
SS		 2236 mutex_init(&codec->mutex);
2237 INIT_LIST_HEAD(&codec->dapm_widgets);
2238 INIT_LIST_HEAD(&codec->dapm_paths);
2239
2240 twl4030_socdev = socdev;
2241 twl4030_init(socdev);
2242
2243 return 0;
2244}
2245
2246static int twl4030_remove(struct platform_device *pdev)
2247{
2248 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2249 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2250
2251 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2252 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2253 snd_soc_free_pcms(socdev);
2254 snd_soc_dapm_free(socdev);
7393958f 2255 kfree(codec->private_data);
cc17557e
SS		 2256 kfree(codec);
2257
2258 return 0;
2259}
2260
2261struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2262 .probe = twl4030_probe,
2263 .remove = twl4030_remove,
2264 .suspend = twl4030_suspend,
2265 .resume = twl4030_resume,
2266};
2267EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2268
24e07db8 2269static int __init twl4030_modinit(void)
64089b84 2270{
7154b3e8 2271 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2272}
24e07db8 2273module_init(twl4030_modinit);
64089b84
MB		 2274
2275static void __exit twl4030_exit(void)
2276{
7154b3e8 2277 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2278}
2279module_exit(twl4030_exit);
2280
cc17557e
SS		 2281MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2282MODULE_AUTHOR("Steve Sakoman");
2283MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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