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ASoC: TWL4030: Correct DAPM_DAC with power control
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
b0bd53a7
PU		 193/*
194 * Some of the gain controls in TWL (mostly those which are associated with
195 * the outputs) are implemented in an interesting way:
196 * 0x0 : Power down (mute)
197 * 0x1 : 6dB
198 * 0x2 : 0 dB
199 * 0x3 : -6 dB
200 * Inverting not going to help with these.
201 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
202 */
203#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
204 xinvert, tlv_array) \
205{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
206 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
207 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
208 .tlv.p = (tlv_array), \
209 .info = snd_soc_info_volsw, \
210 .get = snd_soc_get_volsw_twl4030, \
211 .put = snd_soc_put_volsw_twl4030, \
212 .private_value = (unsigned long)&(struct soc_mixer_control) \
213 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
214 .max = xmax, .invert = xinvert} }
215#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
216 xinvert, tlv_array) \
217{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
218 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
219 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
220 .tlv.p = (tlv_array), \
221 .info = snd_soc_info_volsw_2r, \
222 .get = snd_soc_get_volsw_r2_twl4030,\
223 .put = snd_soc_put_volsw_r2_twl4030, \
224 .private_value = (unsigned long)&(struct soc_mixer_control) \
225 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
226 .max = xmax, .invert = xinvert} }
227#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
228 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
229 xinvert, tlv_array)
230
231static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
232 struct snd_ctl_elem_value *ucontrol)
233{
234 struct soc_mixer_control *mc =
235 (struct soc_mixer_control *)kcontrol->private_value;
236 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
237 unsigned int reg = mc->reg;
238 unsigned int shift = mc->shift;
239 unsigned int rshift = mc->rshift;
240 int max = mc->max;
241 int mask = (1 << fls(max)) - 1;
242
243 ucontrol->value.integer.value[0] =
244 (snd_soc_read(codec, reg) >> shift) & mask;
245 if (ucontrol->value.integer.value[0])
246 ucontrol->value.integer.value[0] =
247 max + 1 - ucontrol->value.integer.value[0];
248
249 if (shift != rshift) {
250 ucontrol->value.integer.value[1] =
251 (snd_soc_read(codec, reg) >> rshift) & mask;
252 if (ucontrol->value.integer.value[1])
253 ucontrol->value.integer.value[1] =
254 max + 1 - ucontrol->value.integer.value[1];
255 }
256
257 return 0;
258}
259
260static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
261 struct snd_ctl_elem_value *ucontrol)
262{
263 struct soc_mixer_control *mc =
264 (struct soc_mixer_control *)kcontrol->private_value;
265 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
266 unsigned int reg = mc->reg;
267 unsigned int shift = mc->shift;
268 unsigned int rshift = mc->rshift;
269 int max = mc->max;
270 int mask = (1 << fls(max)) - 1;
271 unsigned short val, val2, val_mask;
272
273 val = (ucontrol->value.integer.value[0] & mask);
274
275 val_mask = mask << shift;
276 if (val)
277 val = max + 1 - val;
278 val = val << shift;
279 if (shift != rshift) {
280 val2 = (ucontrol->value.integer.value[1] & mask);
281 val_mask |= mask << rshift;
282 if (val2)
283 val2 = max + 1 - val2;
284 val |= val2 << rshift;
285 }
286 return snd_soc_update_bits(codec, reg, val_mask, val);
287}
288
289static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
292 struct soc_mixer_control *mc =
293 (struct soc_mixer_control *)kcontrol->private_value;
294 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
295 unsigned int reg = mc->reg;
296 unsigned int reg2 = mc->rreg;
297 unsigned int shift = mc->shift;
298 int max = mc->max;
299 int mask = (1<<fls(max))-1;
300
301 ucontrol->value.integer.value[0] =
302 (snd_soc_read(codec, reg) >> shift) & mask;
303 ucontrol->value.integer.value[1] =
304 (snd_soc_read(codec, reg2) >> shift) & mask;
305
306 if (ucontrol->value.integer.value[0])
307 ucontrol->value.integer.value[0] =
308 max + 1 - ucontrol->value.integer.value[0];
309 if (ucontrol->value.integer.value[1])
310 ucontrol->value.integer.value[1] =
311 max + 1 - ucontrol->value.integer.value[1];
312
313 return 0;
314}
315
316static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
317 struct snd_ctl_elem_value *ucontrol)
318{
319 struct soc_mixer_control *mc =
320 (struct soc_mixer_control *)kcontrol->private_value;
321 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
322 unsigned int reg = mc->reg;
323 unsigned int reg2 = mc->rreg;
324 unsigned int shift = mc->shift;
325 int max = mc->max;
326 int mask = (1 << fls(max)) - 1;
327 int err;
328 unsigned short val, val2, val_mask;
329
330 val_mask = mask << shift;
331 val = (ucontrol->value.integer.value[0] & mask);
332 val2 = (ucontrol->value.integer.value[1] & mask);
333
334 if (val)
335 val = max + 1 - val;
336 if (val2)
337 val2 = max + 1 - val2;
338
339 val = val << shift;
340 val2 = val2 << shift;
341
342 err = snd_soc_update_bits(codec, reg, val_mask, val);
343 if (err < 0)
344 return err;
345
346 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
347 return err;
348}
349
5920b453
GI		 350static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
352{
353 struct snd_soc_codec *codec = kcontrol->private_data;
354 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
355 int result = 0;
356
357 /* one bit must be set a time */
358 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
359 | TWL4030_MAINMIC_EN;
360 if (reg != 0) {
361 result++;
362 while ((reg & 1) == 0) {
363 result++;
364 reg >>= 1;
365 }
366 }
367
368 ucontrol->value.integer.value[0] = result;
369 return 0;
370}
371
372static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374{
375 struct snd_soc_codec *codec = kcontrol->private_data;
376 int value = ucontrol->value.integer.value[0];
377 u8 anamicl, micbias, avadc_ctl;
378
379 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
380 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
381 | TWL4030_MAINMIC_EN);
382 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
383 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
384 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
385
386 switch (value) {
387 case 1:
388 anamicl |= TWL4030_MAINMIC_EN;
389 micbias |= TWL4030_MICBIAS1_EN;
390 break;
391 case 2:
392 anamicl |= TWL4030_HSMIC_EN;
393 micbias |= TWL4030_HSMICBIAS_EN;
394 break;
395 case 3:
396 anamicl |= TWL4030_AUXL_EN;
397 break;
398 case 4:
399 anamicl |= TWL4030_CKMIC_EN;
400 break;
401 default:
402 break;
403 }
404
405 /* If some input is selected, enable amp and ADC */
406 if (value != 0) {
407 anamicl |= TWL4030_MICAMPL_EN;
408 avadc_ctl |= TWL4030_ADCL_EN;
409 } else {
410 anamicl &= ~TWL4030_MICAMPL_EN;
411 avadc_ctl &= ~TWL4030_ADCL_EN;
412 }
413
414 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
415 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
416 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
417
418 return 1;
419}
420
421static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_codec *codec = kcontrol->private_data;
425 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
426 int value = 0;
427
428 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
429 switch (reg) {
430 case TWL4030_SUBMIC_EN:
431 value = 1;
432 break;
433 case TWL4030_AUXR_EN:
434 value = 2;
435 break;
436 default:
437 break;
438 }
439
440 ucontrol->value.integer.value[0] = value;
441 return 0;
442}
443
444static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
445 struct snd_ctl_elem_value *ucontrol)
446{
447 struct snd_soc_codec *codec = kcontrol->private_data;
448 int value = ucontrol->value.integer.value[0];
449 u8 anamicr, micbias, avadc_ctl;
450
451 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
452 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
453 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
454 micbias &= ~TWL4030_MICBIAS2_EN;
455 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
456
457 switch (value) {
458 case 1:
459 anamicr |= TWL4030_SUBMIC_EN;
460 micbias |= TWL4030_MICBIAS2_EN;
461 break;
462 case 2:
463 anamicr |= TWL4030_AUXR_EN;
464 break;
465 default:
466 break;
467 }
468
469 if (value != 0) {
470 anamicr |= TWL4030_MICAMPR_EN;
471 avadc_ctl |= TWL4030_ADCR_EN;
472 } else {
473 anamicr &= ~TWL4030_MICAMPR_EN;
474 avadc_ctl &= ~TWL4030_ADCR_EN;
475 }
476
477 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
478 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
479 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
480
481 return 1;
482}
483
484static const char *twl4030_left_in_sel[] = {
485 "None",
486 "Main Mic",
487 "Headset Mic",
488 "Line In",
489 "Carkit Mic",
490};
491
492static const char *twl4030_right_in_sel[] = {
493 "None",
494 "Sub Mic",
495 "Line In",
496};
497
498static const struct soc_enum twl4030_left_input_mux =
499 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
500 twl4030_left_in_sel);
501
502static const struct soc_enum twl4030_right_input_mux =
503 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
504 twl4030_right_in_sel);
505
c10b82cf
PU		 506/*
507 * FGAIN volume control:
508 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
509 */
d889a72c 510static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 511
0d33ea0b
PU		 512/*
513 * CGAIN volume control:
514 * 0 dB to 12 dB in 6 dB steps
515 * value 2 and 3 means 12 dB
516 */
d889a72c
PU		 517static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
518
519/*
520 * Analog playback gain
521 * -24 dB to 12 dB in 2 dB steps
522 */
523static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 524
4290239c
PU		 525/*
526 * Gain controls tied to outputs
527 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
528 */
529static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
530
381a22b5
PU		 531/*
532 * Capture gain after the ADCs
533 * from 0 dB to 31 dB in 1 dB steps
534 */
535static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
536
5920b453
GI		 537/*
538 * Gain control for input amplifiers
539 * 0 dB to 30 dB in 6 dB steps
540 */
541static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
542
cc17557e 543static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 544 /* Common playback gain controls */
545 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
546 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
547 0, 0x3f, 0, digital_fine_tlv),
548 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
549 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
550 0, 0x3f, 0, digital_fine_tlv),
551
552 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
553 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
554 6, 0x2, 0, digital_coarse_tlv),
555 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
556 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
557 6, 0x2, 0, digital_coarse_tlv),
558
559 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
560 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
561 3, 0x12, 1, analog_tlv),
562 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
563 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
564 3, 0x12, 1, analog_tlv),
381a22b5 565
4290239c
PU		 566 /* Separate output gain controls */
567 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
568 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
569 4, 3, 0, output_tvl),
570
571 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
572 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
573
574 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
575 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
576 4, 3, 0, output_tvl),
577
578 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
579 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
580
381a22b5
PU		 581 /* Common capture gain controls */
582 SOC_DOUBLE_R_TLV("Capture Volume",
583 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
584 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 585
586 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
587 0, 3, 5, 0, input_gain_tlv),
588
589 /* Input source controls */
590 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
591 twl4030_get_left_input, twl4030_put_left_input),
592 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
593 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 594};
595
596/* add non dapm controls */
597static int twl4030_add_controls(struct snd_soc_codec *codec)
598{
599 int err, i;
600
601 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
602 err = snd_ctl_add(codec->card,
603 snd_soc_cnew(&twl4030_snd_controls[i],
604 codec, NULL));
605 if (err < 0)
606 return err;
607 }
608
609 return 0;
610}
611
612static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
613 SND_SOC_DAPM_INPUT("INL"),
614 SND_SOC_DAPM_INPUT("INR"),
615
616 SND_SOC_DAPM_OUTPUT("OUTL"),
617 SND_SOC_DAPM_OUTPUT("OUTR"),
618
53b5047d
PU		 619 /* DACs */
620 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
621 TWL4030_REG_AVDAC_CTL, 0, 0),
622 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
623 TWL4030_REG_AVDAC_CTL, 1, 0),
624 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
625 TWL4030_REG_AVDAC_CTL, 2, 0),
626 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
627 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e
SS		 628
629 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
630 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
631};
632
633static const struct snd_soc_dapm_route intercon[] = {
634 /* outputs */
53b5047d
PU		 635 {"OUTL", NULL, "DACL2"},
636 {"OUTR", NULL, "DACR2"},
cc17557e
SS		 637
638 /* inputs */
639 {"ADCL", NULL, "INL"},
640 {"ADCR", NULL, "INR"},
641};
642
643static int twl4030_add_widgets(struct snd_soc_codec *codec)
644{
645 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
646 ARRAY_SIZE(twl4030_dapm_widgets));
647
648 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
649
650 snd_soc_dapm_new_widgets(codec);
651 return 0;
652}
653
654static void twl4030_power_up(struct snd_soc_codec *codec)
655{
656 u8 anamicl, regmisc1, byte, popn, hsgain;
657 int i = 0;
658
659 /* set CODECPDZ to turn on codec */
660 twl4030_set_codecpdz(codec);
661
662 /* initiate offset cancellation */
663 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
664 twl4030_write(codec, TWL4030_REG_ANAMICL,
665 anamicl | TWL4030_CNCL_OFFSET_START);
666
667 /* wait for offset cancellation to complete */
668 do {
669 /* this takes a little while, so don't slam i2c */
670 udelay(2000);
671 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
672 TWL4030_REG_ANAMICL);
673 } while ((i++ < 100) &&
674 ((byte & TWL4030_CNCL_OFFSET_START) ==
675 TWL4030_CNCL_OFFSET_START));
676
677 /* anti-pop when changing analog gain */
678 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
679 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
680 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
681
682 /* toggle CODECPDZ as per TRM */
683 twl4030_clear_codecpdz(codec);
684 twl4030_set_codecpdz(codec);
685
686 /* program anti-pop with bias ramp delay */
687 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
688 popn &= TWL4030_RAMP_DELAY;
689 popn |= TWL4030_RAMP_DELAY_645MS;
690 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
691 popn |= TWL4030_VMID_EN;
692 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
693
694 /* enable output stage and gain setting */
695 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
696 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
697
698 /* enable anti-pop ramp */
699 popn |= TWL4030_RAMP_EN;
700 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
701}
702
703static void twl4030_power_down(struct snd_soc_codec *codec)
704{
705 u8 popn, hsgain;
706
707 /* disable anti-pop ramp */
708 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
709 popn &= ~TWL4030_RAMP_EN;
710 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
711
712 /* disable output stage and gain setting */
713 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
714 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
715
716 /* disable bias out */
717 popn &= ~TWL4030_VMID_EN;
718 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
719
720 /* power down */
721 twl4030_clear_codecpdz(codec);
722}
723
724static int twl4030_set_bias_level(struct snd_soc_codec *codec,
725 enum snd_soc_bias_level level)
726{
727 switch (level) {
728 case SND_SOC_BIAS_ON:
729 twl4030_power_up(codec);
730 break;
731 case SND_SOC_BIAS_PREPARE:
732 /* TODO: develop a twl4030_prepare function */
733 break;
734 case SND_SOC_BIAS_STANDBY:
735 /* TODO: develop a twl4030_standby function */
736 twl4030_power_down(codec);
737 break;
738 case SND_SOC_BIAS_OFF:
739 twl4030_power_down(codec);
740 break;
741 }
742 codec->bias_level = level;
743
744 return 0;
745}
746
747static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 748 struct snd_pcm_hw_params *params,
749 struct snd_soc_dai *dai)
cc17557e
SS		 750{
751 struct snd_soc_pcm_runtime *rtd = substream->private_data;
752 struct snd_soc_device *socdev = rtd->socdev;
753 struct snd_soc_codec *codec = socdev->codec;
754 u8 mode, old_mode, format, old_format;
755
756
757 /* bit rate */
758 old_mode = twl4030_read_reg_cache(codec,
759 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
760 mode = old_mode & ~TWL4030_APLL_RATE;
761
762 switch (params_rate(params)) {
763 case 8000:
764 mode |= TWL4030_APLL_RATE_8000;
765 break;
766 case 11025:
767 mode |= TWL4030_APLL_RATE_11025;
768 break;
769 case 12000:
770 mode |= TWL4030_APLL_RATE_12000;
771 break;
772 case 16000:
773 mode |= TWL4030_APLL_RATE_16000;
774 break;
775 case 22050:
776 mode |= TWL4030_APLL_RATE_22050;
777 break;
778 case 24000:
779 mode |= TWL4030_APLL_RATE_24000;
780 break;
781 case 32000:
782 mode |= TWL4030_APLL_RATE_32000;
783 break;
784 case 44100:
785 mode |= TWL4030_APLL_RATE_44100;
786 break;
787 case 48000:
788 mode |= TWL4030_APLL_RATE_48000;
789 break;
790 default:
791 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
792 params_rate(params));
793 return -EINVAL;
794 }
795
796 if (mode != old_mode) {
797 /* change rate and set CODECPDZ */
798 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
799 twl4030_set_codecpdz(codec);
800 }
801
802 /* sample size */
803 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
804 format = old_format;
805 format &= ~TWL4030_DATA_WIDTH;
806 switch (params_format(params)) {
807 case SNDRV_PCM_FORMAT_S16_LE:
808 format |= TWL4030_DATA_WIDTH_16S_16W;
809 break;
810 case SNDRV_PCM_FORMAT_S24_LE:
811 format |= TWL4030_DATA_WIDTH_32S_24W;
812 break;
813 default:
814 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
815 params_format(params));
816 return -EINVAL;
817 }
818
819 if (format != old_format) {
820
821 /* clear CODECPDZ before changing format (codec requirement) */
822 twl4030_clear_codecpdz(codec);
823
824 /* change format */
825 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
826
827 /* set CODECPDZ afterwards */
828 twl4030_set_codecpdz(codec);
829 }
830 return 0;
831}
832
833static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
834 int clk_id, unsigned int freq, int dir)
835{
836 struct snd_soc_codec *codec = codec_dai->codec;
837 u8 infreq;
838
839 switch (freq) {
840 case 19200000:
841 infreq = TWL4030_APLL_INFREQ_19200KHZ;
842 break;
843 case 26000000:
844 infreq = TWL4030_APLL_INFREQ_26000KHZ;
845 break;
846 case 38400000:
847 infreq = TWL4030_APLL_INFREQ_38400KHZ;
848 break;
849 default:
850 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
851 freq);
852 return -EINVAL;
853 }
854
855 infreq |= TWL4030_APLL_EN;
856 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
857
858 return 0;
859}
860
861static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
862 unsigned int fmt)
863{
864 struct snd_soc_codec *codec = codec_dai->codec;
865 u8 old_format, format;
866
867 /* get format */
868 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
869 format = old_format;
870
871 /* set master/slave audio interface */
872 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
873 case SND_SOC_DAIFMT_CBM_CFM:
874 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 875 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 876 break;
877 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 878 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 879 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 880 break;
881 default:
882 return -EINVAL;
883 }
884
885 /* interface format */
886 format &= ~TWL4030_AIF_FORMAT;
887 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
888 case SND_SOC_DAIFMT_I2S:
889 format |= TWL4030_AIF_FORMAT_CODEC;
890 break;
891 default:
892 return -EINVAL;
893 }
894
895 if (format != old_format) {
896
897 /* clear CODECPDZ before changing format (codec requirement) */
898 twl4030_clear_codecpdz(codec);
899
900 /* change format */
901 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
902
903 /* set CODECPDZ afterwards */
904 twl4030_set_codecpdz(codec);
905 }
906
907 return 0;
908}
909
bbba9444 910#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 911#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
912
913struct snd_soc_dai twl4030_dai = {
914 .name = "twl4030",
915 .playback = {
916 .stream_name = "Playback",
917 .channels_min = 2,
918 .channels_max = 2,
919 .rates = TWL4030_RATES,
920 .formats = TWL4030_FORMATS,},
921 .capture = {
922 .stream_name = "Capture",
923 .channels_min = 2,
924 .channels_max = 2,
925 .rates = TWL4030_RATES,
926 .formats = TWL4030_FORMATS,},
927 .ops = {
928 .hw_params = twl4030_hw_params,
cc17557e
SS		 929 .set_sysclk = twl4030_set_dai_sysclk,
930 .set_fmt = twl4030_set_dai_fmt,
931 }
932};
933EXPORT_SYMBOL_GPL(twl4030_dai);
934
935static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
936{
937 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
938 struct snd_soc_codec *codec = socdev->codec;
939
940 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
941
942 return 0;
943}
944
945static int twl4030_resume(struct platform_device *pdev)
946{
947 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
948 struct snd_soc_codec *codec = socdev->codec;
949
950 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
951 twl4030_set_bias_level(codec, codec->suspend_bias_level);
952 return 0;
953}
954
955/*
956 * initialize the driver
957 * register the mixer and dsp interfaces with the kernel
958 */
959
960static int twl4030_init(struct snd_soc_device *socdev)
961{
962 struct snd_soc_codec *codec = socdev->codec;
963 int ret = 0;
964
965 printk(KERN_INFO "TWL4030 Audio Codec init \n");
966
967 codec->name = "twl4030";
968 codec->owner = THIS_MODULE;
969 codec->read = twl4030_read_reg_cache;
970 codec->write = twl4030_write;
971 codec->set_bias_level = twl4030_set_bias_level;
972 codec->dai = &twl4030_dai;
973 codec->num_dai = 1;
974 codec->reg_cache_size = sizeof(twl4030_reg);
975 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
976 GFP_KERNEL);
977 if (codec->reg_cache == NULL)
978 return -ENOMEM;
979
980 /* register pcms */
981 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
982 if (ret < 0) {
983 printk(KERN_ERR "twl4030: failed to create pcms\n");
984 goto pcm_err;
985 }
986
987 twl4030_init_chip(codec);
988
989 /* power on device */
990 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
991
992 twl4030_add_controls(codec);
993 twl4030_add_widgets(codec);
994
968a6025 995 ret = snd_soc_init_card(socdev);
cc17557e
SS		 996 if (ret < 0) {
997 printk(KERN_ERR "twl4030: failed to register card\n");
998 goto card_err;
999 }
1000
1001 return ret;
1002
1003card_err:
1004 snd_soc_free_pcms(socdev);
1005 snd_soc_dapm_free(socdev);
1006pcm_err:
1007 kfree(codec->reg_cache);
1008 return ret;
1009}
1010
1011static struct snd_soc_device *twl4030_socdev;
1012
1013static int twl4030_probe(struct platform_device *pdev)
1014{
1015 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1016 struct snd_soc_codec *codec;
1017
1018 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1019 if (codec == NULL)
1020 return -ENOMEM;
1021
1022 socdev->codec = codec;
1023 mutex_init(&codec->mutex);
1024 INIT_LIST_HEAD(&codec->dapm_widgets);
1025 INIT_LIST_HEAD(&codec->dapm_paths);
1026
1027 twl4030_socdev = socdev;
1028 twl4030_init(socdev);
1029
1030 return 0;
1031}
1032
1033static int twl4030_remove(struct platform_device *pdev)
1034{
1035 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1036 struct snd_soc_codec *codec = socdev->codec;
1037
1038 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1039 kfree(codec);
1040
1041 return 0;
1042}
1043
1044struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1045 .probe = twl4030_probe,
1046 .remove = twl4030_remove,
1047 .suspend = twl4030_suspend,
1048 .resume = twl4030_resume,
1049};
1050EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1051
1052MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1053MODULE_AUTHOR("Steve Sakoman");
1054MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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