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ASoC: sdp3430: No need to configure the Voice port anymore
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad
LG		 43
44/* Shadow register used by the audio driver */
45#define TWL4030_REG_SW_SHADOW 0x4A
46#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
47
48/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
49#define TWL4030_HFL_EN 0x01
50#define TWL4030_HFR_EN 0x02
cc17557e
SS		 51
52/*
53 * twl4030 register cache & default register settings
54 */
55static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
56 0x00, /* this register not used */
33f92ed4 57 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 58 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 59 0x00, /* REG_UNKNOWN (0x3) */
60 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 61 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 62 0x00, /* REG_ANAMICR (0x6) */
63 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 64 0x00, /* REG_ADCMICSEL (0x8) */
65 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 66 0x0f, /* REG_ATXL1PGA (0xA) */
67 0x0f, /* REG_ATXR1PGA (0xB) */
68 0x0f, /* REG_AVTXL2PGA (0xC) */
69 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 70 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 71 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 72 0x3f, /* REG_ARXR1PGA (0x10) */
73 0x3f, /* REG_ARXL1PGA (0x11) */
74 0x3f, /* REG_ARXR2PGA (0x12) */
75 0x3f, /* REG_ARXL2PGA (0x13) */
76 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 77 0x00, /* REG_VSTPGA (0x15) */
78 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 79 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 80 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 81 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
82 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
83 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
84 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 85 0x00, /* REG_ATX2ARXPGA (0x1D) */
86 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 87 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 88 0x00, /* REG_BTSTPGA (0x20) */
89 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 90 0x00, /* REG_HS_SEL (0x22) */
91 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 92 0x00, /* REG_HS_POPN_SET (0x24) */
93 0x00, /* REG_PREDL_CTL (0x25) */
94 0x00, /* REG_PREDR_CTL (0x26) */
95 0x00, /* REG_PRECKL_CTL (0x27) */
96 0x00, /* REG_PRECKR_CTL (0x28) */
97 0x00, /* REG_HFL_CTL (0x29) */
98 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 99 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 100 0x00, /* REG_ALC_SET1 (0x2C) */
101 0x00, /* REG_ALC_SET2 (0x2D) */
102 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 103 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 104 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 105 0x00, /* REG_DTMF_TONEXT1H (0x31) */
106 0x00, /* REG_DTMF_TONEXT1L (0x32) */
107 0x00, /* REG_DTMF_TONEXT2H (0x33) */
108 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 109 0x79, /* REG_DTMF_TONOFF (0x35) */
110 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 111 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
112 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
113 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 114 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 115 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 116 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
117 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 118 0x00, /* REG_MISC_SET_1 (0x3E) */
119 0x00, /* REG_PCMBTMUX (0x3F) */
120 0x00, /* not used (0x40) */
121 0x00, /* not used (0x41) */
122 0x00, /* not used (0x42) */
123 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 124 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 125 0x00, /* REG_VIBRA_CTL (0x45) */
126 0x00, /* REG_VIBRA_SET (0x46) */
127 0x00, /* REG_VIBRA_PWM_SET (0x47) */
128 0x00, /* REG_ANAMIC_GAIN (0x48) */
129 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 130 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 131};
132
7393958f
PU		 133/* codec private data */
134struct twl4030_priv {
7a1fecf5
PU		 135 struct snd_soc_codec codec;
136
7393958f 137 unsigned int codec_powered;
7b4c734e
PU		 138
139 /* reference counts of AIF/APLL users */
2845fa13 140 unsigned int apll_enabled;
7220b9f4
PU		 141
142 struct snd_pcm_substream *master_substream;
143 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 144
145 unsigned int configured;
146 unsigned int rate;
147 unsigned int sample_bits;
148 unsigned int channels;
6943c92e
PU		 149
150 unsigned int sysclk;
151
c96907f2
PU		 152 /* Output (with associated amp) states */
153 u8 hsl_enabled, hsr_enabled;
154 u8 earpiece_enabled;
155 u8 predrivel_enabled, predriver_enabled;
156 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2 157
182f73f6 158 struct twl4030_codec_data *pdata;
7393958f
PU		 159};
160
cc17557e
SS		 161/*
162 * read twl4030 register cache
163 */
164static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
165 unsigned int reg)
166{
d08664fd 167 u8 *cache = codec->reg_cache;
cc17557e 168
91432e97
IM		 169 if (reg >= TWL4030_CACHEREGNUM)
170 return -EIO;
171
cc17557e
SS		 172 return cache[reg];
173}
174
175/*
176 * write twl4030 register cache
177 */
178static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
179 u8 reg, u8 value)
180{
181 u8 *cache = codec->reg_cache;
182
183 if (reg >= TWL4030_CACHEREGNUM)
184 return;
185 cache[reg] = value;
186}
187
188/*
189 * write to the twl4030 register space
190 */
191static int twl4030_write(struct snd_soc_codec *codec,
192 unsigned int reg, unsigned int value)
193{
b2c812e2 194 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 195 int write_to_reg = 0;
196
cc17557e 197 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 198 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
199 /* Decide if the given register can be written */
200 switch (reg) {
201 case TWL4030_REG_EAR_CTL:
202 if (twl4030->earpiece_enabled)
203 write_to_reg = 1;
204 break;
205 case TWL4030_REG_PREDL_CTL:
206 if (twl4030->predrivel_enabled)
207 write_to_reg = 1;
208 break;
209 case TWL4030_REG_PREDR_CTL:
210 if (twl4030->predriver_enabled)
211 write_to_reg = 1;
212 break;
213 case TWL4030_REG_PRECKL_CTL:
214 if (twl4030->carkitl_enabled)
215 write_to_reg = 1;
216 break;
217 case TWL4030_REG_PRECKR_CTL:
218 if (twl4030->carkitr_enabled)
219 write_to_reg = 1;
220 break;
221 case TWL4030_REG_HS_GAIN_SET:
222 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
223 write_to_reg = 1;
224 break;
225 default:
226 /* All other register can be written */
227 write_to_reg = 1;
228 break;
229 }
230 if (write_to_reg)
231 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
232 value, reg);
233 }
234 return 0;
cc17557e
SS		 235}
236
7e6120c5
PU		 237static inline void twl4030_wait_ms(int time)
238{
239 if (time < 60) {
240 time *= 1000;
241 usleep_range(time, time + 500);
242 } else {
243 msleep(time);
244 }
245}
246
db04e2c5 247static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 248{
b2c812e2 249 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 250 int mode;
cc17557e 251
7393958f
PU		 252 if (enable == twl4030->codec_powered)
253 return;
254
db04e2c5 255 if (enable)
57fe7251 256 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 257 else
57fe7251 258 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 259
7a1fecf5
PU		 260 if (mode >= 0) {
261 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
262 twl4030->codec_powered = enable;
263 }
cc17557e
SS		 264
265 /* REVISIT: this delay is present in TI sample drivers */
266 /* but there seems to be no TRM requirement for it */
267 udelay(10);
268}
269
9fdcc0f7 270static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 271{
9fdcc0f7
PU		 272 int i, difference = 0;
273 u8 val;
274
275 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
276 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
277 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
278 if (val != twl4030_reg[i]) {
279 difference++;
280 dev_dbg(codec->dev,
281 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
282 i, val, twl4030_reg[i]);
283 }
284 }
25985edc 285 dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
9fdcc0f7
PU		 286 difference, difference ? "Not OK" : "OK");
287}
cc17557e 288
a3a29b55
PU		 289static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
290{
291 int i;
cc17557e
SS		 292
293 /* set all audio section registers to reasonable defaults */
294 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 295 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 296 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 297
298}
299
2d6d649a
PU		 300static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
301 struct device_node *node)
302{
303 int value;
304
305 of_property_read_u32(node, "ti,digimic_delay",
306 &pdata->digimic_delay);
307 of_property_read_u32(node, "ti,ramp_delay_value",
308 &pdata->ramp_delay_value);
309 of_property_read_u32(node, "ti,offset_cncl_path",
310 &pdata->offset_cncl_path);
311 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
312 pdata->hs_extmute = value;
313
314 pdata->hs_extmute_gpio = of_get_named_gpio(node,
315 "ti,hs_extmute_gpio", 0);
316 if (gpio_is_valid(pdata->hs_extmute_gpio))
317 pdata->hs_extmute = 1;
318}
319
320static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 321{
4ae6df5e 322 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 323 struct device_node *twl4030_codec_node = NULL;
324
325 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
326 "codec");
327
328 if (!pdata && twl4030_codec_node) {
329 pdata = devm_kzalloc(codec->dev,
330 sizeof(struct twl4030_codec_data),
331 GFP_KERNEL);
332 if (!pdata) {
333 dev_err(codec->dev, "Can not allocate memory\n");
334 return NULL;
335 }
336 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
337 }
338
339 return pdata;
340}
341
342static void twl4030_init_chip(struct snd_soc_codec *codec)
343{
344 struct twl4030_codec_data *pdata;
b2c812e2 345 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 346 u8 reg, byte;
347 int i = 0;
7393958f 348
2d6d649a
PU		 349 pdata = twl4030_get_pdata(codec);
350
281ecd16
PU		 351 if (pdata && pdata->hs_extmute &&
352 gpio_is_valid(pdata->hs_extmute_gpio)) {
353 int ret;
354
355 if (!pdata->hs_extmute_gpio)
356 dev_warn(codec->dev,
357 "Extmute GPIO is 0 is this correct?\n");
358
359 ret = gpio_request_one(pdata->hs_extmute_gpio,
360 GPIOF_OUT_INIT_LOW, "hs_extmute");
361 if (ret) {
362 dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
363 pdata->hs_extmute_gpio = -1;
364 }
365 }
366
9fdcc0f7 367 /* Check defaults, if instructed before anything else */
f0fba2ad 368 if (pdata && pdata->check_defaults)
9fdcc0f7 369 twl4030_check_defaults(codec);
7a1fecf5 370
a3a29b55 371 /* Reset registers, if no setup data or if instructed to do so */
f0fba2ad 372 if (!pdata || (pdata && pdata->reset_registers))
a3a29b55 373 twl4030_reset_registers(codec);
7393958f 374
ee4ccac7 375 /* Refresh APLL_CTL register from HW */
9fdcc0f7 376 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 377 TWL4030_REG_APLL_CTL);
378 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 379
ee4ccac7
PU		 380 /* anti-pop when changing analog gain */
381 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
382 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
383 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 384
ee4ccac7
PU		 385 twl4030_write(codec, TWL4030_REG_OPTION,
386 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
387 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 388
3c36cc68
PU		 389 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
390 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
391
ee4ccac7 392 /* Machine dependent setup */
f0fba2ad 393 if (!pdata)
7393958f
PU		 394 return;
395
182f73f6 396 twl4030->pdata = pdata;
ee4ccac7
PU		 397
398 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
399 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 400 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 401 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 402
403 /* initiate offset cancellation */
ee4ccac7
PU		 404 twl4030_codec_enable(codec, 1);
405
406 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
407 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 408 reg |= pdata->offset_cncl_path;
006f367e 409 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 410 reg | TWL4030_CNCL_OFFSET_START);
006f367e 411
7e6120c5
PU		 412 /*
413 * Wait for offset cancellation to complete.
414 * Since this takes a while, do not slam the i2c.
415 * Start polling the status after ~20ms.
416 */
417 msleep(20);
006f367e 418 do {
7e6120c5 419 usleep_range(1000, 2000);
fc7b92fc 420 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 421 TWL4030_REG_ANAMICL);
422 } while ((i++ < 100) &&
423 ((byte & TWL4030_CNCL_OFFSET_START) ==
424 TWL4030_CNCL_OFFSET_START));
425
426 /* Make sure that the reg_cache has the same value as the HW */
427 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
428
006f367e 429 twl4030_codec_enable(codec, 0);
006f367e
PU		 430}
431
ee4ccac7 432static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 433{
ee4ccac7
PU		 434 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
435 int status = -1;
436
437 if (enable) {
438 twl4030->apll_enabled++;
439 if (twl4030->apll_enabled == 1)
57fe7251
PU		 440 status = twl4030_audio_enable_resource(
441 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 442 } else {
443 twl4030->apll_enabled--;
444 if (!twl4030->apll_enabled)
57fe7251
PU		 445 status = twl4030_audio_disable_resource(
446 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 447 }
448
449 if (status >= 0)
450 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 451}
452
5e98a464 453/* Earpiece */
1a787e7a
JS		 454static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
455 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
456 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
457 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
458 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
459};
5e98a464 460
2a6f5c58 461/* PreDrive Left */
1a787e7a
JS		 462static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
463 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
464 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
465 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
466 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
467};
2a6f5c58
PU		 468
469/* PreDrive Right */
1a787e7a
JS		 470static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
471 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
472 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
473 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
474 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
475};
2a6f5c58 476
dfad21a2 477/* Headset Left */
1a787e7a
JS		 478static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
479 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
480 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
481 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
482};
dfad21a2
PU		 483
484/* Headset Right */
1a787e7a
JS		 485static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
486 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
487 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
488 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
489};
dfad21a2 490
5152d8c2 491/* Carkit Left */
1a787e7a
JS		 492static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
493 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
494 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
495 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
496};
5152d8c2
PU		 497
498/* Carkit Right */
1a787e7a
JS		 499static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
500 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
501 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
502 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
503};
5152d8c2 504
df339804
PU		 505/* Handsfree Left */
506static const char *twl4030_handsfreel_texts[] =
1a787e7a 507 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 508
509static const struct soc_enum twl4030_handsfreel_enum =
510 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
511 ARRAY_SIZE(twl4030_handsfreel_texts),
512 twl4030_handsfreel_texts);
513
514static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
515SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
516
0f89bdca
PU		 517/* Handsfree Left virtual mute */
518static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
519 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
520
df339804
PU		 521/* Handsfree Right */
522static const char *twl4030_handsfreer_texts[] =
1a787e7a 523 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 524
525static const struct soc_enum twl4030_handsfreer_enum =
526 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
527 ARRAY_SIZE(twl4030_handsfreer_texts),
528 twl4030_handsfreer_texts);
529
530static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
531SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
532
0f89bdca
PU		 533/* Handsfree Right virtual mute */
534static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
535 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
536
376f7839
PU		 537/* Vibra */
538/* Vibra audio path selection */
539static const char *twl4030_vibra_texts[] =
540 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
541
542static const struct soc_enum twl4030_vibra_enum =
543 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
544 ARRAY_SIZE(twl4030_vibra_texts),
545 twl4030_vibra_texts);
546
547static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
548SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
549
550/* Vibra path selection: local vibrator (PWM) or audio driven */
551static const char *twl4030_vibrapath_texts[] =
552 {"Local vibrator", "Audio"};
553
554static const struct soc_enum twl4030_vibrapath_enum =
555 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
556 ARRAY_SIZE(twl4030_vibrapath_texts),
557 twl4030_vibrapath_texts);
558
559static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
560SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
561
276c6222 562/* Left analog microphone selection */
97b8096d 563static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 564 SOC_DAPM_SINGLE("Main Mic Capture Switch",
565 TWL4030_REG_ANAMICL, 0, 1, 0),
566 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
567 TWL4030_REG_ANAMICL, 1, 1, 0),
568 SOC_DAPM_SINGLE("AUXL Capture Switch",
569 TWL4030_REG_ANAMICL, 2, 1, 0),
570 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
571 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 572};
276c6222
PU		 573
574/* Right analog microphone selection */
97b8096d 575static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 576 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
577 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 578};
276c6222
PU		 579
580/* TX1 L/R Analog/Digital microphone selection */
581static const char *twl4030_micpathtx1_texts[] =
582 {"Analog", "Digimic0"};
583
584static const struct soc_enum twl4030_micpathtx1_enum =
585 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
586 ARRAY_SIZE(twl4030_micpathtx1_texts),
587 twl4030_micpathtx1_texts);
588
589static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
590SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
591
592/* TX2 L/R Analog/Digital microphone selection */
593static const char *twl4030_micpathtx2_texts[] =
594 {"Analog", "Digimic1"};
595
596static const struct soc_enum twl4030_micpathtx2_enum =
597 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
598 ARRAY_SIZE(twl4030_micpathtx2_texts),
599 twl4030_micpathtx2_texts);
600
601static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
602SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
603
7393958f
PU		 604/* Analog bypass for AudioR1 */
605static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
606 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
607
608/* Analog bypass for AudioL1 */
609static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
610 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
611
612/* Analog bypass for AudioR2 */
613static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
614 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
615
616/* Analog bypass for AudioL2 */
617static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
618 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
619
fcd274a3
LCM		 620/* Analog bypass for Voice */
621static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
622 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
623
8b0d3153 624/* Digital bypass gain, mute instead of -30dB */
6bab83fd 625static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 626 TLV_DB_RANGE_HEAD(3),
627 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
628 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 629 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
630};
631
632/* Digital bypass left (TX1L -> RX2L) */
633static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
634 SOC_DAPM_SINGLE_TLV("Volume",
635 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
636 twl4030_dapm_dbypass_tlv);
637
638/* Digital bypass right (TX1R -> RX2R) */
639static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
640 SOC_DAPM_SINGLE_TLV("Volume",
641 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
642 twl4030_dapm_dbypass_tlv);
643
ee8f6894
LCM		 644/*
645 * Voice Sidetone GAIN volume control:
646 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
647 */
648static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
649
650/* Digital bypass voice: sidetone (VUL -> VDL)*/
651static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
652 SOC_DAPM_SINGLE_TLV("Volume",
653 TWL4030_REG_VSTPGA, 0, 0x29, 0,
654 twl4030_dapm_dbypassv_tlv);
655
9008adf9
PU		 656/*
657 * Output PGA builder:
658 * Handle the muting and unmuting of the given output (turning off the
659 * amplifier associated with the output pin)
c96907f2
PU		 660 * On mute bypass the reg_cache and write 0 to the register
661 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 662 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
663 */
664#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
665static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
666 struct snd_kcontrol *kcontrol, int event) \
667{ \
b2c812e2 668 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 669 \
670 switch (event) { \
671 case SND_SOC_DAPM_POST_PMU: \
c96907f2 672 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 673 twl4030_write(w->codec, reg, \
674 twl4030_read_reg_cache(w->codec, reg)); \
675 break; \
676 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 677 twl4030->pin_name##_enabled = 0; \
678 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
679 0, reg); \
9008adf9
PU		 680 break; \
681 } \
682 return 0; \
683}
684
685TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
686TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
687TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
688TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
689TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
690
5a2e9a48 691static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 692{
49d92c7d
SM		 693 unsigned char hs_ctl;
694
5a2e9a48 695 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 696
5a2e9a48
PU		 697 if (ramp) {
698 /* HF ramp-up */
699 hs_ctl |= TWL4030_HF_CTL_REF_EN;
700 twl4030_write(codec, reg, hs_ctl);
701 udelay(10);
49d92c7d 702 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 703 twl4030_write(codec, reg, hs_ctl);
704 udelay(40);
49d92c7d 705 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 706 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 707 twl4030_write(codec, reg, hs_ctl);
49d92c7d 708 } else {
5a2e9a48
PU		 709 /* HF ramp-down */
710 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
711 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
712 twl4030_write(codec, reg, hs_ctl);
713 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
714 twl4030_write(codec, reg, hs_ctl);
715 udelay(40);
716 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
717 twl4030_write(codec, reg, hs_ctl);
49d92c7d 718 }
5a2e9a48 719}
49d92c7d 720
5a2e9a48
PU		 721static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
722 struct snd_kcontrol *kcontrol, int event)
723{
724 switch (event) {
725 case SND_SOC_DAPM_POST_PMU:
726 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
727 break;
728 case SND_SOC_DAPM_POST_PMD:
729 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
730 break;
731 }
732 return 0;
733}
734
735static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
736 struct snd_kcontrol *kcontrol, int event)
737{
738 switch (event) {
739 case SND_SOC_DAPM_POST_PMU:
740 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
741 break;
742 case SND_SOC_DAPM_POST_PMD:
743 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
744 break;
745 }
49d92c7d
SM		 746 return 0;
747}
748
86139a13
JV		 749static int vibramux_event(struct snd_soc_dapm_widget *w,
750 struct snd_kcontrol *kcontrol, int event)
751{
752 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
753 return 0;
754}
755
7729cf74
PU		 756static int apll_event(struct snd_soc_dapm_widget *w,
757 struct snd_kcontrol *kcontrol, int event)
758{
759 switch (event) {
760 case SND_SOC_DAPM_PRE_PMU:
761 twl4030_apll_enable(w->codec, 1);
762 break;
763 case SND_SOC_DAPM_POST_PMD:
764 twl4030_apll_enable(w->codec, 0);
765 break;
766 }
767 return 0;
768}
769
7b4c734e
PU		 770static int aif_event(struct snd_soc_dapm_widget *w,
771 struct snd_kcontrol *kcontrol, int event)
772{
773 u8 audio_if;
774
775 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
776 switch (event) {
777 case SND_SOC_DAPM_PRE_PMU:
778 /* Enable AIF */
779 /* enable the PLL before we use it to clock the DAI */
780 twl4030_apll_enable(w->codec, 1);
781
782 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
783 audio_if | TWL4030_AIF_EN);
784 break;
785 case SND_SOC_DAPM_POST_PMD:
786 /* disable the DAI before we stop it's source PLL */
787 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
788 audio_if & ~TWL4030_AIF_EN);
789 twl4030_apll_enable(w->codec, 0);
790 break;
791 }
792 return 0;
793}
794
6943c92e 795static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 796{
797 unsigned char hs_gain, hs_pop;
b2c812e2 798 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 799 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 800 /* Base values for ramp delay calculation: 2^19 - 2^26 */
801 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
802 8388608, 16777216, 33554432, 67108864};
7e6120c5 803 unsigned int delay;
aad749e5 804
6943c92e
PU		 805 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
806 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 807 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
808 twl4030->sysclk) + 1;
aad749e5 809
4e49ffd1
CVJ		 810 /* Enable external mute control, this dramatically reduces
811 * the pop-noise */
f0fba2ad 812 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 813 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
814 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 815 } else {
816 hs_pop |= TWL4030_EXTMUTE;
817 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
818 }
819 }
820
6943c92e
PU		 821 if (ramp) {
822 /* Headset ramp-up according to the TRM */
aad749e5 823 hs_pop |= TWL4030_VMID_EN;
6943c92e 824 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 825 /* Actually write to the register */
826 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
827 hs_gain,
828 TWL4030_REG_HS_GAIN_SET);
aad749e5 829 hs_pop |= TWL4030_RAMP_EN;
6943c92e 830 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 831 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 832 twl4030_wait_ms(delay);
6943c92e
PU		 833 } else {
834 /* Headset ramp-down _not_ according to
835 * the TRM, but in a way that it is working */
aad749e5 836 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 837 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
838 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 839 twl4030_wait_ms(delay);
aad749e5 840 /* Bypass the reg_cache to mute the headset */
fc7b92fc 841 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 842 hs_gain & (~0x0f),
843 TWL4030_REG_HS_GAIN_SET);
6943c92e 844
aad749e5 845 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 846 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
847 }
4e49ffd1
CVJ		 848
849 /* Disable external mute */
f0fba2ad 850 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 851 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
852 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 853 } else {
854 hs_pop &= ~TWL4030_EXTMUTE;
855 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
856 }
857 }
6943c92e
PU		 858}
859
860static int headsetlpga_event(struct snd_soc_dapm_widget *w,
861 struct snd_kcontrol *kcontrol, int event)
862{
b2c812e2 863 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 864
865 switch (event) {
866 case SND_SOC_DAPM_POST_PMU:
867 /* Do the ramp-up only once */
868 if (!twl4030->hsr_enabled)
869 headset_ramp(w->codec, 1);
870
871 twl4030->hsl_enabled = 1;
872 break;
873 case SND_SOC_DAPM_POST_PMD:
874 /* Do the ramp-down only if both headsetL/R is disabled */
875 if (!twl4030->hsr_enabled)
876 headset_ramp(w->codec, 0);
877
878 twl4030->hsl_enabled = 0;
879 break;
880 }
881 return 0;
882}
883
884static int headsetrpga_event(struct snd_soc_dapm_widget *w,
885 struct snd_kcontrol *kcontrol, int event)
886{
b2c812e2 887 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 888
889 switch (event) {
890 case SND_SOC_DAPM_POST_PMU:
891 /* Do the ramp-up only once */
892 if (!twl4030->hsl_enabled)
893 headset_ramp(w->codec, 1);
894
895 twl4030->hsr_enabled = 1;
896 break;
897 case SND_SOC_DAPM_POST_PMD:
898 /* Do the ramp-down only if both headsetL/R is disabled */
899 if (!twl4030->hsl_enabled)
900 headset_ramp(w->codec, 0);
901
902 twl4030->hsr_enabled = 0;
aad749e5
PU		 903 break;
904 }
905 return 0;
906}
907
01ea6ba2
PU		 908static int digimic_event(struct snd_soc_dapm_widget *w,
909 struct snd_kcontrol *kcontrol, int event)
910{
911 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 912 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 913
182f73f6
PU		 914 if (pdata && pdata->digimic_delay)
915 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 916 return 0;
917}
918
b0bd53a7
PU		 919/*
920 * Some of the gain controls in TWL (mostly those which are associated with
921 * the outputs) are implemented in an interesting way:
922 * 0x0 : Power down (mute)
923 * 0x1 : 6dB
924 * 0x2 : 0 dB
925 * 0x3 : -6 dB
926 * Inverting not going to help with these.
927 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
928 */
b0bd53a7
PU		 929static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
930 struct snd_ctl_elem_value *ucontrol)
931{
932 struct soc_mixer_control *mc =
933 (struct soc_mixer_control *)kcontrol->private_value;
934 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
935 unsigned int reg = mc->reg;
936 unsigned int shift = mc->shift;
937 unsigned int rshift = mc->rshift;
938 int max = mc->max;
939 int mask = (1 << fls(max)) - 1;
940
941 ucontrol->value.integer.value[0] =
942 (snd_soc_read(codec, reg) >> shift) & mask;
943 if (ucontrol->value.integer.value[0])
944 ucontrol->value.integer.value[0] =
945 max + 1 - ucontrol->value.integer.value[0];
946
947 if (shift != rshift) {
948 ucontrol->value.integer.value[1] =
949 (snd_soc_read(codec, reg) >> rshift) & mask;
950 if (ucontrol->value.integer.value[1])
951 ucontrol->value.integer.value[1] =
952 max + 1 - ucontrol->value.integer.value[1];
953 }
954
955 return 0;
956}
957
958static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
959 struct snd_ctl_elem_value *ucontrol)
960{
961 struct soc_mixer_control *mc =
962 (struct soc_mixer_control *)kcontrol->private_value;
963 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
964 unsigned int reg = mc->reg;
965 unsigned int shift = mc->shift;
966 unsigned int rshift = mc->rshift;
967 int max = mc->max;
968 int mask = (1 << fls(max)) - 1;
969 unsigned short val, val2, val_mask;
970
971 val = (ucontrol->value.integer.value[0] & mask);
972
973 val_mask = mask << shift;
974 if (val)
975 val = max + 1 - val;
976 val = val << shift;
977 if (shift != rshift) {
978 val2 = (ucontrol->value.integer.value[1] & mask);
979 val_mask |= mask << rshift;
980 if (val2)
981 val2 = max + 1 - val2;
982 val |= val2 << rshift;
983 }
984 return snd_soc_update_bits(codec, reg, val_mask, val);
985}
986
987static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
988 struct snd_ctl_elem_value *ucontrol)
989{
990 struct soc_mixer_control *mc =
991 (struct soc_mixer_control *)kcontrol->private_value;
992 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
993 unsigned int reg = mc->reg;
994 unsigned int reg2 = mc->rreg;
995 unsigned int shift = mc->shift;
996 int max = mc->max;
997 int mask = (1<<fls(max))-1;
998
999 ucontrol->value.integer.value[0] =
1000 (snd_soc_read(codec, reg) >> shift) & mask;
1001 ucontrol->value.integer.value[1] =
1002 (snd_soc_read(codec, reg2) >> shift) & mask;
1003
1004 if (ucontrol->value.integer.value[0])
1005 ucontrol->value.integer.value[0] =
1006 max + 1 - ucontrol->value.integer.value[0];
1007 if (ucontrol->value.integer.value[1])
1008 ucontrol->value.integer.value[1] =
1009 max + 1 - ucontrol->value.integer.value[1];
1010
1011 return 0;
1012}
1013
1014static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1015 struct snd_ctl_elem_value *ucontrol)
1016{
1017 struct soc_mixer_control *mc =
1018 (struct soc_mixer_control *)kcontrol->private_value;
1019 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1020 unsigned int reg = mc->reg;
1021 unsigned int reg2 = mc->rreg;
1022 unsigned int shift = mc->shift;
1023 int max = mc->max;
1024 int mask = (1 << fls(max)) - 1;
1025 int err;
1026 unsigned short val, val2, val_mask;
1027
1028 val_mask = mask << shift;
1029 val = (ucontrol->value.integer.value[0] & mask);
1030 val2 = (ucontrol->value.integer.value[1] & mask);
1031
1032 if (val)
1033 val = max + 1 - val;
1034 if (val2)
1035 val2 = max + 1 - val2;
1036
1037 val = val << shift;
1038 val2 = val2 << shift;
1039
1040 err = snd_soc_update_bits(codec, reg, val_mask, val);
1041 if (err < 0)
1042 return err;
1043
1044 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1045 return err;
1046}
1047
b74bd40f
LCM		 1048/* Codec operation modes */
1049static const char *twl4030_op_modes_texts[] = {
1050 "Option 2 (voice/audio)", "Option 1 (audio)"
1051};
1052
1053static const struct soc_enum twl4030_op_modes_enum =
1054 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1055 ARRAY_SIZE(twl4030_op_modes_texts),
1056 twl4030_op_modes_texts);
1057
423c238d 1058static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1059 struct snd_ctl_elem_value *ucontrol)
1060{
1061 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1062 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1063 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1064 unsigned short val;
86767b7d 1065 unsigned short mask;
b74bd40f
LCM		 1066
1067 if (twl4030->configured) {
3b8a0795
PU		 1068 dev_err(codec->dev,
1069 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 1070 return -EBUSY;
1071 }
1072
b74bd40f
LCM		 1073 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1074 return -EINVAL;
1075
1076 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 1077 mask = e->mask << e->shift_l;
b74bd40f
LCM		 1078 if (e->shift_l != e->shift_r) {
1079 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1080 return -EINVAL;
1081 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 1082 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 1083 }
1084
1085 return snd_soc_update_bits(codec, e->reg, mask, val);
1086}
1087
c10b82cf
PU		 1088/*
1089 * FGAIN volume control:
1090 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1091 */
d889a72c 1092static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1093
0d33ea0b
PU		 1094/*
1095 * CGAIN volume control:
1096 * 0 dB to 12 dB in 6 dB steps
1097 * value 2 and 3 means 12 dB
1098 */
d889a72c
PU		 1099static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1100
1a787e7a
JS		 1101/*
1102 * Voice Downlink GAIN volume control:
1103 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1104 */
1105static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1106
d889a72c
PU		 1107/*
1108 * Analog playback gain
1109 * -24 dB to 12 dB in 2 dB steps
1110 */
1111static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1112
4290239c
PU		 1113/*
1114 * Gain controls tied to outputs
1115 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1116 */
1117static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1118
18cc8d8d
JS		 1119/*
1120 * Gain control for earpiece amplifier
1121 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1122 */
1123static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1124
381a22b5
PU		 1125/*
1126 * Capture gain after the ADCs
1127 * from 0 dB to 31 dB in 1 dB steps
1128 */
1129static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1130
5920b453
GI		 1131/*
1132 * Gain control for input amplifiers
1133 * 0 dB to 30 dB in 6 dB steps
1134 */
1135static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1136
328d0a13
LCM		 1137/* AVADC clock priority */
1138static const char *twl4030_avadc_clk_priority_texts[] = {
1139 "Voice high priority", "HiFi high priority"
1140};
1141
1142static const struct soc_enum twl4030_avadc_clk_priority_enum =
1143 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1144 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1145 twl4030_avadc_clk_priority_texts);
1146
89492be8
PU		 1147static const char *twl4030_rampdelay_texts[] = {
1148 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1149 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1150 "3495/2581/1748 ms"
1151};
1152
1153static const struct soc_enum twl4030_rampdelay_enum =
1154 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1155 ARRAY_SIZE(twl4030_rampdelay_texts),
1156 twl4030_rampdelay_texts);
1157
376f7839
PU		 1158/* Vibra H-bridge direction mode */
1159static const char *twl4030_vibradirmode_texts[] = {
1160 "Vibra H-bridge direction", "Audio data MSB",
1161};
1162
1163static const struct soc_enum twl4030_vibradirmode_enum =
1164 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1165 ARRAY_SIZE(twl4030_vibradirmode_texts),
1166 twl4030_vibradirmode_texts);
1167
1168/* Vibra H-bridge direction */
1169static const char *twl4030_vibradir_texts[] = {
1170 "Positive polarity", "Negative polarity",
1171};
1172
1173static const struct soc_enum twl4030_vibradir_enum =
1174 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1175 ARRAY_SIZE(twl4030_vibradir_texts),
1176 twl4030_vibradir_texts);
1177
36aeff61
PU		 1178/* Digimic Left and right swapping */
1179static const char *twl4030_digimicswap_texts[] = {
1180 "Not swapped", "Swapped",
1181};
1182
1183static const struct soc_enum twl4030_digimicswap_enum =
1184 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1185 ARRAY_SIZE(twl4030_digimicswap_texts),
1186 twl4030_digimicswap_texts);
1187
cc17557e 1188static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1189 /* Codec operation mode control */
1190 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1191 snd_soc_get_enum_double,
1192 snd_soc_put_twl4030_opmode_enum_double),
1193
d889a72c
PU		 1194 /* Common playback gain controls */
1195 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1196 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1197 0, 0x3f, 0, digital_fine_tlv),
1198 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1199 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1200 0, 0x3f, 0, digital_fine_tlv),
1201
1202 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1203 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1204 6, 0x2, 0, digital_coarse_tlv),
1205 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1206 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1207 6, 0x2, 0, digital_coarse_tlv),
1208
1209 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1210 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1211 3, 0x12, 1, analog_tlv),
1212 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1213 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1214 3, 0x12, 1, analog_tlv),
44c55870
PU		 1215 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1216 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1217 1, 1, 0),
1218 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1219 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1220 1, 1, 0),
381a22b5 1221
1a787e7a
JS		 1222 /* Common voice downlink gain controls */
1223 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1224 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1225
1226 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1227 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1228
1229 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1230 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1231
4290239c 1232 /* Separate output gain controls */
0f9887d1 1233 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1234 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1235 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1236 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1237
0f9887d1
PU		 1238 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1239 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1240 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1241
0f9887d1 1242 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1243 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1244 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1245 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1246
0f9887d1
PU		 1247 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1248 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1249 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1250
381a22b5 1251 /* Common capture gain controls */
276c6222 1252 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1253 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1254 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1255 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1256 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1257 0, 0x1f, 0, digital_capture_tlv),
5920b453 1258
276c6222 1259 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1260 0, 3, 5, 0, input_gain_tlv),
89492be8 1261
328d0a13
LCM		 1262 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1263
89492be8 1264 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1265
1266 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1267 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1268
1269 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1270};
1271
cc17557e 1272static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1273 /* Left channel inputs */
1274 SND_SOC_DAPM_INPUT("MAINMIC"),
1275 SND_SOC_DAPM_INPUT("HSMIC"),
1276 SND_SOC_DAPM_INPUT("AUXL"),
1277 SND_SOC_DAPM_INPUT("CARKITMIC"),
1278 /* Right channel inputs */
1279 SND_SOC_DAPM_INPUT("SUBMIC"),
1280 SND_SOC_DAPM_INPUT("AUXR"),
1281 /* Digital microphones (Stereo) */
1282 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1283 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1284
1285 /* Outputs */
5e98a464 1286 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1287 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1288 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1289 SND_SOC_DAPM_OUTPUT("HSOL"),
1290 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1291 SND_SOC_DAPM_OUTPUT("CARKITL"),
1292 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1293 SND_SOC_DAPM_OUTPUT("HFL"),
1294 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1295 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1296
7b4c734e
PU		 1297 /* AIF and APLL clocks for running DAIs (including loopback) */
1298 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1299 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1300 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1301
53b5047d 1302 /* DACs */
7f51e7d3
PU		 1303 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1304 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1305 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1306 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1307 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1308
927a7747
PU		 1309 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1310 TWL4030_REG_VOICE_IF, 6, 0),
1311
7393958f 1312 /* Analog bypasses */
78e08e2f
PU		 1313 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1314 &twl4030_dapm_abypassr1_control),
1315 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1316 &twl4030_dapm_abypassl1_control),
1317 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1318 &twl4030_dapm_abypassr2_control),
1319 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1320 &twl4030_dapm_abypassl2_control),
1321 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1322 &twl4030_dapm_abypassv_control),
1323
1324 /* Master analog loopback switch */
1325 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1326 NULL, 0),
7393958f 1327
6bab83fd 1328 /* Digital bypasses */
78e08e2f
PU		 1329 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1330 &twl4030_dapm_dbypassl_control),
1331 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1332 &twl4030_dapm_dbypassr_control),
1333 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1334 &twl4030_dapm_dbypassv_control),
6bab83fd 1335
4005d39a
PU		 1336 /* Digital mixers, power control for the physical DACs */
1337 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1338 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1339 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1340 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1341 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1342 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1343 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1344 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1345 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1346 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1347
1348 /* Analog mixers, power control for the physical PGAs */
1349 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1350 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1351 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1352 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1353 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1354 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1355 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1356 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1357 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1358 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1359
7729cf74
PU		 1360 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1361 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1362
7b4c734e
PU		 1363 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1364 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1365
1a787e7a 1366 /* Output MIXER controls */
5e98a464 1367 /* Earpiece */
1a787e7a
JS		 1368 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1369 &twl4030_dapm_earpiece_controls[0],
1370 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1371 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1372 0, 0, NULL, 0, earpiecepga_event,
1373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1374 /* PreDrivL/R */
1a787e7a
JS		 1375 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1376 &twl4030_dapm_predrivel_controls[0],
1377 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1378 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1379 0, 0, NULL, 0, predrivelpga_event,
1380 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1381 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1382 &twl4030_dapm_predriver_controls[0],
1383 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1384 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1385 0, 0, NULL, 0, predriverpga_event,
1386 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1387 /* HeadsetL/R */
6943c92e 1388 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1389 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1390 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1391 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1392 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1393 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1394 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1395 &twl4030_dapm_hsor_controls[0],
1396 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1397 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1398 0, 0, NULL, 0, headsetrpga_event,
1399 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1400 /* CarkitL/R */
1a787e7a
JS		 1401 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1402 &twl4030_dapm_carkitl_controls[0],
1403 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1404 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1405 0, 0, NULL, 0, carkitlpga_event,
1406 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1407 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1408 &twl4030_dapm_carkitr_controls[0],
1409 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1410 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1411 0, 0, NULL, 0, carkitrpga_event,
1412 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1413
1414 /* Output MUX controls */
df339804 1415 /* HandsfreeL/R */
5a2e9a48
PU		 1416 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1417 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1418 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1419 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1420 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1421 0, 0, NULL, 0, handsfreelpga_event,
1422 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1423 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1424 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1425 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1426 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1427 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1428 0, 0, NULL, 0, handsfreerpga_event,
1429 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1430 /* Vibra */
86139a13
JV		 1431 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1432 &twl4030_dapm_vibra_control, vibramux_event,
1433 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1434 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1435 &twl4030_dapm_vibrapath_control),
5e98a464 1436
276c6222
PU		 1437 /* Introducing four virtual ADC, since TWL4030 have four channel for
1438 capture */
7f51e7d3
PU		 1439 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1440 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1441 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1442 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1443
927a7747
PU		 1444 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1445 TWL4030_REG_VOICE_IF, 5, 0),
1446
276c6222
PU		 1447 /* Analog/Digital mic path selection.
1448 TX1 Left/Right: either analog Left/Right or Digimic0
1449 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1450 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1451 &twl4030_dapm_micpathtx1_control),
1452 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1453 &twl4030_dapm_micpathtx2_control),
276c6222 1454
97b8096d 1455 /* Analog input mixers for the capture amplifiers */
9028935d 1456 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1457 TWL4030_REG_ANAMICL, 4, 0,
1458 &twl4030_dapm_analoglmic_controls[0],
1459 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1460 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1461 TWL4030_REG_ANAMICR, 4, 0,
1462 &twl4030_dapm_analogrmic_controls[0],
1463 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1464
fb2a2f84
PU		 1465 SND_SOC_DAPM_PGA("ADC Physical Left",
1466 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1467 SND_SOC_DAPM_PGA("ADC Physical Right",
1468 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1469
01ea6ba2
PU		 1470 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1471 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1472 digimic_event, SND_SOC_DAPM_POST_PMU),
1473 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1474 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1475 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1476
bda7d2a8
PU		 1477 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1478 NULL, 0),
1479 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1480 NULL, 0),
1481
276c6222
PU		 1482 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1483 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1484 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1485
927a7747 1486 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1487};
1488
1489static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1490 /* Stream -> DAC mapping */
1491 {"DAC Right1", NULL, "HiFi Playback"},
1492 {"DAC Left1", NULL, "HiFi Playback"},
1493 {"DAC Right2", NULL, "HiFi Playback"},
1494 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1495 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1496
1497 /* ADC -> Stream mapping */
1498 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1499 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1500 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1501 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1502 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1503 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1504 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1505
4005d39a
PU		 1506 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1507 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1508 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1509 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1510 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1511
7729cf74 1512 /* Supply for the digital part (APLL) */
7729cf74
PU		 1513 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1514
27eeb1fe
PU		 1515 {"DAC Left1", NULL, "AIF Enable"},
1516 {"DAC Right1", NULL, "AIF Enable"},
1517 {"DAC Left2", NULL, "AIF Enable"},
1518 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1519 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1520
c42a59ea
PU		 1521 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1522 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1523
4005d39a
PU		 1524 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1525 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1526 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1527 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1528 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1529
5e98a464
PU		 1530 /* Internal playback routings */
1531 /* Earpiece */
4005d39a
PU		 1532 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1533 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1534 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1535 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1536 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1537 /* PreDrivL */
4005d39a
PU		 1538 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1539 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1540 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1541 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1542 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1543 /* PreDrivR */
4005d39a
PU		 1544 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1545 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1546 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1547 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1548 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1549 /* HeadsetL */
4005d39a
PU		 1550 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1551 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1552 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1553 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1554 /* HeadsetR */
4005d39a
PU		 1555 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1556 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1557 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1558 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1559 /* CarkitL */
4005d39a
PU		 1560 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1561 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1562 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1563 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1564 /* CarkitR */
4005d39a
PU		 1565 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1566 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1567 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1568 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1569 /* HandsfreeL */
4005d39a
PU		 1570 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1571 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1572 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1573 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1574 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1575 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1576 /* HandsfreeR */
4005d39a
PU		 1577 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1578 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1579 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1580 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1581 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1582 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1583 /* Vibra */
1584 {"Vibra Mux", "AudioL1", "DAC Left1"},
1585 {"Vibra Mux", "AudioR1", "DAC Right1"},
1586 {"Vibra Mux", "AudioL2", "DAC Left2"},
1587 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1588
cc17557e 1589 /* outputs */
7b4c734e 1590 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1591 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1592 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1593 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1594 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1595 /* Must be always connected (for APLL) */
1596 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1597 /* Physical outputs */
9008adf9
PU		 1598 {"EARPIECE", NULL, "Earpiece PGA"},
1599 {"PREDRIVEL", NULL, "PredriveL PGA"},
1600 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1601 {"HSOL", NULL, "HeadsetL PGA"},
1602 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1603 {"CARKITL", NULL, "CarkitL PGA"},
1604 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1605 {"HFL", NULL, "HandsfreeL PGA"},
1606 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1607 {"Vibra Route", "Audio", "Vibra Mux"},
1608 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1609
276c6222 1610 /* Capture path */
7b4c734e
PU		 1611 /* Must be always connected (for AIF and APLL) */
1612 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1613 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1614 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1615 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1616 /* Physical inputs */
9028935d
PU		 1617 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1618 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1619 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1620 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1621
9028935d
PU		 1622 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1623 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1624
9028935d
PU		 1625 {"ADC Physical Left", NULL, "Analog Left"},
1626 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1627
1628 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1629 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1630
bda7d2a8
PU		 1631 {"DIGIMIC0", NULL, "micbias1 select"},
1632 {"DIGIMIC1", NULL, "micbias2 select"},
1633
276c6222 1634 /* TX1 Left capture path */
fb2a2f84 1635 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1636 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1637 /* TX1 Right capture path */
fb2a2f84 1638 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1639 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1640 /* TX2 Left capture path */
fb2a2f84 1641 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1642 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1643 /* TX2 Right capture path */
fb2a2f84 1644 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1645 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1646
1647 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1648 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1649 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1650 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1651
c42a59ea
PU		 1652 {"ADC Virtual Left1", NULL, "AIF Enable"},
1653 {"ADC Virtual Right1", NULL, "AIF Enable"},
1654 {"ADC Virtual Left2", NULL, "AIF Enable"},
1655 {"ADC Virtual Right2", NULL, "AIF Enable"},
1656
7393958f 1657 /* Analog bypass routes */
9028935d
PU		 1658 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1659 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1660 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1661 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1662 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1663
78e08e2f
PU		 1664 /* Supply for the Analog loopbacks */
1665 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1666 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1667 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1668 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1669 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1670
7393958f
PU		 1671 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1672 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1673 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1674 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1675 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1676
6bab83fd
PU		 1677 /* Digital bypass routes */
1678 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1679 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1680 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1681
4005d39a
PU		 1682 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1683 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1684 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1685
cc17557e
SS		 1686};
1687
cc17557e
SS		 1688static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1689 enum snd_soc_bias_level level)
1690{
1691 switch (level) {
1692 case SND_SOC_BIAS_ON:
cc17557e
SS		 1693 break;
1694 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1695 break;
1696 case SND_SOC_BIAS_STANDBY:
ce6120cc 1697 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1698 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1699 break;
1700 case SND_SOC_BIAS_OFF:
cbd2db12 1701 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1702 break;
1703 }
ce6120cc 1704 codec->dapm.bias_level = level;
cc17557e
SS		 1705
1706 return 0;
1707}
1708
6b87a91f
PU		 1709static void twl4030_constraints(struct twl4030_priv *twl4030,
1710 struct snd_pcm_substream *mst_substream)
1711{
1712 struct snd_pcm_substream *slv_substream;
1713
1714 /* Pick the stream, which need to be constrained */
1715 if (mst_substream == twl4030->master_substream)
1716 slv_substream = twl4030->slave_substream;
1717 else if (mst_substream == twl4030->slave_substream)
1718 slv_substream = twl4030->master_substream;
1719 else /* This should not happen.. */
1720 return;
1721
1722 /* Set the constraints according to the already configured stream */
1723 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1724 SNDRV_PCM_HW_PARAM_RATE,
1725 twl4030->rate,
1726 twl4030->rate);
1727
1728 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1729 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1730 twl4030->sample_bits,
1731 twl4030->sample_bits);
1732
1733 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1734 SNDRV_PCM_HW_PARAM_CHANNELS,
1735 twl4030->channels,
1736 twl4030->channels);
1737}
1738
8a1f936a
PU		 1739/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1740 * capture has to be enabled/disabled. */
1741static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1742 int enable)
1743{
1744 u8 reg, mask;
1745
1746 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1747
1748 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1749 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1750 else
1751 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1752
1753 if (enable)
1754 reg |= mask;
1755 else
1756 reg &= ~mask;
1757
1758 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1759}
1760
d6648da1
PU		 1761static int twl4030_startup(struct snd_pcm_substream *substream,
1762 struct snd_soc_dai *dai)
7220b9f4 1763{
e6968a17 1764 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1765 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1766
7220b9f4 1767 if (twl4030->master_substream) {
7220b9f4 1768 twl4030->slave_substream = substream;
6b87a91f
PU		 1769 /* The DAI has one configuration for playback and capture, so
1770 * if the DAI has been already configured then constrain this
1771 * substream to match it. */
1772 if (twl4030->configured)
1773 twl4030_constraints(twl4030, twl4030->master_substream);
1774 } else {
8a1f936a
PU		 1775 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1776 TWL4030_OPTION_1)) {
1777 /* In option2 4 channel is not supported, set the
1778 * constraint for the first stream for channels, the
1779 * second stream will 'inherit' this cosntraint */
1780 snd_pcm_hw_constraint_minmax(substream->runtime,
1781 SNDRV_PCM_HW_PARAM_CHANNELS,
1782 2, 2);
1783 }
7220b9f4 1784 twl4030->master_substream = substream;
6b87a91f 1785 }
7220b9f4
PU		 1786
1787 return 0;
1788}
1789
d6648da1
PU		 1790static void twl4030_shutdown(struct snd_pcm_substream *substream,
1791 struct snd_soc_dai *dai)
7220b9f4 1792{
e6968a17 1793 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1794 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1795
1796 if (twl4030->master_substream == substream)
1797 twl4030->master_substream = twl4030->slave_substream;
1798
1799 twl4030->slave_substream = NULL;
6b87a91f
PU		 1800
1801 /* If all streams are closed, or the remaining stream has not yet
1802 * been configured than set the DAI as not configured. */
1803 if (!twl4030->master_substream)
1804 twl4030->configured = 0;
1805 else if (!twl4030->master_substream->runtime->channels)
1806 twl4030->configured = 0;
8a1f936a
PU		 1807
1808 /* If the closing substream had 4 channel, do the necessary cleanup */
1809 if (substream->runtime->channels == 4)
1810 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1811}
1812
cc17557e 1813static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1814 struct snd_pcm_hw_params *params,
1815 struct snd_soc_dai *dai)
cc17557e 1816{
e6968a17 1817 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1818 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1819 u8 mode, old_mode, format, old_format;
1820
8a1f936a
PU		 1821 /* If the substream has 4 channel, do the necessary setup */
1822 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1823 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1824 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1825
1826 /* Safety check: are we in the correct operating mode and
1827 * the interface is in TDM mode? */
1828 if ((mode & TWL4030_OPTION_1) &&
1829 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1830 twl4030_tdm_enable(codec, substream->stream, 1);
1831 else
1832 return -EINVAL;
1833 }
1834
6b87a91f
PU		 1835 if (twl4030->configured)
1836 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1837 return 0;
1838
cc17557e
SS		 1839 /* bit rate */
1840 old_mode = twl4030_read_reg_cache(codec,
1841 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1842 mode = old_mode & ~TWL4030_APLL_RATE;
1843
1844 switch (params_rate(params)) {
1845 case 8000:
1846 mode |= TWL4030_APLL_RATE_8000;
1847 break;
1848 case 11025:
1849 mode |= TWL4030_APLL_RATE_11025;
1850 break;
1851 case 12000:
1852 mode |= TWL4030_APLL_RATE_12000;
1853 break;
1854 case 16000:
1855 mode |= TWL4030_APLL_RATE_16000;
1856 break;
1857 case 22050:
1858 mode |= TWL4030_APLL_RATE_22050;
1859 break;
1860 case 24000:
1861 mode |= TWL4030_APLL_RATE_24000;
1862 break;
1863 case 32000:
1864 mode |= TWL4030_APLL_RATE_32000;
1865 break;
1866 case 44100:
1867 mode |= TWL4030_APLL_RATE_44100;
1868 break;
1869 case 48000:
1870 mode |= TWL4030_APLL_RATE_48000;
1871 break;
103f211d
PU		 1872 case 96000:
1873 mode |= TWL4030_APLL_RATE_96000;
1874 break;
cc17557e 1875 default:
3b8a0795 1876 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1877 params_rate(params));
1878 return -EINVAL;
1879 }
1880
cc17557e
SS		 1881 /* sample size */
1882 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1883 format = old_format;
1884 format &= ~TWL4030_DATA_WIDTH;
1885 switch (params_format(params)) {
1886 case SNDRV_PCM_FORMAT_S16_LE:
1887 format |= TWL4030_DATA_WIDTH_16S_16W;
1888 break;
dcdeda4a 1889 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1890 format |= TWL4030_DATA_WIDTH_32S_24W;
1891 break;
1892 default:
3b8a0795 1893 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1894 params_format(params));
1895 return -EINVAL;
1896 }
1897
2046f175
PU		 1898 if (format != old_format || mode != old_mode) {
1899 if (twl4030->codec_powered) {
1900 /*
1901 * If the codec is powered, than we need to toggle the
1902 * codec power.
1903 */
1904 twl4030_codec_enable(codec, 0);
1905 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1906 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1907 twl4030_codec_enable(codec, 1);
1908 } else {
1909 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1910 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1911 }
cc17557e 1912 }
6b87a91f
PU		 1913
1914 /* Store the important parameters for the DAI configuration and set
1915 * the DAI as configured */
1916 twl4030->configured = 1;
1917 twl4030->rate = params_rate(params);
1918 twl4030->sample_bits = hw_param_interval(params,
1919 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1920 twl4030->channels = params_channels(params);
1921
1922 /* If both playback and capture streams are open, and one of them
1923 * is setting the hw parameters right now (since we are here), set
1924 * constraints to the other stream to match the current one. */
1925 if (twl4030->slave_substream)
1926 twl4030_constraints(twl4030, substream);
1927
cc17557e
SS		 1928 return 0;
1929}
1930
1931static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1932 int clk_id, unsigned int freq, int dir)
1933{
1934 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1935 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1936
1937 switch (freq) {
1938 case 19200000:
cc17557e 1939 case 26000000:
cc17557e 1940 case 38400000:
cc17557e
SS		 1941 break;
1942 default:
3b8a0795 1943 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1944 return -EINVAL;
1945 }
1946
68d01955
PU		 1947 if ((freq / 1000) != twl4030->sysclk) {
1948 dev_err(codec->dev,
3b8a0795 1949 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1950 freq, twl4030->sysclk * 1000);
1951 return -EINVAL;
1952 }
cc17557e
SS		 1953
1954 return 0;
1955}
1956
1957static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1958 unsigned int fmt)
1959{
1960 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1961 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1962 u8 old_format, format;
1963
1964 /* get format */
1965 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1966 format = old_format;
1967
1968 /* set master/slave audio interface */
1969 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1970 case SND_SOC_DAIFMT_CBM_CFM:
1971 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1972 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1973 break;
1974 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1975 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1976 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1977 break;
1978 default:
1979 return -EINVAL;
1980 }
1981
1982 /* interface format */
1983 format &= ~TWL4030_AIF_FORMAT;
1984 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1985 case SND_SOC_DAIFMT_I2S:
1986 format |= TWL4030_AIF_FORMAT_CODEC;
1987 break;
8a1f936a
PU		 1988 case SND_SOC_DAIFMT_DSP_A:
1989 format |= TWL4030_AIF_FORMAT_TDM;
1990 break;
cc17557e
SS		 1991 default:
1992 return -EINVAL;
1993 }
1994
1995 if (format != old_format) {
2046f175
PU		 1996 if (twl4030->codec_powered) {
1997 /*
1998 * If the codec is powered, than we need to toggle the
1999 * codec power.
2000 */
2001 twl4030_codec_enable(codec, 0);
2002 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2003 twl4030_codec_enable(codec, 1);
2004 } else {
2005 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2006 }
cc17557e
SS		 2007 }
2008
2009 return 0;
2010}
2011
68140443
LCM		 2012static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
2013{
2014 struct snd_soc_codec *codec = dai->codec;
2015 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
2016
2017 if (tristate)
2018 reg |= TWL4030_AIF_TRI_EN;
2019 else
2020 reg &= ~TWL4030_AIF_TRI_EN;
2021
2022 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2023}
2024
b7a755a8
MLC		 2025/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2026 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2027static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2028 int enable)
2029{
2030 u8 reg, mask;
2031
2032 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2033
2034 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2035 mask = TWL4030_ARXL1_VRX_EN;
2036 else
2037 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2038
2039 if (enable)
2040 reg |= mask;
2041 else
2042 reg &= ~mask;
2043
2044 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2045}
2046
7154b3e8
JS		 2047static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2048 struct snd_soc_dai *dai)
2049{
e6968a17 2050 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2051 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2052 u8 mode;
2053
2054 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 2055 * not available.
7154b3e8 2056 */
68d01955 2057 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 2058 dev_err(codec->dev,
2059 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2060 __func__, twl4030->sysclk);
7154b3e8
JS		 2061 return -EINVAL;
2062 }
2063
2064 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 2065 * available.
7154b3e8
JS		 2066 */
2067 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2068 & TWL4030_OPT_MODE;
2069
2070 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 2071 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2072 __func__);
7154b3e8
JS		 2073 return -EINVAL;
2074 }
2075
2076 return 0;
2077}
2078
b7a755a8
MLC		 2079static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2080 struct snd_soc_dai *dai)
2081{
e6968a17 2082 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 2083
2084 /* Enable voice digital filters */
2085 twl4030_voice_enable(codec, substream->stream, 0);
2086}
2087
7154b3e8
JS		 2088static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2089 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2090{
e6968a17 2091 struct snd_soc_codec *codec = dai->codec;
2046f175 2092 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2093 u8 old_mode, mode;
2094
b7a755a8
MLC		 2095 /* Enable voice digital filters */
2096 twl4030_voice_enable(codec, substream->stream, 1);
2097
7154b3e8
JS		 2098 /* bit rate */
2099 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2100 & ~(TWL4030_CODECPDZ);
2101 mode = old_mode;
2102
2103 switch (params_rate(params)) {
2104 case 8000:
2105 mode &= ~(TWL4030_SEL_16K);
2106 break;
2107 case 16000:
2108 mode |= TWL4030_SEL_16K;
2109 break;
2110 default:
3b8a0795 2111 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2112 params_rate(params));
2113 return -EINVAL;
2114 }
2115
2116 if (mode != old_mode) {
2046f175
PU		 2117 if (twl4030->codec_powered) {
2118 /*
2119 * If the codec is powered, than we need to toggle the
2120 * codec power.
2121 */
2122 twl4030_codec_enable(codec, 0);
2123 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2124 twl4030_codec_enable(codec, 1);
2125 } else {
2126 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2127 }
7154b3e8
JS		 2128 }
2129
2130 return 0;
2131}
2132
2133static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2134 int clk_id, unsigned int freq, int dir)
2135{
2136 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2137 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2138
68d01955 2139 if (freq != 26000000) {
3b8a0795
PU		 2140 dev_err(codec->dev,
2141 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2142 __func__, freq / 1000);
68d01955
PU		 2143 return -EINVAL;
2144 }
2145 if ((freq / 1000) != twl4030->sysclk) {
2146 dev_err(codec->dev,
3b8a0795 2147 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2148 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2149 return -EINVAL;
2150 }
7154b3e8
JS		 2151 return 0;
2152}
2153
2154static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2155 unsigned int fmt)
2156{
2157 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2158 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2159 u8 old_format, format;
2160
2161 /* get format */
2162 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2163 format = old_format;
2164
2165 /* set master/slave audio interface */
2166 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2167 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2168 format &= ~(TWL4030_VIF_SLAVE_EN);
2169 break;
2170 case SND_SOC_DAIFMT_CBS_CFS:
2171 format |= TWL4030_VIF_SLAVE_EN;
2172 break;
2173 default:
2174 return -EINVAL;
2175 }
2176
2177 /* clock inversion */
2178 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2179 case SND_SOC_DAIFMT_IB_NF:
2180 format &= ~(TWL4030_VIF_FORMAT);
2181 break;
2182 case SND_SOC_DAIFMT_NB_IF:
2183 format |= TWL4030_VIF_FORMAT;
2184 break;
2185 default:
2186 return -EINVAL;
2187 }
2188
2189 if (format != old_format) {
2046f175
PU		 2190 if (twl4030->codec_powered) {
2191 /*
2192 * If the codec is powered, than we need to toggle the
2193 * codec power.
2194 */
2195 twl4030_codec_enable(codec, 0);
2196 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2197 twl4030_codec_enable(codec, 1);
2198 } else {
2199 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2200 }
7154b3e8
JS		 2201 }
2202
2203 return 0;
2204}
2205
68140443
LCM		 2206static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2207{
2208 struct snd_soc_codec *codec = dai->codec;
2209 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2210
2211 if (tristate)
2212 reg |= TWL4030_VIF_TRI_EN;
2213 else
2214 reg &= ~TWL4030_VIF_TRI_EN;
2215
2216 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2217}
2218
bbba9444 2219#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2220#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2221
85e7652d 2222static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2223 .startup = twl4030_startup,
2224 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2225 .hw_params = twl4030_hw_params,
2226 .set_sysclk = twl4030_set_dai_sysclk,
2227 .set_fmt = twl4030_set_dai_fmt,
68140443 2228 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2229};
2230
85e7652d 2231static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2232 .startup = twl4030_voice_startup,
b7a755a8 2233 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2234 .hw_params = twl4030_voice_hw_params,
2235 .set_sysclk = twl4030_voice_set_dai_sysclk,
2236 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2237 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2238};
2239
f0fba2ad 2240static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2241{
f0fba2ad 2242 .name = "twl4030-hifi",
cc17557e 2243 .playback = {
b4852b79 2244 .stream_name = "HiFi Playback",
cc17557e 2245 .channels_min = 2,
8a1f936a 2246 .channels_max = 4,
31ad0f31 2247 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2248 .formats = TWL4030_FORMATS,
2249 .sig_bits = 24,},
cc17557e 2250 .capture = {
7f51e7d3 2251 .stream_name = "HiFi Capture",
cc17557e 2252 .channels_min = 2,
8a1f936a 2253 .channels_max = 4,
cc17557e 2254 .rates = TWL4030_RATES,
8819f65c
PU		 2255 .formats = TWL4030_FORMATS,
2256 .sig_bits = 24,},
f0fba2ad 2257 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2258},
2259{
f0fba2ad 2260 .name = "twl4030-voice",
7154b3e8 2261 .playback = {
b4852b79 2262 .stream_name = "Voice Playback",
7154b3e8
JS		 2263 .channels_min = 1,
2264 .channels_max = 1,
2265 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2266 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2267 .capture = {
7f51e7d3 2268 .stream_name = "Voice Capture",
7154b3e8
JS		 2269 .channels_min = 1,
2270 .channels_max = 2,
2271 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2272 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2273 .ops = &twl4030_dai_voice_ops,
2274},
cc17557e 2275};
cc17557e 2276
84b315ee 2277static int twl4030_soc_suspend(struct snd_soc_codec *codec)
cc17557e 2278{
cc17557e 2279 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
cc17557e
SS		 2280 return 0;
2281}
2282
f0fba2ad 2283static int twl4030_soc_resume(struct snd_soc_codec *codec)
cc17557e 2284{
cc17557e 2285 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2286 return 0;
2287}
2288
f0fba2ad 2289static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2290{
f0fba2ad 2291 struct twl4030_priv *twl4030;
9da28c7b 2292
f2b1ce49
PU		 2293 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2294 GFP_KERNEL);
f0fba2ad 2295 if (twl4030 == NULL) {
3b8a0795 2296 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2297 return -ENOMEM;
cc17557e 2298 }
f0fba2ad
LG		 2299 snd_soc_codec_set_drvdata(codec, twl4030);
2300 /* Set the defaults, and power up the codec */
57fe7251 2301 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2302
2303 twl4030_init_chip(codec);
cc17557e 2304
7a1fecf5 2305 return 0;
cc17557e
SS		 2306}
2307
f0fba2ad 2308static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2309{
5b3b0fa8 2310 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2311 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2312
5dcba5d6
PU		 2313 /* Reset registers to their chip default before leaving */
2314 twl4030_reset_registers(codec);
7a1fecf5 2315 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2316
2317 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2318 gpio_free(pdata->hs_extmute_gpio);
2319
7a1fecf5
PU		 2320 return 0;
2321}
2322
f0fba2ad
LG		 2323static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2324 .probe = twl4030_soc_probe,
2325 .remove = twl4030_soc_remove,
2326 .suspend = twl4030_soc_suspend,
2327 .resume = twl4030_soc_resume,
2328 .read = twl4030_read_reg_cache,
2329 .write = twl4030_write,
2330 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2331 .idle_bias_off = true,
f0fba2ad
LG		 2332 .reg_cache_size = sizeof(twl4030_reg),
2333 .reg_word_size = sizeof(u8),
2334 .reg_cache_default = twl4030_reg,
f7c93f01
PU		 2335
2336 .controls = twl4030_snd_controls,
2337 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2338 .dapm_widgets = twl4030_dapm_widgets,
2339 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2340 .dapm_routes = intercon,
2341 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2342};
2343
05c4c6f7 2344static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2345{
f0fba2ad
LG		 2346 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2347 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2348}
2349
05c4c6f7 2350static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2351{
f0fba2ad 2352 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2353 return 0;
2354}
2355
f0fba2ad 2356MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2357
2358static struct platform_driver twl4030_codec_driver = {
2359 .probe = twl4030_codec_probe,
05c4c6f7 2360 .remove = twl4030_codec_remove,
7a1fecf5 2361 .driver = {
f0fba2ad 2362 .name = "twl4030-codec",
7a1fecf5
PU		 2363 .owner = THIS_MODULE,
2364 },
cc17557e 2365};
cc17557e 2366
5bbcc3c0 2367module_platform_driver(twl4030_codec_driver);
64089b84 2368
cc17557e
SS		 2369MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2370MODULE_AUTHOR("Steve Sakoman");
2371MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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