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ASoC: TWL4030: DAPM mapping of the Earpiece output
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
5e98a464
PU		 193/* Earpiece */
194static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid",
196 "DACR1"};
197
198static const struct soc_enum twl4030_earpiece_enum =
199 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
200 ARRAY_SIZE(twl4030_earpiece_texts),
201 twl4030_earpiece_texts);
202
203static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
204SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
205
e8ff9c41
PU		 206static int outmixer_event(struct snd_soc_dapm_widget *w,
207 struct snd_kcontrol *kcontrol, int event)
208{
209 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
210 int ret = 0;
211 int val;
212
213 switch (e->reg) {
214 case TWL4030_REG_PREDL_CTL:
215 case TWL4030_REG_PREDR_CTL:
216 case TWL4030_REG_EAR_CTL:
217 val = w->value >> e->shift_l;
218 if (val == 3) {
219 printk(KERN_WARNING
220 "Invalid MUX setting for register 0x%02x (%d)\n",
221 e->reg, val);
222 ret = -1;
223 }
224 break;
225 }
226
227 return ret;
228}
229
b0bd53a7
PU		 230/*
231 * Some of the gain controls in TWL (mostly those which are associated with
232 * the outputs) are implemented in an interesting way:
233 * 0x0 : Power down (mute)
234 * 0x1 : 6dB
235 * 0x2 : 0 dB
236 * 0x3 : -6 dB
237 * Inverting not going to help with these.
238 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
239 */
240#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
241 xinvert, tlv_array) \
242{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
243 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
244 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
245 .tlv.p = (tlv_array), \
246 .info = snd_soc_info_volsw, \
247 .get = snd_soc_get_volsw_twl4030, \
248 .put = snd_soc_put_volsw_twl4030, \
249 .private_value = (unsigned long)&(struct soc_mixer_control) \
250 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
251 .max = xmax, .invert = xinvert} }
252#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
253 xinvert, tlv_array) \
254{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
255 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
256 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
257 .tlv.p = (tlv_array), \
258 .info = snd_soc_info_volsw_2r, \
259 .get = snd_soc_get_volsw_r2_twl4030,\
260 .put = snd_soc_put_volsw_r2_twl4030, \
261 .private_value = (unsigned long)&(struct soc_mixer_control) \
262 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
263 .max = xmax, .invert = xinvert} }
264#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
265 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
266 xinvert, tlv_array)
267
268static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
269 struct snd_ctl_elem_value *ucontrol)
270{
271 struct soc_mixer_control *mc =
272 (struct soc_mixer_control *)kcontrol->private_value;
273 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
274 unsigned int reg = mc->reg;
275 unsigned int shift = mc->shift;
276 unsigned int rshift = mc->rshift;
277 int max = mc->max;
278 int mask = (1 << fls(max)) - 1;
279
280 ucontrol->value.integer.value[0] =
281 (snd_soc_read(codec, reg) >> shift) & mask;
282 if (ucontrol->value.integer.value[0])
283 ucontrol->value.integer.value[0] =
284 max + 1 - ucontrol->value.integer.value[0];
285
286 if (shift != rshift) {
287 ucontrol->value.integer.value[1] =
288 (snd_soc_read(codec, reg) >> rshift) & mask;
289 if (ucontrol->value.integer.value[1])
290 ucontrol->value.integer.value[1] =
291 max + 1 - ucontrol->value.integer.value[1];
292 }
293
294 return 0;
295}
296
297static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
303 unsigned int reg = mc->reg;
304 unsigned int shift = mc->shift;
305 unsigned int rshift = mc->rshift;
306 int max = mc->max;
307 int mask = (1 << fls(max)) - 1;
308 unsigned short val, val2, val_mask;
309
310 val = (ucontrol->value.integer.value[0] & mask);
311
312 val_mask = mask << shift;
313 if (val)
314 val = max + 1 - val;
315 val = val << shift;
316 if (shift != rshift) {
317 val2 = (ucontrol->value.integer.value[1] & mask);
318 val_mask |= mask << rshift;
319 if (val2)
320 val2 = max + 1 - val2;
321 val |= val2 << rshift;
322 }
323 return snd_soc_update_bits(codec, reg, val_mask, val);
324}
325
326static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
327 struct snd_ctl_elem_value *ucontrol)
328{
329 struct soc_mixer_control *mc =
330 (struct soc_mixer_control *)kcontrol->private_value;
331 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
332 unsigned int reg = mc->reg;
333 unsigned int reg2 = mc->rreg;
334 unsigned int shift = mc->shift;
335 int max = mc->max;
336 int mask = (1<<fls(max))-1;
337
338 ucontrol->value.integer.value[0] =
339 (snd_soc_read(codec, reg) >> shift) & mask;
340 ucontrol->value.integer.value[1] =
341 (snd_soc_read(codec, reg2) >> shift) & mask;
342
343 if (ucontrol->value.integer.value[0])
344 ucontrol->value.integer.value[0] =
345 max + 1 - ucontrol->value.integer.value[0];
346 if (ucontrol->value.integer.value[1])
347 ucontrol->value.integer.value[1] =
348 max + 1 - ucontrol->value.integer.value[1];
349
350 return 0;
351}
352
353static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355{
356 struct soc_mixer_control *mc =
357 (struct soc_mixer_control *)kcontrol->private_value;
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
359 unsigned int reg = mc->reg;
360 unsigned int reg2 = mc->rreg;
361 unsigned int shift = mc->shift;
362 int max = mc->max;
363 int mask = (1 << fls(max)) - 1;
364 int err;
365 unsigned short val, val2, val_mask;
366
367 val_mask = mask << shift;
368 val = (ucontrol->value.integer.value[0] & mask);
369 val2 = (ucontrol->value.integer.value[1] & mask);
370
371 if (val)
372 val = max + 1 - val;
373 if (val2)
374 val2 = max + 1 - val2;
375
376 val = val << shift;
377 val2 = val2 << shift;
378
379 err = snd_soc_update_bits(codec, reg, val_mask, val);
380 if (err < 0)
381 return err;
382
383 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
384 return err;
385}
386
5920b453
GI		 387static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
388 struct snd_ctl_elem_value *ucontrol)
389{
390 struct snd_soc_codec *codec = kcontrol->private_data;
391 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
392 int result = 0;
393
394 /* one bit must be set a time */
395 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
396 | TWL4030_MAINMIC_EN;
397 if (reg != 0) {
398 result++;
399 while ((reg & 1) == 0) {
400 result++;
401 reg >>= 1;
402 }
403 }
404
405 ucontrol->value.integer.value[0] = result;
406 return 0;
407}
408
409static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct snd_soc_codec *codec = kcontrol->private_data;
413 int value = ucontrol->value.integer.value[0];
414 u8 anamicl, micbias, avadc_ctl;
415
416 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
417 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
418 | TWL4030_MAINMIC_EN);
419 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
420 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
421 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
422
423 switch (value) {
424 case 1:
425 anamicl |= TWL4030_MAINMIC_EN;
426 micbias |= TWL4030_MICBIAS1_EN;
427 break;
428 case 2:
429 anamicl |= TWL4030_HSMIC_EN;
430 micbias |= TWL4030_HSMICBIAS_EN;
431 break;
432 case 3:
433 anamicl |= TWL4030_AUXL_EN;
434 break;
435 case 4:
436 anamicl |= TWL4030_CKMIC_EN;
437 break;
438 default:
439 break;
440 }
441
442 /* If some input is selected, enable amp and ADC */
443 if (value != 0) {
444 anamicl |= TWL4030_MICAMPL_EN;
445 avadc_ctl |= TWL4030_ADCL_EN;
446 } else {
447 anamicl &= ~TWL4030_MICAMPL_EN;
448 avadc_ctl &= ~TWL4030_ADCL_EN;
449 }
450
451 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
452 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
453 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
454
455 return 1;
456}
457
458static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = kcontrol->private_data;
462 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
463 int value = 0;
464
465 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
466 switch (reg) {
467 case TWL4030_SUBMIC_EN:
468 value = 1;
469 break;
470 case TWL4030_AUXR_EN:
471 value = 2;
472 break;
473 default:
474 break;
475 }
476
477 ucontrol->value.integer.value[0] = value;
478 return 0;
479}
480
481static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
483{
484 struct snd_soc_codec *codec = kcontrol->private_data;
485 int value = ucontrol->value.integer.value[0];
486 u8 anamicr, micbias, avadc_ctl;
487
488 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
489 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
490 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
491 micbias &= ~TWL4030_MICBIAS2_EN;
492 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
493
494 switch (value) {
495 case 1:
496 anamicr |= TWL4030_SUBMIC_EN;
497 micbias |= TWL4030_MICBIAS2_EN;
498 break;
499 case 2:
500 anamicr |= TWL4030_AUXR_EN;
501 break;
502 default:
503 break;
504 }
505
506 if (value != 0) {
507 anamicr |= TWL4030_MICAMPR_EN;
508 avadc_ctl |= TWL4030_ADCR_EN;
509 } else {
510 anamicr &= ~TWL4030_MICAMPR_EN;
511 avadc_ctl &= ~TWL4030_ADCR_EN;
512 }
513
514 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
515 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
516 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
517
518 return 1;
519}
520
521static const char *twl4030_left_in_sel[] = {
522 "None",
523 "Main Mic",
524 "Headset Mic",
525 "Line In",
526 "Carkit Mic",
527};
528
529static const char *twl4030_right_in_sel[] = {
530 "None",
531 "Sub Mic",
532 "Line In",
533};
534
535static const struct soc_enum twl4030_left_input_mux =
536 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
537 twl4030_left_in_sel);
538
539static const struct soc_enum twl4030_right_input_mux =
540 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
541 twl4030_right_in_sel);
542
c10b82cf
PU		 543/*
544 * FGAIN volume control:
545 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
546 */
d889a72c 547static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 548
0d33ea0b
PU		 549/*
550 * CGAIN volume control:
551 * 0 dB to 12 dB in 6 dB steps
552 * value 2 and 3 means 12 dB
553 */
d889a72c
PU		 554static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
555
556/*
557 * Analog playback gain
558 * -24 dB to 12 dB in 2 dB steps
559 */
560static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 561
4290239c
PU		 562/*
563 * Gain controls tied to outputs
564 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
565 */
566static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
567
381a22b5
PU		 568/*
569 * Capture gain after the ADCs
570 * from 0 dB to 31 dB in 1 dB steps
571 */
572static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
573
5920b453
GI		 574/*
575 * Gain control for input amplifiers
576 * 0 dB to 30 dB in 6 dB steps
577 */
578static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
579
cc17557e 580static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 581 /* Common playback gain controls */
582 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
583 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
584 0, 0x3f, 0, digital_fine_tlv),
585 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
586 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
587 0, 0x3f, 0, digital_fine_tlv),
588
589 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
590 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
591 6, 0x2, 0, digital_coarse_tlv),
592 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
593 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
594 6, 0x2, 0, digital_coarse_tlv),
595
596 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
597 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
598 3, 0x12, 1, analog_tlv),
599 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
600 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
601 3, 0x12, 1, analog_tlv),
44c55870
PU		 602 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
603 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
604 1, 1, 0),
605 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
606 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
607 1, 1, 0),
381a22b5 608
4290239c
PU		 609 /* Separate output gain controls */
610 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
611 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
612 4, 3, 0, output_tvl),
613
614 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
615 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
616
617 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
618 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
619 4, 3, 0, output_tvl),
620
621 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
622 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
623
381a22b5
PU		 624 /* Common capture gain controls */
625 SOC_DOUBLE_R_TLV("Capture Volume",
626 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
627 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 628
629 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
630 0, 3, 5, 0, input_gain_tlv),
631
632 /* Input source controls */
633 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
634 twl4030_get_left_input, twl4030_put_left_input),
635 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
636 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 637};
638
639/* add non dapm controls */
640static int twl4030_add_controls(struct snd_soc_codec *codec)
641{
642 int err, i;
643
644 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
645 err = snd_ctl_add(codec->card,
646 snd_soc_cnew(&twl4030_snd_controls[i],
647 codec, NULL));
648 if (err < 0)
649 return err;
650 }
651
652 return 0;
653}
654
655static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
656 SND_SOC_DAPM_INPUT("INL"),
657 SND_SOC_DAPM_INPUT("INR"),
658
659 SND_SOC_DAPM_OUTPUT("OUTL"),
660 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 661 SND_SOC_DAPM_OUTPUT("EARPIECE"),
cc17557e 662
53b5047d
PU		 663 /* DACs */
664 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
665 TWL4030_REG_AVDAC_CTL, 0, 0),
666 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
667 TWL4030_REG_AVDAC_CTL, 1, 0),
668 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
669 TWL4030_REG_AVDAC_CTL, 2, 0),
670 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
671 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 672
44c55870
PU		 673 /* Analog PGAs */
674 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
675 0, 0, NULL, 0),
676 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
677 0, 0, NULL, 0),
678 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
679 0, 0, NULL, 0),
680 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
681 0, 0, NULL, 0),
682
5e98a464
PU		 683 /* Output MUX controls */
684 /* Earpiece */
685 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
686 &twl4030_dapm_earpiece_control, outmixer_event,
687 SND_SOC_DAPM_PRE_REG),
688
cc17557e
SS		 689 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
690 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
691};
692
693static const struct snd_soc_dapm_route intercon[] = {
44c55870
PU		 694 {"ARXL1_APGA", NULL, "DACL1"},
695 {"ARXR1_APGA", NULL, "DACR1"},
696 {"ARXL2_APGA", NULL, "DACL2"},
697 {"ARXR2_APGA", NULL, "DACR2"},
698
5e98a464
PU		 699 /* Internal playback routings */
700 /* Earpiece */
701 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
702 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
703 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
704
cc17557e 705 /* outputs */
44c55870
PU		 706 {"OUTL", NULL, "ARXL2_APGA"},
707 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 708 {"EARPIECE", NULL, "Earpiece Mux"},
cc17557e
SS		 709
710 /* inputs */
711 {"ADCL", NULL, "INL"},
712 {"ADCR", NULL, "INR"},
713};
714
715static int twl4030_add_widgets(struct snd_soc_codec *codec)
716{
717 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
718 ARRAY_SIZE(twl4030_dapm_widgets));
719
720 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
721
722 snd_soc_dapm_new_widgets(codec);
723 return 0;
724}
725
726static void twl4030_power_up(struct snd_soc_codec *codec)
727{
728 u8 anamicl, regmisc1, byte, popn, hsgain;
729 int i = 0;
730
731 /* set CODECPDZ to turn on codec */
732 twl4030_set_codecpdz(codec);
733
734 /* initiate offset cancellation */
735 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
736 twl4030_write(codec, TWL4030_REG_ANAMICL,
737 anamicl | TWL4030_CNCL_OFFSET_START);
738
739 /* wait for offset cancellation to complete */
740 do {
741 /* this takes a little while, so don't slam i2c */
742 udelay(2000);
743 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
744 TWL4030_REG_ANAMICL);
745 } while ((i++ < 100) &&
746 ((byte & TWL4030_CNCL_OFFSET_START) ==
747 TWL4030_CNCL_OFFSET_START));
748
749 /* anti-pop when changing analog gain */
750 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
751 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
752 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
753
754 /* toggle CODECPDZ as per TRM */
755 twl4030_clear_codecpdz(codec);
756 twl4030_set_codecpdz(codec);
757
758 /* program anti-pop with bias ramp delay */
759 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
760 popn &= TWL4030_RAMP_DELAY;
761 popn |= TWL4030_RAMP_DELAY_645MS;
762 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
763 popn |= TWL4030_VMID_EN;
764 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
765
766 /* enable output stage and gain setting */
767 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
768 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
769
770 /* enable anti-pop ramp */
771 popn |= TWL4030_RAMP_EN;
772 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
773}
774
775static void twl4030_power_down(struct snd_soc_codec *codec)
776{
777 u8 popn, hsgain;
778
779 /* disable anti-pop ramp */
780 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
781 popn &= ~TWL4030_RAMP_EN;
782 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
783
784 /* disable output stage and gain setting */
785 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
786 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
787
788 /* disable bias out */
789 popn &= ~TWL4030_VMID_EN;
790 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
791
792 /* power down */
793 twl4030_clear_codecpdz(codec);
794}
795
796static int twl4030_set_bias_level(struct snd_soc_codec *codec,
797 enum snd_soc_bias_level level)
798{
799 switch (level) {
800 case SND_SOC_BIAS_ON:
801 twl4030_power_up(codec);
802 break;
803 case SND_SOC_BIAS_PREPARE:
804 /* TODO: develop a twl4030_prepare function */
805 break;
806 case SND_SOC_BIAS_STANDBY:
807 /* TODO: develop a twl4030_standby function */
808 twl4030_power_down(codec);
809 break;
810 case SND_SOC_BIAS_OFF:
811 twl4030_power_down(codec);
812 break;
813 }
814 codec->bias_level = level;
815
816 return 0;
817}
818
819static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 820 struct snd_pcm_hw_params *params,
821 struct snd_soc_dai *dai)
cc17557e
SS		 822{
823 struct snd_soc_pcm_runtime *rtd = substream->private_data;
824 struct snd_soc_device *socdev = rtd->socdev;
825 struct snd_soc_codec *codec = socdev->codec;
826 u8 mode, old_mode, format, old_format;
827
828
829 /* bit rate */
830 old_mode = twl4030_read_reg_cache(codec,
831 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
832 mode = old_mode & ~TWL4030_APLL_RATE;
833
834 switch (params_rate(params)) {
835 case 8000:
836 mode |= TWL4030_APLL_RATE_8000;
837 break;
838 case 11025:
839 mode |= TWL4030_APLL_RATE_11025;
840 break;
841 case 12000:
842 mode |= TWL4030_APLL_RATE_12000;
843 break;
844 case 16000:
845 mode |= TWL4030_APLL_RATE_16000;
846 break;
847 case 22050:
848 mode |= TWL4030_APLL_RATE_22050;
849 break;
850 case 24000:
851 mode |= TWL4030_APLL_RATE_24000;
852 break;
853 case 32000:
854 mode |= TWL4030_APLL_RATE_32000;
855 break;
856 case 44100:
857 mode |= TWL4030_APLL_RATE_44100;
858 break;
859 case 48000:
860 mode |= TWL4030_APLL_RATE_48000;
861 break;
862 default:
863 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
864 params_rate(params));
865 return -EINVAL;
866 }
867
868 if (mode != old_mode) {
869 /* change rate and set CODECPDZ */
870 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
871 twl4030_set_codecpdz(codec);
872 }
873
874 /* sample size */
875 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
876 format = old_format;
877 format &= ~TWL4030_DATA_WIDTH;
878 switch (params_format(params)) {
879 case SNDRV_PCM_FORMAT_S16_LE:
880 format |= TWL4030_DATA_WIDTH_16S_16W;
881 break;
882 case SNDRV_PCM_FORMAT_S24_LE:
883 format |= TWL4030_DATA_WIDTH_32S_24W;
884 break;
885 default:
886 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
887 params_format(params));
888 return -EINVAL;
889 }
890
891 if (format != old_format) {
892
893 /* clear CODECPDZ before changing format (codec requirement) */
894 twl4030_clear_codecpdz(codec);
895
896 /* change format */
897 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
898
899 /* set CODECPDZ afterwards */
900 twl4030_set_codecpdz(codec);
901 }
902 return 0;
903}
904
905static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
906 int clk_id, unsigned int freq, int dir)
907{
908 struct snd_soc_codec *codec = codec_dai->codec;
909 u8 infreq;
910
911 switch (freq) {
912 case 19200000:
913 infreq = TWL4030_APLL_INFREQ_19200KHZ;
914 break;
915 case 26000000:
916 infreq = TWL4030_APLL_INFREQ_26000KHZ;
917 break;
918 case 38400000:
919 infreq = TWL4030_APLL_INFREQ_38400KHZ;
920 break;
921 default:
922 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
923 freq);
924 return -EINVAL;
925 }
926
927 infreq |= TWL4030_APLL_EN;
928 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
929
930 return 0;
931}
932
933static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
934 unsigned int fmt)
935{
936 struct snd_soc_codec *codec = codec_dai->codec;
937 u8 old_format, format;
938
939 /* get format */
940 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
941 format = old_format;
942
943 /* set master/slave audio interface */
944 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
945 case SND_SOC_DAIFMT_CBM_CFM:
946 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 947 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 948 break;
949 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 950 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 951 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 952 break;
953 default:
954 return -EINVAL;
955 }
956
957 /* interface format */
958 format &= ~TWL4030_AIF_FORMAT;
959 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
960 case SND_SOC_DAIFMT_I2S:
961 format |= TWL4030_AIF_FORMAT_CODEC;
962 break;
963 default:
964 return -EINVAL;
965 }
966
967 if (format != old_format) {
968
969 /* clear CODECPDZ before changing format (codec requirement) */
970 twl4030_clear_codecpdz(codec);
971
972 /* change format */
973 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
974
975 /* set CODECPDZ afterwards */
976 twl4030_set_codecpdz(codec);
977 }
978
979 return 0;
980}
981
bbba9444 982#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 983#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
984
985struct snd_soc_dai twl4030_dai = {
986 .name = "twl4030",
987 .playback = {
988 .stream_name = "Playback",
989 .channels_min = 2,
990 .channels_max = 2,
991 .rates = TWL4030_RATES,
992 .formats = TWL4030_FORMATS,},
993 .capture = {
994 .stream_name = "Capture",
995 .channels_min = 2,
996 .channels_max = 2,
997 .rates = TWL4030_RATES,
998 .formats = TWL4030_FORMATS,},
999 .ops = {
1000 .hw_params = twl4030_hw_params,
cc17557e
SS		 1001 .set_sysclk = twl4030_set_dai_sysclk,
1002 .set_fmt = twl4030_set_dai_fmt,
1003 }
1004};
1005EXPORT_SYMBOL_GPL(twl4030_dai);
1006
1007static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1008{
1009 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1010 struct snd_soc_codec *codec = socdev->codec;
1011
1012 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1013
1014 return 0;
1015}
1016
1017static int twl4030_resume(struct platform_device *pdev)
1018{
1019 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1020 struct snd_soc_codec *codec = socdev->codec;
1021
1022 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1023 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1024 return 0;
1025}
1026
1027/*
1028 * initialize the driver
1029 * register the mixer and dsp interfaces with the kernel
1030 */
1031
1032static int twl4030_init(struct snd_soc_device *socdev)
1033{
1034 struct snd_soc_codec *codec = socdev->codec;
1035 int ret = 0;
1036
1037 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1038
1039 codec->name = "twl4030";
1040 codec->owner = THIS_MODULE;
1041 codec->read = twl4030_read_reg_cache;
1042 codec->write = twl4030_write;
1043 codec->set_bias_level = twl4030_set_bias_level;
1044 codec->dai = &twl4030_dai;
1045 codec->num_dai = 1;
1046 codec->reg_cache_size = sizeof(twl4030_reg);
1047 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1048 GFP_KERNEL);
1049 if (codec->reg_cache == NULL)
1050 return -ENOMEM;
1051
1052 /* register pcms */
1053 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1054 if (ret < 0) {
1055 printk(KERN_ERR "twl4030: failed to create pcms\n");
1056 goto pcm_err;
1057 }
1058
1059 twl4030_init_chip(codec);
1060
1061 /* power on device */
1062 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1063
1064 twl4030_add_controls(codec);
1065 twl4030_add_widgets(codec);
1066
968a6025 1067 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1068 if (ret < 0) {
1069 printk(KERN_ERR "twl4030: failed to register card\n");
1070 goto card_err;
1071 }
1072
1073 return ret;
1074
1075card_err:
1076 snd_soc_free_pcms(socdev);
1077 snd_soc_dapm_free(socdev);
1078pcm_err:
1079 kfree(codec->reg_cache);
1080 return ret;
1081}
1082
1083static struct snd_soc_device *twl4030_socdev;
1084
1085static int twl4030_probe(struct platform_device *pdev)
1086{
1087 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1088 struct snd_soc_codec *codec;
1089
1090 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1091 if (codec == NULL)
1092 return -ENOMEM;
1093
1094 socdev->codec = codec;
1095 mutex_init(&codec->mutex);
1096 INIT_LIST_HEAD(&codec->dapm_widgets);
1097 INIT_LIST_HEAD(&codec->dapm_paths);
1098
1099 twl4030_socdev = socdev;
1100 twl4030_init(socdev);
1101
1102 return 0;
1103}
1104
1105static int twl4030_remove(struct platform_device *pdev)
1106{
1107 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1108 struct snd_soc_codec *codec = socdev->codec;
1109
1110 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1111 kfree(codec);
1112
1113 return 0;
1114}
1115
1116struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1117 .probe = twl4030_probe,
1118 .remove = twl4030_remove,
1119 .suspend = twl4030_suspend,
1120 .resume = twl4030_resume,
1121};
1122EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1123
1124MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1125MODULE_AUTHOR("Steve Sakoman");
1126MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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