projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: txx9aclc: dynamically allocate dmaengine devname
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
d08664fd 148 u8 *cache = codec->reg_cache;
cc17557e 149
91432e97
IM		 150 if (reg >= TWL4030_CACHEREGNUM)
151 return -EIO;
152
cc17557e
SS		 153 return cache[reg];
154}
155
156/*
157 * write twl4030 register cache
158 */
159static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
160 u8 reg, u8 value)
161{
162 u8 *cache = codec->reg_cache;
163
164 if (reg >= TWL4030_CACHEREGNUM)
165 return;
166 cache[reg] = value;
167}
168
169/*
170 * write to the twl4030 register space
171 */
172static int twl4030_write(struct snd_soc_codec *codec,
173 unsigned int reg, unsigned int value)
174{
175 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
cc17557e
SS		 181}
182
db04e2c5 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 184{
7393958f 185 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 186 u8 mode;
187
7393958f
PU		 188 if (enable == twl4030->codec_powered)
189 return;
190
cc17557e 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 192 if (enable)
193 mode |= TWL4030_CODECPDZ;
194 else
195 mode &= ~TWL4030_CODECPDZ;
cc17557e 196
db04e2c5 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 198 twl4030->codec_powered = enable;
cc17557e
SS		 199
200 /* REVISIT: this delay is present in TI sample drivers */
201 /* but there seems to be no TRM requirement for it */
202 udelay(10);
203}
204
205static void twl4030_init_chip(struct snd_soc_codec *codec)
206{
16a30fbb 207 u8 *cache = codec->reg_cache;
cc17557e
SS		 208 int i;
209
210 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 211 twl4030_codec_enable(codec, 0);
cc17557e
SS		 212
213 /* set all audio section registers to reasonable defaults */
214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 215 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 216
217}
218
7393958f
PU		 219static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
220{
221 struct twl4030_priv *twl4030 = codec->private_data;
222 u8 reg_val;
223
224 if (mute == twl4030->codec_muted)
225 return;
226
227 if (mute) {
228 /* Bypass the reg_cache and mute the volumes
229 * Headset mute is done in it's own event handler
230 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
231 */
232 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
233 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
234 reg_val & (~TWL4030_EAR_GAIN),
235 TWL4030_REG_EAR_CTL);
236
237 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
238 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
239 reg_val & (~TWL4030_PREDL_GAIN),
240 TWL4030_REG_PREDL_CTL);
241 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
242 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
243 reg_val & (~TWL4030_PREDR_GAIN),
244 TWL4030_REG_PREDL_CTL);
245
246 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
247 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
248 reg_val & (~TWL4030_PRECKL_GAIN),
249 TWL4030_REG_PRECKL_CTL);
250 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
251 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 252 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 253 TWL4030_REG_PRECKR_CTL);
254
255 /* Disable PLL */
256 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
257 reg_val &= ~TWL4030_APLL_EN;
258 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
259 } else {
260 /* Restore the volumes
261 * Headset mute is done in it's own event handler
262 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
263 */
264 twl4030_write(codec, TWL4030_REG_EAR_CTL,
265 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
266
267 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
268 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
269 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
270 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
271
272 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
273 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
274 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
275 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
276
277 /* Enable PLL */
278 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
279 reg_val |= TWL4030_APLL_EN;
280 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
281 }
282
283 twl4030->codec_muted = mute;
284}
285
006f367e
PU		 286static void twl4030_power_up(struct snd_soc_codec *codec)
287{
7393958f 288 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 289 u8 anamicl, regmisc1, byte;
290 int i = 0;
291
7393958f
PU		 292 if (twl4030->codec_powered)
293 return;
294
006f367e
PU		 295 /* set CODECPDZ to turn on codec */
296 twl4030_codec_enable(codec, 1);
297
298 /* initiate offset cancellation */
299 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
300 twl4030_write(codec, TWL4030_REG_ANAMICL,
301 anamicl | TWL4030_CNCL_OFFSET_START);
302
303 /* wait for offset cancellation to complete */
304 do {
305 /* this takes a little while, so don't slam i2c */
306 udelay(2000);
307 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
308 TWL4030_REG_ANAMICL);
309 } while ((i++ < 100) &&
310 ((byte & TWL4030_CNCL_OFFSET_START) ==
311 TWL4030_CNCL_OFFSET_START));
312
313 /* Make sure that the reg_cache has the same value as the HW */
314 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
315
316 /* anti-pop when changing analog gain */
317 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
318 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
319 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
320
321 /* toggle CODECPDZ as per TRM */
322 twl4030_codec_enable(codec, 0);
323 twl4030_codec_enable(codec, 1);
324}
325
7393958f
PU		 326/*
327 * Unconditional power down
328 */
006f367e
PU		 329static void twl4030_power_down(struct snd_soc_codec *codec)
330{
331 /* power down */
332 twl4030_codec_enable(codec, 0);
333}
334
5e98a464 335/* Earpiece */
1a787e7a
JS		 336static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
337 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
338 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
339 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
341};
5e98a464 342
2a6f5c58 343/* PreDrive Left */
1a787e7a
JS		 344static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
345 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
346 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
347 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
348 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
349};
2a6f5c58
PU		 350
351/* PreDrive Right */
1a787e7a
JS		 352static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
353 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
354 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
355 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
356 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
357};
2a6f5c58 358
dfad21a2 359/* Headset Left */
1a787e7a
JS		 360static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
361 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
362 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
363 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
364};
dfad21a2
PU		 365
366/* Headset Right */
1a787e7a
JS		 367static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
368 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
369 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
370 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
371};
dfad21a2 372
5152d8c2 373/* Carkit Left */
1a787e7a
JS		 374static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
375 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
376 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
377 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
378};
5152d8c2
PU		 379
380/* Carkit Right */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
385};
5152d8c2 386
df339804
PU		 387/* Handsfree Left */
388static const char *twl4030_handsfreel_texts[] =
1a787e7a 389 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreel_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreel_texts),
394 twl4030_handsfreel_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
398
0f89bdca
PU		 399/* Handsfree Left virtual mute */
400static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
401 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
402
df339804
PU		 403/* Handsfree Right */
404static const char *twl4030_handsfreer_texts[] =
1a787e7a 405 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 406
407static const struct soc_enum twl4030_handsfreer_enum =
408 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
409 ARRAY_SIZE(twl4030_handsfreer_texts),
410 twl4030_handsfreer_texts);
411
412static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
413SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
414
0f89bdca
PU		 415/* Handsfree Right virtual mute */
416static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
417 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
418
376f7839
PU		 419/* Vibra */
420/* Vibra audio path selection */
421static const char *twl4030_vibra_texts[] =
422 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
423
424static const struct soc_enum twl4030_vibra_enum =
425 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
426 ARRAY_SIZE(twl4030_vibra_texts),
427 twl4030_vibra_texts);
428
429static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
430SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
431
432/* Vibra path selection: local vibrator (PWM) or audio driven */
433static const char *twl4030_vibrapath_texts[] =
434 {"Local vibrator", "Audio"};
435
436static const struct soc_enum twl4030_vibrapath_enum =
437 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
438 ARRAY_SIZE(twl4030_vibrapath_texts),
439 twl4030_vibrapath_texts);
440
441static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
442SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
443
276c6222 444/* Left analog microphone selection */
97b8096d
JS		 445static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
446 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
447 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
448 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
449 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
450};
276c6222
PU		 451
452/* Right analog microphone selection */
97b8096d
JS		 453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
454 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 455 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 456};
276c6222
PU		 457
458/* TX1 L/R Analog/Digital microphone selection */
459static const char *twl4030_micpathtx1_texts[] =
460 {"Analog", "Digimic0"};
461
462static const struct soc_enum twl4030_micpathtx1_enum =
463 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
464 ARRAY_SIZE(twl4030_micpathtx1_texts),
465 twl4030_micpathtx1_texts);
466
467static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
468SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
469
470/* TX2 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx2_texts[] =
472 {"Analog", "Digimic1"};
473
474static const struct soc_enum twl4030_micpathtx2_enum =
475 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
476 ARRAY_SIZE(twl4030_micpathtx2_texts),
477 twl4030_micpathtx2_texts);
478
479static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
480SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
481
7393958f
PU		 482/* Analog bypass for AudioR1 */
483static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
484 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
485
486/* Analog bypass for AudioL1 */
487static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
488 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
489
490/* Analog bypass for AudioR2 */
491static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
492 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
493
494/* Analog bypass for AudioL2 */
495static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
497
fcd274a3
LCM		 498/* Analog bypass for Voice */
499static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
501
6bab83fd
PU		 502/* Digital bypass gain, 0 mutes the bypass */
503static const unsigned int twl4030_dapm_dbypass_tlv[] = {
504 TLV_DB_RANGE_HEAD(2),
505 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
506 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
507};
508
509/* Digital bypass left (TX1L -> RX2L) */
510static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
511 SOC_DAPM_SINGLE_TLV("Volume",
512 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
513 twl4030_dapm_dbypass_tlv);
514
515/* Digital bypass right (TX1R -> RX2R) */
516static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
517 SOC_DAPM_SINGLE_TLV("Volume",
518 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
519 twl4030_dapm_dbypass_tlv);
520
ee8f6894
LCM		 521/*
522 * Voice Sidetone GAIN volume control:
523 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
524 */
525static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
526
527/* Digital bypass voice: sidetone (VUL -> VDL)*/
528static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
529 SOC_DAPM_SINGLE_TLV("Volume",
530 TWL4030_REG_VSTPGA, 0, 0x29, 0,
531 twl4030_dapm_dbypassv_tlv);
532
276c6222
PU		 533static int micpath_event(struct snd_soc_dapm_widget *w,
534 struct snd_kcontrol *kcontrol, int event)
535{
536 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
537 unsigned char adcmicsel, micbias_ctl;
538
539 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
540 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
541 /* Prepare the bits for the given TX path:
542 * shift_l == 0: TX1 microphone path
543 * shift_l == 2: TX2 microphone path */
544 if (e->shift_l) {
545 /* TX2 microphone path */
546 if (adcmicsel & TWL4030_TX2IN_SEL)
547 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
548 else
549 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
550 } else {
551 /* TX1 microphone path */
552 if (adcmicsel & TWL4030_TX1IN_SEL)
553 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
554 else
555 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
556 }
557
558 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
559
560 return 0;
561}
562
5a2e9a48 563static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 564{
49d92c7d
SM		 565 unsigned char hs_ctl;
566
5a2e9a48 567 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 568
5a2e9a48
PU		 569 if (ramp) {
570 /* HF ramp-up */
571 hs_ctl |= TWL4030_HF_CTL_REF_EN;
572 twl4030_write(codec, reg, hs_ctl);
573 udelay(10);
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 575 twl4030_write(codec, reg, hs_ctl);
576 udelay(40);
49d92c7d 577 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 578 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 579 twl4030_write(codec, reg, hs_ctl);
49d92c7d 580 } else {
5a2e9a48
PU		 581 /* HF ramp-down */
582 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
583 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
584 twl4030_write(codec, reg, hs_ctl);
585 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
586 twl4030_write(codec, reg, hs_ctl);
587 udelay(40);
588 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
589 twl4030_write(codec, reg, hs_ctl);
49d92c7d 590 }
5a2e9a48 591}
49d92c7d 592
5a2e9a48
PU		 593static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
594 struct snd_kcontrol *kcontrol, int event)
595{
596 switch (event) {
597 case SND_SOC_DAPM_POST_PMU:
598 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
599 break;
600 case SND_SOC_DAPM_POST_PMD:
601 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
602 break;
603 }
604 return 0;
605}
606
607static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
608 struct snd_kcontrol *kcontrol, int event)
609{
610 switch (event) {
611 case SND_SOC_DAPM_POST_PMU:
612 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
613 break;
614 case SND_SOC_DAPM_POST_PMD:
615 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
616 break;
617 }
49d92c7d
SM		 618 return 0;
619}
620
6943c92e 621static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 622{
623 unsigned char hs_gain, hs_pop;
6943c92e
PU		 624 struct twl4030_priv *twl4030 = codec->private_data;
625 /* Base values for ramp delay calculation: 2^19 - 2^26 */
626 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
627 8388608, 16777216, 33554432, 67108864};
aad749e5 628
6943c92e
PU		 629 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
630 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 631
6943c92e
PU		 632 if (ramp) {
633 /* Headset ramp-up according to the TRM */
aad749e5 634 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 635 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
636 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 637 hs_pop |= TWL4030_RAMP_EN;
6943c92e
PU		 638 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
639 } else {
640 /* Headset ramp-down _not_ according to
641 * the TRM, but in a way that it is working */
aad749e5 642 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 643 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
644 /* Wait ramp delay time + 1, so the VMID can settle */
645 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
646 twl4030->sysclk) + 1);
aad749e5
PU		 647 /* Bypass the reg_cache to mute the headset */
648 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
649 hs_gain & (~0x0f),
650 TWL4030_REG_HS_GAIN_SET);
6943c92e 651
aad749e5 652 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 653 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
654 }
655}
656
657static int headsetlpga_event(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *kcontrol, int event)
659{
660 struct twl4030_priv *twl4030 = w->codec->private_data;
661
662 switch (event) {
663 case SND_SOC_DAPM_POST_PMU:
664 /* Do the ramp-up only once */
665 if (!twl4030->hsr_enabled)
666 headset_ramp(w->codec, 1);
667
668 twl4030->hsl_enabled = 1;
669 break;
670 case SND_SOC_DAPM_POST_PMD:
671 /* Do the ramp-down only if both headsetL/R is disabled */
672 if (!twl4030->hsr_enabled)
673 headset_ramp(w->codec, 0);
674
675 twl4030->hsl_enabled = 0;
676 break;
677 }
678 return 0;
679}
680
681static int headsetrpga_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683{
684 struct twl4030_priv *twl4030 = w->codec->private_data;
685
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 /* Do the ramp-up only once */
689 if (!twl4030->hsl_enabled)
690 headset_ramp(w->codec, 1);
691
692 twl4030->hsr_enabled = 1;
693 break;
694 case SND_SOC_DAPM_POST_PMD:
695 /* Do the ramp-down only if both headsetL/R is disabled */
696 if (!twl4030->hsl_enabled)
697 headset_ramp(w->codec, 0);
698
699 twl4030->hsr_enabled = 0;
aad749e5
PU		 700 break;
701 }
702 return 0;
703}
704
7393958f
PU		 705static int bypass_event(struct snd_soc_dapm_widget *w,
706 struct snd_kcontrol *kcontrol, int event)
707{
708 struct soc_mixer_control *m =
709 (struct soc_mixer_control *)w->kcontrols->private_value;
710 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 711 unsigned char reg, misc;
7393958f
PU		 712
713 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd 714
30808ca7
LCM		 715 /*
716 * bypass_state[0:3] - analog HiFi bypass
717 * bypass_state[4] - analog voice bypass
718 * bypass_state[5] - digital voice bypass
719 * bypass_state[6:7] - digital HiFi bypass
720 */
721 if (m->reg == TWL4030_REG_VSTPGA) {
722 /* Voice digital bypass */
723 if (reg)
724 twl4030->bypass_state |= (1 << 5);
725 else
726 twl4030->bypass_state &= ~(1 << 5);
727 } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
6bab83fd
PU		 728 /* Analog bypass */
729 if (reg & (1 << m->shift))
730 twl4030->bypass_state |=
731 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
732 else
733 twl4030->bypass_state &=
734 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 735 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
736 /* Analog voice bypass */
737 if (reg & (1 << m->shift))
738 twl4030->bypass_state |= (1 << 4);
739 else
740 twl4030->bypass_state &= ~(1 << 4);
6bab83fd
PU		 741 } else {
742 /* Digital bypass */
743 if (reg & (0x7 << m->shift))
ee8f6894 744 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 745 else
ee8f6894 746 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 747 }
7393958f 748
fcd274a3
LCM		 749 /* Enable master analog loopback mode if any analog switch is enabled*/
750 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
751 if (twl4030->bypass_state & 0x1F)
752 misc |= TWL4030_FMLOOP_EN;
753 else
754 misc &= ~TWL4030_FMLOOP_EN;
755 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
756
7393958f
PU		 757 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
758 if (twl4030->bypass_state)
759 twl4030_codec_mute(w->codec, 0);
760 else
761 twl4030_codec_mute(w->codec, 1);
762 }
763 return 0;
764}
765
b0bd53a7
PU		 766/*
767 * Some of the gain controls in TWL (mostly those which are associated with
768 * the outputs) are implemented in an interesting way:
769 * 0x0 : Power down (mute)
770 * 0x1 : 6dB
771 * 0x2 : 0 dB
772 * 0x3 : -6 dB
773 * Inverting not going to help with these.
774 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
775 */
776#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
777 xinvert, tlv_array) \
778{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
779 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
780 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
781 .tlv.p = (tlv_array), \
782 .info = snd_soc_info_volsw, \
783 .get = snd_soc_get_volsw_twl4030, \
784 .put = snd_soc_put_volsw_twl4030, \
785 .private_value = (unsigned long)&(struct soc_mixer_control) \
786 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
787 .max = xmax, .invert = xinvert} }
788#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
789 xinvert, tlv_array) \
790{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
791 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
792 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
793 .tlv.p = (tlv_array), \
794 .info = snd_soc_info_volsw_2r, \
795 .get = snd_soc_get_volsw_r2_twl4030,\
796 .put = snd_soc_put_volsw_r2_twl4030, \
797 .private_value = (unsigned long)&(struct soc_mixer_control) \
798 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 799 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 800#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
801 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
802 xinvert, tlv_array)
803
804static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
805 struct snd_ctl_elem_value *ucontrol)
806{
807 struct soc_mixer_control *mc =
808 (struct soc_mixer_control *)kcontrol->private_value;
809 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
810 unsigned int reg = mc->reg;
811 unsigned int shift = mc->shift;
812 unsigned int rshift = mc->rshift;
813 int max = mc->max;
814 int mask = (1 << fls(max)) - 1;
815
816 ucontrol->value.integer.value[0] =
817 (snd_soc_read(codec, reg) >> shift) & mask;
818 if (ucontrol->value.integer.value[0])
819 ucontrol->value.integer.value[0] =
820 max + 1 - ucontrol->value.integer.value[0];
821
822 if (shift != rshift) {
823 ucontrol->value.integer.value[1] =
824 (snd_soc_read(codec, reg) >> rshift) & mask;
825 if (ucontrol->value.integer.value[1])
826 ucontrol->value.integer.value[1] =
827 max + 1 - ucontrol->value.integer.value[1];
828 }
829
830 return 0;
831}
832
833static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
834 struct snd_ctl_elem_value *ucontrol)
835{
836 struct soc_mixer_control *mc =
837 (struct soc_mixer_control *)kcontrol->private_value;
838 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
839 unsigned int reg = mc->reg;
840 unsigned int shift = mc->shift;
841 unsigned int rshift = mc->rshift;
842 int max = mc->max;
843 int mask = (1 << fls(max)) - 1;
844 unsigned short val, val2, val_mask;
845
846 val = (ucontrol->value.integer.value[0] & mask);
847
848 val_mask = mask << shift;
849 if (val)
850 val = max + 1 - val;
851 val = val << shift;
852 if (shift != rshift) {
853 val2 = (ucontrol->value.integer.value[1] & mask);
854 val_mask |= mask << rshift;
855 if (val2)
856 val2 = max + 1 - val2;
857 val |= val2 << rshift;
858 }
859 return snd_soc_update_bits(codec, reg, val_mask, val);
860}
861
862static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
863 struct snd_ctl_elem_value *ucontrol)
864{
865 struct soc_mixer_control *mc =
866 (struct soc_mixer_control *)kcontrol->private_value;
867 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
868 unsigned int reg = mc->reg;
869 unsigned int reg2 = mc->rreg;
870 unsigned int shift = mc->shift;
871 int max = mc->max;
872 int mask = (1<<fls(max))-1;
873
874 ucontrol->value.integer.value[0] =
875 (snd_soc_read(codec, reg) >> shift) & mask;
876 ucontrol->value.integer.value[1] =
877 (snd_soc_read(codec, reg2) >> shift) & mask;
878
879 if (ucontrol->value.integer.value[0])
880 ucontrol->value.integer.value[0] =
881 max + 1 - ucontrol->value.integer.value[0];
882 if (ucontrol->value.integer.value[1])
883 ucontrol->value.integer.value[1] =
884 max + 1 - ucontrol->value.integer.value[1];
885
886 return 0;
887}
888
889static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
890 struct snd_ctl_elem_value *ucontrol)
891{
892 struct soc_mixer_control *mc =
893 (struct soc_mixer_control *)kcontrol->private_value;
894 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
895 unsigned int reg = mc->reg;
896 unsigned int reg2 = mc->rreg;
897 unsigned int shift = mc->shift;
898 int max = mc->max;
899 int mask = (1 << fls(max)) - 1;
900 int err;
901 unsigned short val, val2, val_mask;
902
903 val_mask = mask << shift;
904 val = (ucontrol->value.integer.value[0] & mask);
905 val2 = (ucontrol->value.integer.value[1] & mask);
906
907 if (val)
908 val = max + 1 - val;
909 if (val2)
910 val2 = max + 1 - val2;
911
912 val = val << shift;
913 val2 = val2 << shift;
914
915 err = snd_soc_update_bits(codec, reg, val_mask, val);
916 if (err < 0)
917 return err;
918
919 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
920 return err;
921}
922
b74bd40f
LCM		 923/* Codec operation modes */
924static const char *twl4030_op_modes_texts[] = {
925 "Option 2 (voice/audio)", "Option 1 (audio)"
926};
927
928static const struct soc_enum twl4030_op_modes_enum =
929 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
930 ARRAY_SIZE(twl4030_op_modes_texts),
931 twl4030_op_modes_texts);
932
423c238d 933static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 934 struct snd_ctl_elem_value *ucontrol)
935{
936 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
937 struct twl4030_priv *twl4030 = codec->private_data;
938 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
939 unsigned short val;
940 unsigned short mask, bitmask;
941
942 if (twl4030->configured) {
943 printk(KERN_ERR "twl4030 operation mode cannot be "
944 "changed on-the-fly\n");
945 return -EBUSY;
946 }
947
948 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
949 ;
950 if (ucontrol->value.enumerated.item[0] > e->max - 1)
951 return -EINVAL;
952
953 val = ucontrol->value.enumerated.item[0] << e->shift_l;
954 mask = (bitmask - 1) << e->shift_l;
955 if (e->shift_l != e->shift_r) {
956 if (ucontrol->value.enumerated.item[1] > e->max - 1)
957 return -EINVAL;
958 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
959 mask |= (bitmask - 1) << e->shift_r;
960 }
961
962 return snd_soc_update_bits(codec, e->reg, mask, val);
963}
964
c10b82cf
PU		 965/*
966 * FGAIN volume control:
967 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
968 */
d889a72c 969static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 970
0d33ea0b
PU		 971/*
972 * CGAIN volume control:
973 * 0 dB to 12 dB in 6 dB steps
974 * value 2 and 3 means 12 dB
975 */
d889a72c
PU		 976static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
977
1a787e7a
JS		 978/*
979 * Voice Downlink GAIN volume control:
980 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
981 */
982static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
983
d889a72c
PU		 984/*
985 * Analog playback gain
986 * -24 dB to 12 dB in 2 dB steps
987 */
988static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 989
4290239c
PU		 990/*
991 * Gain controls tied to outputs
992 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
993 */
994static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
995
18cc8d8d
JS		 996/*
997 * Gain control for earpiece amplifier
998 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
999 */
1000static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1001
381a22b5
PU		 1002/*
1003 * Capture gain after the ADCs
1004 * from 0 dB to 31 dB in 1 dB steps
1005 */
1006static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1007
5920b453
GI		 1008/*
1009 * Gain control for input amplifiers
1010 * 0 dB to 30 dB in 6 dB steps
1011 */
1012static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1013
328d0a13
LCM		 1014/* AVADC clock priority */
1015static const char *twl4030_avadc_clk_priority_texts[] = {
1016 "Voice high priority", "HiFi high priority"
1017};
1018
1019static const struct soc_enum twl4030_avadc_clk_priority_enum =
1020 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1021 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1022 twl4030_avadc_clk_priority_texts);
1023
89492be8
PU		 1024static const char *twl4030_rampdelay_texts[] = {
1025 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1026 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1027 "3495/2581/1748 ms"
1028};
1029
1030static const struct soc_enum twl4030_rampdelay_enum =
1031 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1032 ARRAY_SIZE(twl4030_rampdelay_texts),
1033 twl4030_rampdelay_texts);
1034
376f7839
PU		 1035/* Vibra H-bridge direction mode */
1036static const char *twl4030_vibradirmode_texts[] = {
1037 "Vibra H-bridge direction", "Audio data MSB",
1038};
1039
1040static const struct soc_enum twl4030_vibradirmode_enum =
1041 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1042 ARRAY_SIZE(twl4030_vibradirmode_texts),
1043 twl4030_vibradirmode_texts);
1044
1045/* Vibra H-bridge direction */
1046static const char *twl4030_vibradir_texts[] = {
1047 "Positive polarity", "Negative polarity",
1048};
1049
1050static const struct soc_enum twl4030_vibradir_enum =
1051 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1052 ARRAY_SIZE(twl4030_vibradir_texts),
1053 twl4030_vibradir_texts);
1054
cc17557e 1055static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1056 /* Codec operation mode control */
1057 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1058 snd_soc_get_enum_double,
1059 snd_soc_put_twl4030_opmode_enum_double),
1060
d889a72c
PU		 1061 /* Common playback gain controls */
1062 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1063 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1064 0, 0x3f, 0, digital_fine_tlv),
1065 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1066 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1067 0, 0x3f, 0, digital_fine_tlv),
1068
1069 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1070 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1071 6, 0x2, 0, digital_coarse_tlv),
1072 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1073 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1074 6, 0x2, 0, digital_coarse_tlv),
1075
1076 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1077 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1078 3, 0x12, 1, analog_tlv),
1079 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1080 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1081 3, 0x12, 1, analog_tlv),
44c55870
PU		 1082 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1083 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1084 1, 1, 0),
1085 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1086 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1087 1, 1, 0),
381a22b5 1088
1a787e7a
JS		 1089 /* Common voice downlink gain controls */
1090 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1091 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1092
1093 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1094 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1095
1096 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1097 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1098
4290239c
PU		 1099 /* Separate output gain controls */
1100 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1101 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1102 4, 3, 0, output_tvl),
1103
1104 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1105 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1106
1107 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1108 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1109 4, 3, 0, output_tvl),
1110
1111 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1112 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1113
381a22b5 1114 /* Common capture gain controls */
276c6222 1115 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1116 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1117 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1118 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1119 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1120 0, 0x1f, 0, digital_capture_tlv),
5920b453 1121
276c6222 1122 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1123 0, 3, 5, 0, input_gain_tlv),
89492be8 1124
328d0a13
LCM		 1125 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1126
89492be8 1127 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1128
1129 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1130 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1131};
1132
cc17557e 1133static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1134 /* Left channel inputs */
1135 SND_SOC_DAPM_INPUT("MAINMIC"),
1136 SND_SOC_DAPM_INPUT("HSMIC"),
1137 SND_SOC_DAPM_INPUT("AUXL"),
1138 SND_SOC_DAPM_INPUT("CARKITMIC"),
1139 /* Right channel inputs */
1140 SND_SOC_DAPM_INPUT("SUBMIC"),
1141 SND_SOC_DAPM_INPUT("AUXR"),
1142 /* Digital microphones (Stereo) */
1143 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1144 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1145
1146 /* Outputs */
cc17557e
SS		 1147 SND_SOC_DAPM_OUTPUT("OUTL"),
1148 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1149 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1150 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1151 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1152 SND_SOC_DAPM_OUTPUT("HSOL"),
1153 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1154 SND_SOC_DAPM_OUTPUT("CARKITL"),
1155 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1156 SND_SOC_DAPM_OUTPUT("HFL"),
1157 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1158 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1159
53b5047d 1160 /* DACs */
b4852b79 1161 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1162 SND_SOC_NOPM, 0, 0),
b4852b79 1163 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1164 SND_SOC_NOPM, 0, 0),
b4852b79 1165 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1166 SND_SOC_NOPM, 0, 0),
b4852b79 1167 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1168 SND_SOC_NOPM, 0, 0),
1a787e7a 1169 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1170 SND_SOC_NOPM, 0, 0),
cc17557e 1171
7393958f
PU		 1172 /* Analog bypasses */
1173 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1174 &twl4030_dapm_abypassr1_control, bypass_event,
1175 SND_SOC_DAPM_POST_REG),
1176 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1177 &twl4030_dapm_abypassl1_control,
1178 bypass_event, SND_SOC_DAPM_POST_REG),
1179 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1180 &twl4030_dapm_abypassr2_control,
1181 bypass_event, SND_SOC_DAPM_POST_REG),
1182 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1183 &twl4030_dapm_abypassl2_control,
1184 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1185 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1186 &twl4030_dapm_abypassv_control,
1187 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1188
6bab83fd
PU		 1189 /* Digital bypasses */
1190 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1191 &twl4030_dapm_dbypassl_control, bypass_event,
1192 SND_SOC_DAPM_POST_REG),
1193 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1194 &twl4030_dapm_dbypassr_control, bypass_event,
1195 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1196 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1197 &twl4030_dapm_dbypassv_control, bypass_event,
1198 SND_SOC_DAPM_POST_REG),
6bab83fd 1199
4005d39a
PU		 1200 /* Digital mixers, power control for the physical DACs */
1201 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1202 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1203 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1204 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1205 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1206 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1207 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1208 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1209 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1210 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1211
1212 /* Analog mixers, power control for the physical PGAs */
1213 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1214 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1215 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1216 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1217 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1218 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1219 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1220 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1221 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1222 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1223
1a787e7a 1224 /* Output MIXER controls */
5e98a464 1225 /* Earpiece */
1a787e7a
JS		 1226 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1227 &twl4030_dapm_earpiece_controls[0],
1228 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1229 /* PreDrivL/R */
1a787e7a
JS		 1230 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1231 &twl4030_dapm_predrivel_controls[0],
1232 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1233 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1234 &twl4030_dapm_predriver_controls[0],
1235 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1236 /* HeadsetL/R */
6943c92e 1237 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1238 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1239 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1240 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1241 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1242 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1243 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1244 &twl4030_dapm_hsor_controls[0],
1245 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1246 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1247 0, 0, NULL, 0, headsetrpga_event,
1248 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1249 /* CarkitL/R */
1a787e7a
JS		 1250 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1251 &twl4030_dapm_carkitl_controls[0],
1252 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1253 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1254 &twl4030_dapm_carkitr_controls[0],
1255 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1256
1257 /* Output MUX controls */
df339804 1258 /* HandsfreeL/R */
5a2e9a48
PU		 1259 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1260 &twl4030_dapm_handsfreel_control),
0f89bdca
PU		 1261 SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
1262 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1263 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1264 0, 0, NULL, 0, handsfreelpga_event,
1265 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1266 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1267 &twl4030_dapm_handsfreer_control),
0f89bdca
PU		 1268 SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
1269 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1270 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1271 0, 0, NULL, 0, handsfreerpga_event,
1272 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1273 /* Vibra */
1274 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1275 &twl4030_dapm_vibra_control),
1276 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1277 &twl4030_dapm_vibrapath_control),
5e98a464 1278
276c6222
PU		 1279 /* Introducing four virtual ADC, since TWL4030 have four channel for
1280 capture */
1281 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1282 SND_SOC_NOPM, 0, 0),
1283 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1284 SND_SOC_NOPM, 0, 0),
1285 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1286 SND_SOC_NOPM, 0, 0),
1287 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1288 SND_SOC_NOPM, 0, 0),
1289
1290 /* Analog/Digital mic path selection.
1291 TX1 Left/Right: either analog Left/Right or Digimic0
1292 TX2 Left/Right: either analog Left/Right or Digimic1 */
1293 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1294 &twl4030_dapm_micpathtx1_control, micpath_event,
1295 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1296 SND_SOC_DAPM_POST_REG),
1297 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1298 &twl4030_dapm_micpathtx2_control, micpath_event,
1299 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1300 SND_SOC_DAPM_POST_REG),
1301
97b8096d
JS		 1302 /* Analog input mixers for the capture amplifiers */
1303 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1304 TWL4030_REG_ANAMICL, 4, 0,
1305 &twl4030_dapm_analoglmic_controls[0],
1306 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1307 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1308 TWL4030_REG_ANAMICR, 4, 0,
1309 &twl4030_dapm_analogrmic_controls[0],
1310 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1311
fb2a2f84
PU		 1312 SND_SOC_DAPM_PGA("ADC Physical Left",
1313 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1314 SND_SOC_DAPM_PGA("ADC Physical Right",
1315 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1316
1317 SND_SOC_DAPM_PGA("Digimic0 Enable",
1318 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1319 SND_SOC_DAPM_PGA("Digimic1 Enable",
1320 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1321
1322 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1323 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1324 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1325
cc17557e
SS		 1326};
1327
1328static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1329 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1330 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1331 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1332 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1333 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1334
1335 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1336 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1337 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1338 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1339 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1340
5e98a464
PU		 1341 /* Internal playback routings */
1342 /* Earpiece */
4005d39a
PU		 1343 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1344 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1345 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1346 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1347 /* PreDrivL */
4005d39a
PU		 1348 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1349 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1350 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1351 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1352 /* PreDrivR */
4005d39a
PU		 1353 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1354 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1355 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1356 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1357 /* HeadsetL */
4005d39a
PU		 1358 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1359 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1360 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1361 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1362 /* HeadsetR */
4005d39a
PU		 1363 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1364 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1365 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1366 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1367 /* CarkitL */
4005d39a
PU		 1368 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1369 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1370 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1371 /* CarkitR */
4005d39a
PU		 1372 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1373 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1374 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1375 /* HandsfreeL */
4005d39a
PU		 1376 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1377 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1378 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1379 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
0f89bdca
PU		 1380 {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
1381 {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
df339804 1382 /* HandsfreeR */
4005d39a
PU		 1383 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1384 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1385 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1386 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
0f89bdca
PU		 1387 {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
1388 {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
376f7839
PU		 1389 /* Vibra */
1390 {"Vibra Mux", "AudioL1", "DAC Left1"},
1391 {"Vibra Mux", "AudioR1", "DAC Right1"},
1392 {"Vibra Mux", "AudioL2", "DAC Left2"},
1393 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1394
cc17557e 1395 /* outputs */
4005d39a
PU		 1396 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1397 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1398 {"EARPIECE", NULL, "Earpiece Mixer"},
1399 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1400 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1401 {"HSOL", NULL, "HeadsetL PGA"},
1402 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1403 {"CARKITL", NULL, "CarkitL Mixer"},
1404 {"CARKITR", NULL, "CarkitR Mixer"},
5a2e9a48
PU		 1405 {"HFL", NULL, "HandsfreeL PGA"},
1406 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1407 {"Vibra Route", "Audio", "Vibra Mux"},
1408 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1409
276c6222
PU		 1410 /* Capture path */
1411 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1412 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1413 {"Analog Left Capture Route", "AUXL", "AUXL"},
1414 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1415
1416 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1417 {"Analog Right Capture Route", "AUXR", "AUXR"},
1418
fb2a2f84
PU		 1419 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1420 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1421
1422 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1423 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1424
1425 /* TX1 Left capture path */
fb2a2f84 1426 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1427 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1428 /* TX1 Right capture path */
fb2a2f84 1429 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1430 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1431 /* TX2 Left capture path */
fb2a2f84 1432 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1433 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1434 /* TX2 Right capture path */
fb2a2f84 1435 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1436 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1437
1438 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1439 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1440 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1441 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1442
7393958f
PU		 1443 /* Analog bypass routes */
1444 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1445 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1446 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1447 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1448 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1449
1450 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1451 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1452 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1453 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1454 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1455
6bab83fd
PU		 1456 /* Digital bypass routes */
1457 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1458 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1459 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1460
4005d39a
PU		 1461 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1462 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1463 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1464
cc17557e
SS		 1465};
1466
1467static int twl4030_add_widgets(struct snd_soc_codec *codec)
1468{
1469 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1470 ARRAY_SIZE(twl4030_dapm_widgets));
1471
1472 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1473
1474 snd_soc_dapm_new_widgets(codec);
1475 return 0;
1476}
1477
cc17557e
SS		 1478static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1479 enum snd_soc_bias_level level)
1480{
7393958f
PU		 1481 struct twl4030_priv *twl4030 = codec->private_data;
1482
cc17557e
SS		 1483 switch (level) {
1484 case SND_SOC_BIAS_ON:
7393958f 1485 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1486 break;
1487 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1488 twl4030_power_up(codec);
1489 if (twl4030->bypass_state)
1490 twl4030_codec_mute(codec, 0);
1491 else
1492 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1493 break;
1494 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1495 twl4030_power_up(codec);
1496 if (twl4030->bypass_state)
1497 twl4030_codec_mute(codec, 0);
1498 else
1499 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1500 break;
1501 case SND_SOC_BIAS_OFF:
1502 twl4030_power_down(codec);
1503 break;
1504 }
1505 codec->bias_level = level;
1506
1507 return 0;
1508}
1509
6b87a91f
PU		 1510static void twl4030_constraints(struct twl4030_priv *twl4030,
1511 struct snd_pcm_substream *mst_substream)
1512{
1513 struct snd_pcm_substream *slv_substream;
1514
1515 /* Pick the stream, which need to be constrained */
1516 if (mst_substream == twl4030->master_substream)
1517 slv_substream = twl4030->slave_substream;
1518 else if (mst_substream == twl4030->slave_substream)
1519 slv_substream = twl4030->master_substream;
1520 else /* This should not happen.. */
1521 return;
1522
1523 /* Set the constraints according to the already configured stream */
1524 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1525 SNDRV_PCM_HW_PARAM_RATE,
1526 twl4030->rate,
1527 twl4030->rate);
1528
1529 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1530 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1531 twl4030->sample_bits,
1532 twl4030->sample_bits);
1533
1534 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1535 SNDRV_PCM_HW_PARAM_CHANNELS,
1536 twl4030->channels,
1537 twl4030->channels);
1538}
1539
8a1f936a
PU		 1540/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1541 * capture has to be enabled/disabled. */
1542static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1543 int enable)
1544{
1545 u8 reg, mask;
1546
1547 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1548
1549 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1550 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1551 else
1552 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1553
1554 if (enable)
1555 reg |= mask;
1556 else
1557 reg &= ~mask;
1558
1559 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1560}
1561
d6648da1
PU		 1562static int twl4030_startup(struct snd_pcm_substream *substream,
1563 struct snd_soc_dai *dai)
7220b9f4
PU		 1564{
1565 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1566 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1567 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1568 struct twl4030_priv *twl4030 = codec->private_data;
1569
7220b9f4 1570 if (twl4030->master_substream) {
7220b9f4 1571 twl4030->slave_substream = substream;
6b87a91f
PU		 1572 /* The DAI has one configuration for playback and capture, so
1573 * if the DAI has been already configured then constrain this
1574 * substream to match it. */
1575 if (twl4030->configured)
1576 twl4030_constraints(twl4030, twl4030->master_substream);
1577 } else {
8a1f936a
PU		 1578 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1579 TWL4030_OPTION_1)) {
1580 /* In option2 4 channel is not supported, set the
1581 * constraint for the first stream for channels, the
1582 * second stream will 'inherit' this cosntraint */
1583 snd_pcm_hw_constraint_minmax(substream->runtime,
1584 SNDRV_PCM_HW_PARAM_CHANNELS,
1585 2, 2);
1586 }
7220b9f4 1587 twl4030->master_substream = substream;
6b87a91f 1588 }
7220b9f4
PU		 1589
1590 return 0;
1591}
1592
d6648da1
PU		 1593static void twl4030_shutdown(struct snd_pcm_substream *substream,
1594 struct snd_soc_dai *dai)
7220b9f4
PU		 1595{
1596 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1597 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1598 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1599 struct twl4030_priv *twl4030 = codec->private_data;
1600
1601 if (twl4030->master_substream == substream)
1602 twl4030->master_substream = twl4030->slave_substream;
1603
1604 twl4030->slave_substream = NULL;
6b87a91f
PU		 1605
1606 /* If all streams are closed, or the remaining stream has not yet
1607 * been configured than set the DAI as not configured. */
1608 if (!twl4030->master_substream)
1609 twl4030->configured = 0;
1610 else if (!twl4030->master_substream->runtime->channels)
1611 twl4030->configured = 0;
8a1f936a
PU		 1612
1613 /* If the closing substream had 4 channel, do the necessary cleanup */
1614 if (substream->runtime->channels == 4)
1615 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1616}
1617
cc17557e 1618static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1619 struct snd_pcm_hw_params *params,
1620 struct snd_soc_dai *dai)
cc17557e
SS		 1621{
1622 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1623 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1624 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1625 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1626 u8 mode, old_mode, format, old_format;
1627
8a1f936a
PU		 1628 /* If the substream has 4 channel, do the necessary setup */
1629 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1630 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1631 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1632
1633 /* Safety check: are we in the correct operating mode and
1634 * the interface is in TDM mode? */
1635 if ((mode & TWL4030_OPTION_1) &&
1636 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1637 twl4030_tdm_enable(codec, substream->stream, 1);
1638 else
1639 return -EINVAL;
1640 }
1641
6b87a91f
PU		 1642 if (twl4030->configured)
1643 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1644 return 0;
1645
cc17557e
SS		 1646 /* bit rate */
1647 old_mode = twl4030_read_reg_cache(codec,
1648 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1649 mode = old_mode & ~TWL4030_APLL_RATE;
1650
1651 switch (params_rate(params)) {
1652 case 8000:
1653 mode |= TWL4030_APLL_RATE_8000;
1654 break;
1655 case 11025:
1656 mode |= TWL4030_APLL_RATE_11025;
1657 break;
1658 case 12000:
1659 mode |= TWL4030_APLL_RATE_12000;
1660 break;
1661 case 16000:
1662 mode |= TWL4030_APLL_RATE_16000;
1663 break;
1664 case 22050:
1665 mode |= TWL4030_APLL_RATE_22050;
1666 break;
1667 case 24000:
1668 mode |= TWL4030_APLL_RATE_24000;
1669 break;
1670 case 32000:
1671 mode |= TWL4030_APLL_RATE_32000;
1672 break;
1673 case 44100:
1674 mode |= TWL4030_APLL_RATE_44100;
1675 break;
1676 case 48000:
1677 mode |= TWL4030_APLL_RATE_48000;
1678 break;
103f211d
PU		 1679 case 96000:
1680 mode |= TWL4030_APLL_RATE_96000;
1681 break;
cc17557e
SS		 1682 default:
1683 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1684 params_rate(params));
1685 return -EINVAL;
1686 }
1687
1688 if (mode != old_mode) {
1689 /* change rate and set CODECPDZ */
7393958f 1690 twl4030_codec_enable(codec, 0);
cc17557e 1691 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1692 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1693 }
1694
1695 /* sample size */
1696 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1697 format = old_format;
1698 format &= ~TWL4030_DATA_WIDTH;
1699 switch (params_format(params)) {
1700 case SNDRV_PCM_FORMAT_S16_LE:
1701 format |= TWL4030_DATA_WIDTH_16S_16W;
1702 break;
1703 case SNDRV_PCM_FORMAT_S24_LE:
1704 format |= TWL4030_DATA_WIDTH_32S_24W;
1705 break;
1706 default:
1707 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1708 params_format(params));
1709 return -EINVAL;
1710 }
1711
1712 if (format != old_format) {
1713
1714 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1715 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1716
1717 /* change format */
1718 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1719
1720 /* set CODECPDZ afterwards */
db04e2c5 1721 twl4030_codec_enable(codec, 1);
cc17557e 1722 }
6b87a91f
PU		 1723
1724 /* Store the important parameters for the DAI configuration and set
1725 * the DAI as configured */
1726 twl4030->configured = 1;
1727 twl4030->rate = params_rate(params);
1728 twl4030->sample_bits = hw_param_interval(params,
1729 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1730 twl4030->channels = params_channels(params);
1731
1732 /* If both playback and capture streams are open, and one of them
1733 * is setting the hw parameters right now (since we are here), set
1734 * constraints to the other stream to match the current one. */
1735 if (twl4030->slave_substream)
1736 twl4030_constraints(twl4030, substream);
1737
cc17557e
SS		 1738 return 0;
1739}
1740
1741static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1742 int clk_id, unsigned int freq, int dir)
1743{
1744 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1745 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1746 u8 infreq;
1747
1748 switch (freq) {
1749 case 19200000:
1750 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1751 twl4030->sysclk = 19200;
cc17557e
SS		 1752 break;
1753 case 26000000:
1754 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1755 twl4030->sysclk = 26000;
cc17557e
SS		 1756 break;
1757 case 38400000:
1758 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1759 twl4030->sysclk = 38400;
cc17557e
SS		 1760 break;
1761 default:
1762 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1763 freq);
1764 return -EINVAL;
1765 }
1766
1767 infreq |= TWL4030_APLL_EN;
1768 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1769
1770 return 0;
1771}
1772
1773static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1774 unsigned int fmt)
1775{
1776 struct snd_soc_codec *codec = codec_dai->codec;
1777 u8 old_format, format;
1778
1779 /* get format */
1780 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1781 format = old_format;
1782
1783 /* set master/slave audio interface */
1784 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1785 case SND_SOC_DAIFMT_CBM_CFM:
1786 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1787 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1788 break;
1789 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1790 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1791 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1792 break;
1793 default:
1794 return -EINVAL;
1795 }
1796
1797 /* interface format */
1798 format &= ~TWL4030_AIF_FORMAT;
1799 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1800 case SND_SOC_DAIFMT_I2S:
1801 format |= TWL4030_AIF_FORMAT_CODEC;
1802 break;
8a1f936a
PU		 1803 case SND_SOC_DAIFMT_DSP_A:
1804 format |= TWL4030_AIF_FORMAT_TDM;
1805 break;
cc17557e
SS		 1806 default:
1807 return -EINVAL;
1808 }
1809
1810 if (format != old_format) {
1811
1812 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1813 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1814
1815 /* change format */
1816 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1817
1818 /* set CODECPDZ afterwards */
db04e2c5 1819 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1820 }
1821
1822 return 0;
1823}
1824
b7a755a8
MLC		 1825/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1826 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1827static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1828 int enable)
1829{
1830 u8 reg, mask;
1831
1832 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1833
1834 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1835 mask = TWL4030_ARXL1_VRX_EN;
1836 else
1837 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1838
1839 if (enable)
1840 reg |= mask;
1841 else
1842 reg &= ~mask;
1843
1844 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1845}
1846
7154b3e8
JS		 1847static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1848 struct snd_soc_dai *dai)
1849{
1850 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1851 struct snd_soc_device *socdev = rtd->socdev;
1852 struct snd_soc_codec *codec = socdev->card->codec;
1853 u8 infreq;
1854 u8 mode;
1855
1856 /* If the system master clock is not 26MHz, the voice PCM interface is
1857 * not avilable.
1858 */
1859 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1860 & TWL4030_APLL_INFREQ;
1861
1862 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1863 printk(KERN_ERR "TWL4030 voice startup: "
1864 "MCLK is not 26MHz, call set_sysclk() on init\n");
1865 return -EINVAL;
1866 }
1867
1868 /* If the codec mode is not option2, the voice PCM interface is not
1869 * avilable.
1870 */
1871 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1872 & TWL4030_OPT_MODE;
1873
1874 if (mode != TWL4030_OPTION_2) {
1875 printk(KERN_ERR "TWL4030 voice startup: "
1876 "the codec mode is not option2\n");
1877 return -EINVAL;
1878 }
1879
1880 return 0;
1881}
1882
b7a755a8
MLC		 1883static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1884 struct snd_soc_dai *dai)
1885{
1886 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1887 struct snd_soc_device *socdev = rtd->socdev;
1888 struct snd_soc_codec *codec = socdev->card->codec;
1889
1890 /* Enable voice digital filters */
1891 twl4030_voice_enable(codec, substream->stream, 0);
1892}
1893
7154b3e8
JS		 1894static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1895 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1896{
1897 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1898 struct snd_soc_device *socdev = rtd->socdev;
1899 struct snd_soc_codec *codec = socdev->card->codec;
1900 u8 old_mode, mode;
1901
b7a755a8
MLC		 1902 /* Enable voice digital filters */
1903 twl4030_voice_enable(codec, substream->stream, 1);
1904
7154b3e8
JS		 1905 /* bit rate */
1906 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1907 & ~(TWL4030_CODECPDZ);
1908 mode = old_mode;
1909
1910 switch (params_rate(params)) {
1911 case 8000:
1912 mode &= ~(TWL4030_SEL_16K);
1913 break;
1914 case 16000:
1915 mode |= TWL4030_SEL_16K;
1916 break;
1917 default:
1918 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1919 params_rate(params));
1920 return -EINVAL;
1921 }
1922
1923 if (mode != old_mode) {
1924 /* change rate and set CODECPDZ */
1925 twl4030_codec_enable(codec, 0);
1926 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1927 twl4030_codec_enable(codec, 1);
1928 }
1929
1930 return 0;
1931}
1932
1933static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1934 int clk_id, unsigned int freq, int dir)
1935{
1936 struct snd_soc_codec *codec = codec_dai->codec;
1937 u8 infreq;
1938
1939 switch (freq) {
1940 case 26000000:
1941 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1942 break;
1943 default:
1944 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1945 freq);
1946 return -EINVAL;
1947 }
1948
1949 infreq |= TWL4030_APLL_EN;
1950 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1951
1952 return 0;
1953}
1954
1955static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1956 unsigned int fmt)
1957{
1958 struct snd_soc_codec *codec = codec_dai->codec;
1959 u8 old_format, format;
1960
1961 /* get format */
1962 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1963 format = old_format;
1964
1965 /* set master/slave audio interface */
1966 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 1967 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 1968 format &= ~(TWL4030_VIF_SLAVE_EN);
1969 break;
1970 case SND_SOC_DAIFMT_CBS_CFS:
1971 format |= TWL4030_VIF_SLAVE_EN;
1972 break;
1973 default:
1974 return -EINVAL;
1975 }
1976
1977 /* clock inversion */
1978 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1979 case SND_SOC_DAIFMT_IB_NF:
1980 format &= ~(TWL4030_VIF_FORMAT);
1981 break;
1982 case SND_SOC_DAIFMT_NB_IF:
1983 format |= TWL4030_VIF_FORMAT;
1984 break;
1985 default:
1986 return -EINVAL;
1987 }
1988
1989 if (format != old_format) {
1990 /* change format and set CODECPDZ */
1991 twl4030_codec_enable(codec, 0);
1992 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1993 twl4030_codec_enable(codec, 1);
1994 }
1995
1996 return 0;
1997}
1998
bbba9444 1999#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2000#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2001
10d9e3d9 2002static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2003 .startup = twl4030_startup,
2004 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2005 .hw_params = twl4030_hw_params,
2006 .set_sysclk = twl4030_set_dai_sysclk,
2007 .set_fmt = twl4030_set_dai_fmt,
2008};
2009
7154b3e8
JS		 2010static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2011 .startup = twl4030_voice_startup,
b7a755a8 2012 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2013 .hw_params = twl4030_voice_hw_params,
2014 .set_sysclk = twl4030_voice_set_dai_sysclk,
2015 .set_fmt = twl4030_voice_set_dai_fmt,
2016};
2017
2018struct snd_soc_dai twl4030_dai[] = {
2019{
cc17557e
SS		 2020 .name = "twl4030",
2021 .playback = {
b4852b79 2022 .stream_name = "HiFi Playback",
cc17557e 2023 .channels_min = 2,
8a1f936a 2024 .channels_max = 4,
31ad0f31 2025 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2026 .formats = TWL4030_FORMATS,},
2027 .capture = {
2028 .stream_name = "Capture",
2029 .channels_min = 2,
8a1f936a 2030 .channels_max = 4,
cc17557e
SS		 2031 .rates = TWL4030_RATES,
2032 .formats = TWL4030_FORMATS,},
10d9e3d9 2033 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2034},
2035{
2036 .name = "twl4030 Voice",
2037 .playback = {
b4852b79 2038 .stream_name = "Voice Playback",
7154b3e8
JS		 2039 .channels_min = 1,
2040 .channels_max = 1,
2041 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2042 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2043 .capture = {
2044 .stream_name = "Capture",
2045 .channels_min = 1,
2046 .channels_max = 2,
2047 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2048 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2049 .ops = &twl4030_dai_voice_ops,
2050},
cc17557e
SS		 2051};
2052EXPORT_SYMBOL_GPL(twl4030_dai);
2053
2054static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2055{
2056 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2057 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2058
2059 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2060
2061 return 0;
2062}
2063
2064static int twl4030_resume(struct platform_device *pdev)
2065{
2066 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2067 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2068
2069 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2070 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2071 return 0;
2072}
2073
2074/*
2075 * initialize the driver
2076 * register the mixer and dsp interfaces with the kernel
2077 */
2078
2079static int twl4030_init(struct snd_soc_device *socdev)
2080{
6627a653 2081 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2082 struct twl4030_setup_data *setup = socdev->codec_data;
2083 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2084 int ret = 0;
2085
2086 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2087
2088 codec->name = "twl4030";
2089 codec->owner = THIS_MODULE;
2090 codec->read = twl4030_read_reg_cache;
2091 codec->write = twl4030_write;
2092 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2093 codec->dai = twl4030_dai;
2094 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2095 codec->reg_cache_size = sizeof(twl4030_reg);
2096 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2097 GFP_KERNEL);
2098 if (codec->reg_cache == NULL)
2099 return -ENOMEM;
2100
9da28c7b
PU		 2101 /* Configuration for headset ramp delay from setup data */
2102 if (setup) {
2103 unsigned char hs_pop;
2104
2105 if (setup->sysclk)
2106 twl4030->sysclk = setup->sysclk;
2107 else
2108 twl4030->sysclk = 26000;
2109
2110 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2111 hs_pop &= ~TWL4030_RAMP_DELAY;
2112 hs_pop |= (setup->ramp_delay_value << 2);
2113 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2114 } else {
2115 twl4030->sysclk = 26000;
2116 }
2117
cc17557e
SS		 2118 /* register pcms */
2119 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2120 if (ret < 0) {
2121 printk(KERN_ERR "twl4030: failed to create pcms\n");
2122 goto pcm_err;
2123 }
2124
2125 twl4030_init_chip(codec);
2126
2127 /* power on device */
2128 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2129
3e8e1952
IM		 2130 snd_soc_add_controls(codec, twl4030_snd_controls,
2131 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2132 twl4030_add_widgets(codec);
2133
968a6025 2134 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2135 if (ret < 0) {
2136 printk(KERN_ERR "twl4030: failed to register card\n");
2137 goto card_err;
2138 }
2139
2140 return ret;
2141
2142card_err:
2143 snd_soc_free_pcms(socdev);
2144 snd_soc_dapm_free(socdev);
2145pcm_err:
2146 kfree(codec->reg_cache);
2147 return ret;
2148}
2149
2150static struct snd_soc_device *twl4030_socdev;
2151
2152static int twl4030_probe(struct platform_device *pdev)
2153{
2154 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2155 struct snd_soc_codec *codec;
7393958f 2156 struct twl4030_priv *twl4030;
cc17557e
SS		 2157
2158 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2159 if (codec == NULL)
2160 return -ENOMEM;
2161
7393958f
PU		 2162 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2163 if (twl4030 == NULL) {
2164 kfree(codec);
2165 return -ENOMEM;
2166 }
2167
2168 codec->private_data = twl4030;
6627a653 2169 socdev->card->codec = codec;
cc17557e
SS		 2170 mutex_init(&codec->mutex);
2171 INIT_LIST_HEAD(&codec->dapm_widgets);
2172 INIT_LIST_HEAD(&codec->dapm_paths);
2173
2174 twl4030_socdev = socdev;
2175 twl4030_init(socdev);
2176
2177 return 0;
2178}
2179
2180static int twl4030_remove(struct platform_device *pdev)
2181{
2182 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2183 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2184
2185 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2186 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2187 snd_soc_free_pcms(socdev);
2188 snd_soc_dapm_free(socdev);
7393958f 2189 kfree(codec->private_data);
cc17557e
SS		 2190 kfree(codec);
2191
2192 return 0;
2193}
2194
2195struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2196 .probe = twl4030_probe,
2197 .remove = twl4030_remove,
2198 .suspend = twl4030_suspend,
2199 .resume = twl4030_resume,
2200};
2201EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2202
24e07db8 2203static int __init twl4030_modinit(void)
64089b84 2204{
7154b3e8 2205 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2206}
24e07db8 2207module_init(twl4030_modinit);
64089b84
MB		 2208
2209static void __exit twl4030_exit(void)
2210{
7154b3e8 2211 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2212}
2213module_exit(twl4030_exit);
2214
cc17557e
SS		 2215MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2216MODULE_AUTHOR("Steve Sakoman");
2217MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.153055 seconds and 5 git commands to generate.