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ASoC: tpa6130a2: Remove redundant OOM message
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e 50
7393958f
PU		 51/* codec private data */
52struct twl4030_priv {
7393958f 53 unsigned int codec_powered;
7b4c734e
PU		 54
55 /* reference counts of AIF/APLL users */
2845fa13 56 unsigned int apll_enabled;
7220b9f4
PU		 57
58 struct snd_pcm_substream *master_substream;
59 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 60
61 unsigned int configured;
62 unsigned int rate;
63 unsigned int sample_bits;
64 unsigned int channels;
6943c92e
PU		 65
66 unsigned int sysclk;
67
c96907f2
PU		 68 /* Output (with associated amp) states */
69 u8 hsl_enabled, hsr_enabled;
70 u8 earpiece_enabled;
71 u8 predrivel_enabled, predriver_enabled;
72 u8 carkitl_enabled, carkitr_enabled;
8b3bca29 73 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
01ea6ba2 74
182f73f6 75 struct twl4030_codec_data *pdata;
7393958f
PU		 76};
77
8b3bca29
PU		 78static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
79{
80 int i;
81 u8 byte;
82
83 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
84 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
85 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
86 }
87}
88
efc8acff 89static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg)
cc17557e 90{
efc8acff
PU		 91 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
92 u8 value = 0;
cc17557e
SS		 93
94 if (reg >= TWL4030_CACHEREGNUM)
efc8acff
PU		 95 return -EIO;
96
97 switch (reg) {
98 case TWL4030_REG_EAR_CTL:
99 case TWL4030_REG_PREDL_CTL:
100 case TWL4030_REG_PREDR_CTL:
101 case TWL4030_REG_PRECKL_CTL:
102 case TWL4030_REG_PRECKR_CTL:
103 case TWL4030_REG_HS_GAIN_SET:
104 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
105 break;
106 default:
107 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
108 break;
109 }
110
111 return value;
cc17557e
SS		 112}
113
b703b504 114static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,
a8fc415c 115 unsigned int reg)
cc17557e 116{
a8fc415c 117 bool write_to_reg = false;
c96907f2 118
052901f4
LPC		 119 /* Decide if the given register can be written */
120 switch (reg) {
121 case TWL4030_REG_EAR_CTL:
122 if (twl4030->earpiece_enabled)
a8fc415c 123 write_to_reg = true;
052901f4
LPC		 124 break;
125 case TWL4030_REG_PREDL_CTL:
126 if (twl4030->predrivel_enabled)
a8fc415c 127 write_to_reg = true;
052901f4
LPC		 128 break;
129 case TWL4030_REG_PREDR_CTL:
130 if (twl4030->predriver_enabled)
a8fc415c 131 write_to_reg = true;
052901f4
LPC		 132 break;
133 case TWL4030_REG_PRECKL_CTL:
134 if (twl4030->carkitl_enabled)
a8fc415c 135 write_to_reg = true;
052901f4
LPC		 136 break;
137 case TWL4030_REG_PRECKR_CTL:
138 if (twl4030->carkitr_enabled)
a8fc415c 139 write_to_reg = true;
052901f4
LPC		 140 break;
141 case TWL4030_REG_HS_GAIN_SET:
142 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 143 write_to_reg = true;
052901f4
LPC		 144 break;
145 default:
146 /* All other register can be written */
a8fc415c 147 write_to_reg = true;
052901f4 148 break;
c96907f2 149 }
a8fc415c
PU		 150
151 return write_to_reg;
152}
153
7ded5fe0
PU		 154static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg,
155 unsigned int value)
a8fc415c 156{
a450aa6f
PU		 157 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
158
159 /* Update the ctl cache */
160 switch (reg) {
161 case TWL4030_REG_EAR_CTL:
162 case TWL4030_REG_PREDL_CTL:
163 case TWL4030_REG_PREDR_CTL:
164 case TWL4030_REG_PRECKL_CTL:
165 case TWL4030_REG_PRECKR_CTL:
166 case TWL4030_REG_HS_GAIN_SET:
167 twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
168 break;
169 default:
170 break;
171 }
172
b703b504 173 if (twl4030_can_write_to_chip(twl4030, reg))
a8fc415c 174 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 175
c96907f2 176 return 0;
cc17557e
SS		 177}
178
7e6120c5
PU		 179static inline void twl4030_wait_ms(int time)
180{
181 if (time < 60) {
182 time *= 1000;
183 usleep_range(time, time + 500);
184 } else {
185 msleep(time);
186 }
187}
188
db04e2c5 189static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 190{
b2c812e2 191 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 192 int mode;
cc17557e 193
7393958f
PU		 194 if (enable == twl4030->codec_powered)
195 return;
196
db04e2c5 197 if (enable)
57fe7251 198 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 199 else
57fe7251 200 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 201
efc8acff 202 if (mode >= 0)
7a1fecf5 203 twl4030->codec_powered = enable;
cc17557e
SS		 204
205 /* REVISIT: this delay is present in TI sample drivers */
206 /* but there seems to be no TRM requirement for it */
207 udelay(10);
208}
209
2d6d649a
PU		 210static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
211 struct device_node *node)
212{
213 int value;
214
215 of_property_read_u32(node, "ti,digimic_delay",
216 &pdata->digimic_delay);
217 of_property_read_u32(node, "ti,ramp_delay_value",
218 &pdata->ramp_delay_value);
219 of_property_read_u32(node, "ti,offset_cncl_path",
220 &pdata->offset_cncl_path);
221 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
222 pdata->hs_extmute = value;
223
224 pdata->hs_extmute_gpio = of_get_named_gpio(node,
225 "ti,hs_extmute_gpio", 0);
226 if (gpio_is_valid(pdata->hs_extmute_gpio))
227 pdata->hs_extmute = 1;
228}
229
230static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 231{
4ae6df5e 232 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 233 struct device_node *twl4030_codec_node = NULL;
234
235 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
236 "codec");
237
238 if (!pdata && twl4030_codec_node) {
239 pdata = devm_kzalloc(codec->dev,
240 sizeof(struct twl4030_codec_data),
241 GFP_KERNEL);
242 if (!pdata) {
243 dev_err(codec->dev, "Can not allocate memory\n");
244 return NULL;
245 }
246 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
247 }
248
249 return pdata;
250}
251
252static void twl4030_init_chip(struct snd_soc_codec *codec)
253{
254 struct twl4030_codec_data *pdata;
b2c812e2 255 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 256 u8 reg, byte;
257 int i = 0;
7393958f 258
2d6d649a
PU		 259 pdata = twl4030_get_pdata(codec);
260
5712ded9
PU		 261 if (pdata && pdata->hs_extmute) {
262 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
263 int ret;
264
265 if (!pdata->hs_extmute_gpio)
266 dev_warn(codec->dev,
267 "Extmute GPIO is 0 is this correct?\n");
268
269 ret = gpio_request_one(pdata->hs_extmute_gpio,
270 GPIOF_OUT_INIT_LOW,
271 "hs_extmute");
272 if (ret) {
273 dev_err(codec->dev,
274 "Failed to get hs_extmute GPIO\n");
275 pdata->hs_extmute_gpio = -1;
276 }
277 } else {
278 u8 pin_mux;
279
280 /* Set TWL4030 GPIO6 as EXTMUTE signal */
281 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
282 TWL4030_PMBR1_REG);
283 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
284 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
285 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
286 TWL4030_PMBR1_REG);
281ecd16
PU		 287 }
288 }
289
8b3bca29
PU		 290 /* Initialize the local ctl register cache */
291 tw4030_init_ctl_cache(twl4030);
292
ee4ccac7 293 /* anti-pop when changing analog gain */
efc8acff 294 reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1);
ee4ccac7 295 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
7ded5fe0 296 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 297
ee4ccac7 298 twl4030_write(codec, TWL4030_REG_OPTION,
7ded5fe0
PU		 299 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
300 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 301
3c36cc68
PU		 302 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
303 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
304
ee4ccac7 305 /* Machine dependent setup */
f0fba2ad 306 if (!pdata)
7393958f
PU		 307 return;
308
182f73f6 309 twl4030->pdata = pdata;
ee4ccac7 310
efc8acff 311 reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
ee4ccac7 312 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 313 reg |= (pdata->ramp_delay_value << 2);
efc8acff 314 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 315
316 /* initiate offset cancellation */
ee4ccac7
PU		 317 twl4030_codec_enable(codec, 1);
318
efc8acff 319 reg = twl4030_read(codec, TWL4030_REG_ANAMICL);
ee4ccac7 320 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 321 reg |= pdata->offset_cncl_path;
006f367e 322 twl4030_write(codec, TWL4030_REG_ANAMICL,
7ded5fe0 323 reg | TWL4030_CNCL_OFFSET_START);
006f367e 324
7e6120c5
PU		 325 /*
326 * Wait for offset cancellation to complete.
327 * Since this takes a while, do not slam the i2c.
328 * Start polling the status after ~20ms.
329 */
330 msleep(20);
006f367e 331 do {
7e6120c5 332 usleep_range(1000, 2000);
efc8acff 333 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
fc7b92fc 334 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
7ded5fe0 335 TWL4030_REG_ANAMICL);
efc8acff 336 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
006f367e
PU		 337 } while ((i++ < 100) &&
338 ((byte & TWL4030_CNCL_OFFSET_START) ==
339 TWL4030_CNCL_OFFSET_START));
340
006f367e 341 twl4030_codec_enable(codec, 0);
006f367e
PU		 342}
343
ee4ccac7 344static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 345{
ee4ccac7
PU		 346 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
347 int status = -1;
348
349 if (enable) {
350 twl4030->apll_enabled++;
351 if (twl4030->apll_enabled == 1)
57fe7251
PU		 352 status = twl4030_audio_enable_resource(
353 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 354 } else {
355 twl4030->apll_enabled--;
356 if (!twl4030->apll_enabled)
57fe7251
PU		 357 status = twl4030_audio_disable_resource(
358 TWL4030_AUDIO_RES_APLL);
ee4ccac7 359 }
006f367e
PU		 360}
361
5e98a464 362/* Earpiece */
1a787e7a
JS		 363static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
364 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
365 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
366 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
367 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
368};
5e98a464 369
2a6f5c58 370/* PreDrive Left */
1a787e7a
JS		 371static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
372 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
373 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
374 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
375 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
376};
2a6f5c58
PU		 377
378/* PreDrive Right */
1a787e7a
JS		 379static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
380 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
381 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
382 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
383 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
384};
2a6f5c58 385
dfad21a2 386/* Headset Left */
1a787e7a
JS		 387static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
388 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
389 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
390 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
391};
dfad21a2
PU		 392
393/* Headset Right */
1a787e7a
JS		 394static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
395 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
396 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
397 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
398};
dfad21a2 399
5152d8c2 400/* Carkit Left */
1a787e7a
JS		 401static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
402 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
403 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
404 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
405};
5152d8c2
PU		 406
407/* Carkit Right */
1a787e7a
JS		 408static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
409 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
410 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
411 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
412};
5152d8c2 413
df339804
PU		 414/* Handsfree Left */
415static const char *twl4030_handsfreel_texts[] =
1a787e7a 416 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804 417
9f04fba7
TI		 418static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,
419 TWL4030_REG_HFL_CTL, 0,
420 twl4030_handsfreel_texts);
df339804
PU		 421
422static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
423SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
424
0f89bdca
PU		 425/* Handsfree Left virtual mute */
426static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 427 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 428
df339804
PU		 429/* Handsfree Right */
430static const char *twl4030_handsfreer_texts[] =
1a787e7a 431 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804 432
9f04fba7
TI		 433static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,
434 TWL4030_REG_HFR_CTL, 0,
435 twl4030_handsfreer_texts);
df339804
PU		 436
437static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
438SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
439
0f89bdca
PU		 440/* Handsfree Right virtual mute */
441static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 442 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 443
376f7839
PU		 444/* Vibra */
445/* Vibra audio path selection */
446static const char *twl4030_vibra_texts[] =
447 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
448
9f04fba7
TI		 449static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,
450 TWL4030_REG_VIBRA_CTL, 2,
451 twl4030_vibra_texts);
376f7839
PU		 452
453static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
454SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
455
456/* Vibra path selection: local vibrator (PWM) or audio driven */
457static const char *twl4030_vibrapath_texts[] =
458 {"Local vibrator", "Audio"};
459
9f04fba7
TI		 460static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,
461 TWL4030_REG_VIBRA_CTL, 4,
462 twl4030_vibrapath_texts);
376f7839
PU		 463
464static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
465SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
466
276c6222 467/* Left analog microphone selection */
97b8096d 468static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 469 SOC_DAPM_SINGLE("Main Mic Capture Switch",
470 TWL4030_REG_ANAMICL, 0, 1, 0),
471 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
472 TWL4030_REG_ANAMICL, 1, 1, 0),
473 SOC_DAPM_SINGLE("AUXL Capture Switch",
474 TWL4030_REG_ANAMICL, 2, 1, 0),
475 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
476 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 477};
276c6222
PU		 478
479/* Right analog microphone selection */
97b8096d 480static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 481 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
482 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 483};
276c6222
PU		 484
485/* TX1 L/R Analog/Digital microphone selection */
486static const char *twl4030_micpathtx1_texts[] =
487 {"Analog", "Digimic0"};
488
9f04fba7
TI		 489static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,
490 TWL4030_REG_ADCMICSEL, 0,
491 twl4030_micpathtx1_texts);
276c6222
PU		 492
493static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
494SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
495
496/* TX2 L/R Analog/Digital microphone selection */
497static const char *twl4030_micpathtx2_texts[] =
498 {"Analog", "Digimic1"};
499
9f04fba7
TI		 500static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,
501 TWL4030_REG_ADCMICSEL, 2,
502 twl4030_micpathtx2_texts);
276c6222
PU		 503
504static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
505SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
506
7393958f
PU		 507/* Analog bypass for AudioR1 */
508static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
509 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
510
511/* Analog bypass for AudioL1 */
512static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
513 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
514
515/* Analog bypass for AudioR2 */
516static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
517 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
518
519/* Analog bypass for AudioL2 */
520static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
521 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
522
fcd274a3
LCM		 523/* Analog bypass for Voice */
524static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
525 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
526
8b0d3153 527/* Digital bypass gain, mute instead of -30dB */
6bab83fd 528static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 529 TLV_DB_RANGE_HEAD(3),
530 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
531 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 532 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
533};
534
535/* Digital bypass left (TX1L -> RX2L) */
536static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
537 SOC_DAPM_SINGLE_TLV("Volume",
538 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
539 twl4030_dapm_dbypass_tlv);
540
541/* Digital bypass right (TX1R -> RX2R) */
542static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
543 SOC_DAPM_SINGLE_TLV("Volume",
544 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
545 twl4030_dapm_dbypass_tlv);
546
ee8f6894
LCM		 547/*
548 * Voice Sidetone GAIN volume control:
549 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
550 */
551static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
552
553/* Digital bypass voice: sidetone (VUL -> VDL)*/
554static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
555 SOC_DAPM_SINGLE_TLV("Volume",
556 TWL4030_REG_VSTPGA, 0, 0x29, 0,
557 twl4030_dapm_dbypassv_tlv);
558
9008adf9
PU		 559/*
560 * Output PGA builder:
561 * Handle the muting and unmuting of the given output (turning off the
562 * amplifier associated with the output pin)
c96907f2
PU		 563 * On mute bypass the reg_cache and write 0 to the register
564 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 565 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
566 */
567#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
568static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
7ded5fe0 569 struct snd_kcontrol *kcontrol, int event) \
9008adf9 570{ \
b2c812e2 571 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 572 \
573 switch (event) { \
574 case SND_SOC_DAPM_POST_PMU: \
c96907f2 575 twl4030->pin_name##_enabled = 1; \
efc8acff 576 twl4030_write(w->codec, reg, twl4030_read(w->codec, reg)); \
9008adf9
PU		 577 break; \
578 case SND_SOC_DAPM_POST_PMD: \
c96907f2 579 twl4030->pin_name##_enabled = 0; \
7ded5fe0 580 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \
9008adf9
PU		 581 break; \
582 } \
583 return 0; \
584}
585
586TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
587TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
588TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
589TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
590TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
591
5a2e9a48 592static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 593{
49d92c7d
SM		 594 unsigned char hs_ctl;
595
efc8acff 596 hs_ctl = twl4030_read(codec, reg);
49d92c7d 597
5a2e9a48
PU		 598 if (ramp) {
599 /* HF ramp-up */
600 hs_ctl |= TWL4030_HF_CTL_REF_EN;
601 twl4030_write(codec, reg, hs_ctl);
602 udelay(10);
49d92c7d 603 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 604 twl4030_write(codec, reg, hs_ctl);
605 udelay(40);
49d92c7d 606 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 607 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 608 twl4030_write(codec, reg, hs_ctl);
49d92c7d 609 } else {
5a2e9a48
PU		 610 /* HF ramp-down */
611 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
612 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
613 twl4030_write(codec, reg, hs_ctl);
614 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
615 twl4030_write(codec, reg, hs_ctl);
616 udelay(40);
617 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
618 twl4030_write(codec, reg, hs_ctl);
49d92c7d 619 }
5a2e9a48 620}
49d92c7d 621
5a2e9a48 622static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 623 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 624{
625 switch (event) {
626 case SND_SOC_DAPM_POST_PMU:
627 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
628 break;
629 case SND_SOC_DAPM_POST_PMD:
630 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
631 break;
632 }
633 return 0;
634}
635
636static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 637 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 638{
639 switch (event) {
640 case SND_SOC_DAPM_POST_PMU:
641 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
642 break;
643 case SND_SOC_DAPM_POST_PMD:
644 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
645 break;
646 }
49d92c7d
SM		 647 return 0;
648}
649
86139a13 650static int vibramux_event(struct snd_soc_dapm_widget *w,
7ded5fe0 651 struct snd_kcontrol *kcontrol, int event)
86139a13
JV		 652{
653 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
654 return 0;
655}
656
7729cf74 657static int apll_event(struct snd_soc_dapm_widget *w,
7ded5fe0 658 struct snd_kcontrol *kcontrol, int event)
7729cf74
PU		 659{
660 switch (event) {
661 case SND_SOC_DAPM_PRE_PMU:
662 twl4030_apll_enable(w->codec, 1);
663 break;
664 case SND_SOC_DAPM_POST_PMD:
665 twl4030_apll_enable(w->codec, 0);
666 break;
667 }
668 return 0;
669}
670
7b4c734e 671static int aif_event(struct snd_soc_dapm_widget *w,
7ded5fe0 672 struct snd_kcontrol *kcontrol, int event)
7b4c734e
PU		 673{
674 u8 audio_if;
675
efc8acff 676 audio_if = twl4030_read(w->codec, TWL4030_REG_AUDIO_IF);
7b4c734e
PU		 677 switch (event) {
678 case SND_SOC_DAPM_PRE_PMU:
679 /* Enable AIF */
680 /* enable the PLL before we use it to clock the DAI */
681 twl4030_apll_enable(w->codec, 1);
682
683 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 684 audio_if | TWL4030_AIF_EN);
7b4c734e
PU		 685 break;
686 case SND_SOC_DAPM_POST_PMD:
687 /* disable the DAI before we stop it's source PLL */
688 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 689 audio_if & ~TWL4030_AIF_EN);
7b4c734e
PU		 690 twl4030_apll_enable(w->codec, 0);
691 break;
692 }
693 return 0;
694}
695
6943c92e 696static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 697{
698 unsigned char hs_gain, hs_pop;
b2c812e2 699 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 700 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 701 /* Base values for ramp delay calculation: 2^19 - 2^26 */
702 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
703 8388608, 16777216, 33554432, 67108864};
7e6120c5 704 unsigned int delay;
aad749e5 705
efc8acff
PU		 706 hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET);
707 hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 708 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
709 twl4030->sysclk) + 1;
aad749e5 710
4e49ffd1
CVJ		 711 /* Enable external mute control, this dramatically reduces
712 * the pop-noise */
f0fba2ad 713 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 714 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
715 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 716 } else {
717 hs_pop |= TWL4030_EXTMUTE;
718 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
719 }
720 }
721
6943c92e
PU		 722 if (ramp) {
723 /* Headset ramp-up according to the TRM */
aad749e5 724 hs_pop |= TWL4030_VMID_EN;
6943c92e 725 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2 726 /* Actually write to the register */
7ded5fe0
PU		 727 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
728 TWL4030_REG_HS_GAIN_SET);
aad749e5 729 hs_pop |= TWL4030_RAMP_EN;
6943c92e 730 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 731 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 732 twl4030_wait_ms(delay);
6943c92e
PU		 733 } else {
734 /* Headset ramp-down _not_ according to
735 * the TRM, but in a way that it is working */
aad749e5 736 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 737 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
738 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 739 twl4030_wait_ms(delay);
aad749e5 740 /* Bypass the reg_cache to mute the headset */
7ded5fe0
PU		 741 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
742 TWL4030_REG_HS_GAIN_SET);
6943c92e 743
aad749e5 744 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
746 }
4e49ffd1
CVJ		 747
748 /* Disable external mute */
f0fba2ad 749 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 750 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
751 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 752 } else {
753 hs_pop &= ~TWL4030_EXTMUTE;
754 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
755 }
756 }
6943c92e
PU		 757}
758
759static int headsetlpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 760 struct snd_kcontrol *kcontrol, int event)
6943c92e 761{
b2c812e2 762 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 763
764 switch (event) {
765 case SND_SOC_DAPM_POST_PMU:
766 /* Do the ramp-up only once */
767 if (!twl4030->hsr_enabled)
768 headset_ramp(w->codec, 1);
769
770 twl4030->hsl_enabled = 1;
771 break;
772 case SND_SOC_DAPM_POST_PMD:
773 /* Do the ramp-down only if both headsetL/R is disabled */
774 if (!twl4030->hsr_enabled)
775 headset_ramp(w->codec, 0);
776
777 twl4030->hsl_enabled = 0;
778 break;
779 }
780 return 0;
781}
782
783static int headsetrpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 784 struct snd_kcontrol *kcontrol, int event)
6943c92e 785{
b2c812e2 786 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 787
788 switch (event) {
789 case SND_SOC_DAPM_POST_PMU:
790 /* Do the ramp-up only once */
791 if (!twl4030->hsl_enabled)
792 headset_ramp(w->codec, 1);
793
794 twl4030->hsr_enabled = 1;
795 break;
796 case SND_SOC_DAPM_POST_PMD:
797 /* Do the ramp-down only if both headsetL/R is disabled */
798 if (!twl4030->hsl_enabled)
799 headset_ramp(w->codec, 0);
800
801 twl4030->hsr_enabled = 0;
aad749e5
PU		 802 break;
803 }
804 return 0;
805}
806
01ea6ba2 807static int digimic_event(struct snd_soc_dapm_widget *w,
7ded5fe0 808 struct snd_kcontrol *kcontrol, int event)
01ea6ba2
PU		 809{
810 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 811 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 812
182f73f6
PU		 813 if (pdata && pdata->digimic_delay)
814 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 815 return 0;
816}
817
b0bd53a7
PU		 818/*
819 * Some of the gain controls in TWL (mostly those which are associated with
820 * the outputs) are implemented in an interesting way:
821 * 0x0 : Power down (mute)
822 * 0x1 : 6dB
823 * 0x2 : 0 dB
824 * 0x3 : -6 dB
825 * Inverting not going to help with these.
826 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
827 */
b0bd53a7 828static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 829 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 830{
831 struct soc_mixer_control *mc =
832 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 833 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 834 unsigned int reg = mc->reg;
835 unsigned int shift = mc->shift;
836 unsigned int rshift = mc->rshift;
837 int max = mc->max;
838 int mask = (1 << fls(max)) - 1;
839
840 ucontrol->value.integer.value[0] =
841 (snd_soc_read(codec, reg) >> shift) & mask;
842 if (ucontrol->value.integer.value[0])
843 ucontrol->value.integer.value[0] =
844 max + 1 - ucontrol->value.integer.value[0];
845
846 if (shift != rshift) {
847 ucontrol->value.integer.value[1] =
848 (snd_soc_read(codec, reg) >> rshift) & mask;
849 if (ucontrol->value.integer.value[1])
850 ucontrol->value.integer.value[1] =
851 max + 1 - ucontrol->value.integer.value[1];
852 }
853
854 return 0;
855}
856
857static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 858 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 859{
860 struct soc_mixer_control *mc =
861 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 862 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 863 unsigned int reg = mc->reg;
864 unsigned int shift = mc->shift;
865 unsigned int rshift = mc->rshift;
866 int max = mc->max;
867 int mask = (1 << fls(max)) - 1;
868 unsigned short val, val2, val_mask;
869
870 val = (ucontrol->value.integer.value[0] & mask);
871
872 val_mask = mask << shift;
873 if (val)
874 val = max + 1 - val;
875 val = val << shift;
876 if (shift != rshift) {
877 val2 = (ucontrol->value.integer.value[1] & mask);
878 val_mask |= mask << rshift;
879 if (val2)
880 val2 = max + 1 - val2;
881 val |= val2 << rshift;
882 }
883 return snd_soc_update_bits(codec, reg, val_mask, val);
884}
885
886static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 887 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 888{
889 struct soc_mixer_control *mc =
890 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 891 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 892 unsigned int reg = mc->reg;
893 unsigned int reg2 = mc->rreg;
894 unsigned int shift = mc->shift;
895 int max = mc->max;
896 int mask = (1<<fls(max))-1;
897
898 ucontrol->value.integer.value[0] =
899 (snd_soc_read(codec, reg) >> shift) & mask;
900 ucontrol->value.integer.value[1] =
901 (snd_soc_read(codec, reg2) >> shift) & mask;
902
903 if (ucontrol->value.integer.value[0])
904 ucontrol->value.integer.value[0] =
905 max + 1 - ucontrol->value.integer.value[0];
906 if (ucontrol->value.integer.value[1])
907 ucontrol->value.integer.value[1] =
908 max + 1 - ucontrol->value.integer.value[1];
909
910 return 0;
911}
912
913static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 914 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 915{
916 struct soc_mixer_control *mc =
917 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 918 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 919 unsigned int reg = mc->reg;
920 unsigned int reg2 = mc->rreg;
921 unsigned int shift = mc->shift;
922 int max = mc->max;
923 int mask = (1 << fls(max)) - 1;
924 int err;
925 unsigned short val, val2, val_mask;
926
927 val_mask = mask << shift;
928 val = (ucontrol->value.integer.value[0] & mask);
929 val2 = (ucontrol->value.integer.value[1] & mask);
930
931 if (val)
932 val = max + 1 - val;
933 if (val2)
934 val2 = max + 1 - val2;
935
936 val = val << shift;
937 val2 = val2 << shift;
938
939 err = snd_soc_update_bits(codec, reg, val_mask, val);
940 if (err < 0)
941 return err;
942
943 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
944 return err;
945}
946
b74bd40f
LCM		 947/* Codec operation modes */
948static const char *twl4030_op_modes_texts[] = {
949 "Option 2 (voice/audio)", "Option 1 (audio)"
950};
951
9f04fba7
TI		 952static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
953 TWL4030_REG_CODEC_MODE, 0,
954 twl4030_op_modes_texts);
b74bd40f 955
423c238d 956static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 957 struct snd_ctl_elem_value *ucontrol)
958{
ea53bf77 959 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 960 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 961
962 if (twl4030->configured) {
3b8a0795
PU		 963 dev_err(codec->dev,
964 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 965 return -EBUSY;
966 }
967
6b207c0f 968 return snd_soc_put_enum_double(kcontrol, ucontrol);
b74bd40f
LCM		 969}
970
c10b82cf
PU		 971/*
972 * FGAIN volume control:
973 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
974 */
d889a72c 975static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 976
0d33ea0b
PU		 977/*
978 * CGAIN volume control:
979 * 0 dB to 12 dB in 6 dB steps
980 * value 2 and 3 means 12 dB
981 */
d889a72c
PU		 982static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
983
1a787e7a
JS		 984/*
985 * Voice Downlink GAIN volume control:
986 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
987 */
988static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
989
d889a72c
PU		 990/*
991 * Analog playback gain
992 * -24 dB to 12 dB in 2 dB steps
993 */
994static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 995
4290239c
PU		 996/*
997 * Gain controls tied to outputs
998 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
999 */
1000static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1001
18cc8d8d
JS		 1002/*
1003 * Gain control for earpiece amplifier
1004 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1005 */
1006static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1007
381a22b5
PU		 1008/*
1009 * Capture gain after the ADCs
1010 * from 0 dB to 31 dB in 1 dB steps
1011 */
1012static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1013
5920b453
GI		 1014/*
1015 * Gain control for input amplifiers
1016 * 0 dB to 30 dB in 6 dB steps
1017 */
1018static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1019
328d0a13
LCM		 1020/* AVADC clock priority */
1021static const char *twl4030_avadc_clk_priority_texts[] = {
1022 "Voice high priority", "HiFi high priority"
1023};
1024
9f04fba7
TI		 1025static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,
1026 TWL4030_REG_AVADC_CTL, 2,
1027 twl4030_avadc_clk_priority_texts);
328d0a13 1028
89492be8
PU		 1029static const char *twl4030_rampdelay_texts[] = {
1030 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1031 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1032 "3495/2581/1748 ms"
1033};
1034
9f04fba7
TI		 1035static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,
1036 TWL4030_REG_HS_POPN_SET, 2,
1037 twl4030_rampdelay_texts);
89492be8 1038
376f7839
PU		 1039/* Vibra H-bridge direction mode */
1040static const char *twl4030_vibradirmode_texts[] = {
1041 "Vibra H-bridge direction", "Audio data MSB",
1042};
1043
9f04fba7
TI		 1044static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,
1045 TWL4030_REG_VIBRA_CTL, 5,
1046 twl4030_vibradirmode_texts);
376f7839
PU		 1047
1048/* Vibra H-bridge direction */
1049static const char *twl4030_vibradir_texts[] = {
1050 "Positive polarity", "Negative polarity",
1051};
1052
9f04fba7
TI		 1053static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,
1054 TWL4030_REG_VIBRA_CTL, 1,
1055 twl4030_vibradir_texts);
376f7839 1056
36aeff61
PU		 1057/* Digimic Left and right swapping */
1058static const char *twl4030_digimicswap_texts[] = {
1059 "Not swapped", "Swapped",
1060};
1061
9f04fba7
TI		 1062static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,
1063 TWL4030_REG_MISC_SET_1, 0,
1064 twl4030_digimicswap_texts);
36aeff61 1065
cc17557e 1066static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1067 /* Codec operation mode control */
1068 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1069 snd_soc_get_enum_double,
1070 snd_soc_put_twl4030_opmode_enum_double),
1071
d889a72c
PU		 1072 /* Common playback gain controls */
1073 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1074 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1075 0, 0x3f, 0, digital_fine_tlv),
1076 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1077 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1078 0, 0x3f, 0, digital_fine_tlv),
1079
1080 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1081 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1082 6, 0x2, 0, digital_coarse_tlv),
1083 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1084 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1085 6, 0x2, 0, digital_coarse_tlv),
1086
1087 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1088 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1089 3, 0x12, 1, analog_tlv),
1090 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1091 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1092 3, 0x12, 1, analog_tlv),
44c55870
PU		 1093 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1094 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1095 1, 1, 0),
1096 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1097 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1098 1, 1, 0),
381a22b5 1099
1a787e7a
JS		 1100 /* Common voice downlink gain controls */
1101 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1102 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1103
1104 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1105 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1106
1107 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1108 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1109
4290239c 1110 /* Separate output gain controls */
0f9887d1 1111 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1112 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1113 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1114 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1115
0f9887d1
PU		 1116 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1117 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1118 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1119
0f9887d1 1120 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1121 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1122 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1123 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1124
0f9887d1
PU		 1125 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1126 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1127 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1128
381a22b5 1129 /* Common capture gain controls */
276c6222 1130 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1131 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1132 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1133 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1134 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1135 0, 0x1f, 0, digital_capture_tlv),
5920b453 1136
276c6222 1137 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1138 0, 3, 5, 0, input_gain_tlv),
89492be8 1139
328d0a13
LCM		 1140 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1141
89492be8 1142 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1143
1144 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1145 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1146
1147 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1148};
1149
cc17557e 1150static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1151 /* Left channel inputs */
1152 SND_SOC_DAPM_INPUT("MAINMIC"),
1153 SND_SOC_DAPM_INPUT("HSMIC"),
1154 SND_SOC_DAPM_INPUT("AUXL"),
1155 SND_SOC_DAPM_INPUT("CARKITMIC"),
1156 /* Right channel inputs */
1157 SND_SOC_DAPM_INPUT("SUBMIC"),
1158 SND_SOC_DAPM_INPUT("AUXR"),
1159 /* Digital microphones (Stereo) */
1160 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1161 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1162
1163 /* Outputs */
5e98a464 1164 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1165 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1166 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1167 SND_SOC_DAPM_OUTPUT("HSOL"),
1168 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1169 SND_SOC_DAPM_OUTPUT("CARKITL"),
1170 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1171 SND_SOC_DAPM_OUTPUT("HFL"),
1172 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1173 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1174
7b4c734e
PU		 1175 /* AIF and APLL clocks for running DAIs (including loopback) */
1176 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1177 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1178 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1179
53b5047d 1180 /* DACs */
7f51e7d3
PU		 1181 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1182 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1183 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1184 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1185 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1186
927a7747
PU		 1187 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1188 TWL4030_REG_VOICE_IF, 6, 0),
1189
7393958f 1190 /* Analog bypasses */
78e08e2f
PU		 1191 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1192 &twl4030_dapm_abypassr1_control),
1193 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1194 &twl4030_dapm_abypassl1_control),
1195 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1196 &twl4030_dapm_abypassr2_control),
1197 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1198 &twl4030_dapm_abypassl2_control),
1199 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1200 &twl4030_dapm_abypassv_control),
1201
1202 /* Master analog loopback switch */
1203 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1204 NULL, 0),
7393958f 1205
6bab83fd 1206 /* Digital bypasses */
78e08e2f
PU		 1207 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1208 &twl4030_dapm_dbypassl_control),
1209 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1210 &twl4030_dapm_dbypassr_control),
1211 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1212 &twl4030_dapm_dbypassv_control),
6bab83fd 1213
4005d39a
PU		 1214 /* Digital mixers, power control for the physical DACs */
1215 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1216 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1217 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1218 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1219 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1220 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1221 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1222 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1223 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1224 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1225
1226 /* Analog mixers, power control for the physical PGAs */
1227 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1228 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1229 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1230 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1231 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1232 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1233 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1234 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1235 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1236 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1237
7729cf74
PU		 1238 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1239 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1240
7b4c734e
PU		 1241 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1242 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1243
1a787e7a 1244 /* Output MIXER controls */
5e98a464 1245 /* Earpiece */
1a787e7a
JS		 1246 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1247 &twl4030_dapm_earpiece_controls[0],
1248 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1249 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1250 0, 0, NULL, 0, earpiecepga_event,
1251 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1252 /* PreDrivL/R */
1a787e7a
JS		 1253 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1254 &twl4030_dapm_predrivel_controls[0],
1255 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1256 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1257 0, 0, NULL, 0, predrivelpga_event,
1258 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1259 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1260 &twl4030_dapm_predriver_controls[0],
1261 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1262 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1263 0, 0, NULL, 0, predriverpga_event,
1264 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1265 /* HeadsetL/R */
6943c92e 1266 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1267 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1268 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1269 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1270 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1271 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1272 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1273 &twl4030_dapm_hsor_controls[0],
1274 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1275 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1276 0, 0, NULL, 0, headsetrpga_event,
1277 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1278 /* CarkitL/R */
1a787e7a
JS		 1279 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1280 &twl4030_dapm_carkitl_controls[0],
1281 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1282 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1283 0, 0, NULL, 0, carkitlpga_event,
1284 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1285 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1286 &twl4030_dapm_carkitr_controls[0],
1287 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1288 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1289 0, 0, NULL, 0, carkitrpga_event,
1290 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1291
1292 /* Output MUX controls */
df339804 1293 /* HandsfreeL/R */
5a2e9a48
PU		 1294 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1295 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1296 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1297 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1298 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1299 0, 0, NULL, 0, handsfreelpga_event,
1300 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1301 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1302 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1303 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1304 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1305 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1306 0, 0, NULL, 0, handsfreerpga_event,
1307 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1308 /* Vibra */
86139a13
JV		 1309 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1310 &twl4030_dapm_vibra_control, vibramux_event,
1311 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1312 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1313 &twl4030_dapm_vibrapath_control),
5e98a464 1314
276c6222
PU		 1315 /* Introducing four virtual ADC, since TWL4030 have four channel for
1316 capture */
7f51e7d3
PU		 1317 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1318 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1319 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1320 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1321
927a7747
PU		 1322 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1323 TWL4030_REG_VOICE_IF, 5, 0),
1324
276c6222
PU		 1325 /* Analog/Digital mic path selection.
1326 TX1 Left/Right: either analog Left/Right or Digimic0
1327 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1328 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1329 &twl4030_dapm_micpathtx1_control),
1330 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1331 &twl4030_dapm_micpathtx2_control),
276c6222 1332
97b8096d 1333 /* Analog input mixers for the capture amplifiers */
9028935d 1334 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1335 TWL4030_REG_ANAMICL, 4, 0,
1336 &twl4030_dapm_analoglmic_controls[0],
1337 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1338 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1339 TWL4030_REG_ANAMICR, 4, 0,
1340 &twl4030_dapm_analogrmic_controls[0],
1341 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1342
fb2a2f84
PU		 1343 SND_SOC_DAPM_PGA("ADC Physical Left",
1344 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1345 SND_SOC_DAPM_PGA("ADC Physical Right",
1346 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1347
01ea6ba2
PU		 1348 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1349 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1350 digimic_event, SND_SOC_DAPM_POST_PMU),
1351 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1352 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1353 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1354
bda7d2a8
PU		 1355 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1356 NULL, 0),
1357 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1358 NULL, 0),
1359
e04d6e55
PU		 1360 /* Microphone bias */
1361 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1362 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1363 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1364 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1365 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1366 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1367
927a7747 1368 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1369};
1370
1371static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1372 /* Stream -> DAC mapping */
1373 {"DAC Right1", NULL, "HiFi Playback"},
1374 {"DAC Left1", NULL, "HiFi Playback"},
1375 {"DAC Right2", NULL, "HiFi Playback"},
1376 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1377 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1378
1379 /* ADC -> Stream mapping */
1380 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1381 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1382 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1383 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1384 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1385 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1386 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1387
4005d39a
PU		 1388 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1389 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1390 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1391 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1392 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1393
7729cf74 1394 /* Supply for the digital part (APLL) */
7729cf74
PU		 1395 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1396
27eeb1fe
PU		 1397 {"DAC Left1", NULL, "AIF Enable"},
1398 {"DAC Right1", NULL, "AIF Enable"},
1399 {"DAC Left2", NULL, "AIF Enable"},
1400 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1401 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1402
c42a59ea
PU		 1403 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1404 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1405
4005d39a
PU		 1406 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1407 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1408 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1409 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1410 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1411
5e98a464
PU		 1412 /* Internal playback routings */
1413 /* Earpiece */
4005d39a
PU		 1414 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1415 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1416 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1417 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1418 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1419 /* PreDrivL */
4005d39a
PU		 1420 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1421 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1422 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1423 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1424 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1425 /* PreDrivR */
4005d39a
PU		 1426 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1427 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1428 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1429 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1430 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1431 /* HeadsetL */
4005d39a
PU		 1432 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1433 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1434 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1435 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1436 /* HeadsetR */
4005d39a
PU		 1437 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1438 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1439 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1440 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1441 /* CarkitL */
4005d39a
PU		 1442 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1443 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1444 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1445 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1446 /* CarkitR */
4005d39a
PU		 1447 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1448 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1449 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1450 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1451 /* HandsfreeL */
4005d39a
PU		 1452 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1453 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1454 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1455 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1456 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1457 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1458 /* HandsfreeR */
4005d39a
PU		 1459 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1460 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1461 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1462 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1463 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1464 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1465 /* Vibra */
1466 {"Vibra Mux", "AudioL1", "DAC Left1"},
1467 {"Vibra Mux", "AudioR1", "DAC Right1"},
1468 {"Vibra Mux", "AudioL2", "DAC Left2"},
1469 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1470
cc17557e 1471 /* outputs */
7b4c734e 1472 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1473 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1474 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1475 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1476 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1477 /* Must be always connected (for APLL) */
1478 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1479 /* Physical outputs */
9008adf9
PU		 1480 {"EARPIECE", NULL, "Earpiece PGA"},
1481 {"PREDRIVEL", NULL, "PredriveL PGA"},
1482 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1483 {"HSOL", NULL, "HeadsetL PGA"},
1484 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1485 {"CARKITL", NULL, "CarkitL PGA"},
1486 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1487 {"HFL", NULL, "HandsfreeL PGA"},
1488 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1489 {"Vibra Route", "Audio", "Vibra Mux"},
1490 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1491
276c6222 1492 /* Capture path */
7b4c734e
PU		 1493 /* Must be always connected (for AIF and APLL) */
1494 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1495 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1496 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1497 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1498 /* Physical inputs */
9028935d
PU		 1499 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1500 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1501 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1502 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1503
9028935d
PU		 1504 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1505 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1506
9028935d
PU		 1507 {"ADC Physical Left", NULL, "Analog Left"},
1508 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1509
1510 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1511 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1512
bda7d2a8
PU		 1513 {"DIGIMIC0", NULL, "micbias1 select"},
1514 {"DIGIMIC1", NULL, "micbias2 select"},
1515
276c6222 1516 /* TX1 Left capture path */
fb2a2f84 1517 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1518 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1519 /* TX1 Right capture path */
fb2a2f84 1520 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1521 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1522 /* TX2 Left capture path */
fb2a2f84 1523 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1524 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1525 /* TX2 Right capture path */
fb2a2f84 1526 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1527 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1528
1529 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1530 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1531 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1532 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1533
c42a59ea
PU		 1534 {"ADC Virtual Left1", NULL, "AIF Enable"},
1535 {"ADC Virtual Right1", NULL, "AIF Enable"},
1536 {"ADC Virtual Left2", NULL, "AIF Enable"},
1537 {"ADC Virtual Right2", NULL, "AIF Enable"},
1538
7393958f 1539 /* Analog bypass routes */
9028935d
PU		 1540 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1541 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1542 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1543 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1544 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1545
78e08e2f
PU		 1546 /* Supply for the Analog loopbacks */
1547 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1548 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1549 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1550 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1551 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1552
7393958f
PU		 1553 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1554 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1555 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1556 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1557 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1558
6bab83fd
PU		 1559 /* Digital bypass routes */
1560 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1561 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1562 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1563
4005d39a
PU		 1564 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1565 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1566 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1567
cc17557e
SS		 1568};
1569
cc17557e
SS		 1570static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1571 enum snd_soc_bias_level level)
1572{
1573 switch (level) {
1574 case SND_SOC_BIAS_ON:
cc17557e
SS		 1575 break;
1576 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1577 break;
1578 case SND_SOC_BIAS_STANDBY:
ce6120cc 1579 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1580 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1581 break;
1582 case SND_SOC_BIAS_OFF:
cbd2db12 1583 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1584 break;
1585 }
ce6120cc 1586 codec->dapm.bias_level = level;
cc17557e
SS		 1587
1588 return 0;
1589}
1590
6b87a91f
PU		 1591static void twl4030_constraints(struct twl4030_priv *twl4030,
1592 struct snd_pcm_substream *mst_substream)
1593{
1594 struct snd_pcm_substream *slv_substream;
1595
1596 /* Pick the stream, which need to be constrained */
1597 if (mst_substream == twl4030->master_substream)
1598 slv_substream = twl4030->slave_substream;
1599 else if (mst_substream == twl4030->slave_substream)
1600 slv_substream = twl4030->master_substream;
1601 else /* This should not happen.. */
1602 return;
1603
1604 /* Set the constraints according to the already configured stream */
1605 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1606 SNDRV_PCM_HW_PARAM_RATE,
1607 twl4030->rate,
1608 twl4030->rate);
1609
1610 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1611 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1612 twl4030->sample_bits,
1613 twl4030->sample_bits);
1614
1615 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1616 SNDRV_PCM_HW_PARAM_CHANNELS,
1617 twl4030->channels,
1618 twl4030->channels);
1619}
1620
8a1f936a
PU		 1621/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1622 * capture has to be enabled/disabled. */
1623static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1624 int enable)
8a1f936a
PU		 1625{
1626 u8 reg, mask;
1627
efc8acff 1628 reg = twl4030_read(codec, TWL4030_REG_OPTION);
8a1f936a
PU		 1629
1630 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1631 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1632 else
1633 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1634
1635 if (enable)
1636 reg |= mask;
1637 else
1638 reg &= ~mask;
1639
1640 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1641}
1642
d6648da1
PU		 1643static int twl4030_startup(struct snd_pcm_substream *substream,
1644 struct snd_soc_dai *dai)
7220b9f4 1645{
e6968a17 1646 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1647 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1648
7220b9f4 1649 if (twl4030->master_substream) {
7220b9f4 1650 twl4030->slave_substream = substream;
6b87a91f
PU		 1651 /* The DAI has one configuration for playback and capture, so
1652 * if the DAI has been already configured then constrain this
1653 * substream to match it. */
1654 if (twl4030->configured)
1655 twl4030_constraints(twl4030, twl4030->master_substream);
1656 } else {
efc8acff 1657 if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) &
8a1f936a
PU		 1658 TWL4030_OPTION_1)) {
1659 /* In option2 4 channel is not supported, set the
1660 * constraint for the first stream for channels, the
1661 * second stream will 'inherit' this cosntraint */
1662 snd_pcm_hw_constraint_minmax(substream->runtime,
7ded5fe0
PU		 1663 SNDRV_PCM_HW_PARAM_CHANNELS,
1664 2, 2);
8a1f936a 1665 }
7220b9f4 1666 twl4030->master_substream = substream;
6b87a91f 1667 }
7220b9f4
PU		 1668
1669 return 0;
1670}
1671
d6648da1
PU		 1672static void twl4030_shutdown(struct snd_pcm_substream *substream,
1673 struct snd_soc_dai *dai)
7220b9f4 1674{
e6968a17 1675 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1676 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1677
1678 if (twl4030->master_substream == substream)
1679 twl4030->master_substream = twl4030->slave_substream;
1680
1681 twl4030->slave_substream = NULL;
6b87a91f
PU		 1682
1683 /* If all streams are closed, or the remaining stream has not yet
1684 * been configured than set the DAI as not configured. */
1685 if (!twl4030->master_substream)
1686 twl4030->configured = 0;
1687 else if (!twl4030->master_substream->runtime->channels)
1688 twl4030->configured = 0;
8a1f936a
PU		 1689
1690 /* If the closing substream had 4 channel, do the necessary cleanup */
1691 if (substream->runtime->channels == 4)
1692 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1693}
1694
cc17557e 1695static int twl4030_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1696 struct snd_pcm_hw_params *params,
1697 struct snd_soc_dai *dai)
cc17557e 1698{
e6968a17 1699 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1700 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1701 u8 mode, old_mode, format, old_format;
1702
8a1f936a
PU		 1703 /* If the substream has 4 channel, do the necessary setup */
1704 if (params_channels(params) == 4) {
efc8acff
PU		 1705 format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
1706 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE);
eaf1ac8b
PU		 1707
1708 /* Safety check: are we in the correct operating mode and
1709 * the interface is in TDM mode? */
1710 if ((mode & TWL4030_OPTION_1) &&
1711 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1712 twl4030_tdm_enable(codec, substream->stream, 1);
1713 else
1714 return -EINVAL;
1715 }
1716
6b87a91f
PU		 1717 if (twl4030->configured)
1718 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1719 return 0;
1720
cc17557e 1721 /* bit rate */
efc8acff
PU		 1722 old_mode = twl4030_read(codec,
1723 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
cc17557e
SS		 1724 mode = old_mode & ~TWL4030_APLL_RATE;
1725
1726 switch (params_rate(params)) {
1727 case 8000:
1728 mode |= TWL4030_APLL_RATE_8000;
1729 break;
1730 case 11025:
1731 mode |= TWL4030_APLL_RATE_11025;
1732 break;
1733 case 12000:
1734 mode |= TWL4030_APLL_RATE_12000;
1735 break;
1736 case 16000:
1737 mode |= TWL4030_APLL_RATE_16000;
1738 break;
1739 case 22050:
1740 mode |= TWL4030_APLL_RATE_22050;
1741 break;
1742 case 24000:
1743 mode |= TWL4030_APLL_RATE_24000;
1744 break;
1745 case 32000:
1746 mode |= TWL4030_APLL_RATE_32000;
1747 break;
1748 case 44100:
1749 mode |= TWL4030_APLL_RATE_44100;
1750 break;
1751 case 48000:
1752 mode |= TWL4030_APLL_RATE_48000;
1753 break;
103f211d
PU		 1754 case 96000:
1755 mode |= TWL4030_APLL_RATE_96000;
1756 break;
cc17557e 1757 default:
3b8a0795 1758 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1759 params_rate(params));
1760 return -EINVAL;
1761 }
1762
cc17557e 1763 /* sample size */
efc8acff 1764 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1765 format = old_format;
1766 format &= ~TWL4030_DATA_WIDTH;
1767 switch (params_format(params)) {
1768 case SNDRV_PCM_FORMAT_S16_LE:
1769 format |= TWL4030_DATA_WIDTH_16S_16W;
1770 break;
dcdeda4a 1771 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1772 format |= TWL4030_DATA_WIDTH_32S_24W;
1773 break;
1774 default:
3b8a0795 1775 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1776 params_format(params));
1777 return -EINVAL;
1778 }
1779
2046f175
PU		 1780 if (format != old_format || mode != old_mode) {
1781 if (twl4030->codec_powered) {
1782 /*
1783 * If the codec is powered, than we need to toggle the
1784 * codec power.
1785 */
1786 twl4030_codec_enable(codec, 0);
1787 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1788 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1789 twl4030_codec_enable(codec, 1);
1790 } else {
1791 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1792 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1793 }
cc17557e 1794 }
6b87a91f
PU		 1795
1796 /* Store the important parameters for the DAI configuration and set
1797 * the DAI as configured */
1798 twl4030->configured = 1;
1799 twl4030->rate = params_rate(params);
1800 twl4030->sample_bits = hw_param_interval(params,
1801 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1802 twl4030->channels = params_channels(params);
1803
1804 /* If both playback and capture streams are open, and one of them
1805 * is setting the hw parameters right now (since we are here), set
1806 * constraints to the other stream to match the current one. */
1807 if (twl4030->slave_substream)
1808 twl4030_constraints(twl4030, substream);
1809
cc17557e
SS		 1810 return 0;
1811}
1812
7ded5fe0
PU		 1813static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1814 unsigned int freq, int dir)
cc17557e
SS		 1815{
1816 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1817 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1818
1819 switch (freq) {
1820 case 19200000:
cc17557e 1821 case 26000000:
cc17557e 1822 case 38400000:
cc17557e
SS		 1823 break;
1824 default:
3b8a0795 1825 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1826 return -EINVAL;
1827 }
1828
68d01955
PU		 1829 if ((freq / 1000) != twl4030->sysclk) {
1830 dev_err(codec->dev,
3b8a0795 1831 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1832 freq, twl4030->sysclk * 1000);
1833 return -EINVAL;
1834 }
cc17557e
SS		 1835
1836 return 0;
1837}
1838
7ded5fe0 1839static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
cc17557e
SS		 1840{
1841 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1842 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1843 u8 old_format, format;
1844
1845 /* get format */
efc8acff 1846 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1847 format = old_format;
1848
1849 /* set master/slave audio interface */
1850 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1851 case SND_SOC_DAIFMT_CBM_CFM:
1852 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1853 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1854 break;
1855 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1856 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1857 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1858 break;
1859 default:
1860 return -EINVAL;
1861 }
1862
1863 /* interface format */
1864 format &= ~TWL4030_AIF_FORMAT;
1865 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1866 case SND_SOC_DAIFMT_I2S:
1867 format |= TWL4030_AIF_FORMAT_CODEC;
1868 break;
8a1f936a
PU		 1869 case SND_SOC_DAIFMT_DSP_A:
1870 format |= TWL4030_AIF_FORMAT_TDM;
1871 break;
cc17557e
SS		 1872 default:
1873 return -EINVAL;
1874 }
1875
1876 if (format != old_format) {
2046f175
PU		 1877 if (twl4030->codec_powered) {
1878 /*
1879 * If the codec is powered, than we need to toggle the
1880 * codec power.
1881 */
1882 twl4030_codec_enable(codec, 0);
1883 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1884 twl4030_codec_enable(codec, 1);
1885 } else {
1886 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1887 }
cc17557e
SS		 1888 }
1889
1890 return 0;
1891}
1892
68140443
LCM		 1893static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1894{
1895 struct snd_soc_codec *codec = dai->codec;
efc8acff 1896 u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
68140443
LCM		 1897
1898 if (tristate)
1899 reg |= TWL4030_AIF_TRI_EN;
1900 else
1901 reg &= ~TWL4030_AIF_TRI_EN;
1902
1903 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1904}
1905
b7a755a8
MLC		 1906/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1907 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1908static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1909 int enable)
b7a755a8
MLC		 1910{
1911 u8 reg, mask;
1912
efc8acff 1913 reg = twl4030_read(codec, TWL4030_REG_OPTION);
b7a755a8
MLC		 1914
1915 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1916 mask = TWL4030_ARXL1_VRX_EN;
1917 else
1918 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1919
1920 if (enable)
1921 reg |= mask;
1922 else
1923 reg &= ~mask;
1924
1925 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1926}
1927
7154b3e8 1928static int twl4030_voice_startup(struct snd_pcm_substream *substream,
7ded5fe0 1929 struct snd_soc_dai *dai)
7154b3e8 1930{
e6968a17 1931 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1932 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1933 u8 mode;
1934
1935 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 1936 * not available.
7154b3e8 1937 */
68d01955 1938 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 1939 dev_err(codec->dev,
1940 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1941 __func__, twl4030->sysclk);
7154b3e8
JS		 1942 return -EINVAL;
1943 }
1944
1945 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 1946 * available.
7154b3e8 1947 */
efc8acff 1948 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE)
7154b3e8
JS		 1949 & TWL4030_OPT_MODE;
1950
1951 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 1952 dev_err(codec->dev, "%s: the codec mode is not option2\n",
1953 __func__);
7154b3e8
JS		 1954 return -EINVAL;
1955 }
1956
1957 return 0;
1958}
1959
b7a755a8 1960static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
7ded5fe0 1961 struct snd_soc_dai *dai)
b7a755a8 1962{
e6968a17 1963 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 1964
1965 /* Enable voice digital filters */
1966 twl4030_voice_enable(codec, substream->stream, 0);
1967}
1968
7154b3e8 1969static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1970 struct snd_pcm_hw_params *params,
1971 struct snd_soc_dai *dai)
7154b3e8 1972{
e6968a17 1973 struct snd_soc_codec *codec = dai->codec;
2046f175 1974 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1975 u8 old_mode, mode;
1976
b7a755a8
MLC		 1977 /* Enable voice digital filters */
1978 twl4030_voice_enable(codec, substream->stream, 1);
1979
7154b3e8 1980 /* bit rate */
7ded5fe0
PU		 1981 old_mode = twl4030_read(codec,
1982 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
7154b3e8
JS		 1983 mode = old_mode;
1984
1985 switch (params_rate(params)) {
1986 case 8000:
1987 mode &= ~(TWL4030_SEL_16K);
1988 break;
1989 case 16000:
1990 mode |= TWL4030_SEL_16K;
1991 break;
1992 default:
3b8a0795 1993 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 1994 params_rate(params));
1995 return -EINVAL;
1996 }
1997
1998 if (mode != old_mode) {
2046f175
PU		 1999 if (twl4030->codec_powered) {
2000 /*
2001 * If the codec is powered, than we need to toggle the
2002 * codec power.
2003 */
2004 twl4030_codec_enable(codec, 0);
2005 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2006 twl4030_codec_enable(codec, 1);
2007 } else {
2008 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2009 }
7154b3e8
JS		 2010 }
2011
2012 return 0;
2013}
2014
2015static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
7ded5fe0 2016 int clk_id, unsigned int freq, int dir)
7154b3e8
JS		 2017{
2018 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2019 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2020
68d01955 2021 if (freq != 26000000) {
3b8a0795
PU		 2022 dev_err(codec->dev,
2023 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2024 __func__, freq / 1000);
68d01955
PU		 2025 return -EINVAL;
2026 }
2027 if ((freq / 1000) != twl4030->sysclk) {
2028 dev_err(codec->dev,
3b8a0795 2029 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2030 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2031 return -EINVAL;
2032 }
7154b3e8
JS		 2033 return 0;
2034}
2035
2036static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
7ded5fe0 2037 unsigned int fmt)
7154b3e8
JS		 2038{
2039 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2040 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2041 u8 old_format, format;
2042
2043 /* get format */
efc8acff 2044 old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF);
7154b3e8
JS		 2045 format = old_format;
2046
2047 /* set master/slave audio interface */
2048 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2049 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2050 format &= ~(TWL4030_VIF_SLAVE_EN);
2051 break;
2052 case SND_SOC_DAIFMT_CBS_CFS:
2053 format |= TWL4030_VIF_SLAVE_EN;
2054 break;
2055 default:
2056 return -EINVAL;
2057 }
2058
2059 /* clock inversion */
2060 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2061 case SND_SOC_DAIFMT_IB_NF:
2062 format &= ~(TWL4030_VIF_FORMAT);
2063 break;
2064 case SND_SOC_DAIFMT_NB_IF:
2065 format |= TWL4030_VIF_FORMAT;
2066 break;
2067 default:
2068 return -EINVAL;
2069 }
2070
2071 if (format != old_format) {
2046f175
PU		 2072 if (twl4030->codec_powered) {
2073 /*
2074 * If the codec is powered, than we need to toggle the
2075 * codec power.
2076 */
2077 twl4030_codec_enable(codec, 0);
2078 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2079 twl4030_codec_enable(codec, 1);
2080 } else {
2081 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2082 }
7154b3e8
JS		 2083 }
2084
2085 return 0;
2086}
2087
68140443
LCM		 2088static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2089{
2090 struct snd_soc_codec *codec = dai->codec;
efc8acff 2091 u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF);
68140443
LCM		 2092
2093 if (tristate)
2094 reg |= TWL4030_VIF_TRI_EN;
2095 else
2096 reg &= ~TWL4030_VIF_TRI_EN;
2097
2098 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2099}
2100
bbba9444 2101#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2102#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2103
85e7652d 2104static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2105 .startup = twl4030_startup,
2106 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2107 .hw_params = twl4030_hw_params,
2108 .set_sysclk = twl4030_set_dai_sysclk,
2109 .set_fmt = twl4030_set_dai_fmt,
68140443 2110 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2111};
2112
85e7652d 2113static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2114 .startup = twl4030_voice_startup,
b7a755a8 2115 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2116 .hw_params = twl4030_voice_hw_params,
2117 .set_sysclk = twl4030_voice_set_dai_sysclk,
2118 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2119 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2120};
2121
f0fba2ad 2122static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2123{
f0fba2ad 2124 .name = "twl4030-hifi",
cc17557e 2125 .playback = {
b4852b79 2126 .stream_name = "HiFi Playback",
cc17557e 2127 .channels_min = 2,
8a1f936a 2128 .channels_max = 4,
31ad0f31 2129 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2130 .formats = TWL4030_FORMATS,
2131 .sig_bits = 24,},
cc17557e 2132 .capture = {
7f51e7d3 2133 .stream_name = "HiFi Capture",
cc17557e 2134 .channels_min = 2,
8a1f936a 2135 .channels_max = 4,
cc17557e 2136 .rates = TWL4030_RATES,
8819f65c
PU		 2137 .formats = TWL4030_FORMATS,
2138 .sig_bits = 24,},
f0fba2ad 2139 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2140},
2141{
f0fba2ad 2142 .name = "twl4030-voice",
7154b3e8 2143 .playback = {
b4852b79 2144 .stream_name = "Voice Playback",
7154b3e8
JS		 2145 .channels_min = 1,
2146 .channels_max = 1,
2147 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2148 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2149 .capture = {
7f51e7d3 2150 .stream_name = "Voice Capture",
7154b3e8
JS		 2151 .channels_min = 1,
2152 .channels_max = 2,
2153 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2154 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2155 .ops = &twl4030_dai_voice_ops,
2156},
cc17557e 2157};
cc17557e 2158
f0fba2ad 2159static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2160{
f0fba2ad 2161 struct twl4030_priv *twl4030;
9da28c7b 2162
f2b1ce49
PU		 2163 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2164 GFP_KERNEL);
f0fba2ad 2165 if (twl4030 == NULL) {
3b8a0795 2166 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2167 return -ENOMEM;
cc17557e 2168 }
f0fba2ad
LG		 2169 snd_soc_codec_set_drvdata(codec, twl4030);
2170 /* Set the defaults, and power up the codec */
57fe7251 2171 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2172
2173 twl4030_init_chip(codec);
cc17557e 2174
7a1fecf5 2175 return 0;
cc17557e
SS		 2176}
2177
f0fba2ad 2178static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2179{
5b3b0fa8 2180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2181 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2182
7a1fecf5 2183 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2184
2185 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2186 gpio_free(pdata->hs_extmute_gpio);
2187
7a1fecf5
PU		 2188 return 0;
2189}
2190
f0fba2ad
LG		 2191static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2192 .probe = twl4030_soc_probe,
2193 .remove = twl4030_soc_remove,
efc8acff 2194 .read = twl4030_read,
f0fba2ad
LG		 2195 .write = twl4030_write,
2196 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2197 .idle_bias_off = true,
f7c93f01
PU		 2198
2199 .controls = twl4030_snd_controls,
2200 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2201 .dapm_widgets = twl4030_dapm_widgets,
2202 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2203 .dapm_routes = intercon,
2204 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2205};
2206
05c4c6f7 2207static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2208{
f0fba2ad 2209 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
7ded5fe0 2210 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2211}
2212
05c4c6f7 2213static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2214{
f0fba2ad 2215 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2216 return 0;
2217}
2218
f0fba2ad 2219MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2220
2221static struct platform_driver twl4030_codec_driver = {
2222 .probe = twl4030_codec_probe,
05c4c6f7 2223 .remove = twl4030_codec_remove,
7a1fecf5 2224 .driver = {
f0fba2ad 2225 .name = "twl4030-codec",
7a1fecf5
PU		 2226 .owner = THIS_MODULE,
2227 },
cc17557e 2228};
cc17557e 2229
5bbcc3c0 2230module_platform_driver(twl4030_codec_driver);
64089b84 2231
cc17557e
SS		 2232MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2233MODULE_AUTHOR("Steve Sakoman");
2234MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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