Commit | Line | Data |
---|---|---|
cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
b07682b6 | 29 | #include <linux/i2c/twl.h> |
cc17557e SS |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
db04e2c5 | 45 | 0x91, /* REG_CODEC_MODE (0x1) */ |
cc17557e SS |
46 | 0xc3, /* REG_OPTION (0x2) */ |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
5920b453 GI |
49 | 0x20, /* REG_ANAMICL (0x5) */ |
50 | 0x00, /* REG_ANAMICR (0x6) */ | |
51 | 0x00, /* REG_AVADC_CTL (0x7) */ | |
cc17557e SS |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
c42a59ea | 58 | 0x00, /* REG_AUDIO_IF (0xE) */ |
cc17557e SS |
59 | 0x00, /* REG_VOICE_IF (0xF) */ |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
c8124593 | 67 | 0x00, /* REG_AVDAC_CTL (0x17) */ |
cc17557e SS |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
c8124593 PU |
71 | 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */ |
72 | 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
cc17557e SS |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
e47c796d PU |
78 | 0x00, /* REG_HS_SEL (0x22) */ |
79 | 0x00, /* REG_HS_GAIN_SET (0x23) */ | |
cc17557e SS |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
c8124593 | 102 | 0x06, /* REG_APLL_CTL (0x3A) */ |
cc17557e SS |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
f3b5d300 | 118 | 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */ |
cc17557e SS |
119 | }; |
120 | ||
7393958f PU |
121 | /* codec private data */ |
122 | struct twl4030_priv { | |
7a1fecf5 PU |
123 | struct snd_soc_codec codec; |
124 | ||
7393958f | 125 | unsigned int codec_powered; |
7b4c734e PU |
126 | |
127 | /* reference counts of AIF/APLL users */ | |
2845fa13 | 128 | unsigned int apll_enabled; |
7220b9f4 PU |
129 | |
130 | struct snd_pcm_substream *master_substream; | |
131 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
132 | |
133 | unsigned int configured; | |
134 | unsigned int rate; | |
135 | unsigned int sample_bits; | |
136 | unsigned int channels; | |
6943c92e PU |
137 | |
138 | unsigned int sysclk; | |
139 | ||
c96907f2 PU |
140 | /* Output (with associated amp) states */ |
141 | u8 hsl_enabled, hsr_enabled; | |
142 | u8 earpiece_enabled; | |
143 | u8 predrivel_enabled, predriver_enabled; | |
144 | u8 carkitl_enabled, carkitr_enabled; | |
7393958f PU |
145 | }; |
146 | ||
cc17557e SS |
147 | /* |
148 | * read twl4030 register cache | |
149 | */ | |
150 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
151 | unsigned int reg) | |
152 | { | |
d08664fd | 153 | u8 *cache = codec->reg_cache; |
cc17557e | 154 | |
91432e97 IM |
155 | if (reg >= TWL4030_CACHEREGNUM) |
156 | return -EIO; | |
157 | ||
cc17557e SS |
158 | return cache[reg]; |
159 | } | |
160 | ||
161 | /* | |
162 | * write twl4030 register cache | |
163 | */ | |
164 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
165 | u8 reg, u8 value) | |
166 | { | |
167 | u8 *cache = codec->reg_cache; | |
168 | ||
169 | if (reg >= TWL4030_CACHEREGNUM) | |
170 | return; | |
171 | cache[reg] = value; | |
172 | } | |
173 | ||
174 | /* | |
175 | * write to the twl4030 register space | |
176 | */ | |
177 | static int twl4030_write(struct snd_soc_codec *codec, | |
178 | unsigned int reg, unsigned int value) | |
179 | { | |
b2c812e2 | 180 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
c96907f2 PU |
181 | int write_to_reg = 0; |
182 | ||
cc17557e | 183 | twl4030_write_reg_cache(codec, reg, value); |
c96907f2 PU |
184 | if (likely(reg < TWL4030_REG_SW_SHADOW)) { |
185 | /* Decide if the given register can be written */ | |
186 | switch (reg) { | |
187 | case TWL4030_REG_EAR_CTL: | |
188 | if (twl4030->earpiece_enabled) | |
189 | write_to_reg = 1; | |
190 | break; | |
191 | case TWL4030_REG_PREDL_CTL: | |
192 | if (twl4030->predrivel_enabled) | |
193 | write_to_reg = 1; | |
194 | break; | |
195 | case TWL4030_REG_PREDR_CTL: | |
196 | if (twl4030->predriver_enabled) | |
197 | write_to_reg = 1; | |
198 | break; | |
199 | case TWL4030_REG_PRECKL_CTL: | |
200 | if (twl4030->carkitl_enabled) | |
201 | write_to_reg = 1; | |
202 | break; | |
203 | case TWL4030_REG_PRECKR_CTL: | |
204 | if (twl4030->carkitr_enabled) | |
205 | write_to_reg = 1; | |
206 | break; | |
207 | case TWL4030_REG_HS_GAIN_SET: | |
208 | if (twl4030->hsl_enabled || twl4030->hsr_enabled) | |
209 | write_to_reg = 1; | |
210 | break; | |
211 | default: | |
212 | /* All other register can be written */ | |
213 | write_to_reg = 1; | |
214 | break; | |
215 | } | |
216 | if (write_to_reg) | |
217 | return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
218 | value, reg); | |
219 | } | |
220 | return 0; | |
cc17557e SS |
221 | } |
222 | ||
db04e2c5 | 223 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 224 | { |
b2c812e2 | 225 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 226 | int mode; |
cc17557e | 227 | |
7393958f PU |
228 | if (enable == twl4030->codec_powered) |
229 | return; | |
230 | ||
db04e2c5 | 231 | if (enable) |
7a1fecf5 | 232 | mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER); |
db04e2c5 | 233 | else |
7a1fecf5 | 234 | mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER); |
cc17557e | 235 | |
7a1fecf5 PU |
236 | if (mode >= 0) { |
237 | twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode); | |
238 | twl4030->codec_powered = enable; | |
239 | } | |
cc17557e SS |
240 | |
241 | /* REVISIT: this delay is present in TI sample drivers */ | |
242 | /* but there seems to be no TRM requirement for it */ | |
243 | udelay(10); | |
244 | } | |
245 | ||
246 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
247 | { | |
16a30fbb | 248 | u8 *cache = codec->reg_cache; |
cc17557e SS |
249 | int i; |
250 | ||
251 | /* clear CODECPDZ prior to setting register defaults */ | |
db04e2c5 | 252 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
253 | |
254 | /* set all audio section registers to reasonable defaults */ | |
255 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
68d01955 PU |
256 | if (i != TWL4030_REG_APLL_CTL) |
257 | twl4030_write(codec, i, cache[i]); | |
cc17557e SS |
258 | |
259 | } | |
260 | ||
2845fa13 | 261 | static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable) |
7393958f | 262 | { |
b2c812e2 | 263 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7b4c734e | 264 | int status = -1; |
7393958f | 265 | |
7b4c734e PU |
266 | if (enable) { |
267 | twl4030->apll_enabled++; | |
268 | if (twl4030->apll_enabled == 1) | |
269 | status = twl4030_codec_enable_resource( | |
270 | TWL4030_CODEC_RES_APLL); | |
271 | } else { | |
272 | twl4030->apll_enabled--; | |
273 | if (!twl4030->apll_enabled) | |
274 | status = twl4030_codec_disable_resource( | |
275 | TWL4030_CODEC_RES_APLL); | |
276 | } | |
7a1fecf5 PU |
277 | |
278 | if (status >= 0) | |
279 | twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status); | |
7393958f PU |
280 | } |
281 | ||
006f367e PU |
282 | static void twl4030_power_up(struct snd_soc_codec *codec) |
283 | { | |
b2c812e2 | 284 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
006f367e PU |
285 | u8 anamicl, regmisc1, byte; |
286 | int i = 0; | |
287 | ||
7393958f PU |
288 | if (twl4030->codec_powered) |
289 | return; | |
290 | ||
006f367e PU |
291 | /* set CODECPDZ to turn on codec */ |
292 | twl4030_codec_enable(codec, 1); | |
293 | ||
294 | /* initiate offset cancellation */ | |
295 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
296 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
297 | anamicl | TWL4030_CNCL_OFFSET_START); | |
298 | ||
299 | /* wait for offset cancellation to complete */ | |
300 | do { | |
301 | /* this takes a little while, so don't slam i2c */ | |
302 | udelay(2000); | |
fc7b92fc | 303 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, |
006f367e PU |
304 | TWL4030_REG_ANAMICL); |
305 | } while ((i++ < 100) && | |
306 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
307 | TWL4030_CNCL_OFFSET_START)); | |
308 | ||
309 | /* Make sure that the reg_cache has the same value as the HW */ | |
310 | twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); | |
311 | ||
312 | /* anti-pop when changing analog gain */ | |
313 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
314 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
315 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
316 | ||
317 | /* toggle CODECPDZ as per TRM */ | |
318 | twl4030_codec_enable(codec, 0); | |
319 | twl4030_codec_enable(codec, 1); | |
320 | } | |
321 | ||
7393958f PU |
322 | /* |
323 | * Unconditional power down | |
324 | */ | |
006f367e PU |
325 | static void twl4030_power_down(struct snd_soc_codec *codec) |
326 | { | |
327 | /* power down */ | |
328 | twl4030_codec_enable(codec, 0); | |
329 | } | |
330 | ||
5e98a464 | 331 | /* Earpiece */ |
1a787e7a JS |
332 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
333 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
334 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
335 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
336 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
337 | }; | |
5e98a464 | 338 | |
2a6f5c58 | 339 | /* PreDrive Left */ |
1a787e7a JS |
340 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
341 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
342 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
343 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
344 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
345 | }; | |
2a6f5c58 PU |
346 | |
347 | /* PreDrive Right */ | |
1a787e7a JS |
348 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
349 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
350 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
351 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
352 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
353 | }; | |
2a6f5c58 | 354 | |
dfad21a2 | 355 | /* Headset Left */ |
1a787e7a JS |
356 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
357 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
358 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
359 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
360 | }; | |
dfad21a2 PU |
361 | |
362 | /* Headset Right */ | |
1a787e7a JS |
363 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
364 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
365 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
366 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
367 | }; | |
dfad21a2 | 368 | |
5152d8c2 | 369 | /* Carkit Left */ |
1a787e7a JS |
370 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
371 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
372 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
373 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
374 | }; | |
5152d8c2 PU |
375 | |
376 | /* Carkit Right */ | |
1a787e7a JS |
377 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
378 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
379 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
380 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
381 | }; | |
5152d8c2 | 382 | |
df339804 PU |
383 | /* Handsfree Left */ |
384 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 385 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 PU |
386 | |
387 | static const struct soc_enum twl4030_handsfreel_enum = | |
388 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
389 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
390 | twl4030_handsfreel_texts); | |
391 | ||
392 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
393 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
394 | ||
0f89bdca PU |
395 | /* Handsfree Left virtual mute */ |
396 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
397 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0); | |
398 | ||
df339804 PU |
399 | /* Handsfree Right */ |
400 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 401 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 PU |
402 | |
403 | static const struct soc_enum twl4030_handsfreer_enum = | |
404 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
405 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
406 | twl4030_handsfreer_texts); | |
407 | ||
408 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
409 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
410 | ||
0f89bdca PU |
411 | /* Handsfree Right virtual mute */ |
412 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
413 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0); | |
414 | ||
376f7839 PU |
415 | /* Vibra */ |
416 | /* Vibra audio path selection */ | |
417 | static const char *twl4030_vibra_texts[] = | |
418 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
419 | ||
420 | static const struct soc_enum twl4030_vibra_enum = | |
421 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, | |
422 | ARRAY_SIZE(twl4030_vibra_texts), | |
423 | twl4030_vibra_texts); | |
424 | ||
425 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
426 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
427 | ||
428 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
429 | static const char *twl4030_vibrapath_texts[] = | |
430 | {"Local vibrator", "Audio"}; | |
431 | ||
432 | static const struct soc_enum twl4030_vibrapath_enum = | |
433 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, | |
434 | ARRAY_SIZE(twl4030_vibrapath_texts), | |
435 | twl4030_vibrapath_texts); | |
436 | ||
437 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
438 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
439 | ||
276c6222 | 440 | /* Left analog microphone selection */ |
97b8096d | 441 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
9028935d PU |
442 | SOC_DAPM_SINGLE("Main Mic Capture Switch", |
443 | TWL4030_REG_ANAMICL, 0, 1, 0), | |
444 | SOC_DAPM_SINGLE("Headset Mic Capture Switch", | |
445 | TWL4030_REG_ANAMICL, 1, 1, 0), | |
446 | SOC_DAPM_SINGLE("AUXL Capture Switch", | |
447 | TWL4030_REG_ANAMICL, 2, 1, 0), | |
448 | SOC_DAPM_SINGLE("Carkit Mic Capture Switch", | |
449 | TWL4030_REG_ANAMICL, 3, 1, 0), | |
97b8096d | 450 | }; |
276c6222 PU |
451 | |
452 | /* Right analog microphone selection */ | |
97b8096d | 453 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
9028935d PU |
454 | SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), |
455 | SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), | |
97b8096d | 456 | }; |
276c6222 PU |
457 | |
458 | /* TX1 L/R Analog/Digital microphone selection */ | |
459 | static const char *twl4030_micpathtx1_texts[] = | |
460 | {"Analog", "Digimic0"}; | |
461 | ||
462 | static const struct soc_enum twl4030_micpathtx1_enum = | |
463 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
464 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
465 | twl4030_micpathtx1_texts); | |
466 | ||
467 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
468 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
469 | ||
470 | /* TX2 L/R Analog/Digital microphone selection */ | |
471 | static const char *twl4030_micpathtx2_texts[] = | |
472 | {"Analog", "Digimic1"}; | |
473 | ||
474 | static const struct soc_enum twl4030_micpathtx2_enum = | |
475 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
476 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
477 | twl4030_micpathtx2_texts); | |
478 | ||
479 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
480 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
481 | ||
7393958f PU |
482 | /* Analog bypass for AudioR1 */ |
483 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
484 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
485 | ||
486 | /* Analog bypass for AudioL1 */ | |
487 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
488 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
489 | ||
490 | /* Analog bypass for AudioR2 */ | |
491 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
492 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
493 | ||
494 | /* Analog bypass for AudioL2 */ | |
495 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
496 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
497 | ||
fcd274a3 LCM |
498 | /* Analog bypass for Voice */ |
499 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
500 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
501 | ||
6bab83fd PU |
502 | /* Digital bypass gain, 0 mutes the bypass */ |
503 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { | |
504 | TLV_DB_RANGE_HEAD(2), | |
505 | 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), | |
506 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), | |
507 | }; | |
508 | ||
509 | /* Digital bypass left (TX1L -> RX2L) */ | |
510 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
511 | SOC_DAPM_SINGLE_TLV("Volume", | |
512 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
513 | twl4030_dapm_dbypass_tlv); | |
514 | ||
515 | /* Digital bypass right (TX1R -> RX2R) */ | |
516 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
517 | SOC_DAPM_SINGLE_TLV("Volume", | |
518 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
519 | twl4030_dapm_dbypass_tlv); | |
520 | ||
ee8f6894 LCM |
521 | /* |
522 | * Voice Sidetone GAIN volume control: | |
523 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
524 | */ | |
525 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
526 | ||
527 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
528 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
529 | SOC_DAPM_SINGLE_TLV("Volume", | |
530 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
531 | twl4030_dapm_dbypassv_tlv); | |
532 | ||
276c6222 PU |
533 | static int micpath_event(struct snd_soc_dapm_widget *w, |
534 | struct snd_kcontrol *kcontrol, int event) | |
535 | { | |
536 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
537 | unsigned char adcmicsel, micbias_ctl; | |
538 | ||
539 | adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); | |
540 | micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); | |
541 | /* Prepare the bits for the given TX path: | |
542 | * shift_l == 0: TX1 microphone path | |
543 | * shift_l == 2: TX2 microphone path */ | |
544 | if (e->shift_l) { | |
545 | /* TX2 microphone path */ | |
546 | if (adcmicsel & TWL4030_TX2IN_SEL) | |
547 | micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ | |
548 | else | |
549 | micbias_ctl &= ~TWL4030_MICBIAS2_CTL; | |
550 | } else { | |
551 | /* TX1 microphone path */ | |
552 | if (adcmicsel & TWL4030_TX1IN_SEL) | |
553 | micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ | |
554 | else | |
555 | micbias_ctl &= ~TWL4030_MICBIAS1_CTL; | |
556 | } | |
557 | ||
558 | twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
9008adf9 PU |
563 | /* |
564 | * Output PGA builder: | |
565 | * Handle the muting and unmuting of the given output (turning off the | |
566 | * amplifier associated with the output pin) | |
c96907f2 PU |
567 | * On mute bypass the reg_cache and write 0 to the register |
568 | * On unmute: restore the register content from the reg_cache | |
9008adf9 PU |
569 | * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R |
570 | */ | |
571 | #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ | |
572 | static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ | |
573 | struct snd_kcontrol *kcontrol, int event) \ | |
574 | { \ | |
b2c812e2 | 575 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \ |
9008adf9 PU |
576 | \ |
577 | switch (event) { \ | |
578 | case SND_SOC_DAPM_POST_PMU: \ | |
c96907f2 | 579 | twl4030->pin_name##_enabled = 1; \ |
9008adf9 PU |
580 | twl4030_write(w->codec, reg, \ |
581 | twl4030_read_reg_cache(w->codec, reg)); \ | |
582 | break; \ | |
583 | case SND_SOC_DAPM_POST_PMD: \ | |
c96907f2 PU |
584 | twl4030->pin_name##_enabled = 0; \ |
585 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \ | |
586 | 0, reg); \ | |
9008adf9 PU |
587 | break; \ |
588 | } \ | |
589 | return 0; \ | |
590 | } | |
591 | ||
592 | TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); | |
593 | TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); | |
594 | TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); | |
595 | TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); | |
596 | TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); | |
597 | ||
5a2e9a48 | 598 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 599 | { |
49d92c7d SM |
600 | unsigned char hs_ctl; |
601 | ||
5a2e9a48 | 602 | hs_ctl = twl4030_read_reg_cache(codec, reg); |
49d92c7d | 603 | |
5a2e9a48 PU |
604 | if (ramp) { |
605 | /* HF ramp-up */ | |
606 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
607 | twl4030_write(codec, reg, hs_ctl); | |
608 | udelay(10); | |
49d92c7d | 609 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
610 | twl4030_write(codec, reg, hs_ctl); |
611 | udelay(40); | |
49d92c7d | 612 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 613 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 614 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 615 | } else { |
5a2e9a48 PU |
616 | /* HF ramp-down */ |
617 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
618 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
619 | twl4030_write(codec, reg, hs_ctl); | |
620 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
621 | twl4030_write(codec, reg, hs_ctl); | |
622 | udelay(40); | |
623 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
624 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 625 | } |
5a2e9a48 | 626 | } |
49d92c7d | 627 | |
5a2e9a48 PU |
628 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
629 | struct snd_kcontrol *kcontrol, int event) | |
630 | { | |
631 | switch (event) { | |
632 | case SND_SOC_DAPM_POST_PMU: | |
633 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); | |
634 | break; | |
635 | case SND_SOC_DAPM_POST_PMD: | |
636 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); | |
637 | break; | |
638 | } | |
639 | return 0; | |
640 | } | |
641 | ||
642 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
643 | struct snd_kcontrol *kcontrol, int event) | |
644 | { | |
645 | switch (event) { | |
646 | case SND_SOC_DAPM_POST_PMU: | |
647 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); | |
648 | break; | |
649 | case SND_SOC_DAPM_POST_PMD: | |
650 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); | |
651 | break; | |
652 | } | |
49d92c7d SM |
653 | return 0; |
654 | } | |
655 | ||
86139a13 JV |
656 | static int vibramux_event(struct snd_soc_dapm_widget *w, |
657 | struct snd_kcontrol *kcontrol, int event) | |
658 | { | |
659 | twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff); | |
660 | return 0; | |
661 | } | |
662 | ||
7729cf74 PU |
663 | static int apll_event(struct snd_soc_dapm_widget *w, |
664 | struct snd_kcontrol *kcontrol, int event) | |
665 | { | |
666 | switch (event) { | |
667 | case SND_SOC_DAPM_PRE_PMU: | |
668 | twl4030_apll_enable(w->codec, 1); | |
669 | break; | |
670 | case SND_SOC_DAPM_POST_PMD: | |
671 | twl4030_apll_enable(w->codec, 0); | |
672 | break; | |
673 | } | |
674 | return 0; | |
675 | } | |
676 | ||
7b4c734e PU |
677 | static int aif_event(struct snd_soc_dapm_widget *w, |
678 | struct snd_kcontrol *kcontrol, int event) | |
679 | { | |
680 | u8 audio_if; | |
681 | ||
682 | audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF); | |
683 | switch (event) { | |
684 | case SND_SOC_DAPM_PRE_PMU: | |
685 | /* Enable AIF */ | |
686 | /* enable the PLL before we use it to clock the DAI */ | |
687 | twl4030_apll_enable(w->codec, 1); | |
688 | ||
689 | twl4030_write(w->codec, TWL4030_REG_AUDIO_IF, | |
690 | audio_if | TWL4030_AIF_EN); | |
691 | break; | |
692 | case SND_SOC_DAPM_POST_PMD: | |
693 | /* disable the DAI before we stop it's source PLL */ | |
694 | twl4030_write(w->codec, TWL4030_REG_AUDIO_IF, | |
695 | audio_if & ~TWL4030_AIF_EN); | |
696 | twl4030_apll_enable(w->codec, 0); | |
697 | break; | |
698 | } | |
699 | return 0; | |
700 | } | |
701 | ||
6943c92e | 702 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 | 703 | { |
4e49ffd1 CVJ |
704 | struct snd_soc_device *socdev = codec->socdev; |
705 | struct twl4030_setup_data *setup = socdev->codec_data; | |
706 | ||
aad749e5 | 707 | unsigned char hs_gain, hs_pop; |
b2c812e2 | 708 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
6943c92e PU |
709 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ |
710 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
711 | 8388608, 16777216, 33554432, 67108864}; | |
aad749e5 | 712 | |
6943c92e PU |
713 | hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); |
714 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
aad749e5 | 715 | |
4e49ffd1 CVJ |
716 | /* Enable external mute control, this dramatically reduces |
717 | * the pop-noise */ | |
718 | if (setup && setup->hs_extmute) { | |
719 | if (setup->set_hs_extmute) { | |
720 | setup->set_hs_extmute(1); | |
721 | } else { | |
722 | hs_pop |= TWL4030_EXTMUTE; | |
723 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
724 | } | |
725 | } | |
726 | ||
6943c92e PU |
727 | if (ramp) { |
728 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 729 | hs_pop |= TWL4030_VMID_EN; |
6943c92e | 730 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
c96907f2 PU |
731 | /* Actually write to the register */ |
732 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
733 | hs_gain, | |
734 | TWL4030_REG_HS_GAIN_SET); | |
aad749e5 | 735 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e | 736 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
4e49ffd1 CVJ |
737 | /* Wait ramp delay time + 1, so the VMID can settle */ |
738 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
739 | twl4030->sysclk) + 1); | |
6943c92e PU |
740 | } else { |
741 | /* Headset ramp-down _not_ according to | |
742 | * the TRM, but in a way that it is working */ | |
aad749e5 | 743 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
744 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
745 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
746 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
747 | twl4030->sysclk) + 1); | |
aad749e5 | 748 | /* Bypass the reg_cache to mute the headset */ |
fc7b92fc | 749 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, |
aad749e5 PU |
750 | hs_gain & (~0x0f), |
751 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 752 | |
aad749e5 | 753 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
754 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
755 | } | |
4e49ffd1 CVJ |
756 | |
757 | /* Disable external mute */ | |
758 | if (setup && setup->hs_extmute) { | |
759 | if (setup->set_hs_extmute) { | |
760 | setup->set_hs_extmute(0); | |
761 | } else { | |
762 | hs_pop &= ~TWL4030_EXTMUTE; | |
763 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
764 | } | |
765 | } | |
6943c92e PU |
766 | } |
767 | ||
768 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
769 | struct snd_kcontrol *kcontrol, int event) | |
770 | { | |
b2c812e2 | 771 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
772 | |
773 | switch (event) { | |
774 | case SND_SOC_DAPM_POST_PMU: | |
775 | /* Do the ramp-up only once */ | |
776 | if (!twl4030->hsr_enabled) | |
777 | headset_ramp(w->codec, 1); | |
778 | ||
779 | twl4030->hsl_enabled = 1; | |
780 | break; | |
781 | case SND_SOC_DAPM_POST_PMD: | |
782 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
783 | if (!twl4030->hsr_enabled) | |
784 | headset_ramp(w->codec, 0); | |
785 | ||
786 | twl4030->hsl_enabled = 0; | |
787 | break; | |
788 | } | |
789 | return 0; | |
790 | } | |
791 | ||
792 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
793 | struct snd_kcontrol *kcontrol, int event) | |
794 | { | |
b2c812e2 | 795 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
796 | |
797 | switch (event) { | |
798 | case SND_SOC_DAPM_POST_PMU: | |
799 | /* Do the ramp-up only once */ | |
800 | if (!twl4030->hsl_enabled) | |
801 | headset_ramp(w->codec, 1); | |
802 | ||
803 | twl4030->hsr_enabled = 1; | |
804 | break; | |
805 | case SND_SOC_DAPM_POST_PMD: | |
806 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
807 | if (!twl4030->hsl_enabled) | |
808 | headset_ramp(w->codec, 0); | |
809 | ||
810 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
811 | break; |
812 | } | |
813 | return 0; | |
814 | } | |
815 | ||
b0bd53a7 PU |
816 | /* |
817 | * Some of the gain controls in TWL (mostly those which are associated with | |
818 | * the outputs) are implemented in an interesting way: | |
819 | * 0x0 : Power down (mute) | |
820 | * 0x1 : 6dB | |
821 | * 0x2 : 0 dB | |
822 | * 0x3 : -6 dB | |
823 | * Inverting not going to help with these. | |
824 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
825 | */ | |
826 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
827 | xinvert, tlv_array) \ | |
828 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
829 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
830 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
831 | .tlv.p = (tlv_array), \ | |
832 | .info = snd_soc_info_volsw, \ | |
833 | .get = snd_soc_get_volsw_twl4030, \ | |
834 | .put = snd_soc_put_volsw_twl4030, \ | |
835 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
836 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
837 | .max = xmax, .invert = xinvert} } | |
838 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
839 | xinvert, tlv_array) \ | |
840 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
841 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
842 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
843 | .tlv.p = (tlv_array), \ | |
844 | .info = snd_soc_info_volsw_2r, \ | |
845 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
846 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
847 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
848 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
64089b84 | 849 | .rshift = xshift, .max = xmax, .invert = xinvert} } |
b0bd53a7 PU |
850 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ |
851 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
852 | xinvert, tlv_array) | |
853 | ||
854 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
855 | struct snd_ctl_elem_value *ucontrol) | |
856 | { | |
857 | struct soc_mixer_control *mc = | |
858 | (struct soc_mixer_control *)kcontrol->private_value; | |
859 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
860 | unsigned int reg = mc->reg; | |
861 | unsigned int shift = mc->shift; | |
862 | unsigned int rshift = mc->rshift; | |
863 | int max = mc->max; | |
864 | int mask = (1 << fls(max)) - 1; | |
865 | ||
866 | ucontrol->value.integer.value[0] = | |
867 | (snd_soc_read(codec, reg) >> shift) & mask; | |
868 | if (ucontrol->value.integer.value[0]) | |
869 | ucontrol->value.integer.value[0] = | |
870 | max + 1 - ucontrol->value.integer.value[0]; | |
871 | ||
872 | if (shift != rshift) { | |
873 | ucontrol->value.integer.value[1] = | |
874 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
875 | if (ucontrol->value.integer.value[1]) | |
876 | ucontrol->value.integer.value[1] = | |
877 | max + 1 - ucontrol->value.integer.value[1]; | |
878 | } | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
884 | struct snd_ctl_elem_value *ucontrol) | |
885 | { | |
886 | struct soc_mixer_control *mc = | |
887 | (struct soc_mixer_control *)kcontrol->private_value; | |
888 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
889 | unsigned int reg = mc->reg; | |
890 | unsigned int shift = mc->shift; | |
891 | unsigned int rshift = mc->rshift; | |
892 | int max = mc->max; | |
893 | int mask = (1 << fls(max)) - 1; | |
894 | unsigned short val, val2, val_mask; | |
895 | ||
896 | val = (ucontrol->value.integer.value[0] & mask); | |
897 | ||
898 | val_mask = mask << shift; | |
899 | if (val) | |
900 | val = max + 1 - val; | |
901 | val = val << shift; | |
902 | if (shift != rshift) { | |
903 | val2 = (ucontrol->value.integer.value[1] & mask); | |
904 | val_mask |= mask << rshift; | |
905 | if (val2) | |
906 | val2 = max + 1 - val2; | |
907 | val |= val2 << rshift; | |
908 | } | |
909 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
910 | } | |
911 | ||
912 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
913 | struct snd_ctl_elem_value *ucontrol) | |
914 | { | |
915 | struct soc_mixer_control *mc = | |
916 | (struct soc_mixer_control *)kcontrol->private_value; | |
917 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
918 | unsigned int reg = mc->reg; | |
919 | unsigned int reg2 = mc->rreg; | |
920 | unsigned int shift = mc->shift; | |
921 | int max = mc->max; | |
922 | int mask = (1<<fls(max))-1; | |
923 | ||
924 | ucontrol->value.integer.value[0] = | |
925 | (snd_soc_read(codec, reg) >> shift) & mask; | |
926 | ucontrol->value.integer.value[1] = | |
927 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
928 | ||
929 | if (ucontrol->value.integer.value[0]) | |
930 | ucontrol->value.integer.value[0] = | |
931 | max + 1 - ucontrol->value.integer.value[0]; | |
932 | if (ucontrol->value.integer.value[1]) | |
933 | ucontrol->value.integer.value[1] = | |
934 | max + 1 - ucontrol->value.integer.value[1]; | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
940 | struct snd_ctl_elem_value *ucontrol) | |
941 | { | |
942 | struct soc_mixer_control *mc = | |
943 | (struct soc_mixer_control *)kcontrol->private_value; | |
944 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
945 | unsigned int reg = mc->reg; | |
946 | unsigned int reg2 = mc->rreg; | |
947 | unsigned int shift = mc->shift; | |
948 | int max = mc->max; | |
949 | int mask = (1 << fls(max)) - 1; | |
950 | int err; | |
951 | unsigned short val, val2, val_mask; | |
952 | ||
953 | val_mask = mask << shift; | |
954 | val = (ucontrol->value.integer.value[0] & mask); | |
955 | val2 = (ucontrol->value.integer.value[1] & mask); | |
956 | ||
957 | if (val) | |
958 | val = max + 1 - val; | |
959 | if (val2) | |
960 | val2 = max + 1 - val2; | |
961 | ||
962 | val = val << shift; | |
963 | val2 = val2 << shift; | |
964 | ||
965 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
966 | if (err < 0) | |
967 | return err; | |
968 | ||
969 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
970 | return err; | |
971 | } | |
972 | ||
b74bd40f LCM |
973 | /* Codec operation modes */ |
974 | static const char *twl4030_op_modes_texts[] = { | |
975 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
976 | }; | |
977 | ||
978 | static const struct soc_enum twl4030_op_modes_enum = | |
979 | SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, | |
980 | ARRAY_SIZE(twl4030_op_modes_texts), | |
981 | twl4030_op_modes_texts); | |
982 | ||
423c238d | 983 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
984 | struct snd_ctl_elem_value *ucontrol) |
985 | { | |
986 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 987 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
b74bd40f LCM |
988 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
989 | unsigned short val; | |
990 | unsigned short mask, bitmask; | |
991 | ||
992 | if (twl4030->configured) { | |
993 | printk(KERN_ERR "twl4030 operation mode cannot be " | |
994 | "changed on-the-fly\n"); | |
995 | return -EBUSY; | |
996 | } | |
997 | ||
998 | for (bitmask = 1; bitmask < e->max; bitmask <<= 1) | |
999 | ; | |
1000 | if (ucontrol->value.enumerated.item[0] > e->max - 1) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | val = ucontrol->value.enumerated.item[0] << e->shift_l; | |
1004 | mask = (bitmask - 1) << e->shift_l; | |
1005 | if (e->shift_l != e->shift_r) { | |
1006 | if (ucontrol->value.enumerated.item[1] > e->max - 1) | |
1007 | return -EINVAL; | |
1008 | val |= ucontrol->value.enumerated.item[1] << e->shift_r; | |
1009 | mask |= (bitmask - 1) << e->shift_r; | |
1010 | } | |
1011 | ||
1012 | return snd_soc_update_bits(codec, e->reg, mask, val); | |
1013 | } | |
1014 | ||
c10b82cf PU |
1015 | /* |
1016 | * FGAIN volume control: | |
1017 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
1018 | */ | |
d889a72c | 1019 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 1020 | |
0d33ea0b PU |
1021 | /* |
1022 | * CGAIN volume control: | |
1023 | * 0 dB to 12 dB in 6 dB steps | |
1024 | * value 2 and 3 means 12 dB | |
1025 | */ | |
d889a72c PU |
1026 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
1027 | ||
1a787e7a JS |
1028 | /* |
1029 | * Voice Downlink GAIN volume control: | |
1030 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
1031 | */ | |
1032 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
1033 | ||
d889a72c PU |
1034 | /* |
1035 | * Analog playback gain | |
1036 | * -24 dB to 12 dB in 2 dB steps | |
1037 | */ | |
1038 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 1039 | |
4290239c PU |
1040 | /* |
1041 | * Gain controls tied to outputs | |
1042 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
1043 | */ | |
1044 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
1045 | ||
18cc8d8d JS |
1046 | /* |
1047 | * Gain control for earpiece amplifier | |
1048 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
1049 | */ | |
1050 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
1051 | ||
381a22b5 PU |
1052 | /* |
1053 | * Capture gain after the ADCs | |
1054 | * from 0 dB to 31 dB in 1 dB steps | |
1055 | */ | |
1056 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
1057 | ||
5920b453 GI |
1058 | /* |
1059 | * Gain control for input amplifiers | |
1060 | * 0 dB to 30 dB in 6 dB steps | |
1061 | */ | |
1062 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
1063 | ||
328d0a13 LCM |
1064 | /* AVADC clock priority */ |
1065 | static const char *twl4030_avadc_clk_priority_texts[] = { | |
1066 | "Voice high priority", "HiFi high priority" | |
1067 | }; | |
1068 | ||
1069 | static const struct soc_enum twl4030_avadc_clk_priority_enum = | |
1070 | SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2, | |
1071 | ARRAY_SIZE(twl4030_avadc_clk_priority_texts), | |
1072 | twl4030_avadc_clk_priority_texts); | |
1073 | ||
89492be8 PU |
1074 | static const char *twl4030_rampdelay_texts[] = { |
1075 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1076 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1077 | "3495/2581/1748 ms" | |
1078 | }; | |
1079 | ||
1080 | static const struct soc_enum twl4030_rampdelay_enum = | |
1081 | SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, | |
1082 | ARRAY_SIZE(twl4030_rampdelay_texts), | |
1083 | twl4030_rampdelay_texts); | |
1084 | ||
376f7839 PU |
1085 | /* Vibra H-bridge direction mode */ |
1086 | static const char *twl4030_vibradirmode_texts[] = { | |
1087 | "Vibra H-bridge direction", "Audio data MSB", | |
1088 | }; | |
1089 | ||
1090 | static const struct soc_enum twl4030_vibradirmode_enum = | |
1091 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, | |
1092 | ARRAY_SIZE(twl4030_vibradirmode_texts), | |
1093 | twl4030_vibradirmode_texts); | |
1094 | ||
1095 | /* Vibra H-bridge direction */ | |
1096 | static const char *twl4030_vibradir_texts[] = { | |
1097 | "Positive polarity", "Negative polarity", | |
1098 | }; | |
1099 | ||
1100 | static const struct soc_enum twl4030_vibradir_enum = | |
1101 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, | |
1102 | ARRAY_SIZE(twl4030_vibradir_texts), | |
1103 | twl4030_vibradir_texts); | |
1104 | ||
cc17557e | 1105 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1106 | /* Codec operation mode control */ |
1107 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1108 | snd_soc_get_enum_double, | |
1109 | snd_soc_put_twl4030_opmode_enum_double), | |
1110 | ||
d889a72c PU |
1111 | /* Common playback gain controls */ |
1112 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1113 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1114 | 0, 0x3f, 0, digital_fine_tlv), | |
1115 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1116 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1117 | 0, 0x3f, 0, digital_fine_tlv), | |
1118 | ||
1119 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1120 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1121 | 6, 0x2, 0, digital_coarse_tlv), | |
1122 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1123 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1124 | 6, 0x2, 0, digital_coarse_tlv), | |
1125 | ||
1126 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1127 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1128 | 3, 0x12, 1, analog_tlv), | |
1129 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1130 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1131 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1132 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1133 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1134 | 1, 1, 0), | |
1135 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1136 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1137 | 1, 1, 0), | |
381a22b5 | 1138 | |
1a787e7a JS |
1139 | /* Common voice downlink gain controls */ |
1140 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1141 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1142 | ||
1143 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1144 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1145 | ||
1146 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1147 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1148 | ||
4290239c PU |
1149 | /* Separate output gain controls */ |
1150 | SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", | |
1151 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, | |
1152 | 4, 3, 0, output_tvl), | |
1153 | ||
1154 | SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", | |
1155 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), | |
1156 | ||
1157 | SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", | |
1158 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, | |
1159 | 4, 3, 0, output_tvl), | |
1160 | ||
1161 | SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", | |
18cc8d8d | 1162 | TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl), |
4290239c | 1163 | |
381a22b5 | 1164 | /* Common capture gain controls */ |
276c6222 | 1165 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1166 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1167 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1168 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1169 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1170 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1171 | |
276c6222 | 1172 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1173 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 | 1174 | |
328d0a13 LCM |
1175 | SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), |
1176 | ||
89492be8 | 1177 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), |
376f7839 PU |
1178 | |
1179 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1180 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
cc17557e SS |
1181 | }; |
1182 | ||
cc17557e | 1183 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1184 | /* Left channel inputs */ |
1185 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1186 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1187 | SND_SOC_DAPM_INPUT("AUXL"), | |
1188 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1189 | /* Right channel inputs */ | |
1190 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1191 | SND_SOC_DAPM_INPUT("AUXR"), | |
1192 | /* Digital microphones (Stereo) */ | |
1193 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1194 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1195 | ||
1196 | /* Outputs */ | |
5e98a464 | 1197 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1198 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1199 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1200 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1201 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1202 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1203 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1204 | SND_SOC_DAPM_OUTPUT("HFL"), |
1205 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1206 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1207 | |
7b4c734e PU |
1208 | /* AIF and APLL clocks for running DAIs (including loopback) */ |
1209 | SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"), | |
1210 | SND_SOC_DAPM_INPUT("Virtual HiFi IN"), | |
1211 | SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"), | |
1212 | ||
53b5047d | 1213 | /* DACs */ |
b4852b79 | 1214 | SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback", |
7393958f | 1215 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1216 | SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback", |
7393958f | 1217 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1218 | SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback", |
7393958f | 1219 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1220 | SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback", |
7393958f | 1221 | SND_SOC_NOPM, 0, 0), |
1a787e7a | 1222 | SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback", |
fcd274a3 | 1223 | SND_SOC_NOPM, 0, 0), |
cc17557e | 1224 | |
7393958f | 1225 | /* Analog bypasses */ |
78e08e2f PU |
1226 | SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, |
1227 | &twl4030_dapm_abypassr1_control), | |
1228 | SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1229 | &twl4030_dapm_abypassl1_control), | |
1230 | SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1231 | &twl4030_dapm_abypassr2_control), | |
1232 | SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1233 | &twl4030_dapm_abypassl2_control), | |
1234 | SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1235 | &twl4030_dapm_abypassv_control), | |
1236 | ||
1237 | /* Master analog loopback switch */ | |
1238 | SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0, | |
1239 | NULL, 0), | |
7393958f | 1240 | |
6bab83fd | 1241 | /* Digital bypasses */ |
78e08e2f PU |
1242 | SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0, |
1243 | &twl4030_dapm_dbypassl_control), | |
1244 | SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1245 | &twl4030_dapm_dbypassr_control), | |
1246 | SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1247 | &twl4030_dapm_dbypassv_control), | |
6bab83fd | 1248 | |
4005d39a PU |
1249 | /* Digital mixers, power control for the physical DACs */ |
1250 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1251 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1252 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1253 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1254 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1255 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1256 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1257 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1258 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1259 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1260 | ||
1261 | /* Analog mixers, power control for the physical PGAs */ | |
1262 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1263 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1264 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1265 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1266 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1267 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1268 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1269 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1270 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1271 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1272 | |
7729cf74 PU |
1273 | SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event, |
1274 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
1275 | ||
7b4c734e PU |
1276 | SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event, |
1277 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
c42a59ea | 1278 | |
1a787e7a | 1279 | /* Output MIXER controls */ |
5e98a464 | 1280 | /* Earpiece */ |
1a787e7a JS |
1281 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1282 | &twl4030_dapm_earpiece_controls[0], | |
1283 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
9008adf9 PU |
1284 | SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, |
1285 | 0, 0, NULL, 0, earpiecepga_event, | |
1286 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
2a6f5c58 | 1287 | /* PreDrivL/R */ |
1a787e7a JS |
1288 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1289 | &twl4030_dapm_predrivel_controls[0], | |
1290 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
9008adf9 PU |
1291 | SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, |
1292 | 0, 0, NULL, 0, predrivelpga_event, | |
1293 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1294 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, |
1295 | &twl4030_dapm_predriver_controls[0], | |
1296 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
9008adf9 PU |
1297 | SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, |
1298 | 0, 0, NULL, 0, predriverpga_event, | |
1299 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 | 1300 | /* HeadsetL/R */ |
6943c92e | 1301 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1302 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1303 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1304 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1305 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1306 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1307 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1308 | &twl4030_dapm_hsor_controls[0], | |
1309 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1310 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1311 | 0, 0, NULL, 0, headsetrpga_event, | |
1312 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1313 | /* CarkitL/R */ |
1a787e7a JS |
1314 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1315 | &twl4030_dapm_carkitl_controls[0], | |
1316 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
9008adf9 PU |
1317 | SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, |
1318 | 0, 0, NULL, 0, carkitlpga_event, | |
1319 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1320 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, |
1321 | &twl4030_dapm_carkitr_controls[0], | |
1322 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
9008adf9 PU |
1323 | SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, |
1324 | 0, 0, NULL, 0, carkitrpga_event, | |
1325 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1326 | |
1327 | /* Output MUX controls */ | |
df339804 | 1328 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1329 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1330 | &twl4030_dapm_handsfreel_control), | |
e3c7dbb0 | 1331 | SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1332 | &twl4030_dapm_handsfreelmute_control), |
5a2e9a48 PU |
1333 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1334 | 0, 0, NULL, 0, handsfreelpga_event, | |
1335 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1336 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1337 | &twl4030_dapm_handsfreer_control), | |
e3c7dbb0 | 1338 | SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1339 | &twl4030_dapm_handsfreermute_control), |
5a2e9a48 PU |
1340 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1341 | 0, 0, NULL, 0, handsfreerpga_event, | |
1342 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 | 1343 | /* Vibra */ |
86139a13 JV |
1344 | SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, |
1345 | &twl4030_dapm_vibra_control, vibramux_event, | |
1346 | SND_SOC_DAPM_PRE_PMU), | |
376f7839 PU |
1347 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, |
1348 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1349 | |
276c6222 PU |
1350 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1351 | capture */ | |
1352 | SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", | |
1353 | SND_SOC_NOPM, 0, 0), | |
1354 | SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", | |
1355 | SND_SOC_NOPM, 0, 0), | |
1356 | SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", | |
1357 | SND_SOC_NOPM, 0, 0), | |
1358 | SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", | |
1359 | SND_SOC_NOPM, 0, 0), | |
1360 | ||
1361 | /* Analog/Digital mic path selection. | |
1362 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1363 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
1364 | SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, | |
1365 | &twl4030_dapm_micpathtx1_control, micpath_event, | |
1366 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1367 | SND_SOC_DAPM_POST_REG), | |
1368 | SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1369 | &twl4030_dapm_micpathtx2_control, micpath_event, | |
1370 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1371 | SND_SOC_DAPM_POST_REG), | |
1372 | ||
97b8096d | 1373 | /* Analog input mixers for the capture amplifiers */ |
9028935d | 1374 | SND_SOC_DAPM_MIXER("Analog Left", |
97b8096d JS |
1375 | TWL4030_REG_ANAMICL, 4, 0, |
1376 | &twl4030_dapm_analoglmic_controls[0], | |
1377 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
9028935d | 1378 | SND_SOC_DAPM_MIXER("Analog Right", |
97b8096d JS |
1379 | TWL4030_REG_ANAMICR, 4, 0, |
1380 | &twl4030_dapm_analogrmic_controls[0], | |
1381 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1382 | |
fb2a2f84 PU |
1383 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1384 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1385 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1386 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 PU |
1387 | |
1388 | SND_SOC_DAPM_PGA("Digimic0 Enable", | |
1389 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), | |
1390 | SND_SOC_DAPM_PGA("Digimic1 Enable", | |
1391 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), | |
1392 | ||
1393 | SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), | |
1394 | SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), | |
1395 | SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), | |
7393958f | 1396 | |
cc17557e SS |
1397 | }; |
1398 | ||
1399 | static const struct snd_soc_dapm_route intercon[] = { | |
4005d39a PU |
1400 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1401 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1402 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1403 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1404 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1405 | ||
7729cf74 | 1406 | /* Supply for the digital part (APLL) */ |
7729cf74 PU |
1407 | {"Digital Voice Playback Mixer", NULL, "APLL Enable"}, |
1408 | ||
c42a59ea PU |
1409 | {"Digital R1 Playback Mixer", NULL, "AIF Enable"}, |
1410 | {"Digital L1 Playback Mixer", NULL, "AIF Enable"}, | |
1411 | {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, | |
1412 | {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, | |
1413 | ||
4005d39a PU |
1414 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, |
1415 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1416 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1417 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1418 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1419 | |
5e98a464 PU |
1420 | /* Internal playback routings */ |
1421 | /* Earpiece */ | |
4005d39a PU |
1422 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1423 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1424 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1425 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
9008adf9 | 1426 | {"Earpiece PGA", NULL, "Earpiece Mixer"}, |
2a6f5c58 | 1427 | /* PreDrivL */ |
4005d39a PU |
1428 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1429 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1430 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1431 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1432 | {"PredriveL PGA", NULL, "PredriveL Mixer"}, |
2a6f5c58 | 1433 | /* PreDrivR */ |
4005d39a PU |
1434 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1435 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1436 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1437 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1438 | {"PredriveR PGA", NULL, "PredriveR Mixer"}, |
dfad21a2 | 1439 | /* HeadsetL */ |
4005d39a PU |
1440 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1441 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1442 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1443 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1444 | /* HeadsetR */ |
4005d39a PU |
1445 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1446 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1447 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1448 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1449 | /* CarkitL */ |
4005d39a PU |
1450 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1451 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1452 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1453 | {"CarkitL PGA", NULL, "CarkitL Mixer"}, |
5152d8c2 | 1454 | /* CarkitR */ |
4005d39a PU |
1455 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1456 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1457 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1458 | {"CarkitR PGA", NULL, "CarkitR Mixer"}, |
df339804 | 1459 | /* HandsfreeL */ |
4005d39a PU |
1460 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1461 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1462 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1463 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1464 | {"HandsfreeL", "Switch", "HandsfreeL Mux"}, |
1465 | {"HandsfreeL PGA", NULL, "HandsfreeL"}, | |
df339804 | 1466 | /* HandsfreeR */ |
4005d39a PU |
1467 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1468 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1469 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1470 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1471 | {"HandsfreeR", "Switch", "HandsfreeR Mux"}, |
1472 | {"HandsfreeR PGA", NULL, "HandsfreeR"}, | |
376f7839 PU |
1473 | /* Vibra */ |
1474 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1475 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1476 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1477 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1478 | |
cc17557e | 1479 | /* outputs */ |
7b4c734e PU |
1480 | /* Must be always connected (for AIF and APLL) */ |
1481 | {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"}, | |
1482 | {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"}, | |
1483 | {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"}, | |
1484 | {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"}, | |
1485 | /* Must be always connected (for APLL) */ | |
1486 | {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"}, | |
1487 | /* Physical outputs */ | |
9008adf9 PU |
1488 | {"EARPIECE", NULL, "Earpiece PGA"}, |
1489 | {"PREDRIVEL", NULL, "PredriveL PGA"}, | |
1490 | {"PREDRIVER", NULL, "PredriveR PGA"}, | |
6943c92e PU |
1491 | {"HSOL", NULL, "HeadsetL PGA"}, |
1492 | {"HSOR", NULL, "HeadsetR PGA"}, | |
9008adf9 PU |
1493 | {"CARKITL", NULL, "CarkitL PGA"}, |
1494 | {"CARKITR", NULL, "CarkitR PGA"}, | |
5a2e9a48 PU |
1495 | {"HFL", NULL, "HandsfreeL PGA"}, |
1496 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1497 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1498 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1499 | |
276c6222 | 1500 | /* Capture path */ |
7b4c734e PU |
1501 | /* Must be always connected (for AIF and APLL) */ |
1502 | {"ADC Virtual Left1", NULL, "Virtual HiFi IN"}, | |
1503 | {"ADC Virtual Right1", NULL, "Virtual HiFi IN"}, | |
1504 | {"ADC Virtual Left2", NULL, "Virtual HiFi IN"}, | |
1505 | {"ADC Virtual Right2", NULL, "Virtual HiFi IN"}, | |
1506 | /* Physical inputs */ | |
9028935d PU |
1507 | {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, |
1508 | {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, | |
1509 | {"Analog Left", "AUXL Capture Switch", "AUXL"}, | |
1510 | {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, | |
276c6222 | 1511 | |
9028935d PU |
1512 | {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, |
1513 | {"Analog Right", "AUXR Capture Switch", "AUXR"}, | |
276c6222 | 1514 | |
9028935d PU |
1515 | {"ADC Physical Left", NULL, "Analog Left"}, |
1516 | {"ADC Physical Right", NULL, "Analog Right"}, | |
276c6222 PU |
1517 | |
1518 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1519 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1520 | ||
1521 | /* TX1 Left capture path */ | |
fb2a2f84 | 1522 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1523 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1524 | /* TX1 Right capture path */ | |
fb2a2f84 | 1525 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1526 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1527 | /* TX2 Left capture path */ | |
fb2a2f84 | 1528 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1529 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1530 | /* TX2 Right capture path */ | |
fb2a2f84 | 1531 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1532 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1533 | ||
1534 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1535 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1536 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1537 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1538 | ||
c42a59ea PU |
1539 | {"ADC Virtual Left1", NULL, "AIF Enable"}, |
1540 | {"ADC Virtual Right1", NULL, "AIF Enable"}, | |
1541 | {"ADC Virtual Left2", NULL, "AIF Enable"}, | |
1542 | {"ADC Virtual Right2", NULL, "AIF Enable"}, | |
1543 | ||
7393958f | 1544 | /* Analog bypass routes */ |
9028935d PU |
1545 | {"Right1 Analog Loopback", "Switch", "Analog Right"}, |
1546 | {"Left1 Analog Loopback", "Switch", "Analog Left"}, | |
1547 | {"Right2 Analog Loopback", "Switch", "Analog Right"}, | |
1548 | {"Left2 Analog Loopback", "Switch", "Analog Left"}, | |
1549 | {"Voice Analog Loopback", "Switch", "Analog Left"}, | |
7393958f | 1550 | |
78e08e2f PU |
1551 | /* Supply for the Analog loopbacks */ |
1552 | {"Right1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1553 | {"Left1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1554 | {"Right2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1555 | {"Left2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1556 | {"Voice Analog Loopback", NULL, "FM Loop Enable"}, | |
1557 | ||
7393958f PU |
1558 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, |
1559 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1560 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1561 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1562 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1563 | |
6bab83fd PU |
1564 | /* Digital bypass routes */ |
1565 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1566 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1567 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1568 | |
4005d39a PU |
1569 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1570 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1571 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1572 | |
cc17557e SS |
1573 | }; |
1574 | ||
1575 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
1576 | { | |
1577 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
1578 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
1579 | ||
1580 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
1581 | ||
cc17557e SS |
1582 | return 0; |
1583 | } | |
1584 | ||
cc17557e SS |
1585 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1586 | enum snd_soc_bias_level level) | |
1587 | { | |
1588 | switch (level) { | |
1589 | case SND_SOC_BIAS_ON: | |
cc17557e SS |
1590 | break; |
1591 | case SND_SOC_BIAS_PREPARE: | |
cc17557e SS |
1592 | break; |
1593 | case SND_SOC_BIAS_STANDBY: | |
78e08e2f PU |
1594 | if (codec->bias_level == SND_SOC_BIAS_OFF) |
1595 | twl4030_power_up(codec); | |
cc17557e SS |
1596 | break; |
1597 | case SND_SOC_BIAS_OFF: | |
1598 | twl4030_power_down(codec); | |
1599 | break; | |
1600 | } | |
1601 | codec->bias_level = level; | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
6b87a91f PU |
1606 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1607 | struct snd_pcm_substream *mst_substream) | |
1608 | { | |
1609 | struct snd_pcm_substream *slv_substream; | |
1610 | ||
1611 | /* Pick the stream, which need to be constrained */ | |
1612 | if (mst_substream == twl4030->master_substream) | |
1613 | slv_substream = twl4030->slave_substream; | |
1614 | else if (mst_substream == twl4030->slave_substream) | |
1615 | slv_substream = twl4030->master_substream; | |
1616 | else /* This should not happen.. */ | |
1617 | return; | |
1618 | ||
1619 | /* Set the constraints according to the already configured stream */ | |
1620 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1621 | SNDRV_PCM_HW_PARAM_RATE, | |
1622 | twl4030->rate, | |
1623 | twl4030->rate); | |
1624 | ||
1625 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1626 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1627 | twl4030->sample_bits, | |
1628 | twl4030->sample_bits); | |
1629 | ||
1630 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1631 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1632 | twl4030->channels, | |
1633 | twl4030->channels); | |
1634 | } | |
1635 | ||
8a1f936a PU |
1636 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1637 | * capture has to be enabled/disabled. */ | |
1638 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
1639 | int enable) | |
1640 | { | |
1641 | u8 reg, mask; | |
1642 | ||
1643 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1644 | ||
1645 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1646 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1647 | else | |
1648 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1649 | ||
1650 | if (enable) | |
1651 | reg |= mask; | |
1652 | else | |
1653 | reg &= ~mask; | |
1654 | ||
1655 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1656 | } | |
1657 | ||
d6648da1 PU |
1658 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1659 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1660 | { |
1661 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1662 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1663 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1664 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 | 1665 | |
7220b9f4 | 1666 | if (twl4030->master_substream) { |
7220b9f4 | 1667 | twl4030->slave_substream = substream; |
6b87a91f PU |
1668 | /* The DAI has one configuration for playback and capture, so |
1669 | * if the DAI has been already configured then constrain this | |
1670 | * substream to match it. */ | |
1671 | if (twl4030->configured) | |
1672 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1673 | } else { | |
8a1f936a PU |
1674 | if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) & |
1675 | TWL4030_OPTION_1)) { | |
1676 | /* In option2 4 channel is not supported, set the | |
1677 | * constraint for the first stream for channels, the | |
1678 | * second stream will 'inherit' this cosntraint */ | |
1679 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1680 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1681 | 2, 2); | |
1682 | } | |
7220b9f4 | 1683 | twl4030->master_substream = substream; |
6b87a91f | 1684 | } |
7220b9f4 PU |
1685 | |
1686 | return 0; | |
1687 | } | |
1688 | ||
d6648da1 PU |
1689 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1690 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1691 | { |
1692 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1693 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1694 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1695 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 PU |
1696 | |
1697 | if (twl4030->master_substream == substream) | |
1698 | twl4030->master_substream = twl4030->slave_substream; | |
1699 | ||
1700 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1701 | |
1702 | /* If all streams are closed, or the remaining stream has not yet | |
1703 | * been configured than set the DAI as not configured. */ | |
1704 | if (!twl4030->master_substream) | |
1705 | twl4030->configured = 0; | |
1706 | else if (!twl4030->master_substream->runtime->channels) | |
1707 | twl4030->configured = 0; | |
8a1f936a PU |
1708 | |
1709 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1710 | if (substream->runtime->channels == 4) | |
1711 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1712 | } |
1713 | ||
cc17557e | 1714 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1715 | struct snd_pcm_hw_params *params, |
1716 | struct snd_soc_dai *dai) | |
cc17557e SS |
1717 | { |
1718 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1719 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1720 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1721 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1722 | u8 mode, old_mode, format, old_format; |
1723 | ||
8a1f936a PU |
1724 | /* If the substream has 4 channel, do the necessary setup */ |
1725 | if (params_channels(params) == 4) { | |
eaf1ac8b PU |
1726 | format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); |
1727 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
1728 | ||
1729 | /* Safety check: are we in the correct operating mode and | |
1730 | * the interface is in TDM mode? */ | |
1731 | if ((mode & TWL4030_OPTION_1) && | |
1732 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1733 | twl4030_tdm_enable(codec, substream->stream, 1); |
1734 | else | |
1735 | return -EINVAL; | |
1736 | } | |
1737 | ||
6b87a91f PU |
1738 | if (twl4030->configured) |
1739 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1740 | return 0; |
1741 | ||
cc17557e SS |
1742 | /* bit rate */ |
1743 | old_mode = twl4030_read_reg_cache(codec, | |
1744 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
1745 | mode = old_mode & ~TWL4030_APLL_RATE; | |
1746 | ||
1747 | switch (params_rate(params)) { | |
1748 | case 8000: | |
1749 | mode |= TWL4030_APLL_RATE_8000; | |
1750 | break; | |
1751 | case 11025: | |
1752 | mode |= TWL4030_APLL_RATE_11025; | |
1753 | break; | |
1754 | case 12000: | |
1755 | mode |= TWL4030_APLL_RATE_12000; | |
1756 | break; | |
1757 | case 16000: | |
1758 | mode |= TWL4030_APLL_RATE_16000; | |
1759 | break; | |
1760 | case 22050: | |
1761 | mode |= TWL4030_APLL_RATE_22050; | |
1762 | break; | |
1763 | case 24000: | |
1764 | mode |= TWL4030_APLL_RATE_24000; | |
1765 | break; | |
1766 | case 32000: | |
1767 | mode |= TWL4030_APLL_RATE_32000; | |
1768 | break; | |
1769 | case 44100: | |
1770 | mode |= TWL4030_APLL_RATE_44100; | |
1771 | break; | |
1772 | case 48000: | |
1773 | mode |= TWL4030_APLL_RATE_48000; | |
1774 | break; | |
103f211d PU |
1775 | case 96000: |
1776 | mode |= TWL4030_APLL_RATE_96000; | |
1777 | break; | |
cc17557e SS |
1778 | default: |
1779 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
1780 | params_rate(params)); | |
1781 | return -EINVAL; | |
1782 | } | |
1783 | ||
1784 | if (mode != old_mode) { | |
1785 | /* change rate and set CODECPDZ */ | |
7393958f | 1786 | twl4030_codec_enable(codec, 0); |
cc17557e | 1787 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
db04e2c5 | 1788 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1789 | } |
1790 | ||
1791 | /* sample size */ | |
1792 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1793 | format = old_format; | |
1794 | format &= ~TWL4030_DATA_WIDTH; | |
1795 | switch (params_format(params)) { | |
1796 | case SNDRV_PCM_FORMAT_S16_LE: | |
1797 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1798 | break; | |
1799 | case SNDRV_PCM_FORMAT_S24_LE: | |
1800 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
1801 | break; | |
1802 | default: | |
1803 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
1804 | params_format(params)); | |
1805 | return -EINVAL; | |
1806 | } | |
1807 | ||
1808 | if (format != old_format) { | |
1809 | ||
1810 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1811 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1812 | |
1813 | /* change format */ | |
1814 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1815 | ||
1816 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1817 | twl4030_codec_enable(codec, 1); |
cc17557e | 1818 | } |
6b87a91f PU |
1819 | |
1820 | /* Store the important parameters for the DAI configuration and set | |
1821 | * the DAI as configured */ | |
1822 | twl4030->configured = 1; | |
1823 | twl4030->rate = params_rate(params); | |
1824 | twl4030->sample_bits = hw_param_interval(params, | |
1825 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1826 | twl4030->channels = params_channels(params); | |
1827 | ||
1828 | /* If both playback and capture streams are open, and one of them | |
1829 | * is setting the hw parameters right now (since we are here), set | |
1830 | * constraints to the other stream to match the current one. */ | |
1831 | if (twl4030->slave_substream) | |
1832 | twl4030_constraints(twl4030, substream); | |
1833 | ||
cc17557e SS |
1834 | return 0; |
1835 | } | |
1836 | ||
1837 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1838 | int clk_id, unsigned int freq, int dir) | |
1839 | { | |
1840 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1841 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1842 | |
1843 | switch (freq) { | |
1844 | case 19200000: | |
cc17557e | 1845 | case 26000000: |
cc17557e | 1846 | case 38400000: |
cc17557e SS |
1847 | break; |
1848 | default: | |
68d01955 | 1849 | dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq); |
cc17557e SS |
1850 | return -EINVAL; |
1851 | } | |
1852 | ||
68d01955 PU |
1853 | if ((freq / 1000) != twl4030->sysclk) { |
1854 | dev_err(codec->dev, | |
1855 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
1856 | freq, twl4030->sysclk * 1000); | |
1857 | return -EINVAL; | |
1858 | } | |
cc17557e SS |
1859 | |
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1864 | unsigned int fmt) | |
1865 | { | |
1866 | struct snd_soc_codec *codec = codec_dai->codec; | |
1867 | u8 old_format, format; | |
1868 | ||
1869 | /* get format */ | |
1870 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1871 | format = old_format; | |
1872 | ||
1873 | /* set master/slave audio interface */ | |
1874 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1875 | case SND_SOC_DAIFMT_CBM_CFM: | |
1876 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1877 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1878 | break; |
1879 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1880 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1881 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1882 | break; |
1883 | default: | |
1884 | return -EINVAL; | |
1885 | } | |
1886 | ||
1887 | /* interface format */ | |
1888 | format &= ~TWL4030_AIF_FORMAT; | |
1889 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1890 | case SND_SOC_DAIFMT_I2S: | |
1891 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1892 | break; | |
8a1f936a PU |
1893 | case SND_SOC_DAIFMT_DSP_A: |
1894 | format |= TWL4030_AIF_FORMAT_TDM; | |
1895 | break; | |
cc17557e SS |
1896 | default: |
1897 | return -EINVAL; | |
1898 | } | |
1899 | ||
1900 | if (format != old_format) { | |
1901 | ||
1902 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1903 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1904 | |
1905 | /* change format */ | |
1906 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1907 | ||
1908 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1909 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1910 | } |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
68140443 LCM |
1915 | static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) |
1916 | { | |
1917 | struct snd_soc_codec *codec = dai->codec; | |
1918 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1919 | ||
1920 | if (tristate) | |
1921 | reg |= TWL4030_AIF_TRI_EN; | |
1922 | else | |
1923 | reg &= ~TWL4030_AIF_TRI_EN; | |
1924 | ||
1925 | return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); | |
1926 | } | |
1927 | ||
b7a755a8 MLC |
1928 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1929 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1930 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
1931 | int enable) | |
1932 | { | |
1933 | u8 reg, mask; | |
1934 | ||
1935 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1936 | ||
1937 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1938 | mask = TWL4030_ARXL1_VRX_EN; | |
1939 | else | |
1940 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1941 | ||
1942 | if (enable) | |
1943 | reg |= mask; | |
1944 | else | |
1945 | reg &= ~mask; | |
1946 | ||
1947 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1948 | } | |
1949 | ||
7154b3e8 JS |
1950 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
1951 | struct snd_soc_dai *dai) | |
1952 | { | |
1953 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1954 | struct snd_soc_device *socdev = rtd->socdev; | |
1955 | struct snd_soc_codec *codec = socdev->card->codec; | |
b2c812e2 | 1956 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
1957 | u8 mode; |
1958 | ||
1959 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
1960 | * not avilable. | |
1961 | */ | |
68d01955 PU |
1962 | if (twl4030->sysclk != 26000) { |
1963 | dev_err(codec->dev, "The board is configured for %u Hz, while" | |
1964 | "the Voice interface needs 26MHz APLL mclk\n", | |
1965 | twl4030->sysclk * 1000); | |
7154b3e8 JS |
1966 | return -EINVAL; |
1967 | } | |
1968 | ||
1969 | /* If the codec mode is not option2, the voice PCM interface is not | |
1970 | * avilable. | |
1971 | */ | |
1972 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1973 | & TWL4030_OPT_MODE; | |
1974 | ||
1975 | if (mode != TWL4030_OPTION_2) { | |
1976 | printk(KERN_ERR "TWL4030 voice startup: " | |
1977 | "the codec mode is not option2\n"); | |
1978 | return -EINVAL; | |
1979 | } | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
b7a755a8 MLC |
1984 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
1985 | struct snd_soc_dai *dai) | |
1986 | { | |
1987 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1988 | struct snd_soc_device *socdev = rtd->socdev; | |
1989 | struct snd_soc_codec *codec = socdev->card->codec; | |
1990 | ||
1991 | /* Enable voice digital filters */ | |
1992 | twl4030_voice_enable(codec, substream->stream, 0); | |
1993 | } | |
1994 | ||
7154b3e8 JS |
1995 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
1996 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1997 | { | |
1998 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1999 | struct snd_soc_device *socdev = rtd->socdev; | |
2000 | struct snd_soc_codec *codec = socdev->card->codec; | |
2001 | u8 old_mode, mode; | |
2002 | ||
b7a755a8 MLC |
2003 | /* Enable voice digital filters */ |
2004 | twl4030_voice_enable(codec, substream->stream, 1); | |
2005 | ||
7154b3e8 JS |
2006 | /* bit rate */ |
2007 | old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
2008 | & ~(TWL4030_CODECPDZ); | |
2009 | mode = old_mode; | |
2010 | ||
2011 | switch (params_rate(params)) { | |
2012 | case 8000: | |
2013 | mode &= ~(TWL4030_SEL_16K); | |
2014 | break; | |
2015 | case 16000: | |
2016 | mode |= TWL4030_SEL_16K; | |
2017 | break; | |
2018 | default: | |
2019 | printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n", | |
2020 | params_rate(params)); | |
2021 | return -EINVAL; | |
2022 | } | |
2023 | ||
2024 | if (mode != old_mode) { | |
2025 | /* change rate and set CODECPDZ */ | |
2026 | twl4030_codec_enable(codec, 0); | |
2027 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
2028 | twl4030_codec_enable(codec, 1); | |
2029 | } | |
2030 | ||
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
2035 | int clk_id, unsigned int freq, int dir) | |
2036 | { | |
2037 | struct snd_soc_codec *codec = codec_dai->codec; | |
d4a8ca24 | 2038 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 | 2039 | |
68d01955 PU |
2040 | if (freq != 26000000) { |
2041 | dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice" | |
2042 | "interface needs 26MHz APLL mclk\n", freq); | |
2043 | return -EINVAL; | |
2044 | } | |
2045 | if ((freq / 1000) != twl4030->sysclk) { | |
2046 | dev_err(codec->dev, | |
2047 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
2048 | freq, twl4030->sysclk * 1000); | |
7154b3e8 JS |
2049 | return -EINVAL; |
2050 | } | |
7154b3e8 JS |
2051 | return 0; |
2052 | } | |
2053 | ||
2054 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
2055 | unsigned int fmt) | |
2056 | { | |
2057 | struct snd_soc_codec *codec = codec_dai->codec; | |
2058 | u8 old_format, format; | |
2059 | ||
2060 | /* get format */ | |
2061 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
2062 | format = old_format; | |
2063 | ||
2064 | /* set master/slave audio interface */ | |
2065 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 2066 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
2067 | format &= ~(TWL4030_VIF_SLAVE_EN); |
2068 | break; | |
2069 | case SND_SOC_DAIFMT_CBS_CFS: | |
2070 | format |= TWL4030_VIF_SLAVE_EN; | |
2071 | break; | |
2072 | default: | |
2073 | return -EINVAL; | |
2074 | } | |
2075 | ||
2076 | /* clock inversion */ | |
2077 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2078 | case SND_SOC_DAIFMT_IB_NF: | |
2079 | format &= ~(TWL4030_VIF_FORMAT); | |
2080 | break; | |
2081 | case SND_SOC_DAIFMT_NB_IF: | |
2082 | format |= TWL4030_VIF_FORMAT; | |
2083 | break; | |
2084 | default: | |
2085 | return -EINVAL; | |
2086 | } | |
2087 | ||
2088 | if (format != old_format) { | |
2089 | /* change format and set CODECPDZ */ | |
2090 | twl4030_codec_enable(codec, 0); | |
2091 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2092 | twl4030_codec_enable(codec, 1); | |
2093 | } | |
2094 | ||
2095 | return 0; | |
2096 | } | |
2097 | ||
68140443 LCM |
2098 | static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) |
2099 | { | |
2100 | struct snd_soc_codec *codec = dai->codec; | |
2101 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
2102 | ||
2103 | if (tristate) | |
2104 | reg |= TWL4030_VIF_TRI_EN; | |
2105 | else | |
2106 | reg &= ~TWL4030_VIF_TRI_EN; | |
2107 | ||
2108 | return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); | |
2109 | } | |
2110 | ||
bbba9444 | 2111 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
2112 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
2113 | ||
10d9e3d9 | 2114 | static struct snd_soc_dai_ops twl4030_dai_ops = { |
7220b9f4 PU |
2115 | .startup = twl4030_startup, |
2116 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
2117 | .hw_params = twl4030_hw_params, |
2118 | .set_sysclk = twl4030_set_dai_sysclk, | |
2119 | .set_fmt = twl4030_set_dai_fmt, | |
68140443 | 2120 | .set_tristate = twl4030_set_tristate, |
10d9e3d9 JS |
2121 | }; |
2122 | ||
7154b3e8 JS |
2123 | static struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
2124 | .startup = twl4030_voice_startup, | |
b7a755a8 | 2125 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
2126 | .hw_params = twl4030_voice_hw_params, |
2127 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
2128 | .set_fmt = twl4030_voice_set_dai_fmt, | |
68140443 | 2129 | .set_tristate = twl4030_voice_set_tristate, |
7154b3e8 JS |
2130 | }; |
2131 | ||
2132 | struct snd_soc_dai twl4030_dai[] = { | |
2133 | { | |
cc17557e SS |
2134 | .name = "twl4030", |
2135 | .playback = { | |
b4852b79 | 2136 | .stream_name = "HiFi Playback", |
cc17557e | 2137 | .channels_min = 2, |
8a1f936a | 2138 | .channels_max = 4, |
31ad0f31 | 2139 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
cc17557e SS |
2140 | .formats = TWL4030_FORMATS,}, |
2141 | .capture = { | |
2142 | .stream_name = "Capture", | |
2143 | .channels_min = 2, | |
8a1f936a | 2144 | .channels_max = 4, |
cc17557e SS |
2145 | .rates = TWL4030_RATES, |
2146 | .formats = TWL4030_FORMATS,}, | |
10d9e3d9 | 2147 | .ops = &twl4030_dai_ops, |
7154b3e8 JS |
2148 | }, |
2149 | { | |
2150 | .name = "twl4030 Voice", | |
2151 | .playback = { | |
b4852b79 | 2152 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2153 | .channels_min = 1, |
2154 | .channels_max = 1, | |
2155 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2156 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2157 | .capture = { | |
2158 | .stream_name = "Capture", | |
2159 | .channels_min = 1, | |
2160 | .channels_max = 2, | |
2161 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2162 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2163 | .ops = &twl4030_dai_voice_ops, | |
2164 | }, | |
cc17557e SS |
2165 | }; |
2166 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
2167 | ||
7a1fecf5 | 2168 | static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state) |
cc17557e SS |
2169 | { |
2170 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2171 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2172 | |
2173 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2174 | ||
2175 | return 0; | |
2176 | } | |
2177 | ||
7a1fecf5 | 2178 | static int twl4030_soc_resume(struct platform_device *pdev) |
cc17557e SS |
2179 | { |
2180 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2181 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2182 | |
2183 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
cc17557e SS |
2184 | return 0; |
2185 | } | |
2186 | ||
7a1fecf5 | 2187 | static struct snd_soc_codec *twl4030_codec; |
cc17557e | 2188 | |
7a1fecf5 | 2189 | static int twl4030_soc_probe(struct platform_device *pdev) |
cc17557e | 2190 | { |
7a1fecf5 | 2191 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
9da28c7b | 2192 | struct twl4030_setup_data *setup = socdev->codec_data; |
7a1fecf5 PU |
2193 | struct snd_soc_codec *codec; |
2194 | struct twl4030_priv *twl4030; | |
2195 | int ret; | |
cc17557e | 2196 | |
7a1fecf5 | 2197 | BUG_ON(!twl4030_codec); |
cc17557e | 2198 | |
7a1fecf5 | 2199 | codec = twl4030_codec; |
b2c812e2 | 2200 | twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 2201 | socdev->card->codec = codec; |
cc17557e | 2202 | |
9da28c7b PU |
2203 | /* Configuration for headset ramp delay from setup data */ |
2204 | if (setup) { | |
2205 | unsigned char hs_pop; | |
2206 | ||
68d01955 PU |
2207 | if (setup->sysclk != twl4030->sysclk) |
2208 | dev_warn(&pdev->dev, | |
2209 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
2210 | setup->sysclk, twl4030->sysclk); | |
9da28c7b PU |
2211 | |
2212 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
2213 | hs_pop &= ~TWL4030_RAMP_DELAY; | |
2214 | hs_pop |= (setup->ramp_delay_value << 2); | |
2215 | twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
9da28c7b PU |
2216 | } |
2217 | ||
cc17557e SS |
2218 | /* register pcms */ |
2219 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
2220 | if (ret < 0) { | |
7a1fecf5 PU |
2221 | dev_err(&pdev->dev, "failed to create pcms\n"); |
2222 | return ret; | |
cc17557e SS |
2223 | } |
2224 | ||
3e8e1952 IM |
2225 | snd_soc_add_controls(codec, twl4030_snd_controls, |
2226 | ARRAY_SIZE(twl4030_snd_controls)); | |
cc17557e SS |
2227 | twl4030_add_widgets(codec); |
2228 | ||
7a1fecf5 | 2229 | return 0; |
cc17557e SS |
2230 | } |
2231 | ||
7a1fecf5 | 2232 | static int twl4030_soc_remove(struct platform_device *pdev) |
cc17557e SS |
2233 | { |
2234 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
7a1fecf5 PU |
2235 | struct snd_soc_codec *codec = socdev->card->codec; |
2236 | ||
2237 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2238 | snd_soc_free_pcms(socdev); | |
2239 | snd_soc_dapm_free(socdev); | |
7a1fecf5 PU |
2240 | |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | static int __devinit twl4030_codec_probe(struct platform_device *pdev) | |
2245 | { | |
2246 | struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data; | |
cc17557e | 2247 | struct snd_soc_codec *codec; |
7393958f | 2248 | struct twl4030_priv *twl4030; |
7a1fecf5 | 2249 | int ret; |
cc17557e | 2250 | |
68d01955 PU |
2251 | if (!pdata) { |
2252 | dev_err(&pdev->dev, "platform_data is missing\n"); | |
7a1fecf5 PU |
2253 | return -EINVAL; |
2254 | } | |
cc17557e | 2255 | |
7393958f PU |
2256 | twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); |
2257 | if (twl4030 == NULL) { | |
7a1fecf5 | 2258 | dev_err(&pdev->dev, "Can not allocate memroy\n"); |
7393958f PU |
2259 | return -ENOMEM; |
2260 | } | |
2261 | ||
7a1fecf5 | 2262 | codec = &twl4030->codec; |
b2c812e2 | 2263 | snd_soc_codec_set_drvdata(codec, twl4030); |
7a1fecf5 PU |
2264 | codec->dev = &pdev->dev; |
2265 | twl4030_dai[0].dev = &pdev->dev; | |
2266 | twl4030_dai[1].dev = &pdev->dev; | |
2267 | ||
cc17557e SS |
2268 | mutex_init(&codec->mutex); |
2269 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
2270 | INIT_LIST_HEAD(&codec->dapm_paths); | |
2271 | ||
7a1fecf5 PU |
2272 | codec->name = "twl4030"; |
2273 | codec->owner = THIS_MODULE; | |
2274 | codec->read = twl4030_read_reg_cache; | |
2275 | codec->write = twl4030_write; | |
2276 | codec->set_bias_level = twl4030_set_bias_level; | |
2277 | codec->dai = twl4030_dai; | |
fd63df22 | 2278 | codec->num_dai = ARRAY_SIZE(twl4030_dai); |
7a1fecf5 PU |
2279 | codec->reg_cache_size = sizeof(twl4030_reg); |
2280 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
2281 | GFP_KERNEL); | |
2282 | if (codec->reg_cache == NULL) { | |
2283 | ret = -ENOMEM; | |
2284 | goto error_cache; | |
2285 | } | |
2286 | ||
2287 | platform_set_drvdata(pdev, twl4030); | |
2288 | twl4030_codec = codec; | |
2289 | ||
2290 | /* Set the defaults, and power up the codec */ | |
68d01955 | 2291 | twl4030->sysclk = twl4030_codec_get_mclk() / 1000; |
7a1fecf5 | 2292 | twl4030_init_chip(codec); |
b3f5a272 | 2293 | codec->bias_level = SND_SOC_BIAS_OFF; |
7a1fecf5 PU |
2294 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2295 | ||
2296 | ret = snd_soc_register_codec(codec); | |
2297 | if (ret != 0) { | |
2298 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
2299 | goto error_codec; | |
2300 | } | |
2301 | ||
2302 | ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); | |
2303 | if (ret != 0) { | |
2304 | dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); | |
2305 | snd_soc_unregister_codec(codec); | |
2306 | goto error_codec; | |
2307 | } | |
cc17557e SS |
2308 | |
2309 | return 0; | |
7a1fecf5 PU |
2310 | |
2311 | error_codec: | |
2312 | twl4030_power_down(codec); | |
2313 | kfree(codec->reg_cache); | |
2314 | error_cache: | |
2315 | kfree(twl4030); | |
2316 | return ret; | |
cc17557e SS |
2317 | } |
2318 | ||
7a1fecf5 | 2319 | static int __devexit twl4030_codec_remove(struct platform_device *pdev) |
cc17557e | 2320 | { |
7a1fecf5 | 2321 | struct twl4030_priv *twl4030 = platform_get_drvdata(pdev); |
cc17557e | 2322 | |
cb67286d PU |
2323 | snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); |
2324 | snd_soc_unregister_codec(&twl4030->codec); | |
2325 | kfree(twl4030->codec.reg_cache); | |
7a1fecf5 | 2326 | kfree(twl4030); |
cc17557e | 2327 | |
7a1fecf5 | 2328 | twl4030_codec = NULL; |
cc17557e SS |
2329 | return 0; |
2330 | } | |
2331 | ||
7a1fecf5 PU |
2332 | MODULE_ALIAS("platform:twl4030_codec_audio"); |
2333 | ||
2334 | static struct platform_driver twl4030_codec_driver = { | |
2335 | .probe = twl4030_codec_probe, | |
2336 | .remove = __devexit_p(twl4030_codec_remove), | |
2337 | .driver = { | |
2338 | .name = "twl4030_codec_audio", | |
2339 | .owner = THIS_MODULE, | |
2340 | }, | |
cc17557e | 2341 | }; |
cc17557e | 2342 | |
24e07db8 | 2343 | static int __init twl4030_modinit(void) |
64089b84 | 2344 | { |
7a1fecf5 | 2345 | return platform_driver_register(&twl4030_codec_driver); |
64089b84 | 2346 | } |
24e07db8 | 2347 | module_init(twl4030_modinit); |
64089b84 MB |
2348 | |
2349 | static void __exit twl4030_exit(void) | |
2350 | { | |
7a1fecf5 | 2351 | platform_driver_unregister(&twl4030_codec_driver); |
64089b84 MB |
2352 | } |
2353 | module_exit(twl4030_exit); | |
2354 | ||
7a1fecf5 PU |
2355 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { |
2356 | .probe = twl4030_soc_probe, | |
2357 | .remove = twl4030_soc_remove, | |
2358 | .suspend = twl4030_soc_suspend, | |
2359 | .resume = twl4030_soc_resume, | |
2360 | }; | |
2361 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
2362 | ||
cc17557e SS |
2363 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2364 | MODULE_AUTHOR("Steve Sakoman"); | |
2365 | MODULE_LICENSE("GPL"); |