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Input: twl4030-vibra: Support for DT booted kernel
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
cc17557e 35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e 37
f0fba2ad 38/* Register descriptions are here */
57fe7251 39#include <linux/mfd/twl4030-audio.h>
f0fba2ad
LG		 40
41/* Shadow register used by the audio driver */
42#define TWL4030_REG_SW_SHADOW 0x4A
43#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
44
45/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
46#define TWL4030_HFL_EN 0x01
47#define TWL4030_HFR_EN 0x02
cc17557e
SS		 48
49/*
50 * twl4030 register cache & default register settings
51 */
52static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
53 0x00, /* this register not used */
33f92ed4 54 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 55 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 56 0x00, /* REG_UNKNOWN (0x3) */
57 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 58 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 59 0x00, /* REG_ANAMICR (0x6) */
60 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 61 0x00, /* REG_ADCMICSEL (0x8) */
62 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 63 0x0f, /* REG_ATXL1PGA (0xA) */
64 0x0f, /* REG_ATXR1PGA (0xB) */
65 0x0f, /* REG_AVTXL2PGA (0xC) */
66 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 67 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 68 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 69 0x3f, /* REG_ARXR1PGA (0x10) */
70 0x3f, /* REG_ARXL1PGA (0x11) */
71 0x3f, /* REG_ARXR2PGA (0x12) */
72 0x3f, /* REG_ARXL2PGA (0x13) */
73 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 74 0x00, /* REG_VSTPGA (0x15) */
75 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 76 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 77 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 78 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
79 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
80 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
81 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 82 0x00, /* REG_ATX2ARXPGA (0x1D) */
83 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 84 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 85 0x00, /* REG_BTSTPGA (0x20) */
86 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 87 0x00, /* REG_HS_SEL (0x22) */
88 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 89 0x00, /* REG_HS_POPN_SET (0x24) */
90 0x00, /* REG_PREDL_CTL (0x25) */
91 0x00, /* REG_PREDR_CTL (0x26) */
92 0x00, /* REG_PRECKL_CTL (0x27) */
93 0x00, /* REG_PRECKR_CTL (0x28) */
94 0x00, /* REG_HFL_CTL (0x29) */
95 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 96 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 97 0x00, /* REG_ALC_SET1 (0x2C) */
98 0x00, /* REG_ALC_SET2 (0x2D) */
99 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 100 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 101 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 102 0x00, /* REG_DTMF_TONEXT1H (0x31) */
103 0x00, /* REG_DTMF_TONEXT1L (0x32) */
104 0x00, /* REG_DTMF_TONEXT2H (0x33) */
105 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 106 0x79, /* REG_DTMF_TONOFF (0x35) */
107 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 108 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
109 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
110 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 111 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 112 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 113 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
114 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 115 0x00, /* REG_MISC_SET_1 (0x3E) */
116 0x00, /* REG_PCMBTMUX (0x3F) */
117 0x00, /* not used (0x40) */
118 0x00, /* not used (0x41) */
119 0x00, /* not used (0x42) */
120 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 121 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 122 0x00, /* REG_VIBRA_CTL (0x45) */
123 0x00, /* REG_VIBRA_SET (0x46) */
124 0x00, /* REG_VIBRA_PWM_SET (0x47) */
125 0x00, /* REG_ANAMIC_GAIN (0x48) */
126 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 127 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 128};
129
7393958f
PU		 130/* codec private data */
131struct twl4030_priv {
7a1fecf5
PU		 132 struct snd_soc_codec codec;
133
7393958f 134 unsigned int codec_powered;
7b4c734e
PU		 135
136 /* reference counts of AIF/APLL users */
2845fa13 137 unsigned int apll_enabled;
7220b9f4
PU		 138
139 struct snd_pcm_substream *master_substream;
140 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 141
142 unsigned int configured;
143 unsigned int rate;
144 unsigned int sample_bits;
145 unsigned int channels;
6943c92e
PU		 146
147 unsigned int sysclk;
148
c96907f2
PU		 149 /* Output (with associated amp) states */
150 u8 hsl_enabled, hsr_enabled;
151 u8 earpiece_enabled;
152 u8 predrivel_enabled, predriver_enabled;
153 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2
PU		 154
155 /* Delay needed after enabling the digimic interface */
156 unsigned int digimic_delay;
7393958f
PU		 157};
158
cc17557e
SS		 159/*
160 * read twl4030 register cache
161 */
162static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
163 unsigned int reg)
164{
d08664fd 165 u8 *cache = codec->reg_cache;
cc17557e 166
91432e97
IM		 167 if (reg >= TWL4030_CACHEREGNUM)
168 return -EIO;
169
cc17557e
SS		 170 return cache[reg];
171}
172
173/*
174 * write twl4030 register cache
175 */
176static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
177 u8 reg, u8 value)
178{
179 u8 *cache = codec->reg_cache;
180
181 if (reg >= TWL4030_CACHEREGNUM)
182 return;
183 cache[reg] = value;
184}
185
186/*
187 * write to the twl4030 register space
188 */
189static int twl4030_write(struct snd_soc_codec *codec,
190 unsigned int reg, unsigned int value)
191{
b2c812e2 192 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 193 int write_to_reg = 0;
194
cc17557e 195 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 196 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
197 /* Decide if the given register can be written */
198 switch (reg) {
199 case TWL4030_REG_EAR_CTL:
200 if (twl4030->earpiece_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PREDL_CTL:
204 if (twl4030->predrivel_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_PREDR_CTL:
208 if (twl4030->predriver_enabled)
209 write_to_reg = 1;
210 break;
211 case TWL4030_REG_PRECKL_CTL:
212 if (twl4030->carkitl_enabled)
213 write_to_reg = 1;
214 break;
215 case TWL4030_REG_PRECKR_CTL:
216 if (twl4030->carkitr_enabled)
217 write_to_reg = 1;
218 break;
219 case TWL4030_REG_HS_GAIN_SET:
220 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
221 write_to_reg = 1;
222 break;
223 default:
224 /* All other register can be written */
225 write_to_reg = 1;
226 break;
227 }
228 if (write_to_reg)
229 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
230 value, reg);
231 }
232 return 0;
cc17557e
SS		 233}
234
7e6120c5
PU		 235static inline void twl4030_wait_ms(int time)
236{
237 if (time < 60) {
238 time *= 1000;
239 usleep_range(time, time + 500);
240 } else {
241 msleep(time);
242 }
243}
244
db04e2c5 245static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 246{
b2c812e2 247 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 248 int mode;
cc17557e 249
7393958f
PU		 250 if (enable == twl4030->codec_powered)
251 return;
252
db04e2c5 253 if (enable)
57fe7251 254 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 255 else
57fe7251 256 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 257
7a1fecf5
PU		 258 if (mode >= 0) {
259 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
260 twl4030->codec_powered = enable;
261 }
cc17557e
SS		 262
263 /* REVISIT: this delay is present in TI sample drivers */
264 /* but there seems to be no TRM requirement for it */
265 udelay(10);
266}
267
9fdcc0f7 268static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 269{
9fdcc0f7
PU		 270 int i, difference = 0;
271 u8 val;
272
273 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
274 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
275 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
276 if (val != twl4030_reg[i]) {
277 difference++;
278 dev_dbg(codec->dev,
279 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
280 i, val, twl4030_reg[i]);
281 }
282 }
25985edc 283 dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
9fdcc0f7
PU		 284 difference, difference ? "Not OK" : "OK");
285}
cc17557e 286
a3a29b55
PU		 287static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
288{
289 int i;
cc17557e
SS		 290
291 /* set all audio section registers to reasonable defaults */
292 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 293 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 294 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 295
296}
297
f0fba2ad 298static void twl4030_init_chip(struct snd_soc_codec *codec)
7393958f 299{
4ae6df5e 300 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
b2c812e2 301 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 302 u8 reg, byte;
303 int i = 0;
7393958f 304
9fdcc0f7 305 /* Check defaults, if instructed before anything else */
f0fba2ad 306 if (pdata && pdata->check_defaults)
9fdcc0f7 307 twl4030_check_defaults(codec);
7a1fecf5 308
a3a29b55 309 /* Reset registers, if no setup data or if instructed to do so */
f0fba2ad 310 if (!pdata || (pdata && pdata->reset_registers))
a3a29b55 311 twl4030_reset_registers(codec);
7393958f 312
ee4ccac7 313 /* Refresh APLL_CTL register from HW */
9fdcc0f7 314 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 315 TWL4030_REG_APLL_CTL);
316 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 317
ee4ccac7
PU		 318 /* anti-pop when changing analog gain */
319 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
320 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
321 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 322
ee4ccac7
PU		 323 twl4030_write(codec, TWL4030_REG_OPTION,
324 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
325 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 326
3c36cc68
PU		 327 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
328 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
329
ee4ccac7 330 /* Machine dependent setup */
f0fba2ad 331 if (!pdata)
7393958f
PU		 332 return;
333
f0fba2ad 334 twl4030->digimic_delay = pdata->digimic_delay;
ee4ccac7
PU		 335
336 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
337 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 338 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 339 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 340
341 /* initiate offset cancellation */
ee4ccac7
PU		 342 twl4030_codec_enable(codec, 1);
343
344 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
345 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 346 reg |= pdata->offset_cncl_path;
006f367e 347 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 348 reg | TWL4030_CNCL_OFFSET_START);
006f367e 349
7e6120c5
PU		 350 /*
351 * Wait for offset cancellation to complete.
352 * Since this takes a while, do not slam the i2c.
353 * Start polling the status after ~20ms.
354 */
355 msleep(20);
006f367e 356 do {
7e6120c5 357 usleep_range(1000, 2000);
fc7b92fc 358 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 359 TWL4030_REG_ANAMICL);
360 } while ((i++ < 100) &&
361 ((byte & TWL4030_CNCL_OFFSET_START) ==
362 TWL4030_CNCL_OFFSET_START));
363
364 /* Make sure that the reg_cache has the same value as the HW */
365 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
366
006f367e 367 twl4030_codec_enable(codec, 0);
006f367e
PU		 368}
369
ee4ccac7 370static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 371{
ee4ccac7
PU		 372 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
373 int status = -1;
374
375 if (enable) {
376 twl4030->apll_enabled++;
377 if (twl4030->apll_enabled == 1)
57fe7251
PU		 378 status = twl4030_audio_enable_resource(
379 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 380 } else {
381 twl4030->apll_enabled--;
382 if (!twl4030->apll_enabled)
57fe7251
PU		 383 status = twl4030_audio_disable_resource(
384 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 385 }
386
387 if (status >= 0)
388 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 389}
390
5e98a464 391/* Earpiece */
1a787e7a
JS		 392static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
393 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
394 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
395 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
396 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
397};
5e98a464 398
2a6f5c58 399/* PreDrive Left */
1a787e7a
JS		 400static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
401 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
402 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
403 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
404 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
405};
2a6f5c58
PU		 406
407/* PreDrive Right */
1a787e7a
JS		 408static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
409 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
410 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
411 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
412 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
413};
2a6f5c58 414
dfad21a2 415/* Headset Left */
1a787e7a
JS		 416static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
417 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
418 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
419 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
420};
dfad21a2
PU		 421
422/* Headset Right */
1a787e7a
JS		 423static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
424 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
425 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
426 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
427};
dfad21a2 428
5152d8c2 429/* Carkit Left */
1a787e7a
JS		 430static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
431 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
432 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
433 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
434};
5152d8c2
PU		 435
436/* Carkit Right */
1a787e7a
JS		 437static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
438 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
439 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
440 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
441};
5152d8c2 442
df339804
PU		 443/* Handsfree Left */
444static const char *twl4030_handsfreel_texts[] =
1a787e7a 445 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 446
447static const struct soc_enum twl4030_handsfreel_enum =
448 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
449 ARRAY_SIZE(twl4030_handsfreel_texts),
450 twl4030_handsfreel_texts);
451
452static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
453SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
454
0f89bdca
PU		 455/* Handsfree Left virtual mute */
456static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
457 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
458
df339804
PU		 459/* Handsfree Right */
460static const char *twl4030_handsfreer_texts[] =
1a787e7a 461 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 462
463static const struct soc_enum twl4030_handsfreer_enum =
464 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
465 ARRAY_SIZE(twl4030_handsfreer_texts),
466 twl4030_handsfreer_texts);
467
468static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
469SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
470
0f89bdca
PU		 471/* Handsfree Right virtual mute */
472static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
473 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
474
376f7839
PU		 475/* Vibra */
476/* Vibra audio path selection */
477static const char *twl4030_vibra_texts[] =
478 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
479
480static const struct soc_enum twl4030_vibra_enum =
481 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
482 ARRAY_SIZE(twl4030_vibra_texts),
483 twl4030_vibra_texts);
484
485static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
486SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
487
488/* Vibra path selection: local vibrator (PWM) or audio driven */
489static const char *twl4030_vibrapath_texts[] =
490 {"Local vibrator", "Audio"};
491
492static const struct soc_enum twl4030_vibrapath_enum =
493 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
494 ARRAY_SIZE(twl4030_vibrapath_texts),
495 twl4030_vibrapath_texts);
496
497static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
498SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
499
276c6222 500/* Left analog microphone selection */
97b8096d 501static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 502 SOC_DAPM_SINGLE("Main Mic Capture Switch",
503 TWL4030_REG_ANAMICL, 0, 1, 0),
504 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
505 TWL4030_REG_ANAMICL, 1, 1, 0),
506 SOC_DAPM_SINGLE("AUXL Capture Switch",
507 TWL4030_REG_ANAMICL, 2, 1, 0),
508 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
509 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 510};
276c6222
PU		 511
512/* Right analog microphone selection */
97b8096d 513static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 514 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
515 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 516};
276c6222
PU		 517
518/* TX1 L/R Analog/Digital microphone selection */
519static const char *twl4030_micpathtx1_texts[] =
520 {"Analog", "Digimic0"};
521
522static const struct soc_enum twl4030_micpathtx1_enum =
523 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
524 ARRAY_SIZE(twl4030_micpathtx1_texts),
525 twl4030_micpathtx1_texts);
526
527static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
528SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
529
530/* TX2 L/R Analog/Digital microphone selection */
531static const char *twl4030_micpathtx2_texts[] =
532 {"Analog", "Digimic1"};
533
534static const struct soc_enum twl4030_micpathtx2_enum =
535 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
536 ARRAY_SIZE(twl4030_micpathtx2_texts),
537 twl4030_micpathtx2_texts);
538
539static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
540SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
541
7393958f
PU		 542/* Analog bypass for AudioR1 */
543static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
544 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
545
546/* Analog bypass for AudioL1 */
547static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
548 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
549
550/* Analog bypass for AudioR2 */
551static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
552 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
553
554/* Analog bypass for AudioL2 */
555static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
556 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
557
fcd274a3
LCM		 558/* Analog bypass for Voice */
559static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
560 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
561
8b0d3153 562/* Digital bypass gain, mute instead of -30dB */
6bab83fd 563static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 564 TLV_DB_RANGE_HEAD(3),
565 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
566 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 567 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
568};
569
570/* Digital bypass left (TX1L -> RX2L) */
571static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
572 SOC_DAPM_SINGLE_TLV("Volume",
573 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
574 twl4030_dapm_dbypass_tlv);
575
576/* Digital bypass right (TX1R -> RX2R) */
577static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
578 SOC_DAPM_SINGLE_TLV("Volume",
579 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
580 twl4030_dapm_dbypass_tlv);
581
ee8f6894
LCM		 582/*
583 * Voice Sidetone GAIN volume control:
584 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
585 */
586static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
587
588/* Digital bypass voice: sidetone (VUL -> VDL)*/
589static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
590 SOC_DAPM_SINGLE_TLV("Volume",
591 TWL4030_REG_VSTPGA, 0, 0x29, 0,
592 twl4030_dapm_dbypassv_tlv);
593
9008adf9
PU		 594/*
595 * Output PGA builder:
596 * Handle the muting and unmuting of the given output (turning off the
597 * amplifier associated with the output pin)
c96907f2
PU		 598 * On mute bypass the reg_cache and write 0 to the register
599 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 600 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
601 */
602#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
603static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
604 struct snd_kcontrol *kcontrol, int event) \
605{ \
b2c812e2 606 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 607 \
608 switch (event) { \
609 case SND_SOC_DAPM_POST_PMU: \
c96907f2 610 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 611 twl4030_write(w->codec, reg, \
612 twl4030_read_reg_cache(w->codec, reg)); \
613 break; \
614 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 615 twl4030->pin_name##_enabled = 0; \
616 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
617 0, reg); \
9008adf9
PU		 618 break; \
619 } \
620 return 0; \
621}
622
623TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
624TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
625TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
626TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
627TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
628
5a2e9a48 629static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 630{
49d92c7d
SM		 631 unsigned char hs_ctl;
632
5a2e9a48 633 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 634
5a2e9a48
PU		 635 if (ramp) {
636 /* HF ramp-up */
637 hs_ctl |= TWL4030_HF_CTL_REF_EN;
638 twl4030_write(codec, reg, hs_ctl);
639 udelay(10);
49d92c7d 640 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 641 twl4030_write(codec, reg, hs_ctl);
642 udelay(40);
49d92c7d 643 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 644 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 645 twl4030_write(codec, reg, hs_ctl);
49d92c7d 646 } else {
5a2e9a48
PU		 647 /* HF ramp-down */
648 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
649 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
650 twl4030_write(codec, reg, hs_ctl);
651 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
652 twl4030_write(codec, reg, hs_ctl);
653 udelay(40);
654 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
655 twl4030_write(codec, reg, hs_ctl);
49d92c7d 656 }
5a2e9a48 657}
49d92c7d 658
5a2e9a48
PU		 659static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
660 struct snd_kcontrol *kcontrol, int event)
661{
662 switch (event) {
663 case SND_SOC_DAPM_POST_PMU:
664 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
665 break;
666 case SND_SOC_DAPM_POST_PMD:
667 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
668 break;
669 }
670 return 0;
671}
672
673static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
674 struct snd_kcontrol *kcontrol, int event)
675{
676 switch (event) {
677 case SND_SOC_DAPM_POST_PMU:
678 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
679 break;
680 case SND_SOC_DAPM_POST_PMD:
681 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
682 break;
683 }
49d92c7d
SM		 684 return 0;
685}
686
86139a13
JV		 687static int vibramux_event(struct snd_soc_dapm_widget *w,
688 struct snd_kcontrol *kcontrol, int event)
689{
690 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
691 return 0;
692}
693
7729cf74
PU		 694static int apll_event(struct snd_soc_dapm_widget *w,
695 struct snd_kcontrol *kcontrol, int event)
696{
697 switch (event) {
698 case SND_SOC_DAPM_PRE_PMU:
699 twl4030_apll_enable(w->codec, 1);
700 break;
701 case SND_SOC_DAPM_POST_PMD:
702 twl4030_apll_enable(w->codec, 0);
703 break;
704 }
705 return 0;
706}
707
7b4c734e
PU		 708static int aif_event(struct snd_soc_dapm_widget *w,
709 struct snd_kcontrol *kcontrol, int event)
710{
711 u8 audio_if;
712
713 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
714 switch (event) {
715 case SND_SOC_DAPM_PRE_PMU:
716 /* Enable AIF */
717 /* enable the PLL before we use it to clock the DAI */
718 twl4030_apll_enable(w->codec, 1);
719
720 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
721 audio_if | TWL4030_AIF_EN);
722 break;
723 case SND_SOC_DAPM_POST_PMD:
724 /* disable the DAI before we stop it's source PLL */
725 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
726 audio_if & ~TWL4030_AIF_EN);
727 twl4030_apll_enable(w->codec, 0);
728 break;
729 }
730 return 0;
731}
732
6943c92e 733static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 734{
4ae6df5e 735 struct twl4030_codec_data *pdata = codec->dev->platform_data;
aad749e5 736 unsigned char hs_gain, hs_pop;
b2c812e2 737 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 738 /* Base values for ramp delay calculation: 2^19 - 2^26 */
739 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
740 8388608, 16777216, 33554432, 67108864};
7e6120c5 741 unsigned int delay;
aad749e5 742
6943c92e
PU		 743 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
744 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 745 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
746 twl4030->sysclk) + 1;
aad749e5 747
4e49ffd1
CVJ		 748 /* Enable external mute control, this dramatically reduces
749 * the pop-noise */
f0fba2ad
LG		 750 if (pdata && pdata->hs_extmute) {
751 if (pdata->set_hs_extmute) {
752 pdata->set_hs_extmute(1);
4e49ffd1
CVJ		 753 } else {
754 hs_pop |= TWL4030_EXTMUTE;
755 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
756 }
757 }
758
6943c92e
PU		 759 if (ramp) {
760 /* Headset ramp-up according to the TRM */
aad749e5 761 hs_pop |= TWL4030_VMID_EN;
6943c92e 762 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 763 /* Actually write to the register */
764 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
765 hs_gain,
766 TWL4030_REG_HS_GAIN_SET);
aad749e5 767 hs_pop |= TWL4030_RAMP_EN;
6943c92e 768 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 769 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 770 twl4030_wait_ms(delay);
6943c92e
PU		 771 } else {
772 /* Headset ramp-down _not_ according to
773 * the TRM, but in a way that it is working */
aad749e5 774 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 775 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
776 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 777 twl4030_wait_ms(delay);
aad749e5 778 /* Bypass the reg_cache to mute the headset */
fc7b92fc 779 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 780 hs_gain & (~0x0f),
781 TWL4030_REG_HS_GAIN_SET);
6943c92e 782
aad749e5 783 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 784 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
785 }
4e49ffd1
CVJ		 786
787 /* Disable external mute */
f0fba2ad
LG		 788 if (pdata && pdata->hs_extmute) {
789 if (pdata->set_hs_extmute) {
790 pdata->set_hs_extmute(0);
4e49ffd1
CVJ		 791 } else {
792 hs_pop &= ~TWL4030_EXTMUTE;
793 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
794 }
795 }
6943c92e
PU		 796}
797
798static int headsetlpga_event(struct snd_soc_dapm_widget *w,
799 struct snd_kcontrol *kcontrol, int event)
800{
b2c812e2 801 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 802
803 switch (event) {
804 case SND_SOC_DAPM_POST_PMU:
805 /* Do the ramp-up only once */
806 if (!twl4030->hsr_enabled)
807 headset_ramp(w->codec, 1);
808
809 twl4030->hsl_enabled = 1;
810 break;
811 case SND_SOC_DAPM_POST_PMD:
812 /* Do the ramp-down only if both headsetL/R is disabled */
813 if (!twl4030->hsr_enabled)
814 headset_ramp(w->codec, 0);
815
816 twl4030->hsl_enabled = 0;
817 break;
818 }
819 return 0;
820}
821
822static int headsetrpga_event(struct snd_soc_dapm_widget *w,
823 struct snd_kcontrol *kcontrol, int event)
824{
b2c812e2 825 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 826
827 switch (event) {
828 case SND_SOC_DAPM_POST_PMU:
829 /* Do the ramp-up only once */
830 if (!twl4030->hsl_enabled)
831 headset_ramp(w->codec, 1);
832
833 twl4030->hsr_enabled = 1;
834 break;
835 case SND_SOC_DAPM_POST_PMD:
836 /* Do the ramp-down only if both headsetL/R is disabled */
837 if (!twl4030->hsl_enabled)
838 headset_ramp(w->codec, 0);
839
840 twl4030->hsr_enabled = 0;
aad749e5
PU		 841 break;
842 }
843 return 0;
844}
845
01ea6ba2
PU		 846static int digimic_event(struct snd_soc_dapm_widget *w,
847 struct snd_kcontrol *kcontrol, int event)
848{
849 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
850
851 if (twl4030->digimic_delay)
7e6120c5 852 twl4030_wait_ms(twl4030->digimic_delay);
01ea6ba2
PU		 853 return 0;
854}
855
b0bd53a7
PU		 856/*
857 * Some of the gain controls in TWL (mostly those which are associated with
858 * the outputs) are implemented in an interesting way:
859 * 0x0 : Power down (mute)
860 * 0x1 : 6dB
861 * 0x2 : 0 dB
862 * 0x3 : -6 dB
863 * Inverting not going to help with these.
864 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
865 */
b0bd53a7
PU		 866static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
867 struct snd_ctl_elem_value *ucontrol)
868{
869 struct soc_mixer_control *mc =
870 (struct soc_mixer_control *)kcontrol->private_value;
871 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
872 unsigned int reg = mc->reg;
873 unsigned int shift = mc->shift;
874 unsigned int rshift = mc->rshift;
875 int max = mc->max;
876 int mask = (1 << fls(max)) - 1;
877
878 ucontrol->value.integer.value[0] =
879 (snd_soc_read(codec, reg) >> shift) & mask;
880 if (ucontrol->value.integer.value[0])
881 ucontrol->value.integer.value[0] =
882 max + 1 - ucontrol->value.integer.value[0];
883
884 if (shift != rshift) {
885 ucontrol->value.integer.value[1] =
886 (snd_soc_read(codec, reg) >> rshift) & mask;
887 if (ucontrol->value.integer.value[1])
888 ucontrol->value.integer.value[1] =
889 max + 1 - ucontrol->value.integer.value[1];
890 }
891
892 return 0;
893}
894
895static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
896 struct snd_ctl_elem_value *ucontrol)
897{
898 struct soc_mixer_control *mc =
899 (struct soc_mixer_control *)kcontrol->private_value;
900 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
901 unsigned int reg = mc->reg;
902 unsigned int shift = mc->shift;
903 unsigned int rshift = mc->rshift;
904 int max = mc->max;
905 int mask = (1 << fls(max)) - 1;
906 unsigned short val, val2, val_mask;
907
908 val = (ucontrol->value.integer.value[0] & mask);
909
910 val_mask = mask << shift;
911 if (val)
912 val = max + 1 - val;
913 val = val << shift;
914 if (shift != rshift) {
915 val2 = (ucontrol->value.integer.value[1] & mask);
916 val_mask |= mask << rshift;
917 if (val2)
918 val2 = max + 1 - val2;
919 val |= val2 << rshift;
920 }
921 return snd_soc_update_bits(codec, reg, val_mask, val);
922}
923
924static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
925 struct snd_ctl_elem_value *ucontrol)
926{
927 struct soc_mixer_control *mc =
928 (struct soc_mixer_control *)kcontrol->private_value;
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
930 unsigned int reg = mc->reg;
931 unsigned int reg2 = mc->rreg;
932 unsigned int shift = mc->shift;
933 int max = mc->max;
934 int mask = (1<<fls(max))-1;
935
936 ucontrol->value.integer.value[0] =
937 (snd_soc_read(codec, reg) >> shift) & mask;
938 ucontrol->value.integer.value[1] =
939 (snd_soc_read(codec, reg2) >> shift) & mask;
940
941 if (ucontrol->value.integer.value[0])
942 ucontrol->value.integer.value[0] =
943 max + 1 - ucontrol->value.integer.value[0];
944 if (ucontrol->value.integer.value[1])
945 ucontrol->value.integer.value[1] =
946 max + 1 - ucontrol->value.integer.value[1];
947
948 return 0;
949}
950
951static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
952 struct snd_ctl_elem_value *ucontrol)
953{
954 struct soc_mixer_control *mc =
955 (struct soc_mixer_control *)kcontrol->private_value;
956 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
957 unsigned int reg = mc->reg;
958 unsigned int reg2 = mc->rreg;
959 unsigned int shift = mc->shift;
960 int max = mc->max;
961 int mask = (1 << fls(max)) - 1;
962 int err;
963 unsigned short val, val2, val_mask;
964
965 val_mask = mask << shift;
966 val = (ucontrol->value.integer.value[0] & mask);
967 val2 = (ucontrol->value.integer.value[1] & mask);
968
969 if (val)
970 val = max + 1 - val;
971 if (val2)
972 val2 = max + 1 - val2;
973
974 val = val << shift;
975 val2 = val2 << shift;
976
977 err = snd_soc_update_bits(codec, reg, val_mask, val);
978 if (err < 0)
979 return err;
980
981 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
982 return err;
983}
984
b74bd40f
LCM		 985/* Codec operation modes */
986static const char *twl4030_op_modes_texts[] = {
987 "Option 2 (voice/audio)", "Option 1 (audio)"
988};
989
990static const struct soc_enum twl4030_op_modes_enum =
991 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
992 ARRAY_SIZE(twl4030_op_modes_texts),
993 twl4030_op_modes_texts);
994
423c238d 995static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 996 struct snd_ctl_elem_value *ucontrol)
997{
998 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 999 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1000 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1001 unsigned short val;
86767b7d 1002 unsigned short mask;
b74bd40f
LCM		 1003
1004 if (twl4030->configured) {
3b8a0795
PU		 1005 dev_err(codec->dev,
1006 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 1007 return -EBUSY;
1008 }
1009
b74bd40f
LCM		 1010 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1011 return -EINVAL;
1012
1013 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 1014 mask = e->mask << e->shift_l;
b74bd40f
LCM		 1015 if (e->shift_l != e->shift_r) {
1016 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1017 return -EINVAL;
1018 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 1019 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 1020 }
1021
1022 return snd_soc_update_bits(codec, e->reg, mask, val);
1023}
1024
c10b82cf
PU		 1025/*
1026 * FGAIN volume control:
1027 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1028 */
d889a72c 1029static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1030
0d33ea0b
PU		 1031/*
1032 * CGAIN volume control:
1033 * 0 dB to 12 dB in 6 dB steps
1034 * value 2 and 3 means 12 dB
1035 */
d889a72c
PU		 1036static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1037
1a787e7a
JS		 1038/*
1039 * Voice Downlink GAIN volume control:
1040 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1041 */
1042static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1043
d889a72c
PU		 1044/*
1045 * Analog playback gain
1046 * -24 dB to 12 dB in 2 dB steps
1047 */
1048static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1049
4290239c
PU		 1050/*
1051 * Gain controls tied to outputs
1052 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1053 */
1054static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1055
18cc8d8d
JS		 1056/*
1057 * Gain control for earpiece amplifier
1058 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1059 */
1060static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1061
381a22b5
PU		 1062/*
1063 * Capture gain after the ADCs
1064 * from 0 dB to 31 dB in 1 dB steps
1065 */
1066static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1067
5920b453
GI		 1068/*
1069 * Gain control for input amplifiers
1070 * 0 dB to 30 dB in 6 dB steps
1071 */
1072static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1073
328d0a13
LCM		 1074/* AVADC clock priority */
1075static const char *twl4030_avadc_clk_priority_texts[] = {
1076 "Voice high priority", "HiFi high priority"
1077};
1078
1079static const struct soc_enum twl4030_avadc_clk_priority_enum =
1080 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1081 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1082 twl4030_avadc_clk_priority_texts);
1083
89492be8
PU		 1084static const char *twl4030_rampdelay_texts[] = {
1085 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1086 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1087 "3495/2581/1748 ms"
1088};
1089
1090static const struct soc_enum twl4030_rampdelay_enum =
1091 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1092 ARRAY_SIZE(twl4030_rampdelay_texts),
1093 twl4030_rampdelay_texts);
1094
376f7839
PU		 1095/* Vibra H-bridge direction mode */
1096static const char *twl4030_vibradirmode_texts[] = {
1097 "Vibra H-bridge direction", "Audio data MSB",
1098};
1099
1100static const struct soc_enum twl4030_vibradirmode_enum =
1101 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1102 ARRAY_SIZE(twl4030_vibradirmode_texts),
1103 twl4030_vibradirmode_texts);
1104
1105/* Vibra H-bridge direction */
1106static const char *twl4030_vibradir_texts[] = {
1107 "Positive polarity", "Negative polarity",
1108};
1109
1110static const struct soc_enum twl4030_vibradir_enum =
1111 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1112 ARRAY_SIZE(twl4030_vibradir_texts),
1113 twl4030_vibradir_texts);
1114
36aeff61
PU		 1115/* Digimic Left and right swapping */
1116static const char *twl4030_digimicswap_texts[] = {
1117 "Not swapped", "Swapped",
1118};
1119
1120static const struct soc_enum twl4030_digimicswap_enum =
1121 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1122 ARRAY_SIZE(twl4030_digimicswap_texts),
1123 twl4030_digimicswap_texts);
1124
cc17557e 1125static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1126 /* Codec operation mode control */
1127 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1128 snd_soc_get_enum_double,
1129 snd_soc_put_twl4030_opmode_enum_double),
1130
d889a72c
PU		 1131 /* Common playback gain controls */
1132 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1133 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1134 0, 0x3f, 0, digital_fine_tlv),
1135 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1136 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1137 0, 0x3f, 0, digital_fine_tlv),
1138
1139 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1140 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1141 6, 0x2, 0, digital_coarse_tlv),
1142 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1143 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1144 6, 0x2, 0, digital_coarse_tlv),
1145
1146 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1147 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1148 3, 0x12, 1, analog_tlv),
1149 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1150 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1151 3, 0x12, 1, analog_tlv),
44c55870
PU		 1152 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1153 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1154 1, 1, 0),
1155 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1156 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1157 1, 1, 0),
381a22b5 1158
1a787e7a
JS		 1159 /* Common voice downlink gain controls */
1160 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1161 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1162
1163 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1164 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1165
1166 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1167 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1168
4290239c 1169 /* Separate output gain controls */
0f9887d1 1170 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1171 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1172 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1173 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1174
0f9887d1
PU		 1175 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1176 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1177 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1178
0f9887d1 1179 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1180 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1181 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1182 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1183
0f9887d1
PU		 1184 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1185 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1186 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1187
381a22b5 1188 /* Common capture gain controls */
276c6222 1189 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1190 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1191 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1192 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1193 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1194 0, 0x1f, 0, digital_capture_tlv),
5920b453 1195
276c6222 1196 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1197 0, 3, 5, 0, input_gain_tlv),
89492be8 1198
328d0a13
LCM		 1199 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1200
89492be8 1201 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1202
1203 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1204 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1205
1206 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1207};
1208
cc17557e 1209static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1210 /* Left channel inputs */
1211 SND_SOC_DAPM_INPUT("MAINMIC"),
1212 SND_SOC_DAPM_INPUT("HSMIC"),
1213 SND_SOC_DAPM_INPUT("AUXL"),
1214 SND_SOC_DAPM_INPUT("CARKITMIC"),
1215 /* Right channel inputs */
1216 SND_SOC_DAPM_INPUT("SUBMIC"),
1217 SND_SOC_DAPM_INPUT("AUXR"),
1218 /* Digital microphones (Stereo) */
1219 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1220 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1221
1222 /* Outputs */
5e98a464 1223 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1224 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1225 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1226 SND_SOC_DAPM_OUTPUT("HSOL"),
1227 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1228 SND_SOC_DAPM_OUTPUT("CARKITL"),
1229 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1230 SND_SOC_DAPM_OUTPUT("HFL"),
1231 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1232 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1233
7b4c734e
PU		 1234 /* AIF and APLL clocks for running DAIs (including loopback) */
1235 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1236 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1237 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1238
53b5047d 1239 /* DACs */
7f51e7d3
PU		 1240 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1241 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1242 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1243 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1244 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1245
7393958f 1246 /* Analog bypasses */
78e08e2f
PU		 1247 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1248 &twl4030_dapm_abypassr1_control),
1249 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1250 &twl4030_dapm_abypassl1_control),
1251 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1252 &twl4030_dapm_abypassr2_control),
1253 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1254 &twl4030_dapm_abypassl2_control),
1255 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1256 &twl4030_dapm_abypassv_control),
1257
1258 /* Master analog loopback switch */
1259 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1260 NULL, 0),
7393958f 1261
6bab83fd 1262 /* Digital bypasses */
78e08e2f
PU		 1263 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1264 &twl4030_dapm_dbypassl_control),
1265 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1266 &twl4030_dapm_dbypassr_control),
1267 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1268 &twl4030_dapm_dbypassv_control),
6bab83fd 1269
4005d39a
PU		 1270 /* Digital mixers, power control for the physical DACs */
1271 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1272 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1273 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1274 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1275 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1276 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1277 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1278 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1279 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1280 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1281
1282 /* Analog mixers, power control for the physical PGAs */
1283 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1284 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1285 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1286 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1287 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1288 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1289 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1290 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1291 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1292 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1293
7729cf74
PU		 1294 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1295 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1296
7b4c734e
PU		 1297 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1298 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1299
1a787e7a 1300 /* Output MIXER controls */
5e98a464 1301 /* Earpiece */
1a787e7a
JS		 1302 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1303 &twl4030_dapm_earpiece_controls[0],
1304 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1305 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1306 0, 0, NULL, 0, earpiecepga_event,
1307 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1308 /* PreDrivL/R */
1a787e7a
JS		 1309 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1310 &twl4030_dapm_predrivel_controls[0],
1311 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1312 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1313 0, 0, NULL, 0, predrivelpga_event,
1314 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1315 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1316 &twl4030_dapm_predriver_controls[0],
1317 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1318 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1319 0, 0, NULL, 0, predriverpga_event,
1320 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1321 /* HeadsetL/R */
6943c92e 1322 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1323 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1324 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1325 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1326 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1327 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1328 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1329 &twl4030_dapm_hsor_controls[0],
1330 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1331 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1332 0, 0, NULL, 0, headsetrpga_event,
1333 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1334 /* CarkitL/R */
1a787e7a
JS		 1335 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1336 &twl4030_dapm_carkitl_controls[0],
1337 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1338 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1339 0, 0, NULL, 0, carkitlpga_event,
1340 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1341 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_carkitr_controls[0],
1343 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1344 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1345 0, 0, NULL, 0, carkitrpga_event,
1346 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1347
1348 /* Output MUX controls */
df339804 1349 /* HandsfreeL/R */
5a2e9a48
PU		 1350 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1351 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1352 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1353 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1354 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1355 0, 0, NULL, 0, handsfreelpga_event,
1356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1357 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1358 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1359 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1360 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1361 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1362 0, 0, NULL, 0, handsfreerpga_event,
1363 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1364 /* Vibra */
86139a13
JV		 1365 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1366 &twl4030_dapm_vibra_control, vibramux_event,
1367 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1368 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1369 &twl4030_dapm_vibrapath_control),
5e98a464 1370
276c6222
PU		 1371 /* Introducing four virtual ADC, since TWL4030 have four channel for
1372 capture */
7f51e7d3
PU		 1373 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1374 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1375 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1376 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222
PU		 1377
1378 /* Analog/Digital mic path selection.
1379 TX1 Left/Right: either analog Left/Right or Digimic0
1380 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1381 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1382 &twl4030_dapm_micpathtx1_control),
1383 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1384 &twl4030_dapm_micpathtx2_control),
276c6222 1385
97b8096d 1386 /* Analog input mixers for the capture amplifiers */
9028935d 1387 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1388 TWL4030_REG_ANAMICL, 4, 0,
1389 &twl4030_dapm_analoglmic_controls[0],
1390 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1391 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1392 TWL4030_REG_ANAMICR, 4, 0,
1393 &twl4030_dapm_analogrmic_controls[0],
1394 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1395
fb2a2f84
PU		 1396 SND_SOC_DAPM_PGA("ADC Physical Left",
1397 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1398 SND_SOC_DAPM_PGA("ADC Physical Right",
1399 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1400
01ea6ba2
PU		 1401 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1402 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1403 digimic_event, SND_SOC_DAPM_POST_PMU),
1404 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1405 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1406 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1407
bda7d2a8
PU		 1408 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1409 NULL, 0),
1410 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1411 NULL, 0),
1412
276c6222
PU		 1413 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1414 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1415 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1416
cc17557e
SS		 1417};
1418
1419static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1420 /* Stream -> DAC mapping */
1421 {"DAC Right1", NULL, "HiFi Playback"},
1422 {"DAC Left1", NULL, "HiFi Playback"},
1423 {"DAC Right2", NULL, "HiFi Playback"},
1424 {"DAC Left2", NULL, "HiFi Playback"},
1425 {"DAC Voice", NULL, "Voice Playback"},
1426
1427 /* ADC -> Stream mapping */
1428 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1429 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1430 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1431 {"HiFi Capture", NULL, "ADC Virtual Right2"},
1432 {"Voice Capture", NULL, "ADC Virtual Left1"},
1433 {"Voice Capture", NULL, "ADC Virtual Right1"},
1434 {"Voice Capture", NULL, "ADC Virtual Left2"},
1435 {"Voice Capture", NULL, "ADC Virtual Right2"},
1436
4005d39a
PU		 1437 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1438 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1439 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1440 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1441 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1442
7729cf74 1443 /* Supply for the digital part (APLL) */
7729cf74
PU		 1444 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1445
27eeb1fe
PU		 1446 {"DAC Left1", NULL, "AIF Enable"},
1447 {"DAC Right1", NULL, "AIF Enable"},
1448 {"DAC Left2", NULL, "AIF Enable"},
1449 {"DAC Right1", NULL, "AIF Enable"},
1450
c42a59ea
PU		 1451 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1452 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1453
4005d39a
PU		 1454 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1455 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1456 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1457 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1458 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1459
5e98a464
PU		 1460 /* Internal playback routings */
1461 /* Earpiece */
4005d39a
PU		 1462 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1463 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1464 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1465 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1466 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1467 /* PreDrivL */
4005d39a
PU		 1468 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1469 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1470 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1471 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1472 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1473 /* PreDrivR */
4005d39a
PU		 1474 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1475 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1476 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1477 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1478 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1479 /* HeadsetL */
4005d39a
PU		 1480 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1481 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1482 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1483 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1484 /* HeadsetR */
4005d39a
PU		 1485 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1486 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1487 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1488 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1489 /* CarkitL */
4005d39a
PU		 1490 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1491 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1492 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1493 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1494 /* CarkitR */
4005d39a
PU		 1495 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1496 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1497 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1498 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1499 /* HandsfreeL */
4005d39a
PU		 1500 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1501 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1502 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1503 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1504 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1505 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1506 /* HandsfreeR */
4005d39a
PU		 1507 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1508 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1509 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1510 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1511 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1512 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1513 /* Vibra */
1514 {"Vibra Mux", "AudioL1", "DAC Left1"},
1515 {"Vibra Mux", "AudioR1", "DAC Right1"},
1516 {"Vibra Mux", "AudioL2", "DAC Left2"},
1517 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1518
cc17557e 1519 /* outputs */
7b4c734e 1520 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1521 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1522 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1523 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1524 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1525 /* Must be always connected (for APLL) */
1526 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1527 /* Physical outputs */
9008adf9
PU		 1528 {"EARPIECE", NULL, "Earpiece PGA"},
1529 {"PREDRIVEL", NULL, "PredriveL PGA"},
1530 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1531 {"HSOL", NULL, "HeadsetL PGA"},
1532 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1533 {"CARKITL", NULL, "CarkitL PGA"},
1534 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1535 {"HFL", NULL, "HandsfreeL PGA"},
1536 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1537 {"Vibra Route", "Audio", "Vibra Mux"},
1538 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1539
276c6222 1540 /* Capture path */
7b4c734e
PU		 1541 /* Must be always connected (for AIF and APLL) */
1542 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1543 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1544 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1545 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1546 /* Physical inputs */
9028935d
PU		 1547 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1548 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1549 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1550 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1551
9028935d
PU		 1552 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1553 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1554
9028935d
PU		 1555 {"ADC Physical Left", NULL, "Analog Left"},
1556 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1557
1558 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1559 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1560
bda7d2a8
PU		 1561 {"DIGIMIC0", NULL, "micbias1 select"},
1562 {"DIGIMIC1", NULL, "micbias2 select"},
1563
276c6222 1564 /* TX1 Left capture path */
fb2a2f84 1565 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1566 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1567 /* TX1 Right capture path */
fb2a2f84 1568 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1569 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1570 /* TX2 Left capture path */
fb2a2f84 1571 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1572 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1573 /* TX2 Right capture path */
fb2a2f84 1574 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1575 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1576
1577 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1578 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1579 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1580 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1581
c42a59ea
PU		 1582 {"ADC Virtual Left1", NULL, "AIF Enable"},
1583 {"ADC Virtual Right1", NULL, "AIF Enable"},
1584 {"ADC Virtual Left2", NULL, "AIF Enable"},
1585 {"ADC Virtual Right2", NULL, "AIF Enable"},
1586
7393958f 1587 /* Analog bypass routes */
9028935d
PU		 1588 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1589 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1590 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1591 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1592 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1593
78e08e2f
PU		 1594 /* Supply for the Analog loopbacks */
1595 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1596 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1597 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1598 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1599 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1600
7393958f
PU		 1601 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1602 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1603 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1604 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1605 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1606
6bab83fd
PU		 1607 /* Digital bypass routes */
1608 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1609 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1610 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1611
4005d39a
PU		 1612 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1613 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1614 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1615
cc17557e
SS		 1616};
1617
cc17557e
SS		 1618static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1619 enum snd_soc_bias_level level)
1620{
1621 switch (level) {
1622 case SND_SOC_BIAS_ON:
cc17557e
SS		 1623 break;
1624 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1625 break;
1626 case SND_SOC_BIAS_STANDBY:
ce6120cc 1627 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1628 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1629 break;
1630 case SND_SOC_BIAS_OFF:
cbd2db12 1631 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1632 break;
1633 }
ce6120cc 1634 codec->dapm.bias_level = level;
cc17557e
SS		 1635
1636 return 0;
1637}
1638
6b87a91f
PU		 1639static void twl4030_constraints(struct twl4030_priv *twl4030,
1640 struct snd_pcm_substream *mst_substream)
1641{
1642 struct snd_pcm_substream *slv_substream;
1643
1644 /* Pick the stream, which need to be constrained */
1645 if (mst_substream == twl4030->master_substream)
1646 slv_substream = twl4030->slave_substream;
1647 else if (mst_substream == twl4030->slave_substream)
1648 slv_substream = twl4030->master_substream;
1649 else /* This should not happen.. */
1650 return;
1651
1652 /* Set the constraints according to the already configured stream */
1653 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1654 SNDRV_PCM_HW_PARAM_RATE,
1655 twl4030->rate,
1656 twl4030->rate);
1657
1658 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1659 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1660 twl4030->sample_bits,
1661 twl4030->sample_bits);
1662
1663 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1664 SNDRV_PCM_HW_PARAM_CHANNELS,
1665 twl4030->channels,
1666 twl4030->channels);
1667}
1668
8a1f936a
PU		 1669/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1670 * capture has to be enabled/disabled. */
1671static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1672 int enable)
1673{
1674 u8 reg, mask;
1675
1676 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1677
1678 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1679 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1680 else
1681 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1682
1683 if (enable)
1684 reg |= mask;
1685 else
1686 reg &= ~mask;
1687
1688 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1689}
1690
d6648da1
PU		 1691static int twl4030_startup(struct snd_pcm_substream *substream,
1692 struct snd_soc_dai *dai)
7220b9f4 1693{
e6968a17 1694 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1695 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1696
7220b9f4 1697 if (twl4030->master_substream) {
7220b9f4 1698 twl4030->slave_substream = substream;
6b87a91f
PU		 1699 /* The DAI has one configuration for playback and capture, so
1700 * if the DAI has been already configured then constrain this
1701 * substream to match it. */
1702 if (twl4030->configured)
1703 twl4030_constraints(twl4030, twl4030->master_substream);
1704 } else {
8a1f936a
PU		 1705 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1706 TWL4030_OPTION_1)) {
1707 /* In option2 4 channel is not supported, set the
1708 * constraint for the first stream for channels, the
1709 * second stream will 'inherit' this cosntraint */
1710 snd_pcm_hw_constraint_minmax(substream->runtime,
1711 SNDRV_PCM_HW_PARAM_CHANNELS,
1712 2, 2);
1713 }
7220b9f4 1714 twl4030->master_substream = substream;
6b87a91f 1715 }
7220b9f4
PU		 1716
1717 return 0;
1718}
1719
d6648da1
PU		 1720static void twl4030_shutdown(struct snd_pcm_substream *substream,
1721 struct snd_soc_dai *dai)
7220b9f4 1722{
e6968a17 1723 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1724 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1725
1726 if (twl4030->master_substream == substream)
1727 twl4030->master_substream = twl4030->slave_substream;
1728
1729 twl4030->slave_substream = NULL;
6b87a91f
PU		 1730
1731 /* If all streams are closed, or the remaining stream has not yet
1732 * been configured than set the DAI as not configured. */
1733 if (!twl4030->master_substream)
1734 twl4030->configured = 0;
1735 else if (!twl4030->master_substream->runtime->channels)
1736 twl4030->configured = 0;
8a1f936a
PU		 1737
1738 /* If the closing substream had 4 channel, do the necessary cleanup */
1739 if (substream->runtime->channels == 4)
1740 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1741}
1742
cc17557e 1743static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1744 struct snd_pcm_hw_params *params,
1745 struct snd_soc_dai *dai)
cc17557e 1746{
e6968a17 1747 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1748 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1749 u8 mode, old_mode, format, old_format;
1750
8a1f936a
PU		 1751 /* If the substream has 4 channel, do the necessary setup */
1752 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1753 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1754 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1755
1756 /* Safety check: are we in the correct operating mode and
1757 * the interface is in TDM mode? */
1758 if ((mode & TWL4030_OPTION_1) &&
1759 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1760 twl4030_tdm_enable(codec, substream->stream, 1);
1761 else
1762 return -EINVAL;
1763 }
1764
6b87a91f
PU		 1765 if (twl4030->configured)
1766 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1767 return 0;
1768
cc17557e
SS		 1769 /* bit rate */
1770 old_mode = twl4030_read_reg_cache(codec,
1771 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1772 mode = old_mode & ~TWL4030_APLL_RATE;
1773
1774 switch (params_rate(params)) {
1775 case 8000:
1776 mode |= TWL4030_APLL_RATE_8000;
1777 break;
1778 case 11025:
1779 mode |= TWL4030_APLL_RATE_11025;
1780 break;
1781 case 12000:
1782 mode |= TWL4030_APLL_RATE_12000;
1783 break;
1784 case 16000:
1785 mode |= TWL4030_APLL_RATE_16000;
1786 break;
1787 case 22050:
1788 mode |= TWL4030_APLL_RATE_22050;
1789 break;
1790 case 24000:
1791 mode |= TWL4030_APLL_RATE_24000;
1792 break;
1793 case 32000:
1794 mode |= TWL4030_APLL_RATE_32000;
1795 break;
1796 case 44100:
1797 mode |= TWL4030_APLL_RATE_44100;
1798 break;
1799 case 48000:
1800 mode |= TWL4030_APLL_RATE_48000;
1801 break;
103f211d
PU		 1802 case 96000:
1803 mode |= TWL4030_APLL_RATE_96000;
1804 break;
cc17557e 1805 default:
3b8a0795 1806 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1807 params_rate(params));
1808 return -EINVAL;
1809 }
1810
cc17557e
SS		 1811 /* sample size */
1812 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1813 format = old_format;
1814 format &= ~TWL4030_DATA_WIDTH;
1815 switch (params_format(params)) {
1816 case SNDRV_PCM_FORMAT_S16_LE:
1817 format |= TWL4030_DATA_WIDTH_16S_16W;
1818 break;
dcdeda4a 1819 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1820 format |= TWL4030_DATA_WIDTH_32S_24W;
1821 break;
1822 default:
3b8a0795 1823 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1824 params_format(params));
1825 return -EINVAL;
1826 }
1827
2046f175
PU		 1828 if (format != old_format || mode != old_mode) {
1829 if (twl4030->codec_powered) {
1830 /*
1831 * If the codec is powered, than we need to toggle the
1832 * codec power.
1833 */
1834 twl4030_codec_enable(codec, 0);
1835 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1836 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1837 twl4030_codec_enable(codec, 1);
1838 } else {
1839 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1840 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1841 }
cc17557e 1842 }
6b87a91f
PU		 1843
1844 /* Store the important parameters for the DAI configuration and set
1845 * the DAI as configured */
1846 twl4030->configured = 1;
1847 twl4030->rate = params_rate(params);
1848 twl4030->sample_bits = hw_param_interval(params,
1849 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1850 twl4030->channels = params_channels(params);
1851
1852 /* If both playback and capture streams are open, and one of them
1853 * is setting the hw parameters right now (since we are here), set
1854 * constraints to the other stream to match the current one. */
1855 if (twl4030->slave_substream)
1856 twl4030_constraints(twl4030, substream);
1857
cc17557e
SS		 1858 return 0;
1859}
1860
1861static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1862 int clk_id, unsigned int freq, int dir)
1863{
1864 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1865 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1866
1867 switch (freq) {
1868 case 19200000:
cc17557e 1869 case 26000000:
cc17557e 1870 case 38400000:
cc17557e
SS		 1871 break;
1872 default:
3b8a0795 1873 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1874 return -EINVAL;
1875 }
1876
68d01955
PU		 1877 if ((freq / 1000) != twl4030->sysclk) {
1878 dev_err(codec->dev,
3b8a0795 1879 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1880 freq, twl4030->sysclk * 1000);
1881 return -EINVAL;
1882 }
cc17557e
SS		 1883
1884 return 0;
1885}
1886
1887static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1888 unsigned int fmt)
1889{
1890 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1891 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1892 u8 old_format, format;
1893
1894 /* get format */
1895 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1896 format = old_format;
1897
1898 /* set master/slave audio interface */
1899 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1900 case SND_SOC_DAIFMT_CBM_CFM:
1901 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1902 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1903 break;
1904 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1905 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1906 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1907 break;
1908 default:
1909 return -EINVAL;
1910 }
1911
1912 /* interface format */
1913 format &= ~TWL4030_AIF_FORMAT;
1914 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1915 case SND_SOC_DAIFMT_I2S:
1916 format |= TWL4030_AIF_FORMAT_CODEC;
1917 break;
8a1f936a
PU		 1918 case SND_SOC_DAIFMT_DSP_A:
1919 format |= TWL4030_AIF_FORMAT_TDM;
1920 break;
cc17557e
SS		 1921 default:
1922 return -EINVAL;
1923 }
1924
1925 if (format != old_format) {
2046f175
PU		 1926 if (twl4030->codec_powered) {
1927 /*
1928 * If the codec is powered, than we need to toggle the
1929 * codec power.
1930 */
1931 twl4030_codec_enable(codec, 0);
1932 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1933 twl4030_codec_enable(codec, 1);
1934 } else {
1935 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1936 }
cc17557e
SS		 1937 }
1938
1939 return 0;
1940}
1941
68140443
LCM		 1942static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1943{
1944 struct snd_soc_codec *codec = dai->codec;
1945 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1946
1947 if (tristate)
1948 reg |= TWL4030_AIF_TRI_EN;
1949 else
1950 reg &= ~TWL4030_AIF_TRI_EN;
1951
1952 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1953}
1954
b7a755a8
MLC		 1955/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1956 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1957static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1958 int enable)
1959{
1960 u8 reg, mask;
1961
1962 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1963
1964 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1965 mask = TWL4030_ARXL1_VRX_EN;
1966 else
1967 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1968
1969 if (enable)
1970 reg |= mask;
1971 else
1972 reg &= ~mask;
1973
1974 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1975}
1976
7154b3e8
JS		 1977static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1978 struct snd_soc_dai *dai)
1979{
e6968a17 1980 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1981 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1982 u8 mode;
1983
1984 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 1985 * not available.
7154b3e8 1986 */
68d01955 1987 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 1988 dev_err(codec->dev,
1989 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1990 __func__, twl4030->sysclk);
7154b3e8
JS		 1991 return -EINVAL;
1992 }
1993
1994 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 1995 * available.
7154b3e8
JS		 1996 */
1997 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1998 & TWL4030_OPT_MODE;
1999
2000 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 2001 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2002 __func__);
7154b3e8
JS		 2003 return -EINVAL;
2004 }
2005
2006 return 0;
2007}
2008
b7a755a8
MLC		 2009static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2010 struct snd_soc_dai *dai)
2011{
e6968a17 2012 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 2013
2014 /* Enable voice digital filters */
2015 twl4030_voice_enable(codec, substream->stream, 0);
2016}
2017
7154b3e8
JS		 2018static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2019 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2020{
e6968a17 2021 struct snd_soc_codec *codec = dai->codec;
2046f175 2022 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2023 u8 old_mode, mode;
2024
b7a755a8
MLC		 2025 /* Enable voice digital filters */
2026 twl4030_voice_enable(codec, substream->stream, 1);
2027
7154b3e8
JS		 2028 /* bit rate */
2029 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2030 & ~(TWL4030_CODECPDZ);
2031 mode = old_mode;
2032
2033 switch (params_rate(params)) {
2034 case 8000:
2035 mode &= ~(TWL4030_SEL_16K);
2036 break;
2037 case 16000:
2038 mode |= TWL4030_SEL_16K;
2039 break;
2040 default:
3b8a0795 2041 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2042 params_rate(params));
2043 return -EINVAL;
2044 }
2045
2046 if (mode != old_mode) {
2046f175
PU		 2047 if (twl4030->codec_powered) {
2048 /*
2049 * If the codec is powered, than we need to toggle the
2050 * codec power.
2051 */
2052 twl4030_codec_enable(codec, 0);
2053 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2054 twl4030_codec_enable(codec, 1);
2055 } else {
2056 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2057 }
7154b3e8
JS		 2058 }
2059
2060 return 0;
2061}
2062
2063static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2064 int clk_id, unsigned int freq, int dir)
2065{
2066 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2067 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2068
68d01955 2069 if (freq != 26000000) {
3b8a0795
PU		 2070 dev_err(codec->dev,
2071 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2072 __func__, freq / 1000);
68d01955
PU		 2073 return -EINVAL;
2074 }
2075 if ((freq / 1000) != twl4030->sysclk) {
2076 dev_err(codec->dev,
3b8a0795 2077 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2078 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2079 return -EINVAL;
2080 }
7154b3e8
JS		 2081 return 0;
2082}
2083
2084static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2085 unsigned int fmt)
2086{
2087 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2088 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2089 u8 old_format, format;
2090
2091 /* get format */
2092 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2093 format = old_format;
2094
2095 /* set master/slave audio interface */
2096 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2097 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2098 format &= ~(TWL4030_VIF_SLAVE_EN);
2099 break;
2100 case SND_SOC_DAIFMT_CBS_CFS:
2101 format |= TWL4030_VIF_SLAVE_EN;
2102 break;
2103 default:
2104 return -EINVAL;
2105 }
2106
2107 /* clock inversion */
2108 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2109 case SND_SOC_DAIFMT_IB_NF:
2110 format &= ~(TWL4030_VIF_FORMAT);
2111 break;
2112 case SND_SOC_DAIFMT_NB_IF:
2113 format |= TWL4030_VIF_FORMAT;
2114 break;
2115 default:
2116 return -EINVAL;
2117 }
2118
2119 if (format != old_format) {
2046f175
PU		 2120 if (twl4030->codec_powered) {
2121 /*
2122 * If the codec is powered, than we need to toggle the
2123 * codec power.
2124 */
2125 twl4030_codec_enable(codec, 0);
2126 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2127 twl4030_codec_enable(codec, 1);
2128 } else {
2129 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2130 }
7154b3e8
JS		 2131 }
2132
2133 return 0;
2134}
2135
68140443
LCM		 2136static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2137{
2138 struct snd_soc_codec *codec = dai->codec;
2139 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2140
2141 if (tristate)
2142 reg |= TWL4030_VIF_TRI_EN;
2143 else
2144 reg &= ~TWL4030_VIF_TRI_EN;
2145
2146 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2147}
2148
bbba9444 2149#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2150#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2151
85e7652d 2152static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2153 .startup = twl4030_startup,
2154 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2155 .hw_params = twl4030_hw_params,
2156 .set_sysclk = twl4030_set_dai_sysclk,
2157 .set_fmt = twl4030_set_dai_fmt,
68140443 2158 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2159};
2160
85e7652d 2161static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2162 .startup = twl4030_voice_startup,
b7a755a8 2163 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2164 .hw_params = twl4030_voice_hw_params,
2165 .set_sysclk = twl4030_voice_set_dai_sysclk,
2166 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2167 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2168};
2169
f0fba2ad 2170static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2171{
f0fba2ad 2172 .name = "twl4030-hifi",
cc17557e 2173 .playback = {
b4852b79 2174 .stream_name = "HiFi Playback",
cc17557e 2175 .channels_min = 2,
8a1f936a 2176 .channels_max = 4,
31ad0f31 2177 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2178 .formats = TWL4030_FORMATS,
2179 .sig_bits = 24,},
cc17557e 2180 .capture = {
7f51e7d3 2181 .stream_name = "HiFi Capture",
cc17557e 2182 .channels_min = 2,
8a1f936a 2183 .channels_max = 4,
cc17557e 2184 .rates = TWL4030_RATES,
8819f65c
PU		 2185 .formats = TWL4030_FORMATS,
2186 .sig_bits = 24,},
f0fba2ad 2187 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2188},
2189{
f0fba2ad 2190 .name = "twl4030-voice",
7154b3e8 2191 .playback = {
b4852b79 2192 .stream_name = "Voice Playback",
7154b3e8
JS		 2193 .channels_min = 1,
2194 .channels_max = 1,
2195 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2196 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2197 .capture = {
7f51e7d3 2198 .stream_name = "Voice Capture",
7154b3e8
JS		 2199 .channels_min = 1,
2200 .channels_max = 2,
2201 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2202 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2203 .ops = &twl4030_dai_voice_ops,
2204},
cc17557e 2205};
cc17557e 2206
84b315ee 2207static int twl4030_soc_suspend(struct snd_soc_codec *codec)
cc17557e 2208{
cc17557e 2209 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
cc17557e
SS		 2210 return 0;
2211}
2212
f0fba2ad 2213static int twl4030_soc_resume(struct snd_soc_codec *codec)
cc17557e 2214{
cc17557e 2215 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2216 return 0;
2217}
2218
f0fba2ad 2219static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2220{
f0fba2ad 2221 struct twl4030_priv *twl4030;
9da28c7b 2222
f0fba2ad
LG		 2223 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2224 if (twl4030 == NULL) {
3b8a0795 2225 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2226 return -ENOMEM;
cc17557e 2227 }
f0fba2ad
LG		 2228 snd_soc_codec_set_drvdata(codec, twl4030);
2229 /* Set the defaults, and power up the codec */
57fe7251 2230 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2231
2232 twl4030_init_chip(codec);
cc17557e 2233
7a1fecf5 2234 return 0;
cc17557e
SS		 2235}
2236
f0fba2ad 2237static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2238{
5b3b0fa8
AL		 2239 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2240
5dcba5d6
PU		 2241 /* Reset registers to their chip default before leaving */
2242 twl4030_reset_registers(codec);
7a1fecf5 2243 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
5b3b0fa8 2244 kfree(twl4030);
7a1fecf5
PU		 2245 return 0;
2246}
2247
f0fba2ad
LG		 2248static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2249 .probe = twl4030_soc_probe,
2250 .remove = twl4030_soc_remove,
2251 .suspend = twl4030_soc_suspend,
2252 .resume = twl4030_soc_resume,
2253 .read = twl4030_read_reg_cache,
2254 .write = twl4030_write,
2255 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2256 .idle_bias_off = true,
f0fba2ad
LG		 2257 .reg_cache_size = sizeof(twl4030_reg),
2258 .reg_word_size = sizeof(u8),
2259 .reg_cache_default = twl4030_reg,
f7c93f01
PU		 2260
2261 .controls = twl4030_snd_controls,
2262 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2263 .dapm_widgets = twl4030_dapm_widgets,
2264 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2265 .dapm_routes = intercon,
2266 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2267};
2268
7a1fecf5
PU		 2269static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2270{
4ae6df5e 2271 struct twl4030_codec_data *pdata = pdev->dev.platform_data;
cc17557e 2272
68d01955
PU		 2273 if (!pdata) {
2274 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2275 return -EINVAL;
2276 }
cc17557e 2277
f0fba2ad
LG		 2278 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2279 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2280}
2281
7a1fecf5 2282static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2283{
f0fba2ad 2284 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2285 return 0;
2286}
2287
f0fba2ad 2288MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2289
2290static struct platform_driver twl4030_codec_driver = {
2291 .probe = twl4030_codec_probe,
2292 .remove = __devexit_p(twl4030_codec_remove),
2293 .driver = {
f0fba2ad 2294 .name = "twl4030-codec",
7a1fecf5
PU		 2295 .owner = THIS_MODULE,
2296 },
cc17557e 2297};
cc17557e 2298
5bbcc3c0 2299module_platform_driver(twl4030_codec_driver);
64089b84 2300
cc17557e
SS		 2301MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2302MODULE_AUTHOR("Steve Sakoman");
2303MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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