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ASoC: Enforce symmetric rates for PXA2xx I2S
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
7393958f
PU		 133};
134
cc17557e
SS		 135/*
136 * read twl4030 register cache
137 */
138static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140{
141 u8 *cache = codec->reg_cache;
142
91432e97
IM		 143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
cc17557e
SS		 146 return cache[reg];
147}
148
149/*
150 * write twl4030 register cache
151 */
152static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154{
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160}
161
162/*
163 * write to the twl4030 register space
164 */
165static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167{
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170}
171
db04e2c5 172static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 173{
7393958f 174 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 175 u8 mode;
176
7393958f
PU		 177 if (enable == twl4030->codec_powered)
178 return;
179
cc17557e 180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
cc17557e 185
db04e2c5 186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 187 twl4030->codec_powered = enable;
cc17557e
SS		 188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192}
193
194static void twl4030_init_chip(struct snd_soc_codec *codec)
195{
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 199 twl4030_codec_enable(codec, 0);
cc17557e
SS		 200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205}
206
7393958f
PU		 207static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208{
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 240 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272}
273
006f367e
PU		 274static void twl4030_power_up(struct snd_soc_codec *codec)
275{
7393958f 276 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
7393958f
PU		 280 if (twl4030->codec_powered)
281 return;
282
006f367e
PU		 283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312}
313
7393958f
PU		 314/*
315 * Unconditional power down
316 */
006f367e
PU		 317static void twl4030_power_down(struct snd_soc_codec *codec)
318{
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321}
322
5e98a464 323/* Earpiece */
1a787e7a
JS		 324static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
326 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
327 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
328 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
329};
5e98a464 330
2a6f5c58 331/* PreDrive Left */
1a787e7a
JS		 332static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
337};
2a6f5c58
PU		 338
339/* PreDrive Right */
1a787e7a
JS		 340static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
345};
2a6f5c58 346
dfad21a2 347/* Headset Left */
1a787e7a
JS		 348static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
352};
dfad21a2
PU		 353
354/* Headset Right */
1a787e7a
JS		 355static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
357 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
358 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
359};
dfad21a2 360
5152d8c2 361/* Carkit Left */
1a787e7a
JS		 362static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
366};
5152d8c2
PU		 367
368/* Carkit Right */
1a787e7a
JS		 369static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
370 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
371 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
372 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
373};
5152d8c2 374
df339804
PU		 375/* Handsfree Left */
376static const char *twl4030_handsfreel_texts[] =
1a787e7a 377 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 378
379static const struct soc_enum twl4030_handsfreel_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
381 ARRAY_SIZE(twl4030_handsfreel_texts),
382 twl4030_handsfreel_texts);
383
384static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
385SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
386
387/* Handsfree Right */
388static const char *twl4030_handsfreer_texts[] =
1a787e7a 389 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreer_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreer_texts),
394 twl4030_handsfreer_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
398
376f7839
PU		 399/* Vibra */
400/* Vibra audio path selection */
401static const char *twl4030_vibra_texts[] =
402 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
403
404static const struct soc_enum twl4030_vibra_enum =
405 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
406 ARRAY_SIZE(twl4030_vibra_texts),
407 twl4030_vibra_texts);
408
409static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
410SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
411
412/* Vibra path selection: local vibrator (PWM) or audio driven */
413static const char *twl4030_vibrapath_texts[] =
414 {"Local vibrator", "Audio"};
415
416static const struct soc_enum twl4030_vibrapath_enum =
417 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
418 ARRAY_SIZE(twl4030_vibrapath_texts),
419 twl4030_vibrapath_texts);
420
421static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
422SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
423
276c6222
PU		 424/* Left analog microphone selection */
425static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 426 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
427
428static const unsigned int twl4030_analoglmic_values[] =
429 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 430
cb1ace04 431static const struct soc_enum twl4030_analoglmic_enum =
2f423577 432 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 433 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 434 twl4030_analoglmic_texts,
435 twl4030_analoglmic_values);
276c6222
PU		 436
437static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 438SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 439
440/* Right analog microphone selection */
441static const char *twl4030_analogrmic_texts[] =
2f423577 442 {"Off", "Sub mic", "AUXR"};
276c6222 443
2f423577
PU		 444static const unsigned int twl4030_analogrmic_values[] =
445 {0x0, 0x1, 0x4};
446
cb1ace04 447static const struct soc_enum twl4030_analogrmic_enum =
2f423577 448 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 449 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 450 twl4030_analogrmic_texts,
451 twl4030_analogrmic_values);
276c6222
PU		 452
453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 454SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 455
456/* TX1 L/R Analog/Digital microphone selection */
457static const char *twl4030_micpathtx1_texts[] =
458 {"Analog", "Digimic0"};
459
460static const struct soc_enum twl4030_micpathtx1_enum =
461 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
462 ARRAY_SIZE(twl4030_micpathtx1_texts),
463 twl4030_micpathtx1_texts);
464
465static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
466SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
467
468/* TX2 L/R Analog/Digital microphone selection */
469static const char *twl4030_micpathtx2_texts[] =
470 {"Analog", "Digimic1"};
471
472static const struct soc_enum twl4030_micpathtx2_enum =
473 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
474 ARRAY_SIZE(twl4030_micpathtx2_texts),
475 twl4030_micpathtx2_texts);
476
477static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
478SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
479
7393958f
PU		 480/* Analog bypass for AudioR1 */
481static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
482 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
483
484/* Analog bypass for AudioL1 */
485static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
486 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
487
488/* Analog bypass for AudioR2 */
489static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
490 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
491
492/* Analog bypass for AudioL2 */
493static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
494 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
495
fcd274a3
LCM		 496/* Analog bypass for Voice */
497static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
498 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
499
6bab83fd
PU		 500/* Digital bypass gain, 0 mutes the bypass */
501static const unsigned int twl4030_dapm_dbypass_tlv[] = {
502 TLV_DB_RANGE_HEAD(2),
503 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
504 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
505};
506
507/* Digital bypass left (TX1L -> RX2L) */
508static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
509 SOC_DAPM_SINGLE_TLV("Volume",
510 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
511 twl4030_dapm_dbypass_tlv);
512
513/* Digital bypass right (TX1R -> RX2R) */
514static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
515 SOC_DAPM_SINGLE_TLV("Volume",
516 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
517 twl4030_dapm_dbypass_tlv);
518
ee8f6894
LCM		 519/*
520 * Voice Sidetone GAIN volume control:
521 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
522 */
523static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
524
525/* Digital bypass voice: sidetone (VUL -> VDL)*/
526static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
527 SOC_DAPM_SINGLE_TLV("Volume",
528 TWL4030_REG_VSTPGA, 0, 0x29, 0,
529 twl4030_dapm_dbypassv_tlv);
530
276c6222
PU		 531static int micpath_event(struct snd_soc_dapm_widget *w,
532 struct snd_kcontrol *kcontrol, int event)
533{
534 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
535 unsigned char adcmicsel, micbias_ctl;
536
537 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
538 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
539 /* Prepare the bits for the given TX path:
540 * shift_l == 0: TX1 microphone path
541 * shift_l == 2: TX2 microphone path */
542 if (e->shift_l) {
543 /* TX2 microphone path */
544 if (adcmicsel & TWL4030_TX2IN_SEL)
545 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
546 else
547 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
548 } else {
549 /* TX1 microphone path */
550 if (adcmicsel & TWL4030_TX1IN_SEL)
551 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
552 else
553 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
554 }
555
556 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
557
558 return 0;
559}
560
49d92c7d
SM		 561static int handsfree_event(struct snd_soc_dapm_widget *w,
562 struct snd_kcontrol *kcontrol, int event)
563{
564 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
565 unsigned char hs_ctl;
566
567 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
568
569 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
570 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
571 twl4030_write(w->codec, e->reg, hs_ctl);
572 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
573 twl4030_write(w->codec, e->reg, hs_ctl);
574 hs_ctl |= TWL4030_HF_CTL_HB_EN;
575 twl4030_write(w->codec, e->reg, hs_ctl);
576 } else {
577 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
578 | TWL4030_HF_CTL_HB_EN);
579 twl4030_write(w->codec, e->reg, hs_ctl);
580 }
581
582 return 0;
583}
584
aad749e5
PU		 585static int headsetl_event(struct snd_soc_dapm_widget *w,
586 struct snd_kcontrol *kcontrol, int event)
587{
588 unsigned char hs_gain, hs_pop;
589
590 /* Save the current volume */
591 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
89492be8 592 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
aad749e5
PU		 593
594 switch (event) {
595 case SND_SOC_DAPM_POST_PMU:
596 /* Do the anti-pop/bias ramp enable according to the TRM */
aad749e5
PU		 597 hs_pop |= TWL4030_VMID_EN;
598 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
599 /* Is this needed? Can we just use whatever gain here? */
600 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
601 (hs_gain & (~0x0f)) | 0x0a);
602 hs_pop |= TWL4030_RAMP_EN;
603 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
604
605 /* Restore the original volume */
606 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
607 break;
608 case SND_SOC_DAPM_POST_PMD:
609 /* Do the anti-pop/bias ramp disable according to the TRM */
aad749e5
PU		 610 hs_pop &= ~TWL4030_RAMP_EN;
611 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
612 /* Bypass the reg_cache to mute the headset */
613 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
614 hs_gain & (~0x0f),
615 TWL4030_REG_HS_GAIN_SET);
616 hs_pop &= ~TWL4030_VMID_EN;
617 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
618 break;
619 }
620 return 0;
621}
622
7393958f
PU		 623static int bypass_event(struct snd_soc_dapm_widget *w,
624 struct snd_kcontrol *kcontrol, int event)
625{
626 struct soc_mixer_control *m =
627 (struct soc_mixer_control *)w->kcontrols->private_value;
628 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 629 unsigned char reg, misc;
7393958f
PU		 630
631 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 632
633 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
634 /* Analog bypass */
635 if (reg & (1 << m->shift))
636 twl4030->bypass_state |=
637 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
638 else
639 twl4030->bypass_state &=
640 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 641 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
642 /* Analog voice bypass */
643 if (reg & (1 << m->shift))
644 twl4030->bypass_state |= (1 << 4);
645 else
646 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 647 } else if (m->reg == TWL4030_REG_VSTPGA) {
648 /* Voice digital bypass */
649 if (reg)
650 twl4030->bypass_state |= (1 << 5);
651 else
652 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 653 } else {
654 /* Digital bypass */
655 if (reg & (0x7 << m->shift))
ee8f6894 656 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 657 else
ee8f6894 658 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 659 }
7393958f 660
fcd274a3
LCM		 661 /* Enable master analog loopback mode if any analog switch is enabled*/
662 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
663 if (twl4030->bypass_state & 0x1F)
664 misc |= TWL4030_FMLOOP_EN;
665 else
666 misc &= ~TWL4030_FMLOOP_EN;
667 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
668
7393958f
PU		 669 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
670 if (twl4030->bypass_state)
671 twl4030_codec_mute(w->codec, 0);
672 else
673 twl4030_codec_mute(w->codec, 1);
674 }
675 return 0;
676}
677
b0bd53a7
PU		 678/*
679 * Some of the gain controls in TWL (mostly those which are associated with
680 * the outputs) are implemented in an interesting way:
681 * 0x0 : Power down (mute)
682 * 0x1 : 6dB
683 * 0x2 : 0 dB
684 * 0x3 : -6 dB
685 * Inverting not going to help with these.
686 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
687 */
688#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
689 xinvert, tlv_array) \
690{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
691 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
692 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
693 .tlv.p = (tlv_array), \
694 .info = snd_soc_info_volsw, \
695 .get = snd_soc_get_volsw_twl4030, \
696 .put = snd_soc_put_volsw_twl4030, \
697 .private_value = (unsigned long)&(struct soc_mixer_control) \
698 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
699 .max = xmax, .invert = xinvert} }
700#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
701 xinvert, tlv_array) \
702{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
703 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
704 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
705 .tlv.p = (tlv_array), \
706 .info = snd_soc_info_volsw_2r, \
707 .get = snd_soc_get_volsw_r2_twl4030,\
708 .put = snd_soc_put_volsw_r2_twl4030, \
709 .private_value = (unsigned long)&(struct soc_mixer_control) \
710 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 711 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 712#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
713 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
714 xinvert, tlv_array)
715
716static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
717 struct snd_ctl_elem_value *ucontrol)
718{
719 struct soc_mixer_control *mc =
720 (struct soc_mixer_control *)kcontrol->private_value;
721 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
722 unsigned int reg = mc->reg;
723 unsigned int shift = mc->shift;
724 unsigned int rshift = mc->rshift;
725 int max = mc->max;
726 int mask = (1 << fls(max)) - 1;
727
728 ucontrol->value.integer.value[0] =
729 (snd_soc_read(codec, reg) >> shift) & mask;
730 if (ucontrol->value.integer.value[0])
731 ucontrol->value.integer.value[0] =
732 max + 1 - ucontrol->value.integer.value[0];
733
734 if (shift != rshift) {
735 ucontrol->value.integer.value[1] =
736 (snd_soc_read(codec, reg) >> rshift) & mask;
737 if (ucontrol->value.integer.value[1])
738 ucontrol->value.integer.value[1] =
739 max + 1 - ucontrol->value.integer.value[1];
740 }
741
742 return 0;
743}
744
745static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
746 struct snd_ctl_elem_value *ucontrol)
747{
748 struct soc_mixer_control *mc =
749 (struct soc_mixer_control *)kcontrol->private_value;
750 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
751 unsigned int reg = mc->reg;
752 unsigned int shift = mc->shift;
753 unsigned int rshift = mc->rshift;
754 int max = mc->max;
755 int mask = (1 << fls(max)) - 1;
756 unsigned short val, val2, val_mask;
757
758 val = (ucontrol->value.integer.value[0] & mask);
759
760 val_mask = mask << shift;
761 if (val)
762 val = max + 1 - val;
763 val = val << shift;
764 if (shift != rshift) {
765 val2 = (ucontrol->value.integer.value[1] & mask);
766 val_mask |= mask << rshift;
767 if (val2)
768 val2 = max + 1 - val2;
769 val |= val2 << rshift;
770 }
771 return snd_soc_update_bits(codec, reg, val_mask, val);
772}
773
774static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
775 struct snd_ctl_elem_value *ucontrol)
776{
777 struct soc_mixer_control *mc =
778 (struct soc_mixer_control *)kcontrol->private_value;
779 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
780 unsigned int reg = mc->reg;
781 unsigned int reg2 = mc->rreg;
782 unsigned int shift = mc->shift;
783 int max = mc->max;
784 int mask = (1<<fls(max))-1;
785
786 ucontrol->value.integer.value[0] =
787 (snd_soc_read(codec, reg) >> shift) & mask;
788 ucontrol->value.integer.value[1] =
789 (snd_soc_read(codec, reg2) >> shift) & mask;
790
791 if (ucontrol->value.integer.value[0])
792 ucontrol->value.integer.value[0] =
793 max + 1 - ucontrol->value.integer.value[0];
794 if (ucontrol->value.integer.value[1])
795 ucontrol->value.integer.value[1] =
796 max + 1 - ucontrol->value.integer.value[1];
797
798 return 0;
799}
800
801static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_value *ucontrol)
803{
804 struct soc_mixer_control *mc =
805 (struct soc_mixer_control *)kcontrol->private_value;
806 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
807 unsigned int reg = mc->reg;
808 unsigned int reg2 = mc->rreg;
809 unsigned int shift = mc->shift;
810 int max = mc->max;
811 int mask = (1 << fls(max)) - 1;
812 int err;
813 unsigned short val, val2, val_mask;
814
815 val_mask = mask << shift;
816 val = (ucontrol->value.integer.value[0] & mask);
817 val2 = (ucontrol->value.integer.value[1] & mask);
818
819 if (val)
820 val = max + 1 - val;
821 if (val2)
822 val2 = max + 1 - val2;
823
824 val = val << shift;
825 val2 = val2 << shift;
826
827 err = snd_soc_update_bits(codec, reg, val_mask, val);
828 if (err < 0)
829 return err;
830
831 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
832 return err;
833}
834
c10b82cf
PU		 835/*
836 * FGAIN volume control:
837 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
838 */
d889a72c 839static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 840
0d33ea0b
PU		 841/*
842 * CGAIN volume control:
843 * 0 dB to 12 dB in 6 dB steps
844 * value 2 and 3 means 12 dB
845 */
d889a72c
PU		 846static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
847
1a787e7a
JS		 848/*
849 * Voice Downlink GAIN volume control:
850 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
851 */
852static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
853
d889a72c
PU		 854/*
855 * Analog playback gain
856 * -24 dB to 12 dB in 2 dB steps
857 */
858static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 859
4290239c
PU		 860/*
861 * Gain controls tied to outputs
862 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
863 */
864static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
865
18cc8d8d
JS		 866/*
867 * Gain control for earpiece amplifier
868 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
869 */
870static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
871
381a22b5
PU		 872/*
873 * Capture gain after the ADCs
874 * from 0 dB to 31 dB in 1 dB steps
875 */
876static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
877
5920b453
GI		 878/*
879 * Gain control for input amplifiers
880 * 0 dB to 30 dB in 6 dB steps
881 */
882static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
883
89492be8
PU		 884static const char *twl4030_rampdelay_texts[] = {
885 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
886 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
887 "3495/2581/1748 ms"
888};
889
890static const struct soc_enum twl4030_rampdelay_enum =
891 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
892 ARRAY_SIZE(twl4030_rampdelay_texts),
893 twl4030_rampdelay_texts);
894
376f7839
PU		 895/* Vibra H-bridge direction mode */
896static const char *twl4030_vibradirmode_texts[] = {
897 "Vibra H-bridge direction", "Audio data MSB",
898};
899
900static const struct soc_enum twl4030_vibradirmode_enum =
901 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
902 ARRAY_SIZE(twl4030_vibradirmode_texts),
903 twl4030_vibradirmode_texts);
904
905/* Vibra H-bridge direction */
906static const char *twl4030_vibradir_texts[] = {
907 "Positive polarity", "Negative polarity",
908};
909
910static const struct soc_enum twl4030_vibradir_enum =
911 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
912 ARRAY_SIZE(twl4030_vibradir_texts),
913 twl4030_vibradir_texts);
914
cc17557e 915static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 916 /* Common playback gain controls */
917 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
918 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
919 0, 0x3f, 0, digital_fine_tlv),
920 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
921 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
922 0, 0x3f, 0, digital_fine_tlv),
923
924 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
925 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
926 6, 0x2, 0, digital_coarse_tlv),
927 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
928 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
929 6, 0x2, 0, digital_coarse_tlv),
930
931 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
932 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
933 3, 0x12, 1, analog_tlv),
934 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
935 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
936 3, 0x12, 1, analog_tlv),
44c55870
PU		 937 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
938 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
939 1, 1, 0),
940 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
941 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
942 1, 1, 0),
381a22b5 943
1a787e7a
JS		 944 /* Common voice downlink gain controls */
945 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
946 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
947
948 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
949 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
950
951 SOC_SINGLE("DAC Voice Analog Downlink Switch",
952 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
953
4290239c
PU		 954 /* Separate output gain controls */
955 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
956 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
957 4, 3, 0, output_tvl),
958
959 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
960 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
961
962 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
963 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
964 4, 3, 0, output_tvl),
965
966 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 967 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 968
381a22b5 969 /* Common capture gain controls */
276c6222 970 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 971 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
972 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 973 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
974 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
975 0, 0x1f, 0, digital_capture_tlv),
5920b453 976
276c6222 977 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 978 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 979
980 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 981
982 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
983 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 984};
985
cc17557e 986static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 987 /* Left channel inputs */
988 SND_SOC_DAPM_INPUT("MAINMIC"),
989 SND_SOC_DAPM_INPUT("HSMIC"),
990 SND_SOC_DAPM_INPUT("AUXL"),
991 SND_SOC_DAPM_INPUT("CARKITMIC"),
992 /* Right channel inputs */
993 SND_SOC_DAPM_INPUT("SUBMIC"),
994 SND_SOC_DAPM_INPUT("AUXR"),
995 /* Digital microphones (Stereo) */
996 SND_SOC_DAPM_INPUT("DIGIMIC0"),
997 SND_SOC_DAPM_INPUT("DIGIMIC1"),
998
999 /* Outputs */
cc17557e
SS		 1000 SND_SOC_DAPM_OUTPUT("OUTL"),
1001 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1002 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1003 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1004 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1005 SND_SOC_DAPM_OUTPUT("HSOL"),
1006 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1007 SND_SOC_DAPM_OUTPUT("CARKITL"),
1008 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1009 SND_SOC_DAPM_OUTPUT("HFL"),
1010 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1011 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1012
53b5047d 1013 /* DACs */
1e5fa31f 1014 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 1015 SND_SOC_NOPM, 0, 0),
1e5fa31f 1016 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 1017 SND_SOC_NOPM, 0, 0),
1e5fa31f 1018 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 1019 SND_SOC_NOPM, 0, 0),
1e5fa31f 1020 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 1021 SND_SOC_NOPM, 0, 0),
1a787e7a 1022 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1023 SND_SOC_NOPM, 0, 0),
cc17557e 1024
44c55870
PU		 1025 /* Analog PGAs */
1026 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
1027 0, 0, NULL, 0),
1028 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
1029 0, 0, NULL, 0),
1030 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
1031 0, 0, NULL, 0),
1032 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
1033 0, 0, NULL, 0),
1a787e7a
JS		 1034 SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
1035 0, 0, NULL, 0),
44c55870 1036
7393958f
PU		 1037 /* Analog bypasses */
1038 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1039 &twl4030_dapm_abypassr1_control, bypass_event,
1040 SND_SOC_DAPM_POST_REG),
1041 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1042 &twl4030_dapm_abypassl1_control,
1043 bypass_event, SND_SOC_DAPM_POST_REG),
1044 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1045 &twl4030_dapm_abypassr2_control,
1046 bypass_event, SND_SOC_DAPM_POST_REG),
1047 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1048 &twl4030_dapm_abypassl2_control,
1049 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1050 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1051 &twl4030_dapm_abypassv_control,
1052 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1053
6bab83fd
PU		 1054 /* Digital bypasses */
1055 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1056 &twl4030_dapm_dbypassl_control, bypass_event,
1057 SND_SOC_DAPM_POST_REG),
1058 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1059 &twl4030_dapm_dbypassr_control, bypass_event,
1060 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1061 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1062 &twl4030_dapm_dbypassv_control, bypass_event,
1063 SND_SOC_DAPM_POST_REG),
6bab83fd 1064
7393958f
PU		 1065 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1066 0, 0, NULL, 0),
1067 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1068 1, 0, NULL, 0),
1069 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1070 2, 0, NULL, 0),
1071 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1072 3, 0, NULL, 0),
fcd274a3
LCM		 1073 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", TWL4030_REG_AVDAC_CTL,
1074 4, 0, NULL, 0),
7393958f 1075
1a787e7a 1076 /* Output MIXER controls */
5e98a464 1077 /* Earpiece */
1a787e7a
JS		 1078 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1079 &twl4030_dapm_earpiece_controls[0],
1080 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1081 /* PreDrivL/R */
1a787e7a
JS		 1082 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1083 &twl4030_dapm_predrivel_controls[0],
1084 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1085 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1086 &twl4030_dapm_predriver_controls[0],
1087 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1088 /* HeadsetL/R */
1a787e7a
JS		 1089 SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1090 &twl4030_dapm_hsol_controls[0],
1091 ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
1092 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1093 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1094 &twl4030_dapm_hsor_controls[0],
1095 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
5152d8c2 1096 /* CarkitL/R */
1a787e7a
JS		 1097 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1098 &twl4030_dapm_carkitl_controls[0],
1099 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1100 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1101 &twl4030_dapm_carkitr_controls[0],
1102 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1103
1104 /* Output MUX controls */
df339804 1105 /* HandsfreeL/R */
49d92c7d
SM		 1106 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1107 &twl4030_dapm_handsfreel_control, handsfree_event,
1108 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1109 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1110 &twl4030_dapm_handsfreer_control, handsfree_event,
1111 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1112 /* Vibra */
1113 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1114 &twl4030_dapm_vibra_control),
1115 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1116 &twl4030_dapm_vibrapath_control),
5e98a464 1117
276c6222
PU		 1118 /* Introducing four virtual ADC, since TWL4030 have four channel for
1119 capture */
1120 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1121 SND_SOC_NOPM, 0, 0),
1122 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1123 SND_SOC_NOPM, 0, 0),
1124 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1125 SND_SOC_NOPM, 0, 0),
1126 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1127 SND_SOC_NOPM, 0, 0),
1128
1129 /* Analog/Digital mic path selection.
1130 TX1 Left/Right: either analog Left/Right or Digimic0
1131 TX2 Left/Right: either analog Left/Right or Digimic1 */
1132 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1133 &twl4030_dapm_micpathtx1_control, micpath_event,
1134 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1135 SND_SOC_DAPM_POST_REG),
1136 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1137 &twl4030_dapm_micpathtx2_control, micpath_event,
1138 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1139 SND_SOC_DAPM_POST_REG),
1140
fb2a2f84 1141 /* Analog input muxes with switch for the capture amplifiers */
2f423577 1142 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 1143 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1144 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1145 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1146
fb2a2f84
PU		 1147 SND_SOC_DAPM_PGA("ADC Physical Left",
1148 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1149 SND_SOC_DAPM_PGA("ADC Physical Right",
1150 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1151
1152 SND_SOC_DAPM_PGA("Digimic0 Enable",
1153 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1154 SND_SOC_DAPM_PGA("Digimic1 Enable",
1155 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1156
1157 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1158 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1159 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1160
cc17557e
SS		 1161};
1162
1163static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1164 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1165 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1166 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1167 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
fcd274a3 1168 {"Analog Voice Playback Mixer", NULL, "DAC Voice"},
7393958f
PU		 1169
1170 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1171 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1172 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1173 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
fcd274a3 1174 {"VDL_APGA", NULL, "Analog Voice Playback Mixer"},
1a787e7a 1175
5e98a464
PU		 1176 /* Internal playback routings */
1177 /* Earpiece */
1a787e7a
JS		 1178 {"Earpiece Mixer", "Voice", "VDL_APGA"},
1179 {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
1180 {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
1181 {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
2a6f5c58 1182 /* PreDrivL */
1a787e7a
JS		 1183 {"PredriveL Mixer", "Voice", "VDL_APGA"},
1184 {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
1185 {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
1186 {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
2a6f5c58 1187 /* PreDrivR */
1a787e7a
JS		 1188 {"PredriveR Mixer", "Voice", "VDL_APGA"},
1189 {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
1190 {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
1191 {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1192 /* HeadsetL */
1a787e7a
JS		 1193 {"HeadsetL Mixer", "Voice", "VDL_APGA"},
1194 {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
1195 {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
dfad21a2 1196 /* HeadsetR */
1a787e7a
JS		 1197 {"HeadsetR Mixer", "Voice", "VDL_APGA"},
1198 {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
1199 {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
5152d8c2 1200 /* CarkitL */
1a787e7a
JS		 1201 {"CarkitL Mixer", "Voice", "VDL_APGA"},
1202 {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
1203 {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
5152d8c2 1204 /* CarkitR */
1a787e7a
JS		 1205 {"CarkitR Mixer", "Voice", "VDL_APGA"},
1206 {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
1207 {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
df339804 1208 /* HandsfreeL */
1a787e7a
JS		 1209 {"HandsfreeL Mux", "Voice", "VDL_APGA"},
1210 {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
1211 {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
1212 {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
df339804 1213 /* HandsfreeR */
1a787e7a
JS		 1214 {"HandsfreeR Mux", "Voice", "VDL_APGA"},
1215 {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
1216 {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
1217 {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
376f7839
PU		 1218 /* Vibra */
1219 {"Vibra Mux", "AudioL1", "DAC Left1"},
1220 {"Vibra Mux", "AudioR1", "DAC Right1"},
1221 {"Vibra Mux", "AudioL2", "DAC Left2"},
1222 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1223
cc17557e 1224 /* outputs */
44c55870
PU		 1225 {"OUTL", NULL, "ARXL2_APGA"},
1226 {"OUTR", NULL, "ARXR2_APGA"},
1a787e7a
JS		 1227 {"EARPIECE", NULL, "Earpiece Mixer"},
1228 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1229 {"PREDRIVER", NULL, "PredriveR Mixer"},
1230 {"HSOL", NULL, "HeadsetL Mixer"},
1231 {"HSOR", NULL, "HeadsetR Mixer"},
1232 {"CARKITL", NULL, "CarkitL Mixer"},
1233 {"CARKITR", NULL, "CarkitR Mixer"},
df339804
PU		 1234 {"HFL", NULL, "HandsfreeL Mux"},
1235 {"HFR", NULL, "HandsfreeR Mux"},
376f7839
PU		 1236 {"Vibra Route", "Audio", "Vibra Mux"},
1237 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1238
276c6222
PU		 1239 /* Capture path */
1240 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1241 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1242 {"Analog Left Capture Route", "AUXL", "AUXL"},
1243 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1244
1245 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1246 {"Analog Right Capture Route", "AUXR", "AUXR"},
1247
fb2a2f84
PU		 1248 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1249 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1250
1251 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1252 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1253
1254 /* TX1 Left capture path */
fb2a2f84 1255 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1256 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1257 /* TX1 Right capture path */
fb2a2f84 1258 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1259 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1260 /* TX2 Left capture path */
fb2a2f84 1261 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1262 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1263 /* TX2 Right capture path */
fb2a2f84 1264 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1265 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1266
1267 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1268 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1269 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1270 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1271
7393958f
PU		 1272 /* Analog bypass routes */
1273 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1274 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1275 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1276 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1277 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1278
1279 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1280 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1281 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1282 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1283 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1284
6bab83fd
PU		 1285 /* Digital bypass routes */
1286 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1287 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1288 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd
PU		 1289
1290 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1291 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
ee8f6894 1292 {"Analog Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1293
cc17557e
SS		 1294};
1295
1296static int twl4030_add_widgets(struct snd_soc_codec *codec)
1297{
1298 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1299 ARRAY_SIZE(twl4030_dapm_widgets));
1300
1301 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1302
1303 snd_soc_dapm_new_widgets(codec);
1304 return 0;
1305}
1306
cc17557e
SS		 1307static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1308 enum snd_soc_bias_level level)
1309{
7393958f
PU		 1310 struct twl4030_priv *twl4030 = codec->private_data;
1311
cc17557e
SS		 1312 switch (level) {
1313 case SND_SOC_BIAS_ON:
7393958f 1314 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1315 break;
1316 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1317 twl4030_power_up(codec);
1318 if (twl4030->bypass_state)
1319 twl4030_codec_mute(codec, 0);
1320 else
1321 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1322 break;
1323 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1324 twl4030_power_up(codec);
1325 if (twl4030->bypass_state)
1326 twl4030_codec_mute(codec, 0);
1327 else
1328 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1329 break;
1330 case SND_SOC_BIAS_OFF:
1331 twl4030_power_down(codec);
1332 break;
1333 }
1334 codec->bias_level = level;
1335
1336 return 0;
1337}
1338
6b87a91f
PU		 1339static void twl4030_constraints(struct twl4030_priv *twl4030,
1340 struct snd_pcm_substream *mst_substream)
1341{
1342 struct snd_pcm_substream *slv_substream;
1343
1344 /* Pick the stream, which need to be constrained */
1345 if (mst_substream == twl4030->master_substream)
1346 slv_substream = twl4030->slave_substream;
1347 else if (mst_substream == twl4030->slave_substream)
1348 slv_substream = twl4030->master_substream;
1349 else /* This should not happen.. */
1350 return;
1351
1352 /* Set the constraints according to the already configured stream */
1353 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1354 SNDRV_PCM_HW_PARAM_RATE,
1355 twl4030->rate,
1356 twl4030->rate);
1357
1358 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1359 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1360 twl4030->sample_bits,
1361 twl4030->sample_bits);
1362
1363 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1364 SNDRV_PCM_HW_PARAM_CHANNELS,
1365 twl4030->channels,
1366 twl4030->channels);
1367}
1368
8a1f936a
PU		 1369/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1370 * capture has to be enabled/disabled. */
1371static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1372 int enable)
1373{
1374 u8 reg, mask;
1375
1376 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1377
1378 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1379 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1380 else
1381 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1382
1383 if (enable)
1384 reg |= mask;
1385 else
1386 reg &= ~mask;
1387
1388 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1389}
1390
d6648da1
PU		 1391static int twl4030_startup(struct snd_pcm_substream *substream,
1392 struct snd_soc_dai *dai)
7220b9f4
PU		 1393{
1394 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1395 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1396 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1397 struct twl4030_priv *twl4030 = codec->private_data;
1398
7220b9f4 1399 if (twl4030->master_substream) {
7220b9f4 1400 twl4030->slave_substream = substream;
6b87a91f
PU		 1401 /* The DAI has one configuration for playback and capture, so
1402 * if the DAI has been already configured then constrain this
1403 * substream to match it. */
1404 if (twl4030->configured)
1405 twl4030_constraints(twl4030, twl4030->master_substream);
1406 } else {
8a1f936a
PU		 1407 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1408 TWL4030_OPTION_1)) {
1409 /* In option2 4 channel is not supported, set the
1410 * constraint for the first stream for channels, the
1411 * second stream will 'inherit' this cosntraint */
1412 snd_pcm_hw_constraint_minmax(substream->runtime,
1413 SNDRV_PCM_HW_PARAM_CHANNELS,
1414 2, 2);
1415 }
7220b9f4 1416 twl4030->master_substream = substream;
6b87a91f 1417 }
7220b9f4
PU		 1418
1419 return 0;
1420}
1421
d6648da1
PU		 1422static void twl4030_shutdown(struct snd_pcm_substream *substream,
1423 struct snd_soc_dai *dai)
7220b9f4
PU		 1424{
1425 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1426 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1427 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1428 struct twl4030_priv *twl4030 = codec->private_data;
1429
1430 if (twl4030->master_substream == substream)
1431 twl4030->master_substream = twl4030->slave_substream;
1432
1433 twl4030->slave_substream = NULL;
6b87a91f
PU		 1434
1435 /* If all streams are closed, or the remaining stream has not yet
1436 * been configured than set the DAI as not configured. */
1437 if (!twl4030->master_substream)
1438 twl4030->configured = 0;
1439 else if (!twl4030->master_substream->runtime->channels)
1440 twl4030->configured = 0;
8a1f936a
PU		 1441
1442 /* If the closing substream had 4 channel, do the necessary cleanup */
1443 if (substream->runtime->channels == 4)
1444 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1445}
1446
cc17557e 1447static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1448 struct snd_pcm_hw_params *params,
1449 struct snd_soc_dai *dai)
cc17557e
SS		 1450{
1451 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1452 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1453 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1454 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1455 u8 mode, old_mode, format, old_format;
1456
8a1f936a
PU		 1457 /* If the substream has 4 channel, do the necessary setup */
1458 if (params_channels(params) == 4) {
1459 /* Safety check: are we in the correct operating mode? */
1460 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1461 TWL4030_OPTION_1))
1462 twl4030_tdm_enable(codec, substream->stream, 1);
1463 else
1464 return -EINVAL;
1465 }
1466
6b87a91f
PU		 1467 if (twl4030->configured)
1468 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1469 return 0;
1470
cc17557e
SS		 1471 /* bit rate */
1472 old_mode = twl4030_read_reg_cache(codec,
1473 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1474 mode = old_mode & ~TWL4030_APLL_RATE;
1475
1476 switch (params_rate(params)) {
1477 case 8000:
1478 mode |= TWL4030_APLL_RATE_8000;
1479 break;
1480 case 11025:
1481 mode |= TWL4030_APLL_RATE_11025;
1482 break;
1483 case 12000:
1484 mode |= TWL4030_APLL_RATE_12000;
1485 break;
1486 case 16000:
1487 mode |= TWL4030_APLL_RATE_16000;
1488 break;
1489 case 22050:
1490 mode |= TWL4030_APLL_RATE_22050;
1491 break;
1492 case 24000:
1493 mode |= TWL4030_APLL_RATE_24000;
1494 break;
1495 case 32000:
1496 mode |= TWL4030_APLL_RATE_32000;
1497 break;
1498 case 44100:
1499 mode |= TWL4030_APLL_RATE_44100;
1500 break;
1501 case 48000:
1502 mode |= TWL4030_APLL_RATE_48000;
1503 break;
103f211d
PU		 1504 case 96000:
1505 mode |= TWL4030_APLL_RATE_96000;
1506 break;
cc17557e
SS		 1507 default:
1508 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1509 params_rate(params));
1510 return -EINVAL;
1511 }
1512
1513 if (mode != old_mode) {
1514 /* change rate and set CODECPDZ */
7393958f 1515 twl4030_codec_enable(codec, 0);
cc17557e 1516 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1517 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1518 }
1519
1520 /* sample size */
1521 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1522 format = old_format;
1523 format &= ~TWL4030_DATA_WIDTH;
1524 switch (params_format(params)) {
1525 case SNDRV_PCM_FORMAT_S16_LE:
1526 format |= TWL4030_DATA_WIDTH_16S_16W;
1527 break;
1528 case SNDRV_PCM_FORMAT_S24_LE:
1529 format |= TWL4030_DATA_WIDTH_32S_24W;
1530 break;
1531 default:
1532 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1533 params_format(params));
1534 return -EINVAL;
1535 }
1536
1537 if (format != old_format) {
1538
1539 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1540 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1541
1542 /* change format */
1543 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1544
1545 /* set CODECPDZ afterwards */
db04e2c5 1546 twl4030_codec_enable(codec, 1);
cc17557e 1547 }
6b87a91f
PU		 1548
1549 /* Store the important parameters for the DAI configuration and set
1550 * the DAI as configured */
1551 twl4030->configured = 1;
1552 twl4030->rate = params_rate(params);
1553 twl4030->sample_bits = hw_param_interval(params,
1554 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1555 twl4030->channels = params_channels(params);
1556
1557 /* If both playback and capture streams are open, and one of them
1558 * is setting the hw parameters right now (since we are here), set
1559 * constraints to the other stream to match the current one. */
1560 if (twl4030->slave_substream)
1561 twl4030_constraints(twl4030, substream);
1562
cc17557e
SS		 1563 return 0;
1564}
1565
1566static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1567 int clk_id, unsigned int freq, int dir)
1568{
1569 struct snd_soc_codec *codec = codec_dai->codec;
1570 u8 infreq;
1571
1572 switch (freq) {
1573 case 19200000:
1574 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1575 break;
1576 case 26000000:
1577 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1578 break;
1579 case 38400000:
1580 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1581 break;
1582 default:
1583 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1584 freq);
1585 return -EINVAL;
1586 }
1587
1588 infreq |= TWL4030_APLL_EN;
1589 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1590
1591 return 0;
1592}
1593
1594static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1595 unsigned int fmt)
1596{
1597 struct snd_soc_codec *codec = codec_dai->codec;
1598 u8 old_format, format;
1599
1600 /* get format */
1601 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1602 format = old_format;
1603
1604 /* set master/slave audio interface */
1605 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1606 case SND_SOC_DAIFMT_CBM_CFM:
1607 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1608 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1609 break;
1610 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1611 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1612 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1613 break;
1614 default:
1615 return -EINVAL;
1616 }
1617
1618 /* interface format */
1619 format &= ~TWL4030_AIF_FORMAT;
1620 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1621 case SND_SOC_DAIFMT_I2S:
1622 format |= TWL4030_AIF_FORMAT_CODEC;
1623 break;
8a1f936a
PU		 1624 case SND_SOC_DAIFMT_DSP_A:
1625 format |= TWL4030_AIF_FORMAT_TDM;
1626 break;
cc17557e
SS		 1627 default:
1628 return -EINVAL;
1629 }
1630
1631 if (format != old_format) {
1632
1633 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1634 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1635
1636 /* change format */
1637 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1638
1639 /* set CODECPDZ afterwards */
db04e2c5 1640 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1641 }
1642
1643 return 0;
1644}
1645
7154b3e8
JS		 1646static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1647 struct snd_soc_dai *dai)
1648{
1649 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1650 struct snd_soc_device *socdev = rtd->socdev;
1651 struct snd_soc_codec *codec = socdev->card->codec;
1652 u8 infreq;
1653 u8 mode;
1654
1655 /* If the system master clock is not 26MHz, the voice PCM interface is
1656 * not avilable.
1657 */
1658 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1659 & TWL4030_APLL_INFREQ;
1660
1661 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1662 printk(KERN_ERR "TWL4030 voice startup: "
1663 "MCLK is not 26MHz, call set_sysclk() on init\n");
1664 return -EINVAL;
1665 }
1666
1667 /* If the codec mode is not option2, the voice PCM interface is not
1668 * avilable.
1669 */
1670 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1671 & TWL4030_OPT_MODE;
1672
1673 if (mode != TWL4030_OPTION_2) {
1674 printk(KERN_ERR "TWL4030 voice startup: "
1675 "the codec mode is not option2\n");
1676 return -EINVAL;
1677 }
1678
1679 return 0;
1680}
1681
1682static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1683 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1684{
1685 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1686 struct snd_soc_device *socdev = rtd->socdev;
1687 struct snd_soc_codec *codec = socdev->card->codec;
1688 u8 old_mode, mode;
1689
1690 /* bit rate */
1691 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1692 & ~(TWL4030_CODECPDZ);
1693 mode = old_mode;
1694
1695 switch (params_rate(params)) {
1696 case 8000:
1697 mode &= ~(TWL4030_SEL_16K);
1698 break;
1699 case 16000:
1700 mode |= TWL4030_SEL_16K;
1701 break;
1702 default:
1703 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1704 params_rate(params));
1705 return -EINVAL;
1706 }
1707
1708 if (mode != old_mode) {
1709 /* change rate and set CODECPDZ */
1710 twl4030_codec_enable(codec, 0);
1711 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1712 twl4030_codec_enable(codec, 1);
1713 }
1714
1715 return 0;
1716}
1717
1718static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1719 int clk_id, unsigned int freq, int dir)
1720{
1721 struct snd_soc_codec *codec = codec_dai->codec;
1722 u8 infreq;
1723
1724 switch (freq) {
1725 case 26000000:
1726 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1727 break;
1728 default:
1729 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1730 freq);
1731 return -EINVAL;
1732 }
1733
1734 infreq |= TWL4030_APLL_EN;
1735 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1736
1737 return 0;
1738}
1739
1740static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1741 unsigned int fmt)
1742{
1743 struct snd_soc_codec *codec = codec_dai->codec;
1744 u8 old_format, format;
1745
1746 /* get format */
1747 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1748 format = old_format;
1749
1750 /* set master/slave audio interface */
1751 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1752 case SND_SOC_DAIFMT_CBS_CFM:
1753 format &= ~(TWL4030_VIF_SLAVE_EN);
1754 break;
1755 case SND_SOC_DAIFMT_CBS_CFS:
1756 format |= TWL4030_VIF_SLAVE_EN;
1757 break;
1758 default:
1759 return -EINVAL;
1760 }
1761
1762 /* clock inversion */
1763 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1764 case SND_SOC_DAIFMT_IB_NF:
1765 format &= ~(TWL4030_VIF_FORMAT);
1766 break;
1767 case SND_SOC_DAIFMT_NB_IF:
1768 format |= TWL4030_VIF_FORMAT;
1769 break;
1770 default:
1771 return -EINVAL;
1772 }
1773
1774 if (format != old_format) {
1775 /* change format and set CODECPDZ */
1776 twl4030_codec_enable(codec, 0);
1777 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1778 twl4030_codec_enable(codec, 1);
1779 }
1780
1781 return 0;
1782}
1783
bbba9444 1784#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1785#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1786
10d9e3d9 1787static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1788 .startup = twl4030_startup,
1789 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1790 .hw_params = twl4030_hw_params,
1791 .set_sysclk = twl4030_set_dai_sysclk,
1792 .set_fmt = twl4030_set_dai_fmt,
1793};
1794
7154b3e8
JS		 1795static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1796 .startup = twl4030_voice_startup,
1797 .hw_params = twl4030_voice_hw_params,
1798 .set_sysclk = twl4030_voice_set_dai_sysclk,
1799 .set_fmt = twl4030_voice_set_dai_fmt,
1800};
1801
1802struct snd_soc_dai twl4030_dai[] = {
1803{
cc17557e
SS		 1804 .name = "twl4030",
1805 .playback = {
1806 .stream_name = "Playback",
1807 .channels_min = 2,
8a1f936a 1808 .channels_max = 4,
31ad0f31 1809 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1810 .formats = TWL4030_FORMATS,},
1811 .capture = {
1812 .stream_name = "Capture",
1813 .channels_min = 2,
8a1f936a 1814 .channels_max = 4,
cc17557e
SS		 1815 .rates = TWL4030_RATES,
1816 .formats = TWL4030_FORMATS,},
10d9e3d9 1817 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1818},
1819{
1820 .name = "twl4030 Voice",
1821 .playback = {
1822 .stream_name = "Playback",
1823 .channels_min = 1,
1824 .channels_max = 1,
1825 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1826 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1827 .capture = {
1828 .stream_name = "Capture",
1829 .channels_min = 1,
1830 .channels_max = 2,
1831 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1832 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1833 .ops = &twl4030_dai_voice_ops,
1834},
cc17557e
SS		 1835};
1836EXPORT_SYMBOL_GPL(twl4030_dai);
1837
1838static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1839{
1840 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1841 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1842
1843 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1844
1845 return 0;
1846}
1847
1848static int twl4030_resume(struct platform_device *pdev)
1849{
1850 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1851 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1852
1853 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1854 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1855 return 0;
1856}
1857
1858/*
1859 * initialize the driver
1860 * register the mixer and dsp interfaces with the kernel
1861 */
1862
1863static int twl4030_init(struct snd_soc_device *socdev)
1864{
6627a653 1865 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1866 int ret = 0;
1867
1868 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1869
1870 codec->name = "twl4030";
1871 codec->owner = THIS_MODULE;
1872 codec->read = twl4030_read_reg_cache;
1873 codec->write = twl4030_write;
1874 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 1875 codec->dai = twl4030_dai;
1876 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 1877 codec->reg_cache_size = sizeof(twl4030_reg);
1878 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1879 GFP_KERNEL);
1880 if (codec->reg_cache == NULL)
1881 return -ENOMEM;
1882
1883 /* register pcms */
1884 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1885 if (ret < 0) {
1886 printk(KERN_ERR "twl4030: failed to create pcms\n");
1887 goto pcm_err;
1888 }
1889
1890 twl4030_init_chip(codec);
1891
1892 /* power on device */
1893 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1894
3e8e1952
IM		 1895 snd_soc_add_controls(codec, twl4030_snd_controls,
1896 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1897 twl4030_add_widgets(codec);
1898
968a6025 1899 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1900 if (ret < 0) {
1901 printk(KERN_ERR "twl4030: failed to register card\n");
1902 goto card_err;
1903 }
1904
1905 return ret;
1906
1907card_err:
1908 snd_soc_free_pcms(socdev);
1909 snd_soc_dapm_free(socdev);
1910pcm_err:
1911 kfree(codec->reg_cache);
1912 return ret;
1913}
1914
1915static struct snd_soc_device *twl4030_socdev;
1916
1917static int twl4030_probe(struct platform_device *pdev)
1918{
1919 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1920 struct snd_soc_codec *codec;
7393958f 1921 struct twl4030_priv *twl4030;
cc17557e
SS		 1922
1923 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1924 if (codec == NULL)
1925 return -ENOMEM;
1926
7393958f
PU		 1927 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1928 if (twl4030 == NULL) {
1929 kfree(codec);
1930 return -ENOMEM;
1931 }
1932
1933 codec->private_data = twl4030;
6627a653 1934 socdev->card->codec = codec;
cc17557e
SS		 1935 mutex_init(&codec->mutex);
1936 INIT_LIST_HEAD(&codec->dapm_widgets);
1937 INIT_LIST_HEAD(&codec->dapm_paths);
1938
1939 twl4030_socdev = socdev;
1940 twl4030_init(socdev);
1941
1942 return 0;
1943}
1944
1945static int twl4030_remove(struct platform_device *pdev)
1946{
1947 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1948 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1949
1950 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1951 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1952 snd_soc_free_pcms(socdev);
1953 snd_soc_dapm_free(socdev);
7393958f 1954 kfree(codec->private_data);
cc17557e
SS		 1955 kfree(codec);
1956
1957 return 0;
1958}
1959
1960struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1961 .probe = twl4030_probe,
1962 .remove = twl4030_remove,
1963 .suspend = twl4030_suspend,
1964 .resume = twl4030_resume,
1965};
1966EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1967
24e07db8 1968static int __init twl4030_modinit(void)
64089b84 1969{
7154b3e8 1970 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 1971}
24e07db8 1972module_init(twl4030_modinit);
64089b84
MB		 1973
1974static void __exit twl4030_exit(void)
1975{
7154b3e8 1976 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 1977}
1978module_exit(twl4030_exit);
1979
cc17557e
SS		 1980MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1981MODULE_AUTHOR("Steve Sakoman");
1982MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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