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ASoC: Add regulator support for WM8731
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
7a1fecf5
PU		 123 struct snd_soc_codec codec;
124
7393958f
PU		 125 unsigned int bypass_state;
126 unsigned int codec_powered;
127 unsigned int codec_muted;
7220b9f4
PU		 128
129 struct snd_pcm_substream *master_substream;
130 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 131
132 unsigned int configured;
133 unsigned int rate;
134 unsigned int sample_bits;
135 unsigned int channels;
6943c92e
PU		 136
137 unsigned int sysclk;
138
139 /* Headset output state handling */
140 unsigned int hsl_enabled;
141 unsigned int hsr_enabled;
7393958f
PU		 142};
143
cc17557e
SS		 144/*
145 * read twl4030 register cache
146 */
147static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
148 unsigned int reg)
149{
d08664fd 150 u8 *cache = codec->reg_cache;
cc17557e 151
91432e97
IM		 152 if (reg >= TWL4030_CACHEREGNUM)
153 return -EIO;
154
cc17557e
SS		 155 return cache[reg];
156}
157
158/*
159 * write twl4030 register cache
160 */
161static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
162 u8 reg, u8 value)
163{
164 u8 *cache = codec->reg_cache;
165
166 if (reg >= TWL4030_CACHEREGNUM)
167 return;
168 cache[reg] = value;
169}
170
171/*
172 * write to the twl4030 register space
173 */
174static int twl4030_write(struct snd_soc_codec *codec,
175 unsigned int reg, unsigned int value)
176{
177 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 178 if (likely(reg < TWL4030_REG_SW_SHADOW))
179 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
180 reg);
181 else
182 return 0;
cc17557e
SS		 183}
184
db04e2c5 185static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 186{
7393958f 187 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 188 int mode;
cc17557e 189
7393958f
PU		 190 if (enable == twl4030->codec_powered)
191 return;
192
db04e2c5 193 if (enable)
7a1fecf5 194 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 195 else
7a1fecf5 196 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 197
7a1fecf5
PU		 198 if (mode >= 0) {
199 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
200 twl4030->codec_powered = enable;
201 }
cc17557e
SS		 202
203 /* REVISIT: this delay is present in TI sample drivers */
204 /* but there seems to be no TRM requirement for it */
205 udelay(10);
206}
207
208static void twl4030_init_chip(struct snd_soc_codec *codec)
209{
16a30fbb 210 u8 *cache = codec->reg_cache;
cc17557e
SS		 211 int i;
212
213 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 214 twl4030_codec_enable(codec, 0);
cc17557e
SS		 215
216 /* set all audio section registers to reasonable defaults */
217 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 218 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 219
220}
221
7393958f
PU		 222static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
223{
224 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 225 int status;
7393958f
PU		 226
227 if (mute == twl4030->codec_muted)
228 return;
229
7a1fecf5 230 if (mute)
7393958f 231 /* Disable PLL */
7a1fecf5
PU		 232 status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
233 else
7393958f 234 /* Enable PLL */
7a1fecf5
PU		 235 status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
236
237 if (status >= 0)
238 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
7393958f
PU		 239
240 twl4030->codec_muted = mute;
241}
242
006f367e
PU		 243static void twl4030_power_up(struct snd_soc_codec *codec)
244{
7393958f 245 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 246 u8 anamicl, regmisc1, byte;
247 int i = 0;
248
7393958f
PU		 249 if (twl4030->codec_powered)
250 return;
251
006f367e
PU		 252 /* set CODECPDZ to turn on codec */
253 twl4030_codec_enable(codec, 1);
254
255 /* initiate offset cancellation */
256 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
257 twl4030_write(codec, TWL4030_REG_ANAMICL,
258 anamicl | TWL4030_CNCL_OFFSET_START);
259
260 /* wait for offset cancellation to complete */
261 do {
262 /* this takes a little while, so don't slam i2c */
263 udelay(2000);
264 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
265 TWL4030_REG_ANAMICL);
266 } while ((i++ < 100) &&
267 ((byte & TWL4030_CNCL_OFFSET_START) ==
268 TWL4030_CNCL_OFFSET_START));
269
270 /* Make sure that the reg_cache has the same value as the HW */
271 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
272
273 /* anti-pop when changing analog gain */
274 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
275 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
276 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
277
278 /* toggle CODECPDZ as per TRM */
279 twl4030_codec_enable(codec, 0);
280 twl4030_codec_enable(codec, 1);
281}
282
7393958f
PU		 283/*
284 * Unconditional power down
285 */
006f367e
PU		 286static void twl4030_power_down(struct snd_soc_codec *codec)
287{
288 /* power down */
289 twl4030_codec_enable(codec, 0);
290}
291
5e98a464 292/* Earpiece */
1a787e7a
JS		 293static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
294 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
295 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
296 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
297 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
298};
5e98a464 299
2a6f5c58 300/* PreDrive Left */
1a787e7a
JS		 301static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
302 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
303 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
304 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
305 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
306};
2a6f5c58
PU		 307
308/* PreDrive Right */
1a787e7a
JS		 309static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
310 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
311 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
312 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
313 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
314};
2a6f5c58 315
dfad21a2 316/* Headset Left */
1a787e7a
JS		 317static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
318 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
319 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
320 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
321};
dfad21a2
PU		 322
323/* Headset Right */
1a787e7a
JS		 324static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
326 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
327 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
328};
dfad21a2 329
5152d8c2 330/* Carkit Left */
1a787e7a
JS		 331static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
332 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
333 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
334 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
335};
5152d8c2
PU		 336
337/* Carkit Right */
1a787e7a
JS		 338static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
339 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
341 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
342};
5152d8c2 343
df339804
PU		 344/* Handsfree Left */
345static const char *twl4030_handsfreel_texts[] =
1a787e7a 346 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 347
348static const struct soc_enum twl4030_handsfreel_enum =
349 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
350 ARRAY_SIZE(twl4030_handsfreel_texts),
351 twl4030_handsfreel_texts);
352
353static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
354SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
355
0f89bdca
PU		 356/* Handsfree Left virtual mute */
357static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
358 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
359
df339804
PU		 360/* Handsfree Right */
361static const char *twl4030_handsfreer_texts[] =
1a787e7a 362 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 363
364static const struct soc_enum twl4030_handsfreer_enum =
365 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
366 ARRAY_SIZE(twl4030_handsfreer_texts),
367 twl4030_handsfreer_texts);
368
369static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
370SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
371
0f89bdca
PU		 372/* Handsfree Right virtual mute */
373static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
374 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
375
376f7839
PU		 376/* Vibra */
377/* Vibra audio path selection */
378static const char *twl4030_vibra_texts[] =
379 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
380
381static const struct soc_enum twl4030_vibra_enum =
382 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
383 ARRAY_SIZE(twl4030_vibra_texts),
384 twl4030_vibra_texts);
385
386static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
387SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
388
389/* Vibra path selection: local vibrator (PWM) or audio driven */
390static const char *twl4030_vibrapath_texts[] =
391 {"Local vibrator", "Audio"};
392
393static const struct soc_enum twl4030_vibrapath_enum =
394 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
395 ARRAY_SIZE(twl4030_vibrapath_texts),
396 twl4030_vibrapath_texts);
397
398static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
399SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
400
276c6222 401/* Left analog microphone selection */
97b8096d 402static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 403 SOC_DAPM_SINGLE("Main Mic Capture Switch",
404 TWL4030_REG_ANAMICL, 0, 1, 0),
405 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
406 TWL4030_REG_ANAMICL, 1, 1, 0),
407 SOC_DAPM_SINGLE("AUXL Capture Switch",
408 TWL4030_REG_ANAMICL, 2, 1, 0),
409 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
410 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 411};
276c6222
PU		 412
413/* Right analog microphone selection */
97b8096d 414static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 415 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
416 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 417};
276c6222
PU		 418
419/* TX1 L/R Analog/Digital microphone selection */
420static const char *twl4030_micpathtx1_texts[] =
421 {"Analog", "Digimic0"};
422
423static const struct soc_enum twl4030_micpathtx1_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
425 ARRAY_SIZE(twl4030_micpathtx1_texts),
426 twl4030_micpathtx1_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
429SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
430
431/* TX2 L/R Analog/Digital microphone selection */
432static const char *twl4030_micpathtx2_texts[] =
433 {"Analog", "Digimic1"};
434
435static const struct soc_enum twl4030_micpathtx2_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
437 ARRAY_SIZE(twl4030_micpathtx2_texts),
438 twl4030_micpathtx2_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
441SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
442
7393958f
PU		 443/* Analog bypass for AudioR1 */
444static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
445 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
446
447/* Analog bypass for AudioL1 */
448static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
449 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
450
451/* Analog bypass for AudioR2 */
452static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
453 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
454
455/* Analog bypass for AudioL2 */
456static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
457 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
458
fcd274a3
LCM		 459/* Analog bypass for Voice */
460static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
461 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
462
6bab83fd
PU		 463/* Digital bypass gain, 0 mutes the bypass */
464static const unsigned int twl4030_dapm_dbypass_tlv[] = {
465 TLV_DB_RANGE_HEAD(2),
466 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
467 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
468};
469
470/* Digital bypass left (TX1L -> RX2L) */
471static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
472 SOC_DAPM_SINGLE_TLV("Volume",
473 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
474 twl4030_dapm_dbypass_tlv);
475
476/* Digital bypass right (TX1R -> RX2R) */
477static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
478 SOC_DAPM_SINGLE_TLV("Volume",
479 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
480 twl4030_dapm_dbypass_tlv);
481
ee8f6894
LCM		 482/*
483 * Voice Sidetone GAIN volume control:
484 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
485 */
486static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
487
488/* Digital bypass voice: sidetone (VUL -> VDL)*/
489static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
490 SOC_DAPM_SINGLE_TLV("Volume",
491 TWL4030_REG_VSTPGA, 0, 0x29, 0,
492 twl4030_dapm_dbypassv_tlv);
493
276c6222
PU		 494static int micpath_event(struct snd_soc_dapm_widget *w,
495 struct snd_kcontrol *kcontrol, int event)
496{
497 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
498 unsigned char adcmicsel, micbias_ctl;
499
500 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
501 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
502 /* Prepare the bits for the given TX path:
503 * shift_l == 0: TX1 microphone path
504 * shift_l == 2: TX2 microphone path */
505 if (e->shift_l) {
506 /* TX2 microphone path */
507 if (adcmicsel & TWL4030_TX2IN_SEL)
508 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
509 else
510 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
511 } else {
512 /* TX1 microphone path */
513 if (adcmicsel & TWL4030_TX1IN_SEL)
514 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
515 else
516 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
517 }
518
519 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
520
521 return 0;
522}
523
9008adf9
PU		 524/*
525 * Output PGA builder:
526 * Handle the muting and unmuting of the given output (turning off the
527 * amplifier associated with the output pin)
528 * On mute bypass the reg_cache and mute the volume
529 * On unmute: restore the register content
530 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
531 */
532#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
533static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
534 struct snd_kcontrol *kcontrol, int event) \
535{ \
536 u8 reg_val; \
537 \
538 switch (event) { \
539 case SND_SOC_DAPM_POST_PMU: \
540 twl4030_write(w->codec, reg, \
541 twl4030_read_reg_cache(w->codec, reg)); \
542 break; \
543 case SND_SOC_DAPM_POST_PMD: \
544 reg_val = twl4030_read_reg_cache(w->codec, reg); \
545 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
546 reg_val & (~mask), \
547 reg); \
548 break; \
549 } \
550 return 0; \
551}
552
553TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
554TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
555TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
556TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
557TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
558
5a2e9a48 559static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 560{
49d92c7d
SM		 561 unsigned char hs_ctl;
562
5a2e9a48 563 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 564
5a2e9a48
PU		 565 if (ramp) {
566 /* HF ramp-up */
567 hs_ctl |= TWL4030_HF_CTL_REF_EN;
568 twl4030_write(codec, reg, hs_ctl);
569 udelay(10);
49d92c7d 570 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 571 twl4030_write(codec, reg, hs_ctl);
572 udelay(40);
49d92c7d 573 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 575 twl4030_write(codec, reg, hs_ctl);
49d92c7d 576 } else {
5a2e9a48
PU		 577 /* HF ramp-down */
578 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
579 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
580 twl4030_write(codec, reg, hs_ctl);
581 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
582 twl4030_write(codec, reg, hs_ctl);
583 udelay(40);
584 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
585 twl4030_write(codec, reg, hs_ctl);
49d92c7d 586 }
5a2e9a48 587}
49d92c7d 588
5a2e9a48
PU		 589static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
590 struct snd_kcontrol *kcontrol, int event)
591{
592 switch (event) {
593 case SND_SOC_DAPM_POST_PMU:
594 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
595 break;
596 case SND_SOC_DAPM_POST_PMD:
597 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
598 break;
599 }
600 return 0;
601}
602
603static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
604 struct snd_kcontrol *kcontrol, int event)
605{
606 switch (event) {
607 case SND_SOC_DAPM_POST_PMU:
608 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
609 break;
610 case SND_SOC_DAPM_POST_PMD:
611 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
612 break;
613 }
49d92c7d
SM		 614 return 0;
615}
616
6943c92e 617static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 618{
4e49ffd1
CVJ		 619 struct snd_soc_device *socdev = codec->socdev;
620 struct twl4030_setup_data *setup = socdev->codec_data;
621
aad749e5 622 unsigned char hs_gain, hs_pop;
6943c92e
PU		 623 struct twl4030_priv *twl4030 = codec->private_data;
624 /* Base values for ramp delay calculation: 2^19 - 2^26 */
625 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
626 8388608, 16777216, 33554432, 67108864};
aad749e5 627
6943c92e
PU		 628 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
629 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 630
4e49ffd1
CVJ		 631 /* Enable external mute control, this dramatically reduces
632 * the pop-noise */
633 if (setup && setup->hs_extmute) {
634 if (setup->set_hs_extmute) {
635 setup->set_hs_extmute(1);
636 } else {
637 hs_pop |= TWL4030_EXTMUTE;
638 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
639 }
640 }
641
6943c92e
PU		 642 if (ramp) {
643 /* Headset ramp-up according to the TRM */
aad749e5 644 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 645 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
646 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 647 hs_pop |= TWL4030_RAMP_EN;
6943c92e 648 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 649 /* Wait ramp delay time + 1, so the VMID can settle */
650 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
651 twl4030->sysclk) + 1);
6943c92e
PU		 652 } else {
653 /* Headset ramp-down _not_ according to
654 * the TRM, but in a way that it is working */
aad749e5 655 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 656 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
657 /* Wait ramp delay time + 1, so the VMID can settle */
658 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
659 twl4030->sysclk) + 1);
aad749e5
PU		 660 /* Bypass the reg_cache to mute the headset */
661 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
662 hs_gain & (~0x0f),
663 TWL4030_REG_HS_GAIN_SET);
6943c92e 664
aad749e5 665 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 666 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
667 }
4e49ffd1
CVJ		 668
669 /* Disable external mute */
670 if (setup && setup->hs_extmute) {
671 if (setup->set_hs_extmute) {
672 setup->set_hs_extmute(0);
673 } else {
674 hs_pop &= ~TWL4030_EXTMUTE;
675 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
676 }
677 }
6943c92e
PU		 678}
679
680static int headsetlpga_event(struct snd_soc_dapm_widget *w,
681 struct snd_kcontrol *kcontrol, int event)
682{
683 struct twl4030_priv *twl4030 = w->codec->private_data;
684
685 switch (event) {
686 case SND_SOC_DAPM_POST_PMU:
687 /* Do the ramp-up only once */
688 if (!twl4030->hsr_enabled)
689 headset_ramp(w->codec, 1);
690
691 twl4030->hsl_enabled = 1;
692 break;
693 case SND_SOC_DAPM_POST_PMD:
694 /* Do the ramp-down only if both headsetL/R is disabled */
695 if (!twl4030->hsr_enabled)
696 headset_ramp(w->codec, 0);
697
698 twl4030->hsl_enabled = 0;
699 break;
700 }
701 return 0;
702}
703
704static int headsetrpga_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 struct twl4030_priv *twl4030 = w->codec->private_data;
708
709 switch (event) {
710 case SND_SOC_DAPM_POST_PMU:
711 /* Do the ramp-up only once */
712 if (!twl4030->hsl_enabled)
713 headset_ramp(w->codec, 1);
714
715 twl4030->hsr_enabled = 1;
716 break;
717 case SND_SOC_DAPM_POST_PMD:
718 /* Do the ramp-down only if both headsetL/R is disabled */
719 if (!twl4030->hsl_enabled)
720 headset_ramp(w->codec, 0);
721
722 twl4030->hsr_enabled = 0;
aad749e5
PU		 723 break;
724 }
725 return 0;
726}
727
7393958f
PU		 728static int bypass_event(struct snd_soc_dapm_widget *w,
729 struct snd_kcontrol *kcontrol, int event)
730{
731 struct soc_mixer_control *m =
732 (struct soc_mixer_control *)w->kcontrols->private_value;
733 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 734 unsigned char reg, misc;
7393958f
PU		 735
736 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd 737
30808ca7
LCM		 738 /*
739 * bypass_state[0:3] - analog HiFi bypass
740 * bypass_state[4] - analog voice bypass
741 * bypass_state[5] - digital voice bypass
742 * bypass_state[6:7] - digital HiFi bypass
743 */
744 if (m->reg == TWL4030_REG_VSTPGA) {
745 /* Voice digital bypass */
746 if (reg)
747 twl4030->bypass_state |= (1 << 5);
748 else
749 twl4030->bypass_state &= ~(1 << 5);
750 } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
6bab83fd
PU		 751 /* Analog bypass */
752 if (reg & (1 << m->shift))
753 twl4030->bypass_state |=
754 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
755 else
756 twl4030->bypass_state &=
757 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 758 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
759 /* Analog voice bypass */
760 if (reg & (1 << m->shift))
761 twl4030->bypass_state |= (1 << 4);
762 else
763 twl4030->bypass_state &= ~(1 << 4);
6bab83fd
PU		 764 } else {
765 /* Digital bypass */
766 if (reg & (0x7 << m->shift))
ee8f6894 767 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 768 else
ee8f6894 769 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 770 }
7393958f 771
fcd274a3
LCM		 772 /* Enable master analog loopback mode if any analog switch is enabled*/
773 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
774 if (twl4030->bypass_state & 0x1F)
775 misc |= TWL4030_FMLOOP_EN;
776 else
777 misc &= ~TWL4030_FMLOOP_EN;
778 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
779
7393958f
PU		 780 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
781 if (twl4030->bypass_state)
782 twl4030_codec_mute(w->codec, 0);
783 else
784 twl4030_codec_mute(w->codec, 1);
785 }
786 return 0;
787}
788
b0bd53a7
PU		 789/*
790 * Some of the gain controls in TWL (mostly those which are associated with
791 * the outputs) are implemented in an interesting way:
792 * 0x0 : Power down (mute)
793 * 0x1 : 6dB
794 * 0x2 : 0 dB
795 * 0x3 : -6 dB
796 * Inverting not going to help with these.
797 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
798 */
799#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
800 xinvert, tlv_array) \
801{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
802 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
803 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
804 .tlv.p = (tlv_array), \
805 .info = snd_soc_info_volsw, \
806 .get = snd_soc_get_volsw_twl4030, \
807 .put = snd_soc_put_volsw_twl4030, \
808 .private_value = (unsigned long)&(struct soc_mixer_control) \
809 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
810 .max = xmax, .invert = xinvert} }
811#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
812 xinvert, tlv_array) \
813{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
814 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
815 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
816 .tlv.p = (tlv_array), \
817 .info = snd_soc_info_volsw_2r, \
818 .get = snd_soc_get_volsw_r2_twl4030,\
819 .put = snd_soc_put_volsw_r2_twl4030, \
820 .private_value = (unsigned long)&(struct soc_mixer_control) \
821 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 822 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 823#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
824 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
825 xinvert, tlv_array)
826
827static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
828 struct snd_ctl_elem_value *ucontrol)
829{
830 struct soc_mixer_control *mc =
831 (struct soc_mixer_control *)kcontrol->private_value;
832 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
833 unsigned int reg = mc->reg;
834 unsigned int shift = mc->shift;
835 unsigned int rshift = mc->rshift;
836 int max = mc->max;
837 int mask = (1 << fls(max)) - 1;
838
839 ucontrol->value.integer.value[0] =
840 (snd_soc_read(codec, reg) >> shift) & mask;
841 if (ucontrol->value.integer.value[0])
842 ucontrol->value.integer.value[0] =
843 max + 1 - ucontrol->value.integer.value[0];
844
845 if (shift != rshift) {
846 ucontrol->value.integer.value[1] =
847 (snd_soc_read(codec, reg) >> rshift) & mask;
848 if (ucontrol->value.integer.value[1])
849 ucontrol->value.integer.value[1] =
850 max + 1 - ucontrol->value.integer.value[1];
851 }
852
853 return 0;
854}
855
856static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
857 struct snd_ctl_elem_value *ucontrol)
858{
859 struct soc_mixer_control *mc =
860 (struct soc_mixer_control *)kcontrol->private_value;
861 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
862 unsigned int reg = mc->reg;
863 unsigned int shift = mc->shift;
864 unsigned int rshift = mc->rshift;
865 int max = mc->max;
866 int mask = (1 << fls(max)) - 1;
867 unsigned short val, val2, val_mask;
868
869 val = (ucontrol->value.integer.value[0] & mask);
870
871 val_mask = mask << shift;
872 if (val)
873 val = max + 1 - val;
874 val = val << shift;
875 if (shift != rshift) {
876 val2 = (ucontrol->value.integer.value[1] & mask);
877 val_mask |= mask << rshift;
878 if (val2)
879 val2 = max + 1 - val2;
880 val |= val2 << rshift;
881 }
882 return snd_soc_update_bits(codec, reg, val_mask, val);
883}
884
885static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
886 struct snd_ctl_elem_value *ucontrol)
887{
888 struct soc_mixer_control *mc =
889 (struct soc_mixer_control *)kcontrol->private_value;
890 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
891 unsigned int reg = mc->reg;
892 unsigned int reg2 = mc->rreg;
893 unsigned int shift = mc->shift;
894 int max = mc->max;
895 int mask = (1<<fls(max))-1;
896
897 ucontrol->value.integer.value[0] =
898 (snd_soc_read(codec, reg) >> shift) & mask;
899 ucontrol->value.integer.value[1] =
900 (snd_soc_read(codec, reg2) >> shift) & mask;
901
902 if (ucontrol->value.integer.value[0])
903 ucontrol->value.integer.value[0] =
904 max + 1 - ucontrol->value.integer.value[0];
905 if (ucontrol->value.integer.value[1])
906 ucontrol->value.integer.value[1] =
907 max + 1 - ucontrol->value.integer.value[1];
908
909 return 0;
910}
911
912static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
913 struct snd_ctl_elem_value *ucontrol)
914{
915 struct soc_mixer_control *mc =
916 (struct soc_mixer_control *)kcontrol->private_value;
917 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
918 unsigned int reg = mc->reg;
919 unsigned int reg2 = mc->rreg;
920 unsigned int shift = mc->shift;
921 int max = mc->max;
922 int mask = (1 << fls(max)) - 1;
923 int err;
924 unsigned short val, val2, val_mask;
925
926 val_mask = mask << shift;
927 val = (ucontrol->value.integer.value[0] & mask);
928 val2 = (ucontrol->value.integer.value[1] & mask);
929
930 if (val)
931 val = max + 1 - val;
932 if (val2)
933 val2 = max + 1 - val2;
934
935 val = val << shift;
936 val2 = val2 << shift;
937
938 err = snd_soc_update_bits(codec, reg, val_mask, val);
939 if (err < 0)
940 return err;
941
942 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
943 return err;
944}
945
b74bd40f
LCM		 946/* Codec operation modes */
947static const char *twl4030_op_modes_texts[] = {
948 "Option 2 (voice/audio)", "Option 1 (audio)"
949};
950
951static const struct soc_enum twl4030_op_modes_enum =
952 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
953 ARRAY_SIZE(twl4030_op_modes_texts),
954 twl4030_op_modes_texts);
955
423c238d 956static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 957 struct snd_ctl_elem_value *ucontrol)
958{
959 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
960 struct twl4030_priv *twl4030 = codec->private_data;
961 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
962 unsigned short val;
963 unsigned short mask, bitmask;
964
965 if (twl4030->configured) {
966 printk(KERN_ERR "twl4030 operation mode cannot be "
967 "changed on-the-fly\n");
968 return -EBUSY;
969 }
970
971 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
972 ;
973 if (ucontrol->value.enumerated.item[0] > e->max - 1)
974 return -EINVAL;
975
976 val = ucontrol->value.enumerated.item[0] << e->shift_l;
977 mask = (bitmask - 1) << e->shift_l;
978 if (e->shift_l != e->shift_r) {
979 if (ucontrol->value.enumerated.item[1] > e->max - 1)
980 return -EINVAL;
981 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
982 mask |= (bitmask - 1) << e->shift_r;
983 }
984
985 return snd_soc_update_bits(codec, e->reg, mask, val);
986}
987
c10b82cf
PU		 988/*
989 * FGAIN volume control:
990 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
991 */
d889a72c 992static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 993
0d33ea0b
PU		 994/*
995 * CGAIN volume control:
996 * 0 dB to 12 dB in 6 dB steps
997 * value 2 and 3 means 12 dB
998 */
d889a72c
PU		 999static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1000
1a787e7a
JS		 1001/*
1002 * Voice Downlink GAIN volume control:
1003 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1004 */
1005static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1006
d889a72c
PU		 1007/*
1008 * Analog playback gain
1009 * -24 dB to 12 dB in 2 dB steps
1010 */
1011static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1012
4290239c
PU		 1013/*
1014 * Gain controls tied to outputs
1015 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1016 */
1017static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1018
18cc8d8d
JS		 1019/*
1020 * Gain control for earpiece amplifier
1021 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1022 */
1023static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1024
381a22b5
PU		 1025/*
1026 * Capture gain after the ADCs
1027 * from 0 dB to 31 dB in 1 dB steps
1028 */
1029static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1030
5920b453
GI		 1031/*
1032 * Gain control for input amplifiers
1033 * 0 dB to 30 dB in 6 dB steps
1034 */
1035static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1036
328d0a13
LCM		 1037/* AVADC clock priority */
1038static const char *twl4030_avadc_clk_priority_texts[] = {
1039 "Voice high priority", "HiFi high priority"
1040};
1041
1042static const struct soc_enum twl4030_avadc_clk_priority_enum =
1043 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1044 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1045 twl4030_avadc_clk_priority_texts);
1046
89492be8
PU		 1047static const char *twl4030_rampdelay_texts[] = {
1048 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1049 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1050 "3495/2581/1748 ms"
1051};
1052
1053static const struct soc_enum twl4030_rampdelay_enum =
1054 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1055 ARRAY_SIZE(twl4030_rampdelay_texts),
1056 twl4030_rampdelay_texts);
1057
376f7839
PU		 1058/* Vibra H-bridge direction mode */
1059static const char *twl4030_vibradirmode_texts[] = {
1060 "Vibra H-bridge direction", "Audio data MSB",
1061};
1062
1063static const struct soc_enum twl4030_vibradirmode_enum =
1064 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1065 ARRAY_SIZE(twl4030_vibradirmode_texts),
1066 twl4030_vibradirmode_texts);
1067
1068/* Vibra H-bridge direction */
1069static const char *twl4030_vibradir_texts[] = {
1070 "Positive polarity", "Negative polarity",
1071};
1072
1073static const struct soc_enum twl4030_vibradir_enum =
1074 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1075 ARRAY_SIZE(twl4030_vibradir_texts),
1076 twl4030_vibradir_texts);
1077
cc17557e 1078static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1079 /* Codec operation mode control */
1080 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1081 snd_soc_get_enum_double,
1082 snd_soc_put_twl4030_opmode_enum_double),
1083
d889a72c
PU		 1084 /* Common playback gain controls */
1085 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1086 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1087 0, 0x3f, 0, digital_fine_tlv),
1088 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1089 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1090 0, 0x3f, 0, digital_fine_tlv),
1091
1092 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1093 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1094 6, 0x2, 0, digital_coarse_tlv),
1095 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1096 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1097 6, 0x2, 0, digital_coarse_tlv),
1098
1099 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1100 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1101 3, 0x12, 1, analog_tlv),
1102 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1103 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1104 3, 0x12, 1, analog_tlv),
44c55870
PU		 1105 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1106 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1107 1, 1, 0),
1108 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1109 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1110 1, 1, 0),
381a22b5 1111
1a787e7a
JS		 1112 /* Common voice downlink gain controls */
1113 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1114 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1115
1116 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1117 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1118
1119 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1120 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1121
4290239c
PU		 1122 /* Separate output gain controls */
1123 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1124 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1125 4, 3, 0, output_tvl),
1126
1127 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1128 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1129
1130 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1131 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1132 4, 3, 0, output_tvl),
1133
1134 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1135 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1136
381a22b5 1137 /* Common capture gain controls */
276c6222 1138 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1139 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1140 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1141 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1142 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1143 0, 0x1f, 0, digital_capture_tlv),
5920b453 1144
276c6222 1145 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1146 0, 3, 5, 0, input_gain_tlv),
89492be8 1147
328d0a13
LCM		 1148 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1149
89492be8 1150 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1151
1152 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1153 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1154};
1155
cc17557e 1156static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1157 /* Left channel inputs */
1158 SND_SOC_DAPM_INPUT("MAINMIC"),
1159 SND_SOC_DAPM_INPUT("HSMIC"),
1160 SND_SOC_DAPM_INPUT("AUXL"),
1161 SND_SOC_DAPM_INPUT("CARKITMIC"),
1162 /* Right channel inputs */
1163 SND_SOC_DAPM_INPUT("SUBMIC"),
1164 SND_SOC_DAPM_INPUT("AUXR"),
1165 /* Digital microphones (Stereo) */
1166 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1167 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1168
1169 /* Outputs */
cc17557e
SS		 1170 SND_SOC_DAPM_OUTPUT("OUTL"),
1171 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1172 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1173 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1174 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1175 SND_SOC_DAPM_OUTPUT("HSOL"),
1176 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1177 SND_SOC_DAPM_OUTPUT("CARKITL"),
1178 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1179 SND_SOC_DAPM_OUTPUT("HFL"),
1180 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1181 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1182
53b5047d 1183 /* DACs */
b4852b79 1184 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1185 SND_SOC_NOPM, 0, 0),
b4852b79 1186 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1187 SND_SOC_NOPM, 0, 0),
b4852b79 1188 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1189 SND_SOC_NOPM, 0, 0),
b4852b79 1190 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1191 SND_SOC_NOPM, 0, 0),
1a787e7a 1192 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1193 SND_SOC_NOPM, 0, 0),
cc17557e 1194
7393958f
PU		 1195 /* Analog bypasses */
1196 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1197 &twl4030_dapm_abypassr1_control, bypass_event,
1198 SND_SOC_DAPM_POST_REG),
1199 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1200 &twl4030_dapm_abypassl1_control,
1201 bypass_event, SND_SOC_DAPM_POST_REG),
1202 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1203 &twl4030_dapm_abypassr2_control,
1204 bypass_event, SND_SOC_DAPM_POST_REG),
1205 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1206 &twl4030_dapm_abypassl2_control,
1207 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1208 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1209 &twl4030_dapm_abypassv_control,
1210 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1211
6bab83fd
PU		 1212 /* Digital bypasses */
1213 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1214 &twl4030_dapm_dbypassl_control, bypass_event,
1215 SND_SOC_DAPM_POST_REG),
1216 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1217 &twl4030_dapm_dbypassr_control, bypass_event,
1218 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1219 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1220 &twl4030_dapm_dbypassv_control, bypass_event,
1221 SND_SOC_DAPM_POST_REG),
6bab83fd 1222
4005d39a
PU		 1223 /* Digital mixers, power control for the physical DACs */
1224 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1225 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1226 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1227 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1228 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1229 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1230 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1231 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1232 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1233 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1234
1235 /* Analog mixers, power control for the physical PGAs */
1236 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1237 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1238 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1239 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1240 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1241 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1242 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1243 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1244 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1245 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1246
1a787e7a 1247 /* Output MIXER controls */
5e98a464 1248 /* Earpiece */
1a787e7a
JS		 1249 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1250 &twl4030_dapm_earpiece_controls[0],
1251 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1252 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1253 0, 0, NULL, 0, earpiecepga_event,
1254 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1255 /* PreDrivL/R */
1a787e7a
JS		 1256 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1257 &twl4030_dapm_predrivel_controls[0],
1258 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1259 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1260 0, 0, NULL, 0, predrivelpga_event,
1261 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1262 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1263 &twl4030_dapm_predriver_controls[0],
1264 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1265 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1266 0, 0, NULL, 0, predriverpga_event,
1267 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1268 /* HeadsetL/R */
6943c92e 1269 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1270 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1271 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1272 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1273 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1274 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1275 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1276 &twl4030_dapm_hsor_controls[0],
1277 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1278 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1279 0, 0, NULL, 0, headsetrpga_event,
1280 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1281 /* CarkitL/R */
1a787e7a
JS		 1282 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1283 &twl4030_dapm_carkitl_controls[0],
1284 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1285 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1286 0, 0, NULL, 0, carkitlpga_event,
1287 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1288 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1289 &twl4030_dapm_carkitr_controls[0],
1290 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1291 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1292 0, 0, NULL, 0, carkitrpga_event,
1293 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1294
1295 /* Output MUX controls */
df339804 1296 /* HandsfreeL/R */
5a2e9a48
PU		 1297 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1298 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1299 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1300 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1301 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1302 0, 0, NULL, 0, handsfreelpga_event,
1303 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1304 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1305 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1306 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1307 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1308 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1309 0, 0, NULL, 0, handsfreerpga_event,
1310 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1311 /* Vibra */
1312 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1313 &twl4030_dapm_vibra_control),
1314 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1315 &twl4030_dapm_vibrapath_control),
5e98a464 1316
276c6222
PU		 1317 /* Introducing four virtual ADC, since TWL4030 have four channel for
1318 capture */
1319 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1320 SND_SOC_NOPM, 0, 0),
1321 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1322 SND_SOC_NOPM, 0, 0),
1323 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1324 SND_SOC_NOPM, 0, 0),
1325 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1326 SND_SOC_NOPM, 0, 0),
1327
1328 /* Analog/Digital mic path selection.
1329 TX1 Left/Right: either analog Left/Right or Digimic0
1330 TX2 Left/Right: either analog Left/Right or Digimic1 */
1331 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1332 &twl4030_dapm_micpathtx1_control, micpath_event,
1333 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1334 SND_SOC_DAPM_POST_REG),
1335 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1336 &twl4030_dapm_micpathtx2_control, micpath_event,
1337 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1338 SND_SOC_DAPM_POST_REG),
1339
97b8096d 1340 /* Analog input mixers for the capture amplifiers */
9028935d 1341 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1342 TWL4030_REG_ANAMICL, 4, 0,
1343 &twl4030_dapm_analoglmic_controls[0],
1344 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1345 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1346 TWL4030_REG_ANAMICR, 4, 0,
1347 &twl4030_dapm_analogrmic_controls[0],
1348 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1349
fb2a2f84
PU		 1350 SND_SOC_DAPM_PGA("ADC Physical Left",
1351 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1352 SND_SOC_DAPM_PGA("ADC Physical Right",
1353 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1354
1355 SND_SOC_DAPM_PGA("Digimic0 Enable",
1356 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1357 SND_SOC_DAPM_PGA("Digimic1 Enable",
1358 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1359
1360 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1361 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1362 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1363
cc17557e
SS		 1364};
1365
1366static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1367 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1368 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1369 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1370 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1371 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1372
1373 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1374 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1375 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1376 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1377 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1378
5e98a464
PU		 1379 /* Internal playback routings */
1380 /* Earpiece */
4005d39a
PU		 1381 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1382 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1383 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1384 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1385 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1386 /* PreDrivL */
4005d39a
PU		 1387 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1388 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1389 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1390 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1391 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1392 /* PreDrivR */
4005d39a
PU		 1393 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1394 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1395 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1396 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1397 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1398 /* HeadsetL */
4005d39a
PU		 1399 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1400 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1401 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1402 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1403 /* HeadsetR */
4005d39a
PU		 1404 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1405 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1406 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1407 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1408 /* CarkitL */
4005d39a
PU		 1409 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1410 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1411 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1412 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1413 /* CarkitR */
4005d39a
PU		 1414 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1415 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1416 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1417 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1418 /* HandsfreeL */
4005d39a
PU		 1419 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1420 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1421 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1422 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1423 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1424 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1425 /* HandsfreeR */
4005d39a
PU		 1426 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1427 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1428 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1429 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1430 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1431 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1432 /* Vibra */
1433 {"Vibra Mux", "AudioL1", "DAC Left1"},
1434 {"Vibra Mux", "AudioR1", "DAC Right1"},
1435 {"Vibra Mux", "AudioL2", "DAC Left2"},
1436 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1437
cc17557e 1438 /* outputs */
4005d39a
PU		 1439 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1440 {"OUTR", NULL, "Analog R2 Playback Mixer"},
9008adf9
PU		 1441 {"EARPIECE", NULL, "Earpiece PGA"},
1442 {"PREDRIVEL", NULL, "PredriveL PGA"},
1443 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1444 {"HSOL", NULL, "HeadsetL PGA"},
1445 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1446 {"CARKITL", NULL, "CarkitL PGA"},
1447 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1448 {"HFL", NULL, "HandsfreeL PGA"},
1449 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1450 {"Vibra Route", "Audio", "Vibra Mux"},
1451 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1452
276c6222 1453 /* Capture path */
9028935d
PU		 1454 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1455 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1456 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1457 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1458
9028935d
PU		 1459 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1460 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1461
9028935d
PU		 1462 {"ADC Physical Left", NULL, "Analog Left"},
1463 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1464
1465 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1466 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1467
1468 /* TX1 Left capture path */
fb2a2f84 1469 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1470 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1471 /* TX1 Right capture path */
fb2a2f84 1472 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1473 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1474 /* TX2 Left capture path */
fb2a2f84 1475 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1476 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1477 /* TX2 Right capture path */
fb2a2f84 1478 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1479 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1480
1481 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1482 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1483 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1484 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1485
7393958f 1486 /* Analog bypass routes */
9028935d
PU		 1487 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1488 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1489 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1490 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1491 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f
PU		 1492
1493 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1494 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1495 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1496 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1497 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1498
6bab83fd
PU		 1499 /* Digital bypass routes */
1500 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1501 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1502 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1503
4005d39a
PU		 1504 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1505 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1506 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1507
cc17557e
SS		 1508};
1509
1510static int twl4030_add_widgets(struct snd_soc_codec *codec)
1511{
1512 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1513 ARRAY_SIZE(twl4030_dapm_widgets));
1514
1515 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1516
1517 snd_soc_dapm_new_widgets(codec);
1518 return 0;
1519}
1520
cc17557e
SS		 1521static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1522 enum snd_soc_bias_level level)
1523{
7393958f
PU		 1524 struct twl4030_priv *twl4030 = codec->private_data;
1525
cc17557e
SS		 1526 switch (level) {
1527 case SND_SOC_BIAS_ON:
7393958f 1528 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1529 break;
1530 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1531 twl4030_power_up(codec);
1532 if (twl4030->bypass_state)
1533 twl4030_codec_mute(codec, 0);
1534 else
1535 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1536 break;
1537 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1538 twl4030_power_up(codec);
1539 if (twl4030->bypass_state)
1540 twl4030_codec_mute(codec, 0);
1541 else
1542 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1543 break;
1544 case SND_SOC_BIAS_OFF:
1545 twl4030_power_down(codec);
1546 break;
1547 }
1548 codec->bias_level = level;
1549
1550 return 0;
1551}
1552
6b87a91f
PU		 1553static void twl4030_constraints(struct twl4030_priv *twl4030,
1554 struct snd_pcm_substream *mst_substream)
1555{
1556 struct snd_pcm_substream *slv_substream;
1557
1558 /* Pick the stream, which need to be constrained */
1559 if (mst_substream == twl4030->master_substream)
1560 slv_substream = twl4030->slave_substream;
1561 else if (mst_substream == twl4030->slave_substream)
1562 slv_substream = twl4030->master_substream;
1563 else /* This should not happen.. */
1564 return;
1565
1566 /* Set the constraints according to the already configured stream */
1567 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1568 SNDRV_PCM_HW_PARAM_RATE,
1569 twl4030->rate,
1570 twl4030->rate);
1571
1572 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1573 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1574 twl4030->sample_bits,
1575 twl4030->sample_bits);
1576
1577 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1578 SNDRV_PCM_HW_PARAM_CHANNELS,
1579 twl4030->channels,
1580 twl4030->channels);
1581}
1582
8a1f936a
PU		 1583/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1584 * capture has to be enabled/disabled. */
1585static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1586 int enable)
1587{
1588 u8 reg, mask;
1589
1590 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1591
1592 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1593 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1594 else
1595 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1596
1597 if (enable)
1598 reg |= mask;
1599 else
1600 reg &= ~mask;
1601
1602 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1603}
1604
d6648da1
PU		 1605static int twl4030_startup(struct snd_pcm_substream *substream,
1606 struct snd_soc_dai *dai)
7220b9f4
PU		 1607{
1608 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1609 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1610 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1611 struct twl4030_priv *twl4030 = codec->private_data;
1612
7220b9f4 1613 if (twl4030->master_substream) {
7220b9f4 1614 twl4030->slave_substream = substream;
6b87a91f
PU		 1615 /* The DAI has one configuration for playback and capture, so
1616 * if the DAI has been already configured then constrain this
1617 * substream to match it. */
1618 if (twl4030->configured)
1619 twl4030_constraints(twl4030, twl4030->master_substream);
1620 } else {
8a1f936a
PU		 1621 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1622 TWL4030_OPTION_1)) {
1623 /* In option2 4 channel is not supported, set the
1624 * constraint for the first stream for channels, the
1625 * second stream will 'inherit' this cosntraint */
1626 snd_pcm_hw_constraint_minmax(substream->runtime,
1627 SNDRV_PCM_HW_PARAM_CHANNELS,
1628 2, 2);
1629 }
7220b9f4 1630 twl4030->master_substream = substream;
6b87a91f 1631 }
7220b9f4
PU		 1632
1633 return 0;
1634}
1635
d6648da1
PU		 1636static void twl4030_shutdown(struct snd_pcm_substream *substream,
1637 struct snd_soc_dai *dai)
7220b9f4
PU		 1638{
1639 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1640 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1641 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1642 struct twl4030_priv *twl4030 = codec->private_data;
1643
1644 if (twl4030->master_substream == substream)
1645 twl4030->master_substream = twl4030->slave_substream;
1646
1647 twl4030->slave_substream = NULL;
6b87a91f
PU		 1648
1649 /* If all streams are closed, or the remaining stream has not yet
1650 * been configured than set the DAI as not configured. */
1651 if (!twl4030->master_substream)
1652 twl4030->configured = 0;
1653 else if (!twl4030->master_substream->runtime->channels)
1654 twl4030->configured = 0;
8a1f936a
PU		 1655
1656 /* If the closing substream had 4 channel, do the necessary cleanup */
1657 if (substream->runtime->channels == 4)
1658 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1659}
1660
cc17557e 1661static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1662 struct snd_pcm_hw_params *params,
1663 struct snd_soc_dai *dai)
cc17557e
SS		 1664{
1665 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1666 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1667 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1668 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1669 u8 mode, old_mode, format, old_format;
1670
8a1f936a
PU		 1671 /* If the substream has 4 channel, do the necessary setup */
1672 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1673 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1674 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1675
1676 /* Safety check: are we in the correct operating mode and
1677 * the interface is in TDM mode? */
1678 if ((mode & TWL4030_OPTION_1) &&
1679 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1680 twl4030_tdm_enable(codec, substream->stream, 1);
1681 else
1682 return -EINVAL;
1683 }
1684
6b87a91f
PU		 1685 if (twl4030->configured)
1686 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1687 return 0;
1688
cc17557e
SS		 1689 /* bit rate */
1690 old_mode = twl4030_read_reg_cache(codec,
1691 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1692 mode = old_mode & ~TWL4030_APLL_RATE;
1693
1694 switch (params_rate(params)) {
1695 case 8000:
1696 mode |= TWL4030_APLL_RATE_8000;
1697 break;
1698 case 11025:
1699 mode |= TWL4030_APLL_RATE_11025;
1700 break;
1701 case 12000:
1702 mode |= TWL4030_APLL_RATE_12000;
1703 break;
1704 case 16000:
1705 mode |= TWL4030_APLL_RATE_16000;
1706 break;
1707 case 22050:
1708 mode |= TWL4030_APLL_RATE_22050;
1709 break;
1710 case 24000:
1711 mode |= TWL4030_APLL_RATE_24000;
1712 break;
1713 case 32000:
1714 mode |= TWL4030_APLL_RATE_32000;
1715 break;
1716 case 44100:
1717 mode |= TWL4030_APLL_RATE_44100;
1718 break;
1719 case 48000:
1720 mode |= TWL4030_APLL_RATE_48000;
1721 break;
103f211d
PU		 1722 case 96000:
1723 mode |= TWL4030_APLL_RATE_96000;
1724 break;
cc17557e
SS		 1725 default:
1726 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1727 params_rate(params));
1728 return -EINVAL;
1729 }
1730
1731 if (mode != old_mode) {
1732 /* change rate and set CODECPDZ */
7393958f 1733 twl4030_codec_enable(codec, 0);
cc17557e 1734 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1735 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1736 }
1737
1738 /* sample size */
1739 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1740 format = old_format;
1741 format &= ~TWL4030_DATA_WIDTH;
1742 switch (params_format(params)) {
1743 case SNDRV_PCM_FORMAT_S16_LE:
1744 format |= TWL4030_DATA_WIDTH_16S_16W;
1745 break;
1746 case SNDRV_PCM_FORMAT_S24_LE:
1747 format |= TWL4030_DATA_WIDTH_32S_24W;
1748 break;
1749 default:
1750 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1751 params_format(params));
1752 return -EINVAL;
1753 }
1754
1755 if (format != old_format) {
1756
1757 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1758 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1759
1760 /* change format */
1761 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1762
1763 /* set CODECPDZ afterwards */
db04e2c5 1764 twl4030_codec_enable(codec, 1);
cc17557e 1765 }
6b87a91f
PU		 1766
1767 /* Store the important parameters for the DAI configuration and set
1768 * the DAI as configured */
1769 twl4030->configured = 1;
1770 twl4030->rate = params_rate(params);
1771 twl4030->sample_bits = hw_param_interval(params,
1772 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1773 twl4030->channels = params_channels(params);
1774
1775 /* If both playback and capture streams are open, and one of them
1776 * is setting the hw parameters right now (since we are here), set
1777 * constraints to the other stream to match the current one. */
1778 if (twl4030->slave_substream)
1779 twl4030_constraints(twl4030, substream);
1780
cc17557e
SS		 1781 return 0;
1782}
1783
1784static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1785 int clk_id, unsigned int freq, int dir)
1786{
1787 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1788 struct twl4030_priv *twl4030 = codec->private_data;
d8707cec 1789 u8 apll_ctrl;
cc17557e 1790
d8707cec
PU		 1791 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1792 apll_ctrl &= ~TWL4030_APLL_INFREQ;
cc17557e
SS		 1793 switch (freq) {
1794 case 19200000:
d8707cec 1795 apll_ctrl |= TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1796 twl4030->sysclk = 19200;
cc17557e
SS		 1797 break;
1798 case 26000000:
d8707cec 1799 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1800 twl4030->sysclk = 26000;
cc17557e
SS		 1801 break;
1802 case 38400000:
d8707cec 1803 apll_ctrl |= TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1804 twl4030->sysclk = 38400;
cc17557e
SS		 1805 break;
1806 default:
1807 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1808 freq);
1809 return -EINVAL;
1810 }
1811
d8707cec 1812 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
cc17557e
SS		 1813
1814 return 0;
1815}
1816
1817static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1818 unsigned int fmt)
1819{
1820 struct snd_soc_codec *codec = codec_dai->codec;
1821 u8 old_format, format;
1822
1823 /* get format */
1824 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1825 format = old_format;
1826
1827 /* set master/slave audio interface */
1828 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1829 case SND_SOC_DAIFMT_CBM_CFM:
1830 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1831 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1832 break;
1833 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1834 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1835 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1836 break;
1837 default:
1838 return -EINVAL;
1839 }
1840
1841 /* interface format */
1842 format &= ~TWL4030_AIF_FORMAT;
1843 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1844 case SND_SOC_DAIFMT_I2S:
1845 format |= TWL4030_AIF_FORMAT_CODEC;
1846 break;
8a1f936a
PU		 1847 case SND_SOC_DAIFMT_DSP_A:
1848 format |= TWL4030_AIF_FORMAT_TDM;
1849 break;
cc17557e
SS		 1850 default:
1851 return -EINVAL;
1852 }
1853
1854 if (format != old_format) {
1855
1856 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1857 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1858
1859 /* change format */
1860 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1861
1862 /* set CODECPDZ afterwards */
db04e2c5 1863 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1864 }
1865
1866 return 0;
1867}
1868
68140443
LCM		 1869static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1870{
1871 struct snd_soc_codec *codec = dai->codec;
1872 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1873
1874 if (tristate)
1875 reg |= TWL4030_AIF_TRI_EN;
1876 else
1877 reg &= ~TWL4030_AIF_TRI_EN;
1878
1879 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1880}
1881
b7a755a8
MLC		 1882/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1883 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1884static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1885 int enable)
1886{
1887 u8 reg, mask;
1888
1889 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1890
1891 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1892 mask = TWL4030_ARXL1_VRX_EN;
1893 else
1894 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1895
1896 if (enable)
1897 reg |= mask;
1898 else
1899 reg &= ~mask;
1900
1901 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1902}
1903
7154b3e8
JS		 1904static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1905 struct snd_soc_dai *dai)
1906{
1907 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1908 struct snd_soc_device *socdev = rtd->socdev;
1909 struct snd_soc_codec *codec = socdev->card->codec;
1910 u8 infreq;
1911 u8 mode;
1912
1913 /* If the system master clock is not 26MHz, the voice PCM interface is
1914 * not avilable.
1915 */
1916 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1917 & TWL4030_APLL_INFREQ;
1918
1919 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1920 printk(KERN_ERR "TWL4030 voice startup: "
1921 "MCLK is not 26MHz, call set_sysclk() on init\n");
1922 return -EINVAL;
1923 }
1924
1925 /* If the codec mode is not option2, the voice PCM interface is not
1926 * avilable.
1927 */
1928 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1929 & TWL4030_OPT_MODE;
1930
1931 if (mode != TWL4030_OPTION_2) {
1932 printk(KERN_ERR "TWL4030 voice startup: "
1933 "the codec mode is not option2\n");
1934 return -EINVAL;
1935 }
1936
1937 return 0;
1938}
1939
b7a755a8
MLC		 1940static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1941 struct snd_soc_dai *dai)
1942{
1943 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1944 struct snd_soc_device *socdev = rtd->socdev;
1945 struct snd_soc_codec *codec = socdev->card->codec;
1946
1947 /* Enable voice digital filters */
1948 twl4030_voice_enable(codec, substream->stream, 0);
1949}
1950
7154b3e8
JS		 1951static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1952 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1953{
1954 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1955 struct snd_soc_device *socdev = rtd->socdev;
1956 struct snd_soc_codec *codec = socdev->card->codec;
1957 u8 old_mode, mode;
1958
b7a755a8
MLC		 1959 /* Enable voice digital filters */
1960 twl4030_voice_enable(codec, substream->stream, 1);
1961
7154b3e8
JS		 1962 /* bit rate */
1963 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1964 & ~(TWL4030_CODECPDZ);
1965 mode = old_mode;
1966
1967 switch (params_rate(params)) {
1968 case 8000:
1969 mode &= ~(TWL4030_SEL_16K);
1970 break;
1971 case 16000:
1972 mode |= TWL4030_SEL_16K;
1973 break;
1974 default:
1975 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1976 params_rate(params));
1977 return -EINVAL;
1978 }
1979
1980 if (mode != old_mode) {
1981 /* change rate and set CODECPDZ */
1982 twl4030_codec_enable(codec, 0);
1983 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1984 twl4030_codec_enable(codec, 1);
1985 }
1986
1987 return 0;
1988}
1989
1990static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1991 int clk_id, unsigned int freq, int dir)
1992{
1993 struct snd_soc_codec *codec = codec_dai->codec;
d8707cec 1994 u8 apll_ctrl;
7154b3e8 1995
d8707cec
PU		 1996 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1997 apll_ctrl &= ~TWL4030_APLL_INFREQ;
7154b3e8
JS		 1998 switch (freq) {
1999 case 26000000:
d8707cec 2000 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
7154b3e8
JS		 2001 break;
2002 default:
2003 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
2004 freq);
2005 return -EINVAL;
2006 }
2007
d8707cec 2008 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
7154b3e8
JS		 2009
2010 return 0;
2011}
2012
2013static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2014 unsigned int fmt)
2015{
2016 struct snd_soc_codec *codec = codec_dai->codec;
2017 u8 old_format, format;
2018
2019 /* get format */
2020 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2021 format = old_format;
2022
2023 /* set master/slave audio interface */
2024 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2025 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2026 format &= ~(TWL4030_VIF_SLAVE_EN);
2027 break;
2028 case SND_SOC_DAIFMT_CBS_CFS:
2029 format |= TWL4030_VIF_SLAVE_EN;
2030 break;
2031 default:
2032 return -EINVAL;
2033 }
2034
2035 /* clock inversion */
2036 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2037 case SND_SOC_DAIFMT_IB_NF:
2038 format &= ~(TWL4030_VIF_FORMAT);
2039 break;
2040 case SND_SOC_DAIFMT_NB_IF:
2041 format |= TWL4030_VIF_FORMAT;
2042 break;
2043 default:
2044 return -EINVAL;
2045 }
2046
2047 if (format != old_format) {
2048 /* change format and set CODECPDZ */
2049 twl4030_codec_enable(codec, 0);
2050 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2051 twl4030_codec_enable(codec, 1);
2052 }
2053
2054 return 0;
2055}
2056
68140443
LCM		 2057static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2058{
2059 struct snd_soc_codec *codec = dai->codec;
2060 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2061
2062 if (tristate)
2063 reg |= TWL4030_VIF_TRI_EN;
2064 else
2065 reg &= ~TWL4030_VIF_TRI_EN;
2066
2067 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2068}
2069
bbba9444 2070#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2071#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2072
10d9e3d9 2073static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2074 .startup = twl4030_startup,
2075 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2076 .hw_params = twl4030_hw_params,
2077 .set_sysclk = twl4030_set_dai_sysclk,
2078 .set_fmt = twl4030_set_dai_fmt,
68140443 2079 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2080};
2081
7154b3e8
JS		 2082static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2083 .startup = twl4030_voice_startup,
b7a755a8 2084 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2085 .hw_params = twl4030_voice_hw_params,
2086 .set_sysclk = twl4030_voice_set_dai_sysclk,
2087 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2088 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2089};
2090
2091struct snd_soc_dai twl4030_dai[] = {
2092{
cc17557e
SS		 2093 .name = "twl4030",
2094 .playback = {
b4852b79 2095 .stream_name = "HiFi Playback",
cc17557e 2096 .channels_min = 2,
8a1f936a 2097 .channels_max = 4,
31ad0f31 2098 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2099 .formats = TWL4030_FORMATS,},
2100 .capture = {
2101 .stream_name = "Capture",
2102 .channels_min = 2,
8a1f936a 2103 .channels_max = 4,
cc17557e
SS		 2104 .rates = TWL4030_RATES,
2105 .formats = TWL4030_FORMATS,},
10d9e3d9 2106 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2107},
2108{
2109 .name = "twl4030 Voice",
2110 .playback = {
b4852b79 2111 .stream_name = "Voice Playback",
7154b3e8
JS		 2112 .channels_min = 1,
2113 .channels_max = 1,
2114 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2115 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2116 .capture = {
2117 .stream_name = "Capture",
2118 .channels_min = 1,
2119 .channels_max = 2,
2120 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2121 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2122 .ops = &twl4030_dai_voice_ops,
2123},
cc17557e
SS		 2124};
2125EXPORT_SYMBOL_GPL(twl4030_dai);
2126
7a1fecf5 2127static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2128{
2129 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2130 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2131
2132 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2133
2134 return 0;
2135}
2136
7a1fecf5 2137static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2138{
2139 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2140 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2141
2142 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2143 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2144 return 0;
2145}
2146
7a1fecf5 2147static struct snd_soc_codec *twl4030_codec;
cc17557e 2148
7a1fecf5 2149static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2150{
7a1fecf5 2151 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
9da28c7b 2152 struct twl4030_setup_data *setup = socdev->codec_data;
7a1fecf5
PU		 2153 struct snd_soc_codec *codec;
2154 struct twl4030_priv *twl4030;
2155 int ret;
cc17557e 2156
7a1fecf5 2157 BUG_ON(!twl4030_codec);
cc17557e 2158
7a1fecf5
PU		 2159 codec = twl4030_codec;
2160 twl4030 = codec->private_data;
2161 socdev->card->codec = codec;
cc17557e 2162
9da28c7b
PU		 2163 /* Configuration for headset ramp delay from setup data */
2164 if (setup) {
2165 unsigned char hs_pop;
2166
2167 if (setup->sysclk)
2168 twl4030->sysclk = setup->sysclk;
2169 else
2170 twl4030->sysclk = 26000;
2171
2172 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2173 hs_pop &= ~TWL4030_RAMP_DELAY;
2174 hs_pop |= (setup->ramp_delay_value << 2);
2175 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2176 } else {
2177 twl4030->sysclk = 26000;
2178 }
2179
cc17557e
SS		 2180 /* register pcms */
2181 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2182 if (ret < 0) {
7a1fecf5
PU		 2183 dev_err(&pdev->dev, "failed to create pcms\n");
2184 return ret;
cc17557e
SS		 2185 }
2186
3e8e1952
IM		 2187 snd_soc_add_controls(codec, twl4030_snd_controls,
2188 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2189 twl4030_add_widgets(codec);
2190
968a6025 2191 ret = snd_soc_init_card(socdev);
cc17557e 2192 if (ret < 0) {
7a1fecf5 2193 dev_err(&pdev->dev, "failed to register card\n");
cc17557e
SS		 2194 goto card_err;
2195 }
2196
7a1fecf5 2197 return 0;
cc17557e
SS		 2198
2199card_err:
2200 snd_soc_free_pcms(socdev);
2201 snd_soc_dapm_free(socdev);
7a1fecf5 2202
cc17557e
SS		 2203 return ret;
2204}
2205
7a1fecf5 2206static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2207{
2208 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2209 struct snd_soc_codec *codec = socdev->card->codec;
2210
2211 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2212 snd_soc_free_pcms(socdev);
2213 snd_soc_dapm_free(socdev);
2214 kfree(codec->private_data);
2215 kfree(codec);
2216
2217 return 0;
2218}
2219
2220static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2221{
2222 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2223 struct snd_soc_codec *codec;
7393958f 2224 struct twl4030_priv *twl4030;
7a1fecf5 2225 int ret;
cc17557e 2226
7a1fecf5
PU		 2227 if (!pdata || !(pdata->audio_mclk == 19200000 ||
2228 pdata->audio_mclk == 26000000 ||
2229 pdata->audio_mclk == 38400000)) {
2230 dev_err(&pdev->dev, "Invalid platform_data\n");
2231 return -EINVAL;
2232 }
cc17557e 2233
7393958f
PU		 2234 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2235 if (twl4030 == NULL) {
7a1fecf5 2236 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2237 return -ENOMEM;
2238 }
2239
7a1fecf5 2240 codec = &twl4030->codec;
7393958f 2241 codec->private_data = twl4030;
7a1fecf5
PU		 2242 codec->dev = &pdev->dev;
2243 twl4030_dai[0].dev = &pdev->dev;
2244 twl4030_dai[1].dev = &pdev->dev;
2245
cc17557e
SS		 2246 mutex_init(&codec->mutex);
2247 INIT_LIST_HEAD(&codec->dapm_widgets);
2248 INIT_LIST_HEAD(&codec->dapm_paths);
2249
7a1fecf5
PU		 2250 codec->name = "twl4030";
2251 codec->owner = THIS_MODULE;
2252 codec->read = twl4030_read_reg_cache;
2253 codec->write = twl4030_write;
2254 codec->set_bias_level = twl4030_set_bias_level;
2255 codec->dai = twl4030_dai;
2256 codec->num_dai = ARRAY_SIZE(twl4030_dai),
2257 codec->reg_cache_size = sizeof(twl4030_reg);
2258 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2259 GFP_KERNEL);
2260 if (codec->reg_cache == NULL) {
2261 ret = -ENOMEM;
2262 goto error_cache;
2263 }
2264
2265 platform_set_drvdata(pdev, twl4030);
2266 twl4030_codec = codec;
2267
2268 /* Set the defaults, and power up the codec */
2269 twl4030_init_chip(codec);
2270 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2271
2272 ret = snd_soc_register_codec(codec);
2273 if (ret != 0) {
2274 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2275 goto error_codec;
2276 }
2277
2278 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2279 if (ret != 0) {
2280 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2281 snd_soc_unregister_codec(codec);
2282 goto error_codec;
2283 }
cc17557e
SS		 2284
2285 return 0;
7a1fecf5
PU		 2286
2287error_codec:
2288 twl4030_power_down(codec);
2289 kfree(codec->reg_cache);
2290error_cache:
2291 kfree(twl4030);
2292 return ret;
cc17557e
SS		 2293}
2294
7a1fecf5 2295static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2296{
7a1fecf5 2297 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2298
7a1fecf5 2299 kfree(twl4030);
cc17557e 2300
7a1fecf5 2301 twl4030_codec = NULL;
cc17557e
SS		 2302 return 0;
2303}
2304
7a1fecf5
PU		 2305MODULE_ALIAS("platform:twl4030_codec_audio");
2306
2307static struct platform_driver twl4030_codec_driver = {
2308 .probe = twl4030_codec_probe,
2309 .remove = __devexit_p(twl4030_codec_remove),
2310 .driver = {
2311 .name = "twl4030_codec_audio",
2312 .owner = THIS_MODULE,
2313 },
cc17557e 2314};
cc17557e 2315
24e07db8 2316static int __init twl4030_modinit(void)
64089b84 2317{
7a1fecf5 2318 return platform_driver_register(&twl4030_codec_driver);
64089b84 2319}
24e07db8 2320module_init(twl4030_modinit);
64089b84
MB		 2321
2322static void __exit twl4030_exit(void)
2323{
7a1fecf5 2324 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2325}
2326module_exit(twl4030_exit);
2327
7a1fecf5
PU		 2328struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2329 .probe = twl4030_soc_probe,
2330 .remove = twl4030_soc_remove,
2331 .suspend = twl4030_soc_suspend,
2332 .resume = twl4030_soc_resume,
2333};
2334EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2335
cc17557e
SS		 2336MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2337MODULE_AUTHOR("Steve Sakoman");
2338MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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