projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: CS4270: export de-emphasis filter as ALSA control
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
7a1fecf5
PU		 123 struct snd_soc_codec codec;
124
7393958f 125 unsigned int codec_powered;
2845fa13 126 unsigned int apll_enabled;
7220b9f4
PU		 127
128 struct snd_pcm_substream *master_substream;
129 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 130
131 unsigned int configured;
132 unsigned int rate;
133 unsigned int sample_bits;
134 unsigned int channels;
6943c92e
PU		 135
136 unsigned int sysclk;
137
138 /* Headset output state handling */
139 unsigned int hsl_enabled;
140 unsigned int hsr_enabled;
7393958f
PU		 141};
142
cc17557e
SS		 143/*
144 * read twl4030 register cache
145 */
146static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
147 unsigned int reg)
148{
d08664fd 149 u8 *cache = codec->reg_cache;
cc17557e 150
91432e97
IM		 151 if (reg >= TWL4030_CACHEREGNUM)
152 return -EIO;
153
cc17557e
SS		 154 return cache[reg];
155}
156
157/*
158 * write twl4030 register cache
159 */
160static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
161 u8 reg, u8 value)
162{
163 u8 *cache = codec->reg_cache;
164
165 if (reg >= TWL4030_CACHEREGNUM)
166 return;
167 cache[reg] = value;
168}
169
170/*
171 * write to the twl4030 register space
172 */
173static int twl4030_write(struct snd_soc_codec *codec,
174 unsigned int reg, unsigned int value)
175{
176 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 177 if (likely(reg < TWL4030_REG_SW_SHADOW))
178 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
179 reg);
180 else
181 return 0;
cc17557e
SS		 182}
183
db04e2c5 184static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 185{
7393958f 186 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 187 int mode;
cc17557e 188
7393958f
PU		 189 if (enable == twl4030->codec_powered)
190 return;
191
db04e2c5 192 if (enable)
7a1fecf5 193 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 194 else
7a1fecf5 195 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 196
7a1fecf5
PU		 197 if (mode >= 0) {
198 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
199 twl4030->codec_powered = enable;
200 }
cc17557e
SS		 201
202 /* REVISIT: this delay is present in TI sample drivers */
203 /* but there seems to be no TRM requirement for it */
204 udelay(10);
205}
206
207static void twl4030_init_chip(struct snd_soc_codec *codec)
208{
16a30fbb 209 u8 *cache = codec->reg_cache;
cc17557e
SS		 210 int i;
211
212 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 213 twl4030_codec_enable(codec, 0);
cc17557e
SS		 214
215 /* set all audio section registers to reasonable defaults */
216 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 217 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 218
219}
220
2845fa13 221static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
7393958f
PU		 222{
223 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 224 int status;
7393958f 225
2845fa13 226 if (enable == twl4030->apll_enabled)
7393958f
PU		 227 return;
228
2845fa13 229 if (enable)
7393958f 230 /* Enable PLL */
7a1fecf5 231 status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
2845fa13
PU		 232 else
233 /* Disable PLL */
234 status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
7a1fecf5
PU		 235
236 if (status >= 0)
237 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
7393958f 238
2845fa13 239 twl4030->apll_enabled = enable;
7393958f
PU		 240}
241
006f367e
PU		 242static void twl4030_power_up(struct snd_soc_codec *codec)
243{
7393958f 244 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 245 u8 anamicl, regmisc1, byte;
246 int i = 0;
247
7393958f
PU		 248 if (twl4030->codec_powered)
249 return;
250
006f367e
PU		 251 /* set CODECPDZ to turn on codec */
252 twl4030_codec_enable(codec, 1);
253
254 /* initiate offset cancellation */
255 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
256 twl4030_write(codec, TWL4030_REG_ANAMICL,
257 anamicl | TWL4030_CNCL_OFFSET_START);
258
259 /* wait for offset cancellation to complete */
260 do {
261 /* this takes a little while, so don't slam i2c */
262 udelay(2000);
263 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
264 TWL4030_REG_ANAMICL);
265 } while ((i++ < 100) &&
266 ((byte & TWL4030_CNCL_OFFSET_START) ==
267 TWL4030_CNCL_OFFSET_START));
268
269 /* Make sure that the reg_cache has the same value as the HW */
270 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
271
272 /* anti-pop when changing analog gain */
273 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
274 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
275 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
276
277 /* toggle CODECPDZ as per TRM */
278 twl4030_codec_enable(codec, 0);
279 twl4030_codec_enable(codec, 1);
280}
281
7393958f
PU		 282/*
283 * Unconditional power down
284 */
006f367e
PU		 285static void twl4030_power_down(struct snd_soc_codec *codec)
286{
287 /* power down */
288 twl4030_codec_enable(codec, 0);
289}
290
5e98a464 291/* Earpiece */
1a787e7a
JS		 292static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
293 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
294 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
295 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
296 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
297};
5e98a464 298
2a6f5c58 299/* PreDrive Left */
1a787e7a
JS		 300static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
301 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
302 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
303 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
304 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
305};
2a6f5c58
PU		 306
307/* PreDrive Right */
1a787e7a
JS		 308static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
309 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
310 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
311 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
312 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
313};
2a6f5c58 314
dfad21a2 315/* Headset Left */
1a787e7a
JS		 316static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
317 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
318 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
319 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
320};
dfad21a2
PU		 321
322/* Headset Right */
1a787e7a
JS		 323static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
324 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
325 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
326 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
327};
dfad21a2 328
5152d8c2 329/* Carkit Left */
1a787e7a
JS		 330static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
331 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
332 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
333 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
334};
5152d8c2
PU		 335
336/* Carkit Right */
1a787e7a
JS		 337static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
338 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
340 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
341};
5152d8c2 342
df339804
PU		 343/* Handsfree Left */
344static const char *twl4030_handsfreel_texts[] =
1a787e7a 345 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 346
347static const struct soc_enum twl4030_handsfreel_enum =
348 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
349 ARRAY_SIZE(twl4030_handsfreel_texts),
350 twl4030_handsfreel_texts);
351
352static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
353SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
354
0f89bdca
PU		 355/* Handsfree Left virtual mute */
356static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
357 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
358
df339804
PU		 359/* Handsfree Right */
360static const char *twl4030_handsfreer_texts[] =
1a787e7a 361 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 362
363static const struct soc_enum twl4030_handsfreer_enum =
364 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
365 ARRAY_SIZE(twl4030_handsfreer_texts),
366 twl4030_handsfreer_texts);
367
368static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
369SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
370
0f89bdca
PU		 371/* Handsfree Right virtual mute */
372static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
373 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
374
376f7839
PU		 375/* Vibra */
376/* Vibra audio path selection */
377static const char *twl4030_vibra_texts[] =
378 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
379
380static const struct soc_enum twl4030_vibra_enum =
381 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
382 ARRAY_SIZE(twl4030_vibra_texts),
383 twl4030_vibra_texts);
384
385static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
386SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
387
388/* Vibra path selection: local vibrator (PWM) or audio driven */
389static const char *twl4030_vibrapath_texts[] =
390 {"Local vibrator", "Audio"};
391
392static const struct soc_enum twl4030_vibrapath_enum =
393 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
394 ARRAY_SIZE(twl4030_vibrapath_texts),
395 twl4030_vibrapath_texts);
396
397static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
398SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
399
276c6222 400/* Left analog microphone selection */
97b8096d 401static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 402 SOC_DAPM_SINGLE("Main Mic Capture Switch",
403 TWL4030_REG_ANAMICL, 0, 1, 0),
404 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
405 TWL4030_REG_ANAMICL, 1, 1, 0),
406 SOC_DAPM_SINGLE("AUXL Capture Switch",
407 TWL4030_REG_ANAMICL, 2, 1, 0),
408 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
409 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 410};
276c6222
PU		 411
412/* Right analog microphone selection */
97b8096d 413static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 414 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
415 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 416};
276c6222
PU		 417
418/* TX1 L/R Analog/Digital microphone selection */
419static const char *twl4030_micpathtx1_texts[] =
420 {"Analog", "Digimic0"};
421
422static const struct soc_enum twl4030_micpathtx1_enum =
423 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
424 ARRAY_SIZE(twl4030_micpathtx1_texts),
425 twl4030_micpathtx1_texts);
426
427static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
428SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
429
430/* TX2 L/R Analog/Digital microphone selection */
431static const char *twl4030_micpathtx2_texts[] =
432 {"Analog", "Digimic1"};
433
434static const struct soc_enum twl4030_micpathtx2_enum =
435 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
436 ARRAY_SIZE(twl4030_micpathtx2_texts),
437 twl4030_micpathtx2_texts);
438
439static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
440SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
441
7393958f
PU		 442/* Analog bypass for AudioR1 */
443static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
444 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
445
446/* Analog bypass for AudioL1 */
447static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
448 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
449
450/* Analog bypass for AudioR2 */
451static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
452 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
453
454/* Analog bypass for AudioL2 */
455static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
456 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
457
fcd274a3
LCM		 458/* Analog bypass for Voice */
459static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
460 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
461
6bab83fd
PU		 462/* Digital bypass gain, 0 mutes the bypass */
463static const unsigned int twl4030_dapm_dbypass_tlv[] = {
464 TLV_DB_RANGE_HEAD(2),
465 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
466 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
467};
468
469/* Digital bypass left (TX1L -> RX2L) */
470static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
471 SOC_DAPM_SINGLE_TLV("Volume",
472 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
473 twl4030_dapm_dbypass_tlv);
474
475/* Digital bypass right (TX1R -> RX2R) */
476static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
477 SOC_DAPM_SINGLE_TLV("Volume",
478 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
479 twl4030_dapm_dbypass_tlv);
480
ee8f6894
LCM		 481/*
482 * Voice Sidetone GAIN volume control:
483 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
484 */
485static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
486
487/* Digital bypass voice: sidetone (VUL -> VDL)*/
488static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
489 SOC_DAPM_SINGLE_TLV("Volume",
490 TWL4030_REG_VSTPGA, 0, 0x29, 0,
491 twl4030_dapm_dbypassv_tlv);
492
276c6222
PU		 493static int micpath_event(struct snd_soc_dapm_widget *w,
494 struct snd_kcontrol *kcontrol, int event)
495{
496 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
497 unsigned char adcmicsel, micbias_ctl;
498
499 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
500 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
501 /* Prepare the bits for the given TX path:
502 * shift_l == 0: TX1 microphone path
503 * shift_l == 2: TX2 microphone path */
504 if (e->shift_l) {
505 /* TX2 microphone path */
506 if (adcmicsel & TWL4030_TX2IN_SEL)
507 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
508 else
509 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
510 } else {
511 /* TX1 microphone path */
512 if (adcmicsel & TWL4030_TX1IN_SEL)
513 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
514 else
515 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
516 }
517
518 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
519
520 return 0;
521}
522
9008adf9
PU		 523/*
524 * Output PGA builder:
525 * Handle the muting and unmuting of the given output (turning off the
526 * amplifier associated with the output pin)
527 * On mute bypass the reg_cache and mute the volume
528 * On unmute: restore the register content
529 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
530 */
531#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
532static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
533 struct snd_kcontrol *kcontrol, int event) \
534{ \
535 u8 reg_val; \
536 \
537 switch (event) { \
538 case SND_SOC_DAPM_POST_PMU: \
539 twl4030_write(w->codec, reg, \
540 twl4030_read_reg_cache(w->codec, reg)); \
541 break; \
542 case SND_SOC_DAPM_POST_PMD: \
543 reg_val = twl4030_read_reg_cache(w->codec, reg); \
544 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
545 reg_val & (~mask), \
546 reg); \
547 break; \
548 } \
549 return 0; \
550}
551
552TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
553TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
554TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
555TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
556TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
557
5a2e9a48 558static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 559{
49d92c7d
SM		 560 unsigned char hs_ctl;
561
5a2e9a48 562 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 563
5a2e9a48
PU		 564 if (ramp) {
565 /* HF ramp-up */
566 hs_ctl |= TWL4030_HF_CTL_REF_EN;
567 twl4030_write(codec, reg, hs_ctl);
568 udelay(10);
49d92c7d 569 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 570 twl4030_write(codec, reg, hs_ctl);
571 udelay(40);
49d92c7d 572 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 573 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 574 twl4030_write(codec, reg, hs_ctl);
49d92c7d 575 } else {
5a2e9a48
PU		 576 /* HF ramp-down */
577 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
578 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
579 twl4030_write(codec, reg, hs_ctl);
580 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
581 twl4030_write(codec, reg, hs_ctl);
582 udelay(40);
583 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
584 twl4030_write(codec, reg, hs_ctl);
49d92c7d 585 }
5a2e9a48 586}
49d92c7d 587
5a2e9a48
PU		 588static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
589 struct snd_kcontrol *kcontrol, int event)
590{
591 switch (event) {
592 case SND_SOC_DAPM_POST_PMU:
593 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
594 break;
595 case SND_SOC_DAPM_POST_PMD:
596 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
597 break;
598 }
599 return 0;
600}
601
602static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
603 struct snd_kcontrol *kcontrol, int event)
604{
605 switch (event) {
606 case SND_SOC_DAPM_POST_PMU:
607 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
608 break;
609 case SND_SOC_DAPM_POST_PMD:
610 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
611 break;
612 }
49d92c7d
SM		 613 return 0;
614}
615
6943c92e 616static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 617{
4e49ffd1
CVJ		 618 struct snd_soc_device *socdev = codec->socdev;
619 struct twl4030_setup_data *setup = socdev->codec_data;
620
aad749e5 621 unsigned char hs_gain, hs_pop;
6943c92e
PU		 622 struct twl4030_priv *twl4030 = codec->private_data;
623 /* Base values for ramp delay calculation: 2^19 - 2^26 */
624 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
625 8388608, 16777216, 33554432, 67108864};
aad749e5 626
6943c92e
PU		 627 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
628 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 629
4e49ffd1
CVJ		 630 /* Enable external mute control, this dramatically reduces
631 * the pop-noise */
632 if (setup && setup->hs_extmute) {
633 if (setup->set_hs_extmute) {
634 setup->set_hs_extmute(1);
635 } else {
636 hs_pop |= TWL4030_EXTMUTE;
637 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
638 }
639 }
640
6943c92e
PU		 641 if (ramp) {
642 /* Headset ramp-up according to the TRM */
aad749e5 643 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 644 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
645 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 646 hs_pop |= TWL4030_RAMP_EN;
6943c92e 647 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 648 /* Wait ramp delay time + 1, so the VMID can settle */
649 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
650 twl4030->sysclk) + 1);
6943c92e
PU		 651 } else {
652 /* Headset ramp-down _not_ according to
653 * the TRM, but in a way that it is working */
aad749e5 654 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 655 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
656 /* Wait ramp delay time + 1, so the VMID can settle */
657 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
658 twl4030->sysclk) + 1);
aad749e5
PU		 659 /* Bypass the reg_cache to mute the headset */
660 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
661 hs_gain & (~0x0f),
662 TWL4030_REG_HS_GAIN_SET);
6943c92e 663
aad749e5 664 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 665 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
666 }
4e49ffd1
CVJ		 667
668 /* Disable external mute */
669 if (setup && setup->hs_extmute) {
670 if (setup->set_hs_extmute) {
671 setup->set_hs_extmute(0);
672 } else {
673 hs_pop &= ~TWL4030_EXTMUTE;
674 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
675 }
676 }
6943c92e
PU		 677}
678
679static int headsetlpga_event(struct snd_soc_dapm_widget *w,
680 struct snd_kcontrol *kcontrol, int event)
681{
682 struct twl4030_priv *twl4030 = w->codec->private_data;
683
684 switch (event) {
685 case SND_SOC_DAPM_POST_PMU:
686 /* Do the ramp-up only once */
687 if (!twl4030->hsr_enabled)
688 headset_ramp(w->codec, 1);
689
690 twl4030->hsl_enabled = 1;
691 break;
692 case SND_SOC_DAPM_POST_PMD:
693 /* Do the ramp-down only if both headsetL/R is disabled */
694 if (!twl4030->hsr_enabled)
695 headset_ramp(w->codec, 0);
696
697 twl4030->hsl_enabled = 0;
698 break;
699 }
700 return 0;
701}
702
703static int headsetrpga_event(struct snd_soc_dapm_widget *w,
704 struct snd_kcontrol *kcontrol, int event)
705{
706 struct twl4030_priv *twl4030 = w->codec->private_data;
707
708 switch (event) {
709 case SND_SOC_DAPM_POST_PMU:
710 /* Do the ramp-up only once */
711 if (!twl4030->hsl_enabled)
712 headset_ramp(w->codec, 1);
713
714 twl4030->hsr_enabled = 1;
715 break;
716 case SND_SOC_DAPM_POST_PMD:
717 /* Do the ramp-down only if both headsetL/R is disabled */
718 if (!twl4030->hsl_enabled)
719 headset_ramp(w->codec, 0);
720
721 twl4030->hsr_enabled = 0;
aad749e5
PU		 722 break;
723 }
724 return 0;
725}
726
b0bd53a7
PU		 727/*
728 * Some of the gain controls in TWL (mostly those which are associated with
729 * the outputs) are implemented in an interesting way:
730 * 0x0 : Power down (mute)
731 * 0x1 : 6dB
732 * 0x2 : 0 dB
733 * 0x3 : -6 dB
734 * Inverting not going to help with these.
735 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
736 */
737#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
738 xinvert, tlv_array) \
739{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
740 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
741 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
742 .tlv.p = (tlv_array), \
743 .info = snd_soc_info_volsw, \
744 .get = snd_soc_get_volsw_twl4030, \
745 .put = snd_soc_put_volsw_twl4030, \
746 .private_value = (unsigned long)&(struct soc_mixer_control) \
747 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
748 .max = xmax, .invert = xinvert} }
749#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
750 xinvert, tlv_array) \
751{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
752 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
753 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
754 .tlv.p = (tlv_array), \
755 .info = snd_soc_info_volsw_2r, \
756 .get = snd_soc_get_volsw_r2_twl4030,\
757 .put = snd_soc_put_volsw_r2_twl4030, \
758 .private_value = (unsigned long)&(struct soc_mixer_control) \
759 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 760 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 761#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
762 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
763 xinvert, tlv_array)
764
765static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
766 struct snd_ctl_elem_value *ucontrol)
767{
768 struct soc_mixer_control *mc =
769 (struct soc_mixer_control *)kcontrol->private_value;
770 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
771 unsigned int reg = mc->reg;
772 unsigned int shift = mc->shift;
773 unsigned int rshift = mc->rshift;
774 int max = mc->max;
775 int mask = (1 << fls(max)) - 1;
776
777 ucontrol->value.integer.value[0] =
778 (snd_soc_read(codec, reg) >> shift) & mask;
779 if (ucontrol->value.integer.value[0])
780 ucontrol->value.integer.value[0] =
781 max + 1 - ucontrol->value.integer.value[0];
782
783 if (shift != rshift) {
784 ucontrol->value.integer.value[1] =
785 (snd_soc_read(codec, reg) >> rshift) & mask;
786 if (ucontrol->value.integer.value[1])
787 ucontrol->value.integer.value[1] =
788 max + 1 - ucontrol->value.integer.value[1];
789 }
790
791 return 0;
792}
793
794static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
795 struct snd_ctl_elem_value *ucontrol)
796{
797 struct soc_mixer_control *mc =
798 (struct soc_mixer_control *)kcontrol->private_value;
799 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
800 unsigned int reg = mc->reg;
801 unsigned int shift = mc->shift;
802 unsigned int rshift = mc->rshift;
803 int max = mc->max;
804 int mask = (1 << fls(max)) - 1;
805 unsigned short val, val2, val_mask;
806
807 val = (ucontrol->value.integer.value[0] & mask);
808
809 val_mask = mask << shift;
810 if (val)
811 val = max + 1 - val;
812 val = val << shift;
813 if (shift != rshift) {
814 val2 = (ucontrol->value.integer.value[1] & mask);
815 val_mask |= mask << rshift;
816 if (val2)
817 val2 = max + 1 - val2;
818 val |= val2 << rshift;
819 }
820 return snd_soc_update_bits(codec, reg, val_mask, val);
821}
822
823static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
824 struct snd_ctl_elem_value *ucontrol)
825{
826 struct soc_mixer_control *mc =
827 (struct soc_mixer_control *)kcontrol->private_value;
828 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
829 unsigned int reg = mc->reg;
830 unsigned int reg2 = mc->rreg;
831 unsigned int shift = mc->shift;
832 int max = mc->max;
833 int mask = (1<<fls(max))-1;
834
835 ucontrol->value.integer.value[0] =
836 (snd_soc_read(codec, reg) >> shift) & mask;
837 ucontrol->value.integer.value[1] =
838 (snd_soc_read(codec, reg2) >> shift) & mask;
839
840 if (ucontrol->value.integer.value[0])
841 ucontrol->value.integer.value[0] =
842 max + 1 - ucontrol->value.integer.value[0];
843 if (ucontrol->value.integer.value[1])
844 ucontrol->value.integer.value[1] =
845 max + 1 - ucontrol->value.integer.value[1];
846
847 return 0;
848}
849
850static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
851 struct snd_ctl_elem_value *ucontrol)
852{
853 struct soc_mixer_control *mc =
854 (struct soc_mixer_control *)kcontrol->private_value;
855 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
856 unsigned int reg = mc->reg;
857 unsigned int reg2 = mc->rreg;
858 unsigned int shift = mc->shift;
859 int max = mc->max;
860 int mask = (1 << fls(max)) - 1;
861 int err;
862 unsigned short val, val2, val_mask;
863
864 val_mask = mask << shift;
865 val = (ucontrol->value.integer.value[0] & mask);
866 val2 = (ucontrol->value.integer.value[1] & mask);
867
868 if (val)
869 val = max + 1 - val;
870 if (val2)
871 val2 = max + 1 - val2;
872
873 val = val << shift;
874 val2 = val2 << shift;
875
876 err = snd_soc_update_bits(codec, reg, val_mask, val);
877 if (err < 0)
878 return err;
879
880 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
881 return err;
882}
883
b74bd40f
LCM		 884/* Codec operation modes */
885static const char *twl4030_op_modes_texts[] = {
886 "Option 2 (voice/audio)", "Option 1 (audio)"
887};
888
889static const struct soc_enum twl4030_op_modes_enum =
890 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
891 ARRAY_SIZE(twl4030_op_modes_texts),
892 twl4030_op_modes_texts);
893
423c238d 894static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 895 struct snd_ctl_elem_value *ucontrol)
896{
897 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
898 struct twl4030_priv *twl4030 = codec->private_data;
899 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
900 unsigned short val;
901 unsigned short mask, bitmask;
902
903 if (twl4030->configured) {
904 printk(KERN_ERR "twl4030 operation mode cannot be "
905 "changed on-the-fly\n");
906 return -EBUSY;
907 }
908
909 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
910 ;
911 if (ucontrol->value.enumerated.item[0] > e->max - 1)
912 return -EINVAL;
913
914 val = ucontrol->value.enumerated.item[0] << e->shift_l;
915 mask = (bitmask - 1) << e->shift_l;
916 if (e->shift_l != e->shift_r) {
917 if (ucontrol->value.enumerated.item[1] > e->max - 1)
918 return -EINVAL;
919 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
920 mask |= (bitmask - 1) << e->shift_r;
921 }
922
923 return snd_soc_update_bits(codec, e->reg, mask, val);
924}
925
c10b82cf
PU		 926/*
927 * FGAIN volume control:
928 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
929 */
d889a72c 930static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 931
0d33ea0b
PU		 932/*
933 * CGAIN volume control:
934 * 0 dB to 12 dB in 6 dB steps
935 * value 2 and 3 means 12 dB
936 */
d889a72c
PU		 937static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
938
1a787e7a
JS		 939/*
940 * Voice Downlink GAIN volume control:
941 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
942 */
943static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
944
d889a72c
PU		 945/*
946 * Analog playback gain
947 * -24 dB to 12 dB in 2 dB steps
948 */
949static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 950
4290239c
PU		 951/*
952 * Gain controls tied to outputs
953 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
954 */
955static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
956
18cc8d8d
JS		 957/*
958 * Gain control for earpiece amplifier
959 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
960 */
961static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
962
381a22b5
PU		 963/*
964 * Capture gain after the ADCs
965 * from 0 dB to 31 dB in 1 dB steps
966 */
967static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
968
5920b453
GI		 969/*
970 * Gain control for input amplifiers
971 * 0 dB to 30 dB in 6 dB steps
972 */
973static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
974
328d0a13
LCM		 975/* AVADC clock priority */
976static const char *twl4030_avadc_clk_priority_texts[] = {
977 "Voice high priority", "HiFi high priority"
978};
979
980static const struct soc_enum twl4030_avadc_clk_priority_enum =
981 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
982 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
983 twl4030_avadc_clk_priority_texts);
984
89492be8
PU		 985static const char *twl4030_rampdelay_texts[] = {
986 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
987 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
988 "3495/2581/1748 ms"
989};
990
991static const struct soc_enum twl4030_rampdelay_enum =
992 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
993 ARRAY_SIZE(twl4030_rampdelay_texts),
994 twl4030_rampdelay_texts);
995
376f7839
PU		 996/* Vibra H-bridge direction mode */
997static const char *twl4030_vibradirmode_texts[] = {
998 "Vibra H-bridge direction", "Audio data MSB",
999};
1000
1001static const struct soc_enum twl4030_vibradirmode_enum =
1002 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1003 ARRAY_SIZE(twl4030_vibradirmode_texts),
1004 twl4030_vibradirmode_texts);
1005
1006/* Vibra H-bridge direction */
1007static const char *twl4030_vibradir_texts[] = {
1008 "Positive polarity", "Negative polarity",
1009};
1010
1011static const struct soc_enum twl4030_vibradir_enum =
1012 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1013 ARRAY_SIZE(twl4030_vibradir_texts),
1014 twl4030_vibradir_texts);
1015
cc17557e 1016static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1017 /* Codec operation mode control */
1018 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1019 snd_soc_get_enum_double,
1020 snd_soc_put_twl4030_opmode_enum_double),
1021
d889a72c
PU		 1022 /* Common playback gain controls */
1023 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1024 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1025 0, 0x3f, 0, digital_fine_tlv),
1026 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1027 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1028 0, 0x3f, 0, digital_fine_tlv),
1029
1030 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1031 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1032 6, 0x2, 0, digital_coarse_tlv),
1033 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1034 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1035 6, 0x2, 0, digital_coarse_tlv),
1036
1037 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1038 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1039 3, 0x12, 1, analog_tlv),
1040 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1041 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1042 3, 0x12, 1, analog_tlv),
44c55870
PU		 1043 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1044 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1045 1, 1, 0),
1046 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1047 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1048 1, 1, 0),
381a22b5 1049
1a787e7a
JS		 1050 /* Common voice downlink gain controls */
1051 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1052 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1053
1054 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1055 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1056
1057 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1058 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1059
4290239c
PU		 1060 /* Separate output gain controls */
1061 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1062 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1063 4, 3, 0, output_tvl),
1064
1065 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1066 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1067
1068 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1069 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1070 4, 3, 0, output_tvl),
1071
1072 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1073 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1074
381a22b5 1075 /* Common capture gain controls */
276c6222 1076 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1077 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1078 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1079 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1080 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1081 0, 0x1f, 0, digital_capture_tlv),
5920b453 1082
276c6222 1083 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1084 0, 3, 5, 0, input_gain_tlv),
89492be8 1085
328d0a13
LCM		 1086 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1087
89492be8 1088 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1089
1090 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1091 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1092};
1093
cc17557e 1094static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1095 /* Left channel inputs */
1096 SND_SOC_DAPM_INPUT("MAINMIC"),
1097 SND_SOC_DAPM_INPUT("HSMIC"),
1098 SND_SOC_DAPM_INPUT("AUXL"),
1099 SND_SOC_DAPM_INPUT("CARKITMIC"),
1100 /* Right channel inputs */
1101 SND_SOC_DAPM_INPUT("SUBMIC"),
1102 SND_SOC_DAPM_INPUT("AUXR"),
1103 /* Digital microphones (Stereo) */
1104 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1105 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1106
1107 /* Outputs */
cc17557e
SS		 1108 SND_SOC_DAPM_OUTPUT("OUTL"),
1109 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1110 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1111 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1112 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1113 SND_SOC_DAPM_OUTPUT("HSOL"),
1114 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1115 SND_SOC_DAPM_OUTPUT("CARKITL"),
1116 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1117 SND_SOC_DAPM_OUTPUT("HFL"),
1118 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1119 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1120
53b5047d 1121 /* DACs */
b4852b79 1122 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1123 SND_SOC_NOPM, 0, 0),
b4852b79 1124 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1125 SND_SOC_NOPM, 0, 0),
b4852b79 1126 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1127 SND_SOC_NOPM, 0, 0),
b4852b79 1128 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1129 SND_SOC_NOPM, 0, 0),
1a787e7a 1130 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1131 SND_SOC_NOPM, 0, 0),
cc17557e 1132
7393958f 1133 /* Analog bypasses */
78e08e2f
PU		 1134 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1135 &twl4030_dapm_abypassr1_control),
1136 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1137 &twl4030_dapm_abypassl1_control),
1138 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1139 &twl4030_dapm_abypassr2_control),
1140 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1141 &twl4030_dapm_abypassl2_control),
1142 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1143 &twl4030_dapm_abypassv_control),
1144
1145 /* Master analog loopback switch */
1146 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1147 NULL, 0),
7393958f 1148
6bab83fd 1149 /* Digital bypasses */
78e08e2f
PU		 1150 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1151 &twl4030_dapm_dbypassl_control),
1152 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1153 &twl4030_dapm_dbypassr_control),
1154 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1155 &twl4030_dapm_dbypassv_control),
6bab83fd 1156
4005d39a
PU		 1157 /* Digital mixers, power control for the physical DACs */
1158 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1159 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1160 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1161 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1162 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1163 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1164 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1165 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1166 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1167 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1168
1169 /* Analog mixers, power control for the physical PGAs */
1170 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1171 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1172 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1173 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1174 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1175 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1176 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1177 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1178 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1179 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1180
1a787e7a 1181 /* Output MIXER controls */
5e98a464 1182 /* Earpiece */
1a787e7a
JS		 1183 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1184 &twl4030_dapm_earpiece_controls[0],
1185 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1186 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1187 0, 0, NULL, 0, earpiecepga_event,
1188 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1189 /* PreDrivL/R */
1a787e7a
JS		 1190 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1191 &twl4030_dapm_predrivel_controls[0],
1192 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1193 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1194 0, 0, NULL, 0, predrivelpga_event,
1195 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1196 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1197 &twl4030_dapm_predriver_controls[0],
1198 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1199 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1200 0, 0, NULL, 0, predriverpga_event,
1201 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1202 /* HeadsetL/R */
6943c92e 1203 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1204 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1205 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1206 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1207 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1208 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1209 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1210 &twl4030_dapm_hsor_controls[0],
1211 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1212 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1213 0, 0, NULL, 0, headsetrpga_event,
1214 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1215 /* CarkitL/R */
1a787e7a
JS		 1216 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1217 &twl4030_dapm_carkitl_controls[0],
1218 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1219 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1220 0, 0, NULL, 0, carkitlpga_event,
1221 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1222 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1223 &twl4030_dapm_carkitr_controls[0],
1224 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1225 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1226 0, 0, NULL, 0, carkitrpga_event,
1227 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1228
1229 /* Output MUX controls */
df339804 1230 /* HandsfreeL/R */
5a2e9a48
PU		 1231 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1232 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1233 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1234 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1235 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1236 0, 0, NULL, 0, handsfreelpga_event,
1237 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1238 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1239 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1240 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1241 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1242 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1243 0, 0, NULL, 0, handsfreerpga_event,
1244 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1245 /* Vibra */
1246 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1247 &twl4030_dapm_vibra_control),
1248 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1249 &twl4030_dapm_vibrapath_control),
5e98a464 1250
276c6222
PU		 1251 /* Introducing four virtual ADC, since TWL4030 have four channel for
1252 capture */
1253 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1254 SND_SOC_NOPM, 0, 0),
1255 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1256 SND_SOC_NOPM, 0, 0),
1257 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1258 SND_SOC_NOPM, 0, 0),
1259 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1260 SND_SOC_NOPM, 0, 0),
1261
1262 /* Analog/Digital mic path selection.
1263 TX1 Left/Right: either analog Left/Right or Digimic0
1264 TX2 Left/Right: either analog Left/Right or Digimic1 */
1265 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1266 &twl4030_dapm_micpathtx1_control, micpath_event,
1267 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1268 SND_SOC_DAPM_POST_REG),
1269 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1270 &twl4030_dapm_micpathtx2_control, micpath_event,
1271 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1272 SND_SOC_DAPM_POST_REG),
1273
97b8096d 1274 /* Analog input mixers for the capture amplifiers */
9028935d 1275 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1276 TWL4030_REG_ANAMICL, 4, 0,
1277 &twl4030_dapm_analoglmic_controls[0],
1278 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1279 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1280 TWL4030_REG_ANAMICR, 4, 0,
1281 &twl4030_dapm_analogrmic_controls[0],
1282 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1283
fb2a2f84
PU		 1284 SND_SOC_DAPM_PGA("ADC Physical Left",
1285 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1286 SND_SOC_DAPM_PGA("ADC Physical Right",
1287 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1288
1289 SND_SOC_DAPM_PGA("Digimic0 Enable",
1290 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1291 SND_SOC_DAPM_PGA("Digimic1 Enable",
1292 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1293
1294 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1295 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1296 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1297
cc17557e
SS		 1298};
1299
1300static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1301 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1302 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1303 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1304 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1305 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1306
1307 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1308 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1309 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1310 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1311 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1312
5e98a464
PU		 1313 /* Internal playback routings */
1314 /* Earpiece */
4005d39a
PU		 1315 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1316 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1317 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1318 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1319 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1320 /* PreDrivL */
4005d39a
PU		 1321 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1322 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1323 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1324 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1325 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1326 /* PreDrivR */
4005d39a
PU		 1327 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1328 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1329 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1330 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1331 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1332 /* HeadsetL */
4005d39a
PU		 1333 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1334 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1335 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1336 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1337 /* HeadsetR */
4005d39a
PU		 1338 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1339 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1340 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1341 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1342 /* CarkitL */
4005d39a
PU		 1343 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1344 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1345 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1346 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1347 /* CarkitR */
4005d39a
PU		 1348 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1349 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1350 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1351 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1352 /* HandsfreeL */
4005d39a
PU		 1353 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1354 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1355 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1356 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1357 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1358 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1359 /* HandsfreeR */
4005d39a
PU		 1360 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1361 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1362 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1363 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1364 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1365 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1366 /* Vibra */
1367 {"Vibra Mux", "AudioL1", "DAC Left1"},
1368 {"Vibra Mux", "AudioR1", "DAC Right1"},
1369 {"Vibra Mux", "AudioL2", "DAC Left2"},
1370 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1371
cc17557e 1372 /* outputs */
4005d39a
PU		 1373 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1374 {"OUTR", NULL, "Analog R2 Playback Mixer"},
9008adf9
PU		 1375 {"EARPIECE", NULL, "Earpiece PGA"},
1376 {"PREDRIVEL", NULL, "PredriveL PGA"},
1377 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1378 {"HSOL", NULL, "HeadsetL PGA"},
1379 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1380 {"CARKITL", NULL, "CarkitL PGA"},
1381 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1382 {"HFL", NULL, "HandsfreeL PGA"},
1383 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1384 {"Vibra Route", "Audio", "Vibra Mux"},
1385 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1386
276c6222 1387 /* Capture path */
9028935d
PU		 1388 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1389 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1390 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1391 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1392
9028935d
PU		 1393 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1394 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1395
9028935d
PU		 1396 {"ADC Physical Left", NULL, "Analog Left"},
1397 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1398
1399 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1400 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1401
1402 /* TX1 Left capture path */
fb2a2f84 1403 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1404 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1405 /* TX1 Right capture path */
fb2a2f84 1406 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1407 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1408 /* TX2 Left capture path */
fb2a2f84 1409 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1410 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1411 /* TX2 Right capture path */
fb2a2f84 1412 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1413 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1414
1415 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1416 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1417 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1418 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1419
7393958f 1420 /* Analog bypass routes */
9028935d
PU		 1421 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1422 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1423 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1424 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1425 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1426
78e08e2f
PU		 1427 /* Supply for the Analog loopbacks */
1428 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1429 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1430 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1431 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1432 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1433
7393958f
PU		 1434 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1435 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1436 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1437 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1438 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1439
6bab83fd
PU		 1440 /* Digital bypass routes */
1441 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1442 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1443 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1444
4005d39a
PU		 1445 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1446 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1447 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1448
cc17557e
SS		 1449};
1450
1451static int twl4030_add_widgets(struct snd_soc_codec *codec)
1452{
1453 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1454 ARRAY_SIZE(twl4030_dapm_widgets));
1455
1456 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1457
1458 snd_soc_dapm_new_widgets(codec);
1459 return 0;
1460}
1461
cc17557e
SS		 1462static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1463 enum snd_soc_bias_level level)
1464{
1465 switch (level) {
1466 case SND_SOC_BIAS_ON:
2845fa13 1467 twl4030_apll_enable(codec, 1);
cc17557e
SS		 1468 break;
1469 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1470 break;
1471 case SND_SOC_BIAS_STANDBY:
78e08e2f
PU		 1472 if (codec->bias_level == SND_SOC_BIAS_OFF)
1473 twl4030_power_up(codec);
2845fa13 1474 twl4030_apll_enable(codec, 0);
cc17557e
SS		 1475 break;
1476 case SND_SOC_BIAS_OFF:
1477 twl4030_power_down(codec);
1478 break;
1479 }
1480 codec->bias_level = level;
1481
1482 return 0;
1483}
1484
6b87a91f
PU		 1485static void twl4030_constraints(struct twl4030_priv *twl4030,
1486 struct snd_pcm_substream *mst_substream)
1487{
1488 struct snd_pcm_substream *slv_substream;
1489
1490 /* Pick the stream, which need to be constrained */
1491 if (mst_substream == twl4030->master_substream)
1492 slv_substream = twl4030->slave_substream;
1493 else if (mst_substream == twl4030->slave_substream)
1494 slv_substream = twl4030->master_substream;
1495 else /* This should not happen.. */
1496 return;
1497
1498 /* Set the constraints according to the already configured stream */
1499 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1500 SNDRV_PCM_HW_PARAM_RATE,
1501 twl4030->rate,
1502 twl4030->rate);
1503
1504 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1505 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1506 twl4030->sample_bits,
1507 twl4030->sample_bits);
1508
1509 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1510 SNDRV_PCM_HW_PARAM_CHANNELS,
1511 twl4030->channels,
1512 twl4030->channels);
1513}
1514
8a1f936a
PU		 1515/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1516 * capture has to be enabled/disabled. */
1517static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1518 int enable)
1519{
1520 u8 reg, mask;
1521
1522 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1523
1524 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1525 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1526 else
1527 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1528
1529 if (enable)
1530 reg |= mask;
1531 else
1532 reg &= ~mask;
1533
1534 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1535}
1536
d6648da1
PU		 1537static int twl4030_startup(struct snd_pcm_substream *substream,
1538 struct snd_soc_dai *dai)
7220b9f4
PU		 1539{
1540 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1541 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1542 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1543 struct twl4030_priv *twl4030 = codec->private_data;
1544
7220b9f4 1545 if (twl4030->master_substream) {
7220b9f4 1546 twl4030->slave_substream = substream;
6b87a91f
PU		 1547 /* The DAI has one configuration for playback and capture, so
1548 * if the DAI has been already configured then constrain this
1549 * substream to match it. */
1550 if (twl4030->configured)
1551 twl4030_constraints(twl4030, twl4030->master_substream);
1552 } else {
8a1f936a
PU		 1553 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1554 TWL4030_OPTION_1)) {
1555 /* In option2 4 channel is not supported, set the
1556 * constraint for the first stream for channels, the
1557 * second stream will 'inherit' this cosntraint */
1558 snd_pcm_hw_constraint_minmax(substream->runtime,
1559 SNDRV_PCM_HW_PARAM_CHANNELS,
1560 2, 2);
1561 }
7220b9f4 1562 twl4030->master_substream = substream;
6b87a91f 1563 }
7220b9f4
PU		 1564
1565 return 0;
1566}
1567
d6648da1
PU		 1568static void twl4030_shutdown(struct snd_pcm_substream *substream,
1569 struct snd_soc_dai *dai)
7220b9f4
PU		 1570{
1571 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1572 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1573 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1574 struct twl4030_priv *twl4030 = codec->private_data;
1575
1576 if (twl4030->master_substream == substream)
1577 twl4030->master_substream = twl4030->slave_substream;
1578
1579 twl4030->slave_substream = NULL;
6b87a91f
PU		 1580
1581 /* If all streams are closed, or the remaining stream has not yet
1582 * been configured than set the DAI as not configured. */
1583 if (!twl4030->master_substream)
1584 twl4030->configured = 0;
1585 else if (!twl4030->master_substream->runtime->channels)
1586 twl4030->configured = 0;
8a1f936a
PU		 1587
1588 /* If the closing substream had 4 channel, do the necessary cleanup */
1589 if (substream->runtime->channels == 4)
1590 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1591}
1592
cc17557e 1593static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1594 struct snd_pcm_hw_params *params,
1595 struct snd_soc_dai *dai)
cc17557e
SS		 1596{
1597 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1598 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1599 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1600 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1601 u8 mode, old_mode, format, old_format;
1602
8a1f936a
PU		 1603 /* If the substream has 4 channel, do the necessary setup */
1604 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1605 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1606 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1607
1608 /* Safety check: are we in the correct operating mode and
1609 * the interface is in TDM mode? */
1610 if ((mode & TWL4030_OPTION_1) &&
1611 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1612 twl4030_tdm_enable(codec, substream->stream, 1);
1613 else
1614 return -EINVAL;
1615 }
1616
6b87a91f
PU		 1617 if (twl4030->configured)
1618 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1619 return 0;
1620
cc17557e
SS		 1621 /* bit rate */
1622 old_mode = twl4030_read_reg_cache(codec,
1623 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1624 mode = old_mode & ~TWL4030_APLL_RATE;
1625
1626 switch (params_rate(params)) {
1627 case 8000:
1628 mode |= TWL4030_APLL_RATE_8000;
1629 break;
1630 case 11025:
1631 mode |= TWL4030_APLL_RATE_11025;
1632 break;
1633 case 12000:
1634 mode |= TWL4030_APLL_RATE_12000;
1635 break;
1636 case 16000:
1637 mode |= TWL4030_APLL_RATE_16000;
1638 break;
1639 case 22050:
1640 mode |= TWL4030_APLL_RATE_22050;
1641 break;
1642 case 24000:
1643 mode |= TWL4030_APLL_RATE_24000;
1644 break;
1645 case 32000:
1646 mode |= TWL4030_APLL_RATE_32000;
1647 break;
1648 case 44100:
1649 mode |= TWL4030_APLL_RATE_44100;
1650 break;
1651 case 48000:
1652 mode |= TWL4030_APLL_RATE_48000;
1653 break;
103f211d
PU		 1654 case 96000:
1655 mode |= TWL4030_APLL_RATE_96000;
1656 break;
cc17557e
SS		 1657 default:
1658 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1659 params_rate(params));
1660 return -EINVAL;
1661 }
1662
1663 if (mode != old_mode) {
1664 /* change rate and set CODECPDZ */
7393958f 1665 twl4030_codec_enable(codec, 0);
cc17557e 1666 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1667 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1668 }
1669
1670 /* sample size */
1671 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1672 format = old_format;
1673 format &= ~TWL4030_DATA_WIDTH;
1674 switch (params_format(params)) {
1675 case SNDRV_PCM_FORMAT_S16_LE:
1676 format |= TWL4030_DATA_WIDTH_16S_16W;
1677 break;
1678 case SNDRV_PCM_FORMAT_S24_LE:
1679 format |= TWL4030_DATA_WIDTH_32S_24W;
1680 break;
1681 default:
1682 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1683 params_format(params));
1684 return -EINVAL;
1685 }
1686
1687 if (format != old_format) {
1688
1689 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1690 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1691
1692 /* change format */
1693 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1694
1695 /* set CODECPDZ afterwards */
db04e2c5 1696 twl4030_codec_enable(codec, 1);
cc17557e 1697 }
6b87a91f
PU		 1698
1699 /* Store the important parameters for the DAI configuration and set
1700 * the DAI as configured */
1701 twl4030->configured = 1;
1702 twl4030->rate = params_rate(params);
1703 twl4030->sample_bits = hw_param_interval(params,
1704 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1705 twl4030->channels = params_channels(params);
1706
1707 /* If both playback and capture streams are open, and one of them
1708 * is setting the hw parameters right now (since we are here), set
1709 * constraints to the other stream to match the current one. */
1710 if (twl4030->slave_substream)
1711 twl4030_constraints(twl4030, substream);
1712
cc17557e
SS		 1713 return 0;
1714}
1715
1716static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1717 int clk_id, unsigned int freq, int dir)
1718{
1719 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1720 struct twl4030_priv *twl4030 = codec->private_data;
d8707cec 1721 u8 apll_ctrl;
cc17557e 1722
d8707cec
PU		 1723 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1724 apll_ctrl &= ~TWL4030_APLL_INFREQ;
cc17557e
SS		 1725 switch (freq) {
1726 case 19200000:
d8707cec 1727 apll_ctrl |= TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1728 twl4030->sysclk = 19200;
cc17557e
SS		 1729 break;
1730 case 26000000:
d8707cec 1731 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1732 twl4030->sysclk = 26000;
cc17557e
SS		 1733 break;
1734 case 38400000:
d8707cec 1735 apll_ctrl |= TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1736 twl4030->sysclk = 38400;
cc17557e
SS		 1737 break;
1738 default:
1739 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1740 freq);
1741 return -EINVAL;
1742 }
1743
d8707cec 1744 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
cc17557e
SS		 1745
1746 return 0;
1747}
1748
1749static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1750 unsigned int fmt)
1751{
1752 struct snd_soc_codec *codec = codec_dai->codec;
1753 u8 old_format, format;
1754
1755 /* get format */
1756 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1757 format = old_format;
1758
1759 /* set master/slave audio interface */
1760 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1761 case SND_SOC_DAIFMT_CBM_CFM:
1762 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1763 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1764 break;
1765 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1766 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1767 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1768 break;
1769 default:
1770 return -EINVAL;
1771 }
1772
1773 /* interface format */
1774 format &= ~TWL4030_AIF_FORMAT;
1775 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1776 case SND_SOC_DAIFMT_I2S:
1777 format |= TWL4030_AIF_FORMAT_CODEC;
1778 break;
8a1f936a
PU		 1779 case SND_SOC_DAIFMT_DSP_A:
1780 format |= TWL4030_AIF_FORMAT_TDM;
1781 break;
cc17557e
SS		 1782 default:
1783 return -EINVAL;
1784 }
1785
1786 if (format != old_format) {
1787
1788 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1789 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1790
1791 /* change format */
1792 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1793
1794 /* set CODECPDZ afterwards */
db04e2c5 1795 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1796 }
1797
1798 return 0;
1799}
1800
68140443
LCM		 1801static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1802{
1803 struct snd_soc_codec *codec = dai->codec;
1804 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1805
1806 if (tristate)
1807 reg |= TWL4030_AIF_TRI_EN;
1808 else
1809 reg &= ~TWL4030_AIF_TRI_EN;
1810
1811 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1812}
1813
b7a755a8
MLC		 1814/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1815 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1816static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1817 int enable)
1818{
1819 u8 reg, mask;
1820
1821 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1822
1823 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1824 mask = TWL4030_ARXL1_VRX_EN;
1825 else
1826 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1827
1828 if (enable)
1829 reg |= mask;
1830 else
1831 reg &= ~mask;
1832
1833 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1834}
1835
7154b3e8
JS		 1836static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1837 struct snd_soc_dai *dai)
1838{
1839 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1840 struct snd_soc_device *socdev = rtd->socdev;
1841 struct snd_soc_codec *codec = socdev->card->codec;
1842 u8 infreq;
1843 u8 mode;
1844
1845 /* If the system master clock is not 26MHz, the voice PCM interface is
1846 * not avilable.
1847 */
1848 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1849 & TWL4030_APLL_INFREQ;
1850
1851 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1852 printk(KERN_ERR "TWL4030 voice startup: "
1853 "MCLK is not 26MHz, call set_sysclk() on init\n");
1854 return -EINVAL;
1855 }
1856
1857 /* If the codec mode is not option2, the voice PCM interface is not
1858 * avilable.
1859 */
1860 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1861 & TWL4030_OPT_MODE;
1862
1863 if (mode != TWL4030_OPTION_2) {
1864 printk(KERN_ERR "TWL4030 voice startup: "
1865 "the codec mode is not option2\n");
1866 return -EINVAL;
1867 }
1868
1869 return 0;
1870}
1871
b7a755a8
MLC		 1872static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1873 struct snd_soc_dai *dai)
1874{
1875 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1876 struct snd_soc_device *socdev = rtd->socdev;
1877 struct snd_soc_codec *codec = socdev->card->codec;
1878
1879 /* Enable voice digital filters */
1880 twl4030_voice_enable(codec, substream->stream, 0);
1881}
1882
7154b3e8
JS		 1883static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1884 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1885{
1886 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1887 struct snd_soc_device *socdev = rtd->socdev;
1888 struct snd_soc_codec *codec = socdev->card->codec;
1889 u8 old_mode, mode;
1890
b7a755a8
MLC		 1891 /* Enable voice digital filters */
1892 twl4030_voice_enable(codec, substream->stream, 1);
1893
7154b3e8
JS		 1894 /* bit rate */
1895 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1896 & ~(TWL4030_CODECPDZ);
1897 mode = old_mode;
1898
1899 switch (params_rate(params)) {
1900 case 8000:
1901 mode &= ~(TWL4030_SEL_16K);
1902 break;
1903 case 16000:
1904 mode |= TWL4030_SEL_16K;
1905 break;
1906 default:
1907 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1908 params_rate(params));
1909 return -EINVAL;
1910 }
1911
1912 if (mode != old_mode) {
1913 /* change rate and set CODECPDZ */
1914 twl4030_codec_enable(codec, 0);
1915 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1916 twl4030_codec_enable(codec, 1);
1917 }
1918
1919 return 0;
1920}
1921
1922static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1923 int clk_id, unsigned int freq, int dir)
1924{
1925 struct snd_soc_codec *codec = codec_dai->codec;
d8707cec 1926 u8 apll_ctrl;
7154b3e8 1927
d8707cec
PU		 1928 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1929 apll_ctrl &= ~TWL4030_APLL_INFREQ;
7154b3e8
JS		 1930 switch (freq) {
1931 case 26000000:
d8707cec 1932 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
7154b3e8
JS		 1933 break;
1934 default:
1935 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1936 freq);
1937 return -EINVAL;
1938 }
1939
d8707cec 1940 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
7154b3e8
JS		 1941
1942 return 0;
1943}
1944
1945static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1946 unsigned int fmt)
1947{
1948 struct snd_soc_codec *codec = codec_dai->codec;
1949 u8 old_format, format;
1950
1951 /* get format */
1952 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1953 format = old_format;
1954
1955 /* set master/slave audio interface */
1956 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 1957 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 1958 format &= ~(TWL4030_VIF_SLAVE_EN);
1959 break;
1960 case SND_SOC_DAIFMT_CBS_CFS:
1961 format |= TWL4030_VIF_SLAVE_EN;
1962 break;
1963 default:
1964 return -EINVAL;
1965 }
1966
1967 /* clock inversion */
1968 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1969 case SND_SOC_DAIFMT_IB_NF:
1970 format &= ~(TWL4030_VIF_FORMAT);
1971 break;
1972 case SND_SOC_DAIFMT_NB_IF:
1973 format |= TWL4030_VIF_FORMAT;
1974 break;
1975 default:
1976 return -EINVAL;
1977 }
1978
1979 if (format != old_format) {
1980 /* change format and set CODECPDZ */
1981 twl4030_codec_enable(codec, 0);
1982 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1983 twl4030_codec_enable(codec, 1);
1984 }
1985
1986 return 0;
1987}
1988
68140443
LCM		 1989static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
1990{
1991 struct snd_soc_codec *codec = dai->codec;
1992 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1993
1994 if (tristate)
1995 reg |= TWL4030_VIF_TRI_EN;
1996 else
1997 reg &= ~TWL4030_VIF_TRI_EN;
1998
1999 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2000}
2001
bbba9444 2002#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2003#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2004
10d9e3d9 2005static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2006 .startup = twl4030_startup,
2007 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2008 .hw_params = twl4030_hw_params,
2009 .set_sysclk = twl4030_set_dai_sysclk,
2010 .set_fmt = twl4030_set_dai_fmt,
68140443 2011 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2012};
2013
7154b3e8
JS		 2014static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2015 .startup = twl4030_voice_startup,
b7a755a8 2016 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2017 .hw_params = twl4030_voice_hw_params,
2018 .set_sysclk = twl4030_voice_set_dai_sysclk,
2019 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2020 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2021};
2022
2023struct snd_soc_dai twl4030_dai[] = {
2024{
cc17557e
SS		 2025 .name = "twl4030",
2026 .playback = {
b4852b79 2027 .stream_name = "HiFi Playback",
cc17557e 2028 .channels_min = 2,
8a1f936a 2029 .channels_max = 4,
31ad0f31 2030 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2031 .formats = TWL4030_FORMATS,},
2032 .capture = {
2033 .stream_name = "Capture",
2034 .channels_min = 2,
8a1f936a 2035 .channels_max = 4,
cc17557e
SS		 2036 .rates = TWL4030_RATES,
2037 .formats = TWL4030_FORMATS,},
10d9e3d9 2038 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2039},
2040{
2041 .name = "twl4030 Voice",
2042 .playback = {
b4852b79 2043 .stream_name = "Voice Playback",
7154b3e8
JS		 2044 .channels_min = 1,
2045 .channels_max = 1,
2046 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2047 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2048 .capture = {
2049 .stream_name = "Capture",
2050 .channels_min = 1,
2051 .channels_max = 2,
2052 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2053 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2054 .ops = &twl4030_dai_voice_ops,
2055},
cc17557e
SS		 2056};
2057EXPORT_SYMBOL_GPL(twl4030_dai);
2058
7a1fecf5 2059static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2060{
2061 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2062 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2063
2064 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2065
2066 return 0;
2067}
2068
7a1fecf5 2069static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2070{
2071 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2072 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2073
2074 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2075 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2076 return 0;
2077}
2078
7a1fecf5 2079static struct snd_soc_codec *twl4030_codec;
cc17557e 2080
7a1fecf5 2081static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2082{
7a1fecf5 2083 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
9da28c7b 2084 struct twl4030_setup_data *setup = socdev->codec_data;
7a1fecf5
PU		 2085 struct snd_soc_codec *codec;
2086 struct twl4030_priv *twl4030;
2087 int ret;
cc17557e 2088
7a1fecf5 2089 BUG_ON(!twl4030_codec);
cc17557e 2090
7a1fecf5
PU		 2091 codec = twl4030_codec;
2092 twl4030 = codec->private_data;
2093 socdev->card->codec = codec;
cc17557e 2094
9da28c7b
PU		 2095 /* Configuration for headset ramp delay from setup data */
2096 if (setup) {
2097 unsigned char hs_pop;
2098
2099 if (setup->sysclk)
2100 twl4030->sysclk = setup->sysclk;
2101 else
2102 twl4030->sysclk = 26000;
2103
2104 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2105 hs_pop &= ~TWL4030_RAMP_DELAY;
2106 hs_pop |= (setup->ramp_delay_value << 2);
2107 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2108 } else {
2109 twl4030->sysclk = 26000;
2110 }
2111
cc17557e
SS		 2112 /* register pcms */
2113 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2114 if (ret < 0) {
7a1fecf5
PU		 2115 dev_err(&pdev->dev, "failed to create pcms\n");
2116 return ret;
cc17557e
SS		 2117 }
2118
3e8e1952
IM		 2119 snd_soc_add_controls(codec, twl4030_snd_controls,
2120 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2121 twl4030_add_widgets(codec);
2122
968a6025 2123 ret = snd_soc_init_card(socdev);
cc17557e 2124 if (ret < 0) {
7a1fecf5 2125 dev_err(&pdev->dev, "failed to register card\n");
cc17557e
SS		 2126 goto card_err;
2127 }
2128
7a1fecf5 2129 return 0;
cc17557e
SS		 2130
2131card_err:
2132 snd_soc_free_pcms(socdev);
2133 snd_soc_dapm_free(socdev);
7a1fecf5 2134
cc17557e
SS		 2135 return ret;
2136}
2137
7a1fecf5 2138static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2139{
2140 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2141 struct snd_soc_codec *codec = socdev->card->codec;
2142
2143 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2144 snd_soc_free_pcms(socdev);
2145 snd_soc_dapm_free(socdev);
2146 kfree(codec->private_data);
2147 kfree(codec);
2148
2149 return 0;
2150}
2151
2152static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2153{
2154 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2155 struct snd_soc_codec *codec;
7393958f 2156 struct twl4030_priv *twl4030;
7a1fecf5 2157 int ret;
cc17557e 2158
7a1fecf5
PU		 2159 if (!pdata || !(pdata->audio_mclk == 19200000 ||
2160 pdata->audio_mclk == 26000000 ||
2161 pdata->audio_mclk == 38400000)) {
2162 dev_err(&pdev->dev, "Invalid platform_data\n");
2163 return -EINVAL;
2164 }
cc17557e 2165
7393958f
PU		 2166 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2167 if (twl4030 == NULL) {
7a1fecf5 2168 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2169 return -ENOMEM;
2170 }
2171
7a1fecf5 2172 codec = &twl4030->codec;
7393958f 2173 codec->private_data = twl4030;
7a1fecf5
PU		 2174 codec->dev = &pdev->dev;
2175 twl4030_dai[0].dev = &pdev->dev;
2176 twl4030_dai[1].dev = &pdev->dev;
2177
cc17557e
SS		 2178 mutex_init(&codec->mutex);
2179 INIT_LIST_HEAD(&codec->dapm_widgets);
2180 INIT_LIST_HEAD(&codec->dapm_paths);
2181
7a1fecf5
PU		 2182 codec->name = "twl4030";
2183 codec->owner = THIS_MODULE;
2184 codec->read = twl4030_read_reg_cache;
2185 codec->write = twl4030_write;
2186 codec->set_bias_level = twl4030_set_bias_level;
2187 codec->dai = twl4030_dai;
2188 codec->num_dai = ARRAY_SIZE(twl4030_dai),
2189 codec->reg_cache_size = sizeof(twl4030_reg);
2190 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2191 GFP_KERNEL);
2192 if (codec->reg_cache == NULL) {
2193 ret = -ENOMEM;
2194 goto error_cache;
2195 }
2196
2197 platform_set_drvdata(pdev, twl4030);
2198 twl4030_codec = codec;
2199
2200 /* Set the defaults, and power up the codec */
2201 twl4030_init_chip(codec);
2202 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2203
2204 ret = snd_soc_register_codec(codec);
2205 if (ret != 0) {
2206 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2207 goto error_codec;
2208 }
2209
2210 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2211 if (ret != 0) {
2212 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2213 snd_soc_unregister_codec(codec);
2214 goto error_codec;
2215 }
cc17557e
SS		 2216
2217 return 0;
7a1fecf5
PU		 2218
2219error_codec:
2220 twl4030_power_down(codec);
2221 kfree(codec->reg_cache);
2222error_cache:
2223 kfree(twl4030);
2224 return ret;
cc17557e
SS		 2225}
2226
7a1fecf5 2227static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2228{
7a1fecf5 2229 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2230
7a1fecf5 2231 kfree(twl4030);
cc17557e 2232
7a1fecf5 2233 twl4030_codec = NULL;
cc17557e
SS		 2234 return 0;
2235}
2236
7a1fecf5
PU		 2237MODULE_ALIAS("platform:twl4030_codec_audio");
2238
2239static struct platform_driver twl4030_codec_driver = {
2240 .probe = twl4030_codec_probe,
2241 .remove = __devexit_p(twl4030_codec_remove),
2242 .driver = {
2243 .name = "twl4030_codec_audio",
2244 .owner = THIS_MODULE,
2245 },
cc17557e 2246};
cc17557e 2247
24e07db8 2248static int __init twl4030_modinit(void)
64089b84 2249{
7a1fecf5 2250 return platform_driver_register(&twl4030_codec_driver);
64089b84 2251}
24e07db8 2252module_init(twl4030_modinit);
64089b84
MB		 2253
2254static void __exit twl4030_exit(void)
2255{
7a1fecf5 2256 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2257}
2258module_exit(twl4030_exit);
2259
7a1fecf5
PU		 2260struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2261 .probe = twl4030_soc_probe,
2262 .remove = twl4030_soc_remove,
2263 .suspend = twl4030_soc_suspend,
2264 .resume = twl4030_soc_resume,
2265};
2266EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2267
cc17557e
SS		 2268MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2269MODULE_AUTHOR("Steve Sakoman");
2270MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.157127 seconds and 5 git commands to generate.