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ASoC: Push platform registration down into the card
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x24, /* REG_ANAMICL (0x5) */
50 0x04, /* REG_ANAMICR (0x6) */
51 0x0a, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
b0bd53a7
PU		 193/*
194 * Some of the gain controls in TWL (mostly those which are associated with
195 * the outputs) are implemented in an interesting way:
196 * 0x0 : Power down (mute)
197 * 0x1 : 6dB
198 * 0x2 : 0 dB
199 * 0x3 : -6 dB
200 * Inverting not going to help with these.
201 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
202 */
203#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
204 xinvert, tlv_array) \
205{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
206 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
207 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
208 .tlv.p = (tlv_array), \
209 .info = snd_soc_info_volsw, \
210 .get = snd_soc_get_volsw_twl4030, \
211 .put = snd_soc_put_volsw_twl4030, \
212 .private_value = (unsigned long)&(struct soc_mixer_control) \
213 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
214 .max = xmax, .invert = xinvert} }
215#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
216 xinvert, tlv_array) \
217{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
218 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
219 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
220 .tlv.p = (tlv_array), \
221 .info = snd_soc_info_volsw_2r, \
222 .get = snd_soc_get_volsw_r2_twl4030,\
223 .put = snd_soc_put_volsw_r2_twl4030, \
224 .private_value = (unsigned long)&(struct soc_mixer_control) \
225 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
226 .max = xmax, .invert = xinvert} }
227#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
228 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
229 xinvert, tlv_array)
230
231static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
232 struct snd_ctl_elem_value *ucontrol)
233{
234 struct soc_mixer_control *mc =
235 (struct soc_mixer_control *)kcontrol->private_value;
236 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
237 unsigned int reg = mc->reg;
238 unsigned int shift = mc->shift;
239 unsigned int rshift = mc->rshift;
240 int max = mc->max;
241 int mask = (1 << fls(max)) - 1;
242
243 ucontrol->value.integer.value[0] =
244 (snd_soc_read(codec, reg) >> shift) & mask;
245 if (ucontrol->value.integer.value[0])
246 ucontrol->value.integer.value[0] =
247 max + 1 - ucontrol->value.integer.value[0];
248
249 if (shift != rshift) {
250 ucontrol->value.integer.value[1] =
251 (snd_soc_read(codec, reg) >> rshift) & mask;
252 if (ucontrol->value.integer.value[1])
253 ucontrol->value.integer.value[1] =
254 max + 1 - ucontrol->value.integer.value[1];
255 }
256
257 return 0;
258}
259
260static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
261 struct snd_ctl_elem_value *ucontrol)
262{
263 struct soc_mixer_control *mc =
264 (struct soc_mixer_control *)kcontrol->private_value;
265 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
266 unsigned int reg = mc->reg;
267 unsigned int shift = mc->shift;
268 unsigned int rshift = mc->rshift;
269 int max = mc->max;
270 int mask = (1 << fls(max)) - 1;
271 unsigned short val, val2, val_mask;
272
273 val = (ucontrol->value.integer.value[0] & mask);
274
275 val_mask = mask << shift;
276 if (val)
277 val = max + 1 - val;
278 val = val << shift;
279 if (shift != rshift) {
280 val2 = (ucontrol->value.integer.value[1] & mask);
281 val_mask |= mask << rshift;
282 if (val2)
283 val2 = max + 1 - val2;
284 val |= val2 << rshift;
285 }
286 return snd_soc_update_bits(codec, reg, val_mask, val);
287}
288
289static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
292 struct soc_mixer_control *mc =
293 (struct soc_mixer_control *)kcontrol->private_value;
294 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
295 unsigned int reg = mc->reg;
296 unsigned int reg2 = mc->rreg;
297 unsigned int shift = mc->shift;
298 int max = mc->max;
299 int mask = (1<<fls(max))-1;
300
301 ucontrol->value.integer.value[0] =
302 (snd_soc_read(codec, reg) >> shift) & mask;
303 ucontrol->value.integer.value[1] =
304 (snd_soc_read(codec, reg2) >> shift) & mask;
305
306 if (ucontrol->value.integer.value[0])
307 ucontrol->value.integer.value[0] =
308 max + 1 - ucontrol->value.integer.value[0];
309 if (ucontrol->value.integer.value[1])
310 ucontrol->value.integer.value[1] =
311 max + 1 - ucontrol->value.integer.value[1];
312
313 return 0;
314}
315
316static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
317 struct snd_ctl_elem_value *ucontrol)
318{
319 struct soc_mixer_control *mc =
320 (struct soc_mixer_control *)kcontrol->private_value;
321 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
322 unsigned int reg = mc->reg;
323 unsigned int reg2 = mc->rreg;
324 unsigned int shift = mc->shift;
325 int max = mc->max;
326 int mask = (1 << fls(max)) - 1;
327 int err;
328 unsigned short val, val2, val_mask;
329
330 val_mask = mask << shift;
331 val = (ucontrol->value.integer.value[0] & mask);
332 val2 = (ucontrol->value.integer.value[1] & mask);
333
334 if (val)
335 val = max + 1 - val;
336 if (val2)
337 val2 = max + 1 - val2;
338
339 val = val << shift;
340 val2 = val2 << shift;
341
342 err = snd_soc_update_bits(codec, reg, val_mask, val);
343 if (err < 0)
344 return err;
345
346 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
347 return err;
348}
349
c10b82cf
PU		 350/*
351 * FGAIN volume control:
352 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
353 */
d889a72c 354static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 355
0d33ea0b
PU		 356/*
357 * CGAIN volume control:
358 * 0 dB to 12 dB in 6 dB steps
359 * value 2 and 3 means 12 dB
360 */
d889a72c
PU		 361static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
362
363/*
364 * Analog playback gain
365 * -24 dB to 12 dB in 2 dB steps
366 */
367static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 368
4290239c
PU		 369/*
370 * Gain controls tied to outputs
371 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
372 */
373static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
374
381a22b5
PU		 375/*
376 * Capture gain after the ADCs
377 * from 0 dB to 31 dB in 1 dB steps
378 */
379static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
380
cc17557e 381static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 382 /* Common playback gain controls */
383 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
384 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
385 0, 0x3f, 0, digital_fine_tlv),
386 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
387 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
388 0, 0x3f, 0, digital_fine_tlv),
389
390 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
391 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
392 6, 0x2, 0, digital_coarse_tlv),
393 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
394 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
395 6, 0x2, 0, digital_coarse_tlv),
396
397 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
398 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
399 3, 0x12, 1, analog_tlv),
400 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
401 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
402 3, 0x12, 1, analog_tlv),
381a22b5 403
4290239c
PU		 404 /* Separate output gain controls */
405 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
406 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
407 4, 3, 0, output_tvl),
408
409 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
410 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
411
412 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
413 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
414 4, 3, 0, output_tvl),
415
416 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
417 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
418
381a22b5
PU		 419 /* Common capture gain controls */
420 SOC_DOUBLE_R_TLV("Capture Volume",
421 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
422 0, 0x1f, 0, digital_capture_tlv),
cc17557e
SS		 423};
424
425/* add non dapm controls */
426static int twl4030_add_controls(struct snd_soc_codec *codec)
427{
428 int err, i;
429
430 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
431 err = snd_ctl_add(codec->card,
432 snd_soc_cnew(&twl4030_snd_controls[i],
433 codec, NULL));
434 if (err < 0)
435 return err;
436 }
437
438 return 0;
439}
440
441static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
442 SND_SOC_DAPM_INPUT("INL"),
443 SND_SOC_DAPM_INPUT("INR"),
444
445 SND_SOC_DAPM_OUTPUT("OUTL"),
446 SND_SOC_DAPM_OUTPUT("OUTR"),
447
448 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
449 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
450
451 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
452 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
453};
454
455static const struct snd_soc_dapm_route intercon[] = {
456 /* outputs */
457 {"OUTL", NULL, "DACL"},
458 {"OUTR", NULL, "DACR"},
459
460 /* inputs */
461 {"ADCL", NULL, "INL"},
462 {"ADCR", NULL, "INR"},
463};
464
465static int twl4030_add_widgets(struct snd_soc_codec *codec)
466{
467 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
468 ARRAY_SIZE(twl4030_dapm_widgets));
469
470 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
471
472 snd_soc_dapm_new_widgets(codec);
473 return 0;
474}
475
476static void twl4030_power_up(struct snd_soc_codec *codec)
477{
478 u8 anamicl, regmisc1, byte, popn, hsgain;
479 int i = 0;
480
481 /* set CODECPDZ to turn on codec */
482 twl4030_set_codecpdz(codec);
483
484 /* initiate offset cancellation */
485 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
486 twl4030_write(codec, TWL4030_REG_ANAMICL,
487 anamicl | TWL4030_CNCL_OFFSET_START);
488
489 /* wait for offset cancellation to complete */
490 do {
491 /* this takes a little while, so don't slam i2c */
492 udelay(2000);
493 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
494 TWL4030_REG_ANAMICL);
495 } while ((i++ < 100) &&
496 ((byte & TWL4030_CNCL_OFFSET_START) ==
497 TWL4030_CNCL_OFFSET_START));
498
499 /* anti-pop when changing analog gain */
500 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
501 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
502 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
503
504 /* toggle CODECPDZ as per TRM */
505 twl4030_clear_codecpdz(codec);
506 twl4030_set_codecpdz(codec);
507
508 /* program anti-pop with bias ramp delay */
509 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
510 popn &= TWL4030_RAMP_DELAY;
511 popn |= TWL4030_RAMP_DELAY_645MS;
512 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
513 popn |= TWL4030_VMID_EN;
514 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
515
516 /* enable output stage and gain setting */
517 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
518 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
519
520 /* enable anti-pop ramp */
521 popn |= TWL4030_RAMP_EN;
522 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
523}
524
525static void twl4030_power_down(struct snd_soc_codec *codec)
526{
527 u8 popn, hsgain;
528
529 /* disable anti-pop ramp */
530 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
531 popn &= ~TWL4030_RAMP_EN;
532 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
533
534 /* disable output stage and gain setting */
535 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
536 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
537
538 /* disable bias out */
539 popn &= ~TWL4030_VMID_EN;
540 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
541
542 /* power down */
543 twl4030_clear_codecpdz(codec);
544}
545
546static int twl4030_set_bias_level(struct snd_soc_codec *codec,
547 enum snd_soc_bias_level level)
548{
549 switch (level) {
550 case SND_SOC_BIAS_ON:
551 twl4030_power_up(codec);
552 break;
553 case SND_SOC_BIAS_PREPARE:
554 /* TODO: develop a twl4030_prepare function */
555 break;
556 case SND_SOC_BIAS_STANDBY:
557 /* TODO: develop a twl4030_standby function */
558 twl4030_power_down(codec);
559 break;
560 case SND_SOC_BIAS_OFF:
561 twl4030_power_down(codec);
562 break;
563 }
564 codec->bias_level = level;
565
566 return 0;
567}
568
569static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 570 struct snd_pcm_hw_params *params,
571 struct snd_soc_dai *dai)
cc17557e
SS		 572{
573 struct snd_soc_pcm_runtime *rtd = substream->private_data;
574 struct snd_soc_device *socdev = rtd->socdev;
575 struct snd_soc_codec *codec = socdev->codec;
576 u8 mode, old_mode, format, old_format;
577
578
579 /* bit rate */
580 old_mode = twl4030_read_reg_cache(codec,
581 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
582 mode = old_mode & ~TWL4030_APLL_RATE;
583
584 switch (params_rate(params)) {
585 case 8000:
586 mode |= TWL4030_APLL_RATE_8000;
587 break;
588 case 11025:
589 mode |= TWL4030_APLL_RATE_11025;
590 break;
591 case 12000:
592 mode |= TWL4030_APLL_RATE_12000;
593 break;
594 case 16000:
595 mode |= TWL4030_APLL_RATE_16000;
596 break;
597 case 22050:
598 mode |= TWL4030_APLL_RATE_22050;
599 break;
600 case 24000:
601 mode |= TWL4030_APLL_RATE_24000;
602 break;
603 case 32000:
604 mode |= TWL4030_APLL_RATE_32000;
605 break;
606 case 44100:
607 mode |= TWL4030_APLL_RATE_44100;
608 break;
609 case 48000:
610 mode |= TWL4030_APLL_RATE_48000;
611 break;
612 default:
613 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
614 params_rate(params));
615 return -EINVAL;
616 }
617
618 if (mode != old_mode) {
619 /* change rate and set CODECPDZ */
620 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
621 twl4030_set_codecpdz(codec);
622 }
623
624 /* sample size */
625 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
626 format = old_format;
627 format &= ~TWL4030_DATA_WIDTH;
628 switch (params_format(params)) {
629 case SNDRV_PCM_FORMAT_S16_LE:
630 format |= TWL4030_DATA_WIDTH_16S_16W;
631 break;
632 case SNDRV_PCM_FORMAT_S24_LE:
633 format |= TWL4030_DATA_WIDTH_32S_24W;
634 break;
635 default:
636 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
637 params_format(params));
638 return -EINVAL;
639 }
640
641 if (format != old_format) {
642
643 /* clear CODECPDZ before changing format (codec requirement) */
644 twl4030_clear_codecpdz(codec);
645
646 /* change format */
647 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
648
649 /* set CODECPDZ afterwards */
650 twl4030_set_codecpdz(codec);
651 }
652 return 0;
653}
654
655static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
656 int clk_id, unsigned int freq, int dir)
657{
658 struct snd_soc_codec *codec = codec_dai->codec;
659 u8 infreq;
660
661 switch (freq) {
662 case 19200000:
663 infreq = TWL4030_APLL_INFREQ_19200KHZ;
664 break;
665 case 26000000:
666 infreq = TWL4030_APLL_INFREQ_26000KHZ;
667 break;
668 case 38400000:
669 infreq = TWL4030_APLL_INFREQ_38400KHZ;
670 break;
671 default:
672 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
673 freq);
674 return -EINVAL;
675 }
676
677 infreq |= TWL4030_APLL_EN;
678 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
679
680 return 0;
681}
682
683static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
684 unsigned int fmt)
685{
686 struct snd_soc_codec *codec = codec_dai->codec;
687 u8 old_format, format;
688
689 /* get format */
690 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
691 format = old_format;
692
693 /* set master/slave audio interface */
694 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
695 case SND_SOC_DAIFMT_CBM_CFM:
696 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 697 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 698 break;
699 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 700 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 701 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 702 break;
703 default:
704 return -EINVAL;
705 }
706
707 /* interface format */
708 format &= ~TWL4030_AIF_FORMAT;
709 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
710 case SND_SOC_DAIFMT_I2S:
711 format |= TWL4030_AIF_FORMAT_CODEC;
712 break;
713 default:
714 return -EINVAL;
715 }
716
717 if (format != old_format) {
718
719 /* clear CODECPDZ before changing format (codec requirement) */
720 twl4030_clear_codecpdz(codec);
721
722 /* change format */
723 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
724
725 /* set CODECPDZ afterwards */
726 twl4030_set_codecpdz(codec);
727 }
728
729 return 0;
730}
731
bbba9444 732#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 733#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
734
735struct snd_soc_dai twl4030_dai = {
736 .name = "twl4030",
737 .playback = {
738 .stream_name = "Playback",
739 .channels_min = 2,
740 .channels_max = 2,
741 .rates = TWL4030_RATES,
742 .formats = TWL4030_FORMATS,},
743 .capture = {
744 .stream_name = "Capture",
745 .channels_min = 2,
746 .channels_max = 2,
747 .rates = TWL4030_RATES,
748 .formats = TWL4030_FORMATS,},
749 .ops = {
750 .hw_params = twl4030_hw_params,
cc17557e
SS		 751 .set_sysclk = twl4030_set_dai_sysclk,
752 .set_fmt = twl4030_set_dai_fmt,
753 }
754};
755EXPORT_SYMBOL_GPL(twl4030_dai);
756
757static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
758{
759 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
760 struct snd_soc_codec *codec = socdev->codec;
761
762 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
763
764 return 0;
765}
766
767static int twl4030_resume(struct platform_device *pdev)
768{
769 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
770 struct snd_soc_codec *codec = socdev->codec;
771
772 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
773 twl4030_set_bias_level(codec, codec->suspend_bias_level);
774 return 0;
775}
776
777/*
778 * initialize the driver
779 * register the mixer and dsp interfaces with the kernel
780 */
781
782static int twl4030_init(struct snd_soc_device *socdev)
783{
784 struct snd_soc_codec *codec = socdev->codec;
785 int ret = 0;
786
787 printk(KERN_INFO "TWL4030 Audio Codec init \n");
788
789 codec->name = "twl4030";
790 codec->owner = THIS_MODULE;
791 codec->read = twl4030_read_reg_cache;
792 codec->write = twl4030_write;
793 codec->set_bias_level = twl4030_set_bias_level;
794 codec->dai = &twl4030_dai;
795 codec->num_dai = 1;
796 codec->reg_cache_size = sizeof(twl4030_reg);
797 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
798 GFP_KERNEL);
799 if (codec->reg_cache == NULL)
800 return -ENOMEM;
801
802 /* register pcms */
803 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
804 if (ret < 0) {
805 printk(KERN_ERR "twl4030: failed to create pcms\n");
806 goto pcm_err;
807 }
808
809 twl4030_init_chip(codec);
810
811 /* power on device */
812 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
813
814 twl4030_add_controls(codec);
815 twl4030_add_widgets(codec);
816
968a6025 817 ret = snd_soc_init_card(socdev);
cc17557e
SS		 818 if (ret < 0) {
819 printk(KERN_ERR "twl4030: failed to register card\n");
820 goto card_err;
821 }
822
823 return ret;
824
825card_err:
826 snd_soc_free_pcms(socdev);
827 snd_soc_dapm_free(socdev);
828pcm_err:
829 kfree(codec->reg_cache);
830 return ret;
831}
832
833static struct snd_soc_device *twl4030_socdev;
834
835static int twl4030_probe(struct platform_device *pdev)
836{
837 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
838 struct snd_soc_codec *codec;
839
840 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
841 if (codec == NULL)
842 return -ENOMEM;
843
844 socdev->codec = codec;
845 mutex_init(&codec->mutex);
846 INIT_LIST_HEAD(&codec->dapm_widgets);
847 INIT_LIST_HEAD(&codec->dapm_paths);
848
849 twl4030_socdev = socdev;
850 twl4030_init(socdev);
851
852 return 0;
853}
854
855static int twl4030_remove(struct platform_device *pdev)
856{
857 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
858 struct snd_soc_codec *codec = socdev->codec;
859
860 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
861 kfree(codec);
862
863 return 0;
864}
865
866struct snd_soc_codec_device soc_codec_dev_twl4030 = {
867 .probe = twl4030_probe,
868 .remove = twl4030_remove,
869 .suspend = twl4030_suspend,
870 .resume = twl4030_resume,
871};
872EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
873
874MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
875MODULE_AUTHOR("Steve Sakoman");
876MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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