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ASoC: twl4030: Introduce local ctl register cache
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e
SS		 50
51/*
52 * twl4030 register cache & default register settings
53 */
54static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
55 0x00, /* this register not used */
33f92ed4 56 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 57 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 58 0x00, /* REG_UNKNOWN (0x3) */
59 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 60 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 61 0x00, /* REG_ANAMICR (0x6) */
62 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 63 0x00, /* REG_ADCMICSEL (0x8) */
64 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 65 0x0f, /* REG_ATXL1PGA (0xA) */
66 0x0f, /* REG_ATXR1PGA (0xB) */
67 0x0f, /* REG_AVTXL2PGA (0xC) */
68 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 69 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 70 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 71 0x3f, /* REG_ARXR1PGA (0x10) */
72 0x3f, /* REG_ARXL1PGA (0x11) */
73 0x3f, /* REG_ARXR2PGA (0x12) */
74 0x3f, /* REG_ARXL2PGA (0x13) */
75 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 76 0x00, /* REG_VSTPGA (0x15) */
77 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 78 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 79 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 80 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
81 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
82 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
83 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 84 0x00, /* REG_ATX2ARXPGA (0x1D) */
85 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 86 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 87 0x00, /* REG_BTSTPGA (0x20) */
88 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 89 0x00, /* REG_HS_SEL (0x22) */
90 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 91 0x00, /* REG_HS_POPN_SET (0x24) */
92 0x00, /* REG_PREDL_CTL (0x25) */
93 0x00, /* REG_PREDR_CTL (0x26) */
94 0x00, /* REG_PRECKL_CTL (0x27) */
95 0x00, /* REG_PRECKR_CTL (0x28) */
96 0x00, /* REG_HFL_CTL (0x29) */
97 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 98 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 99 0x00, /* REG_ALC_SET1 (0x2C) */
100 0x00, /* REG_ALC_SET2 (0x2D) */
101 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 102 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 103 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 104 0x00, /* REG_DTMF_TONEXT1H (0x31) */
105 0x00, /* REG_DTMF_TONEXT1L (0x32) */
106 0x00, /* REG_DTMF_TONEXT2H (0x33) */
107 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 108 0x79, /* REG_DTMF_TONOFF (0x35) */
109 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 110 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
111 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
112 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 113 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 114 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 115 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
116 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 117 0x00, /* REG_MISC_SET_1 (0x3E) */
118 0x00, /* REG_PCMBTMUX (0x3F) */
119 0x00, /* not used (0x40) */
120 0x00, /* not used (0x41) */
121 0x00, /* not used (0x42) */
122 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 123 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 124 0x00, /* REG_VIBRA_CTL (0x45) */
125 0x00, /* REG_VIBRA_SET (0x46) */
126 0x00, /* REG_VIBRA_PWM_SET (0x47) */
127 0x00, /* REG_ANAMIC_GAIN (0x48) */
128 0x00, /* REG_MISC_SET_2 (0x49) */
129};
130
7393958f
PU		 131/* codec private data */
132struct twl4030_priv {
7393958f 133 unsigned int codec_powered;
7b4c734e
PU		 134
135 /* reference counts of AIF/APLL users */
2845fa13 136 unsigned int apll_enabled;
7220b9f4
PU		 137
138 struct snd_pcm_substream *master_substream;
139 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 140
141 unsigned int configured;
142 unsigned int rate;
143 unsigned int sample_bits;
144 unsigned int channels;
6943c92e
PU		 145
146 unsigned int sysclk;
147
c96907f2
PU		 148 /* Output (with associated amp) states */
149 u8 hsl_enabled, hsr_enabled;
150 u8 earpiece_enabled;
151 u8 predrivel_enabled, predriver_enabled;
152 u8 carkitl_enabled, carkitr_enabled;
8b3bca29 153 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
01ea6ba2 154
182f73f6 155 struct twl4030_codec_data *pdata;
7393958f
PU		 156};
157
8b3bca29
PU		 158static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
159{
160 int i;
161 u8 byte;
162
163 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
164 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
165 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
166 }
167}
168
cc17557e
SS		 169/*
170 * read twl4030 register cache
171 */
172static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
173 unsigned int reg)
174{
d08664fd 175 u8 *cache = codec->reg_cache;
cc17557e 176
91432e97
IM		 177 if (reg >= TWL4030_CACHEREGNUM)
178 return -EIO;
179
cc17557e
SS		 180 return cache[reg];
181}
182
183/*
184 * write twl4030 register cache
185 */
186static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
187 u8 reg, u8 value)
188{
189 u8 *cache = codec->reg_cache;
190
191 if (reg >= TWL4030_CACHEREGNUM)
192 return;
193 cache[reg] = value;
194}
195
a8fc415c
PU		 196static bool twl4030_can_write_to_chip(struct snd_soc_codec *codec,
197 unsigned int reg)
cc17557e 198{
b2c812e2 199 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
a8fc415c 200 bool write_to_reg = false;
c96907f2 201
052901f4
LPC		 202 /* Decide if the given register can be written */
203 switch (reg) {
204 case TWL4030_REG_EAR_CTL:
205 if (twl4030->earpiece_enabled)
a8fc415c 206 write_to_reg = true;
052901f4
LPC		 207 break;
208 case TWL4030_REG_PREDL_CTL:
209 if (twl4030->predrivel_enabled)
a8fc415c 210 write_to_reg = true;
052901f4
LPC		 211 break;
212 case TWL4030_REG_PREDR_CTL:
213 if (twl4030->predriver_enabled)
a8fc415c 214 write_to_reg = true;
052901f4
LPC		 215 break;
216 case TWL4030_REG_PRECKL_CTL:
217 if (twl4030->carkitl_enabled)
a8fc415c 218 write_to_reg = true;
052901f4
LPC		 219 break;
220 case TWL4030_REG_PRECKR_CTL:
221 if (twl4030->carkitr_enabled)
a8fc415c 222 write_to_reg = true;
052901f4
LPC		 223 break;
224 case TWL4030_REG_HS_GAIN_SET:
225 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 226 write_to_reg = true;
052901f4
LPC		 227 break;
228 default:
229 /* All other register can be written */
a8fc415c 230 write_to_reg = true;
052901f4 231 break;
c96907f2 232 }
a8fc415c
PU		 233
234 return write_to_reg;
235}
236
237/*
238 * write to the twl4030 register space
239 */
240static int twl4030_write(struct snd_soc_codec *codec,
241 unsigned int reg, unsigned int value)
242{
243 twl4030_write_reg_cache(codec, reg, value);
244 if (twl4030_can_write_to_chip(codec, reg))
245 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 246
c96907f2 247 return 0;
cc17557e
SS		 248}
249
7e6120c5
PU		 250static inline void twl4030_wait_ms(int time)
251{
252 if (time < 60) {
253 time *= 1000;
254 usleep_range(time, time + 500);
255 } else {
256 msleep(time);
257 }
258}
259
db04e2c5 260static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 261{
b2c812e2 262 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 263 int mode;
cc17557e 264
7393958f
PU		 265 if (enable == twl4030->codec_powered)
266 return;
267
db04e2c5 268 if (enable)
57fe7251 269 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 270 else
57fe7251 271 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 272
7a1fecf5
PU		 273 if (mode >= 0) {
274 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
275 twl4030->codec_powered = enable;
276 }
cc17557e
SS		 277
278 /* REVISIT: this delay is present in TI sample drivers */
279 /* but there seems to be no TRM requirement for it */
280 udelay(10);
281}
282
2d6d649a
PU		 283static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
284 struct device_node *node)
285{
286 int value;
287
288 of_property_read_u32(node, "ti,digimic_delay",
289 &pdata->digimic_delay);
290 of_property_read_u32(node, "ti,ramp_delay_value",
291 &pdata->ramp_delay_value);
292 of_property_read_u32(node, "ti,offset_cncl_path",
293 &pdata->offset_cncl_path);
294 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
295 pdata->hs_extmute = value;
296
297 pdata->hs_extmute_gpio = of_get_named_gpio(node,
298 "ti,hs_extmute_gpio", 0);
299 if (gpio_is_valid(pdata->hs_extmute_gpio))
300 pdata->hs_extmute = 1;
301}
302
303static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 304{
4ae6df5e 305 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 306 struct device_node *twl4030_codec_node = NULL;
307
308 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
309 "codec");
310
311 if (!pdata && twl4030_codec_node) {
312 pdata = devm_kzalloc(codec->dev,
313 sizeof(struct twl4030_codec_data),
314 GFP_KERNEL);
315 if (!pdata) {
316 dev_err(codec->dev, "Can not allocate memory\n");
317 return NULL;
318 }
319 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
320 }
321
322 return pdata;
323}
324
325static void twl4030_init_chip(struct snd_soc_codec *codec)
326{
327 struct twl4030_codec_data *pdata;
b2c812e2 328 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 329 u8 reg, byte;
330 int i = 0;
7393958f 331
2d6d649a
PU		 332 pdata = twl4030_get_pdata(codec);
333
5712ded9
PU		 334 if (pdata && pdata->hs_extmute) {
335 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
336 int ret;
337
338 if (!pdata->hs_extmute_gpio)
339 dev_warn(codec->dev,
340 "Extmute GPIO is 0 is this correct?\n");
341
342 ret = gpio_request_one(pdata->hs_extmute_gpio,
343 GPIOF_OUT_INIT_LOW,
344 "hs_extmute");
345 if (ret) {
346 dev_err(codec->dev,
347 "Failed to get hs_extmute GPIO\n");
348 pdata->hs_extmute_gpio = -1;
349 }
350 } else {
351 u8 pin_mux;
352
353 /* Set TWL4030 GPIO6 as EXTMUTE signal */
354 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
355 TWL4030_PMBR1_REG);
356 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
357 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
358 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
359 TWL4030_PMBR1_REG);
281ecd16
PU		 360 }
361 }
362
8b3bca29
PU		 363 /* Initialize the local ctl register cache */
364 tw4030_init_ctl_cache(twl4030);
365
ee4ccac7 366 /* Refresh APLL_CTL register from HW */
9fdcc0f7 367 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 368 TWL4030_REG_APLL_CTL);
369 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 370
ee4ccac7
PU		 371 /* anti-pop when changing analog gain */
372 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
373 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
374 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 375
ee4ccac7
PU		 376 twl4030_write(codec, TWL4030_REG_OPTION,
377 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
378 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 379
3c36cc68
PU		 380 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
381 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
382
ee4ccac7 383 /* Machine dependent setup */
f0fba2ad 384 if (!pdata)
7393958f
PU		 385 return;
386
182f73f6 387 twl4030->pdata = pdata;
ee4ccac7
PU		 388
389 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
390 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 391 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 392 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 393
394 /* initiate offset cancellation */
ee4ccac7
PU		 395 twl4030_codec_enable(codec, 1);
396
397 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
398 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 399 reg |= pdata->offset_cncl_path;
006f367e 400 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 401 reg | TWL4030_CNCL_OFFSET_START);
006f367e 402
7e6120c5
PU		 403 /*
404 * Wait for offset cancellation to complete.
405 * Since this takes a while, do not slam the i2c.
406 * Start polling the status after ~20ms.
407 */
408 msleep(20);
006f367e 409 do {
7e6120c5 410 usleep_range(1000, 2000);
fc7b92fc 411 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 412 TWL4030_REG_ANAMICL);
413 } while ((i++ < 100) &&
414 ((byte & TWL4030_CNCL_OFFSET_START) ==
415 TWL4030_CNCL_OFFSET_START));
416
417 /* Make sure that the reg_cache has the same value as the HW */
418 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
419
006f367e 420 twl4030_codec_enable(codec, 0);
006f367e
PU		 421}
422
ee4ccac7 423static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 424{
ee4ccac7
PU		 425 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
426 int status = -1;
427
428 if (enable) {
429 twl4030->apll_enabled++;
430 if (twl4030->apll_enabled == 1)
57fe7251
PU		 431 status = twl4030_audio_enable_resource(
432 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 433 } else {
434 twl4030->apll_enabled--;
435 if (!twl4030->apll_enabled)
57fe7251
PU		 436 status = twl4030_audio_disable_resource(
437 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 438 }
439
440 if (status >= 0)
441 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 442}
443
5e98a464 444/* Earpiece */
1a787e7a
JS		 445static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
446 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
447 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
448 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
449 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
450};
5e98a464 451
2a6f5c58 452/* PreDrive Left */
1a787e7a
JS		 453static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
454 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
455 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
456 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
457 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
458};
2a6f5c58
PU		 459
460/* PreDrive Right */
1a787e7a
JS		 461static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
462 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
463 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
464 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
465 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
466};
2a6f5c58 467
dfad21a2 468/* Headset Left */
1a787e7a
JS		 469static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
470 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
471 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
472 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
473};
dfad21a2
PU		 474
475/* Headset Right */
1a787e7a
JS		 476static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
477 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
478 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
479 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
480};
dfad21a2 481
5152d8c2 482/* Carkit Left */
1a787e7a
JS		 483static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
484 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
485 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
486 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
487};
5152d8c2
PU		 488
489/* Carkit Right */
1a787e7a
JS		 490static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
491 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
492 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
493 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
494};
5152d8c2 495
df339804
PU		 496/* Handsfree Left */
497static const char *twl4030_handsfreel_texts[] =
1a787e7a 498 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 499
500static const struct soc_enum twl4030_handsfreel_enum =
501 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
502 ARRAY_SIZE(twl4030_handsfreel_texts),
503 twl4030_handsfreel_texts);
504
505static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
506SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
507
0f89bdca
PU		 508/* Handsfree Left virtual mute */
509static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 510 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 511
df339804
PU		 512/* Handsfree Right */
513static const char *twl4030_handsfreer_texts[] =
1a787e7a 514 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 515
516static const struct soc_enum twl4030_handsfreer_enum =
517 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
518 ARRAY_SIZE(twl4030_handsfreer_texts),
519 twl4030_handsfreer_texts);
520
521static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
522SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
523
0f89bdca
PU		 524/* Handsfree Right virtual mute */
525static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 526 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 527
376f7839
PU		 528/* Vibra */
529/* Vibra audio path selection */
530static const char *twl4030_vibra_texts[] =
531 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
532
533static const struct soc_enum twl4030_vibra_enum =
534 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
535 ARRAY_SIZE(twl4030_vibra_texts),
536 twl4030_vibra_texts);
537
538static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
539SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
540
541/* Vibra path selection: local vibrator (PWM) or audio driven */
542static const char *twl4030_vibrapath_texts[] =
543 {"Local vibrator", "Audio"};
544
545static const struct soc_enum twl4030_vibrapath_enum =
546 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
547 ARRAY_SIZE(twl4030_vibrapath_texts),
548 twl4030_vibrapath_texts);
549
550static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
551SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
552
276c6222 553/* Left analog microphone selection */
97b8096d 554static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 555 SOC_DAPM_SINGLE("Main Mic Capture Switch",
556 TWL4030_REG_ANAMICL, 0, 1, 0),
557 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
558 TWL4030_REG_ANAMICL, 1, 1, 0),
559 SOC_DAPM_SINGLE("AUXL Capture Switch",
560 TWL4030_REG_ANAMICL, 2, 1, 0),
561 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
562 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 563};
276c6222
PU		 564
565/* Right analog microphone selection */
97b8096d 566static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 567 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
568 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 569};
276c6222
PU		 570
571/* TX1 L/R Analog/Digital microphone selection */
572static const char *twl4030_micpathtx1_texts[] =
573 {"Analog", "Digimic0"};
574
575static const struct soc_enum twl4030_micpathtx1_enum =
576 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
577 ARRAY_SIZE(twl4030_micpathtx1_texts),
578 twl4030_micpathtx1_texts);
579
580static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
581SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
582
583/* TX2 L/R Analog/Digital microphone selection */
584static const char *twl4030_micpathtx2_texts[] =
585 {"Analog", "Digimic1"};
586
587static const struct soc_enum twl4030_micpathtx2_enum =
588 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
589 ARRAY_SIZE(twl4030_micpathtx2_texts),
590 twl4030_micpathtx2_texts);
591
592static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
593SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
594
7393958f
PU		 595/* Analog bypass for AudioR1 */
596static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
597 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
598
599/* Analog bypass for AudioL1 */
600static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
601 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
602
603/* Analog bypass for AudioR2 */
604static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
605 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
606
607/* Analog bypass for AudioL2 */
608static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
609 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
610
fcd274a3
LCM		 611/* Analog bypass for Voice */
612static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
613 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
614
8b0d3153 615/* Digital bypass gain, mute instead of -30dB */
6bab83fd 616static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 617 TLV_DB_RANGE_HEAD(3),
618 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
619 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 620 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
621};
622
623/* Digital bypass left (TX1L -> RX2L) */
624static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
625 SOC_DAPM_SINGLE_TLV("Volume",
626 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
627 twl4030_dapm_dbypass_tlv);
628
629/* Digital bypass right (TX1R -> RX2R) */
630static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
631 SOC_DAPM_SINGLE_TLV("Volume",
632 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
633 twl4030_dapm_dbypass_tlv);
634
ee8f6894
LCM		 635/*
636 * Voice Sidetone GAIN volume control:
637 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
638 */
639static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
640
641/* Digital bypass voice: sidetone (VUL -> VDL)*/
642static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
643 SOC_DAPM_SINGLE_TLV("Volume",
644 TWL4030_REG_VSTPGA, 0, 0x29, 0,
645 twl4030_dapm_dbypassv_tlv);
646
9008adf9
PU		 647/*
648 * Output PGA builder:
649 * Handle the muting and unmuting of the given output (turning off the
650 * amplifier associated with the output pin)
c96907f2
PU		 651 * On mute bypass the reg_cache and write 0 to the register
652 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 653 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
654 */
655#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
656static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
657 struct snd_kcontrol *kcontrol, int event) \
658{ \
b2c812e2 659 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 660 \
661 switch (event) { \
662 case SND_SOC_DAPM_POST_PMU: \
c96907f2 663 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 664 twl4030_write(w->codec, reg, \
665 twl4030_read_reg_cache(w->codec, reg)); \
666 break; \
667 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 668 twl4030->pin_name##_enabled = 0; \
669 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
670 0, reg); \
9008adf9
PU		 671 break; \
672 } \
673 return 0; \
674}
675
676TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
677TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
678TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
679TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
680TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
681
5a2e9a48 682static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 683{
49d92c7d
SM		 684 unsigned char hs_ctl;
685
5a2e9a48 686 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 687
5a2e9a48
PU		 688 if (ramp) {
689 /* HF ramp-up */
690 hs_ctl |= TWL4030_HF_CTL_REF_EN;
691 twl4030_write(codec, reg, hs_ctl);
692 udelay(10);
49d92c7d 693 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 694 twl4030_write(codec, reg, hs_ctl);
695 udelay(40);
49d92c7d 696 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 697 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 698 twl4030_write(codec, reg, hs_ctl);
49d92c7d 699 } else {
5a2e9a48
PU		 700 /* HF ramp-down */
701 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
702 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
703 twl4030_write(codec, reg, hs_ctl);
704 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
705 twl4030_write(codec, reg, hs_ctl);
706 udelay(40);
707 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
708 twl4030_write(codec, reg, hs_ctl);
49d92c7d 709 }
5a2e9a48 710}
49d92c7d 711
5a2e9a48
PU		 712static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
713 struct snd_kcontrol *kcontrol, int event)
714{
715 switch (event) {
716 case SND_SOC_DAPM_POST_PMU:
717 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
718 break;
719 case SND_SOC_DAPM_POST_PMD:
720 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
721 break;
722 }
723 return 0;
724}
725
726static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
727 struct snd_kcontrol *kcontrol, int event)
728{
729 switch (event) {
730 case SND_SOC_DAPM_POST_PMU:
731 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
732 break;
733 case SND_SOC_DAPM_POST_PMD:
734 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
735 break;
736 }
49d92c7d
SM		 737 return 0;
738}
739
86139a13
JV		 740static int vibramux_event(struct snd_soc_dapm_widget *w,
741 struct snd_kcontrol *kcontrol, int event)
742{
743 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
744 return 0;
745}
746
7729cf74
PU		 747static int apll_event(struct snd_soc_dapm_widget *w,
748 struct snd_kcontrol *kcontrol, int event)
749{
750 switch (event) {
751 case SND_SOC_DAPM_PRE_PMU:
752 twl4030_apll_enable(w->codec, 1);
753 break;
754 case SND_SOC_DAPM_POST_PMD:
755 twl4030_apll_enable(w->codec, 0);
756 break;
757 }
758 return 0;
759}
760
7b4c734e
PU		 761static int aif_event(struct snd_soc_dapm_widget *w,
762 struct snd_kcontrol *kcontrol, int event)
763{
764 u8 audio_if;
765
766 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
767 switch (event) {
768 case SND_SOC_DAPM_PRE_PMU:
769 /* Enable AIF */
770 /* enable the PLL before we use it to clock the DAI */
771 twl4030_apll_enable(w->codec, 1);
772
773 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
774 audio_if | TWL4030_AIF_EN);
775 break;
776 case SND_SOC_DAPM_POST_PMD:
777 /* disable the DAI before we stop it's source PLL */
778 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
779 audio_if & ~TWL4030_AIF_EN);
780 twl4030_apll_enable(w->codec, 0);
781 break;
782 }
783 return 0;
784}
785
6943c92e 786static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 787{
788 unsigned char hs_gain, hs_pop;
b2c812e2 789 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 790 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 791 /* Base values for ramp delay calculation: 2^19 - 2^26 */
792 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
793 8388608, 16777216, 33554432, 67108864};
7e6120c5 794 unsigned int delay;
aad749e5 795
6943c92e
PU		 796 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
797 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 798 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
799 twl4030->sysclk) + 1;
aad749e5 800
4e49ffd1
CVJ		 801 /* Enable external mute control, this dramatically reduces
802 * the pop-noise */
f0fba2ad 803 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 804 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
805 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 806 } else {
807 hs_pop |= TWL4030_EXTMUTE;
808 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
809 }
810 }
811
6943c92e
PU		 812 if (ramp) {
813 /* Headset ramp-up according to the TRM */
aad749e5 814 hs_pop |= TWL4030_VMID_EN;
6943c92e 815 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 816 /* Actually write to the register */
817 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
818 hs_gain,
819 TWL4030_REG_HS_GAIN_SET);
aad749e5 820 hs_pop |= TWL4030_RAMP_EN;
6943c92e 821 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 822 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 823 twl4030_wait_ms(delay);
6943c92e
PU		 824 } else {
825 /* Headset ramp-down _not_ according to
826 * the TRM, but in a way that it is working */
aad749e5 827 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 828 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
829 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 830 twl4030_wait_ms(delay);
aad749e5 831 /* Bypass the reg_cache to mute the headset */
fc7b92fc 832 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 833 hs_gain & (~0x0f),
834 TWL4030_REG_HS_GAIN_SET);
6943c92e 835
aad749e5 836 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 837 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
838 }
4e49ffd1
CVJ		 839
840 /* Disable external mute */
f0fba2ad 841 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 842 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
843 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 844 } else {
845 hs_pop &= ~TWL4030_EXTMUTE;
846 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
847 }
848 }
6943c92e
PU		 849}
850
851static int headsetlpga_event(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853{
b2c812e2 854 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 855
856 switch (event) {
857 case SND_SOC_DAPM_POST_PMU:
858 /* Do the ramp-up only once */
859 if (!twl4030->hsr_enabled)
860 headset_ramp(w->codec, 1);
861
862 twl4030->hsl_enabled = 1;
863 break;
864 case SND_SOC_DAPM_POST_PMD:
865 /* Do the ramp-down only if both headsetL/R is disabled */
866 if (!twl4030->hsr_enabled)
867 headset_ramp(w->codec, 0);
868
869 twl4030->hsl_enabled = 0;
870 break;
871 }
872 return 0;
873}
874
875static int headsetrpga_event(struct snd_soc_dapm_widget *w,
876 struct snd_kcontrol *kcontrol, int event)
877{
b2c812e2 878 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 879
880 switch (event) {
881 case SND_SOC_DAPM_POST_PMU:
882 /* Do the ramp-up only once */
883 if (!twl4030->hsl_enabled)
884 headset_ramp(w->codec, 1);
885
886 twl4030->hsr_enabled = 1;
887 break;
888 case SND_SOC_DAPM_POST_PMD:
889 /* Do the ramp-down only if both headsetL/R is disabled */
890 if (!twl4030->hsl_enabled)
891 headset_ramp(w->codec, 0);
892
893 twl4030->hsr_enabled = 0;
aad749e5
PU		 894 break;
895 }
896 return 0;
897}
898
01ea6ba2
PU		 899static int digimic_event(struct snd_soc_dapm_widget *w,
900 struct snd_kcontrol *kcontrol, int event)
901{
902 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 903 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 904
182f73f6
PU		 905 if (pdata && pdata->digimic_delay)
906 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 907 return 0;
908}
909
b0bd53a7
PU		 910/*
911 * Some of the gain controls in TWL (mostly those which are associated with
912 * the outputs) are implemented in an interesting way:
913 * 0x0 : Power down (mute)
914 * 0x1 : 6dB
915 * 0x2 : 0 dB
916 * 0x3 : -6 dB
917 * Inverting not going to help with these.
918 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
919 */
b0bd53a7
PU		 920static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
921 struct snd_ctl_elem_value *ucontrol)
922{
923 struct soc_mixer_control *mc =
924 (struct soc_mixer_control *)kcontrol->private_value;
925 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
926 unsigned int reg = mc->reg;
927 unsigned int shift = mc->shift;
928 unsigned int rshift = mc->rshift;
929 int max = mc->max;
930 int mask = (1 << fls(max)) - 1;
931
932 ucontrol->value.integer.value[0] =
933 (snd_soc_read(codec, reg) >> shift) & mask;
934 if (ucontrol->value.integer.value[0])
935 ucontrol->value.integer.value[0] =
936 max + 1 - ucontrol->value.integer.value[0];
937
938 if (shift != rshift) {
939 ucontrol->value.integer.value[1] =
940 (snd_soc_read(codec, reg) >> rshift) & mask;
941 if (ucontrol->value.integer.value[1])
942 ucontrol->value.integer.value[1] =
943 max + 1 - ucontrol->value.integer.value[1];
944 }
945
946 return 0;
947}
948
949static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
950 struct snd_ctl_elem_value *ucontrol)
951{
952 struct soc_mixer_control *mc =
953 (struct soc_mixer_control *)kcontrol->private_value;
954 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
955 unsigned int reg = mc->reg;
956 unsigned int shift = mc->shift;
957 unsigned int rshift = mc->rshift;
958 int max = mc->max;
959 int mask = (1 << fls(max)) - 1;
960 unsigned short val, val2, val_mask;
961
962 val = (ucontrol->value.integer.value[0] & mask);
963
964 val_mask = mask << shift;
965 if (val)
966 val = max + 1 - val;
967 val = val << shift;
968 if (shift != rshift) {
969 val2 = (ucontrol->value.integer.value[1] & mask);
970 val_mask |= mask << rshift;
971 if (val2)
972 val2 = max + 1 - val2;
973 val |= val2 << rshift;
974 }
975 return snd_soc_update_bits(codec, reg, val_mask, val);
976}
977
978static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
979 struct snd_ctl_elem_value *ucontrol)
980{
981 struct soc_mixer_control *mc =
982 (struct soc_mixer_control *)kcontrol->private_value;
983 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
984 unsigned int reg = mc->reg;
985 unsigned int reg2 = mc->rreg;
986 unsigned int shift = mc->shift;
987 int max = mc->max;
988 int mask = (1<<fls(max))-1;
989
990 ucontrol->value.integer.value[0] =
991 (snd_soc_read(codec, reg) >> shift) & mask;
992 ucontrol->value.integer.value[1] =
993 (snd_soc_read(codec, reg2) >> shift) & mask;
994
995 if (ucontrol->value.integer.value[0])
996 ucontrol->value.integer.value[0] =
997 max + 1 - ucontrol->value.integer.value[0];
998 if (ucontrol->value.integer.value[1])
999 ucontrol->value.integer.value[1] =
1000 max + 1 - ucontrol->value.integer.value[1];
1001
1002 return 0;
1003}
1004
1005static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1006 struct snd_ctl_elem_value *ucontrol)
1007{
1008 struct soc_mixer_control *mc =
1009 (struct soc_mixer_control *)kcontrol->private_value;
1010 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1011 unsigned int reg = mc->reg;
1012 unsigned int reg2 = mc->rreg;
1013 unsigned int shift = mc->shift;
1014 int max = mc->max;
1015 int mask = (1 << fls(max)) - 1;
1016 int err;
1017 unsigned short val, val2, val_mask;
1018
1019 val_mask = mask << shift;
1020 val = (ucontrol->value.integer.value[0] & mask);
1021 val2 = (ucontrol->value.integer.value[1] & mask);
1022
1023 if (val)
1024 val = max + 1 - val;
1025 if (val2)
1026 val2 = max + 1 - val2;
1027
1028 val = val << shift;
1029 val2 = val2 << shift;
1030
1031 err = snd_soc_update_bits(codec, reg, val_mask, val);
1032 if (err < 0)
1033 return err;
1034
1035 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1036 return err;
1037}
1038
b74bd40f
LCM		 1039/* Codec operation modes */
1040static const char *twl4030_op_modes_texts[] = {
1041 "Option 2 (voice/audio)", "Option 1 (audio)"
1042};
1043
1044static const struct soc_enum twl4030_op_modes_enum =
1045 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1046 ARRAY_SIZE(twl4030_op_modes_texts),
1047 twl4030_op_modes_texts);
1048
423c238d 1049static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1050 struct snd_ctl_elem_value *ucontrol)
1051{
1052 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1053 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1054 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1055 unsigned short val;
86767b7d 1056 unsigned short mask;
b74bd40f
LCM		 1057
1058 if (twl4030->configured) {
3b8a0795
PU		 1059 dev_err(codec->dev,
1060 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 1061 return -EBUSY;
1062 }
1063
b74bd40f
LCM		 1064 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1065 return -EINVAL;
1066
1067 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 1068 mask = e->mask << e->shift_l;
b74bd40f
LCM		 1069 if (e->shift_l != e->shift_r) {
1070 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1071 return -EINVAL;
1072 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 1073 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 1074 }
1075
1076 return snd_soc_update_bits(codec, e->reg, mask, val);
1077}
1078
c10b82cf
PU		 1079/*
1080 * FGAIN volume control:
1081 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1082 */
d889a72c 1083static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1084
0d33ea0b
PU		 1085/*
1086 * CGAIN volume control:
1087 * 0 dB to 12 dB in 6 dB steps
1088 * value 2 and 3 means 12 dB
1089 */
d889a72c
PU		 1090static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1091
1a787e7a
JS		 1092/*
1093 * Voice Downlink GAIN volume control:
1094 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1095 */
1096static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1097
d889a72c
PU		 1098/*
1099 * Analog playback gain
1100 * -24 dB to 12 dB in 2 dB steps
1101 */
1102static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1103
4290239c
PU		 1104/*
1105 * Gain controls tied to outputs
1106 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1107 */
1108static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1109
18cc8d8d
JS		 1110/*
1111 * Gain control for earpiece amplifier
1112 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1113 */
1114static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1115
381a22b5
PU		 1116/*
1117 * Capture gain after the ADCs
1118 * from 0 dB to 31 dB in 1 dB steps
1119 */
1120static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1121
5920b453
GI		 1122/*
1123 * Gain control for input amplifiers
1124 * 0 dB to 30 dB in 6 dB steps
1125 */
1126static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1127
328d0a13
LCM		 1128/* AVADC clock priority */
1129static const char *twl4030_avadc_clk_priority_texts[] = {
1130 "Voice high priority", "HiFi high priority"
1131};
1132
1133static const struct soc_enum twl4030_avadc_clk_priority_enum =
1134 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1135 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1136 twl4030_avadc_clk_priority_texts);
1137
89492be8
PU		 1138static const char *twl4030_rampdelay_texts[] = {
1139 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1140 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1141 "3495/2581/1748 ms"
1142};
1143
1144static const struct soc_enum twl4030_rampdelay_enum =
1145 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1146 ARRAY_SIZE(twl4030_rampdelay_texts),
1147 twl4030_rampdelay_texts);
1148
376f7839
PU		 1149/* Vibra H-bridge direction mode */
1150static const char *twl4030_vibradirmode_texts[] = {
1151 "Vibra H-bridge direction", "Audio data MSB",
1152};
1153
1154static const struct soc_enum twl4030_vibradirmode_enum =
1155 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1156 ARRAY_SIZE(twl4030_vibradirmode_texts),
1157 twl4030_vibradirmode_texts);
1158
1159/* Vibra H-bridge direction */
1160static const char *twl4030_vibradir_texts[] = {
1161 "Positive polarity", "Negative polarity",
1162};
1163
1164static const struct soc_enum twl4030_vibradir_enum =
1165 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1166 ARRAY_SIZE(twl4030_vibradir_texts),
1167 twl4030_vibradir_texts);
1168
36aeff61
PU		 1169/* Digimic Left and right swapping */
1170static const char *twl4030_digimicswap_texts[] = {
1171 "Not swapped", "Swapped",
1172};
1173
1174static const struct soc_enum twl4030_digimicswap_enum =
1175 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1176 ARRAY_SIZE(twl4030_digimicswap_texts),
1177 twl4030_digimicswap_texts);
1178
cc17557e 1179static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1180 /* Codec operation mode control */
1181 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1182 snd_soc_get_enum_double,
1183 snd_soc_put_twl4030_opmode_enum_double),
1184
d889a72c
PU		 1185 /* Common playback gain controls */
1186 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1187 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1188 0, 0x3f, 0, digital_fine_tlv),
1189 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1190 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1191 0, 0x3f, 0, digital_fine_tlv),
1192
1193 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1194 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1195 6, 0x2, 0, digital_coarse_tlv),
1196 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1197 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1198 6, 0x2, 0, digital_coarse_tlv),
1199
1200 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1201 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1202 3, 0x12, 1, analog_tlv),
1203 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1204 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1205 3, 0x12, 1, analog_tlv),
44c55870
PU		 1206 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1207 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1208 1, 1, 0),
1209 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1210 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1211 1, 1, 0),
381a22b5 1212
1a787e7a
JS		 1213 /* Common voice downlink gain controls */
1214 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1215 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1216
1217 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1218 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1219
1220 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1221 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1222
4290239c 1223 /* Separate output gain controls */
0f9887d1 1224 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1225 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1226 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1227 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1228
0f9887d1
PU		 1229 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1230 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1231 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1232
0f9887d1 1233 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1234 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1235 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1236 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1237
0f9887d1
PU		 1238 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1239 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1240 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1241
381a22b5 1242 /* Common capture gain controls */
276c6222 1243 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1244 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1245 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1246 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1247 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1248 0, 0x1f, 0, digital_capture_tlv),
5920b453 1249
276c6222 1250 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1251 0, 3, 5, 0, input_gain_tlv),
89492be8 1252
328d0a13
LCM		 1253 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1254
89492be8 1255 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1256
1257 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1258 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1259
1260 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1261};
1262
cc17557e 1263static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1264 /* Left channel inputs */
1265 SND_SOC_DAPM_INPUT("MAINMIC"),
1266 SND_SOC_DAPM_INPUT("HSMIC"),
1267 SND_SOC_DAPM_INPUT("AUXL"),
1268 SND_SOC_DAPM_INPUT("CARKITMIC"),
1269 /* Right channel inputs */
1270 SND_SOC_DAPM_INPUT("SUBMIC"),
1271 SND_SOC_DAPM_INPUT("AUXR"),
1272 /* Digital microphones (Stereo) */
1273 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1274 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1275
1276 /* Outputs */
5e98a464 1277 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1278 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1279 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1280 SND_SOC_DAPM_OUTPUT("HSOL"),
1281 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1282 SND_SOC_DAPM_OUTPUT("CARKITL"),
1283 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1284 SND_SOC_DAPM_OUTPUT("HFL"),
1285 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1286 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1287
7b4c734e
PU		 1288 /* AIF and APLL clocks for running DAIs (including loopback) */
1289 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1290 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1291 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1292
53b5047d 1293 /* DACs */
7f51e7d3
PU		 1294 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1295 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1296 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1297 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1298 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1299
927a7747
PU		 1300 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1301 TWL4030_REG_VOICE_IF, 6, 0),
1302
7393958f 1303 /* Analog bypasses */
78e08e2f
PU		 1304 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1305 &twl4030_dapm_abypassr1_control),
1306 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1307 &twl4030_dapm_abypassl1_control),
1308 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1309 &twl4030_dapm_abypassr2_control),
1310 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1311 &twl4030_dapm_abypassl2_control),
1312 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1313 &twl4030_dapm_abypassv_control),
1314
1315 /* Master analog loopback switch */
1316 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1317 NULL, 0),
7393958f 1318
6bab83fd 1319 /* Digital bypasses */
78e08e2f
PU		 1320 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1321 &twl4030_dapm_dbypassl_control),
1322 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1323 &twl4030_dapm_dbypassr_control),
1324 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1325 &twl4030_dapm_dbypassv_control),
6bab83fd 1326
4005d39a
PU		 1327 /* Digital mixers, power control for the physical DACs */
1328 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1329 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1330 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1331 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1332 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1333 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1334 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1335 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1336 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1337 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1338
1339 /* Analog mixers, power control for the physical PGAs */
1340 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1341 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1342 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1343 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1344 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1345 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1346 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1347 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1348 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1349 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1350
7729cf74
PU		 1351 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1352 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1353
7b4c734e
PU		 1354 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1355 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1356
1a787e7a 1357 /* Output MIXER controls */
5e98a464 1358 /* Earpiece */
1a787e7a
JS		 1359 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1360 &twl4030_dapm_earpiece_controls[0],
1361 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1362 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1363 0, 0, NULL, 0, earpiecepga_event,
1364 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1365 /* PreDrivL/R */
1a787e7a
JS		 1366 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1367 &twl4030_dapm_predrivel_controls[0],
1368 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1369 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1370 0, 0, NULL, 0, predrivelpga_event,
1371 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1372 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1373 &twl4030_dapm_predriver_controls[0],
1374 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1375 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1376 0, 0, NULL, 0, predriverpga_event,
1377 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1378 /* HeadsetL/R */
6943c92e 1379 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1380 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1381 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1382 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1383 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1384 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1385 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1386 &twl4030_dapm_hsor_controls[0],
1387 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1388 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1389 0, 0, NULL, 0, headsetrpga_event,
1390 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1391 /* CarkitL/R */
1a787e7a
JS		 1392 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1393 &twl4030_dapm_carkitl_controls[0],
1394 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1395 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1396 0, 0, NULL, 0, carkitlpga_event,
1397 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1398 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1399 &twl4030_dapm_carkitr_controls[0],
1400 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1401 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1402 0, 0, NULL, 0, carkitrpga_event,
1403 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1404
1405 /* Output MUX controls */
df339804 1406 /* HandsfreeL/R */
5a2e9a48
PU		 1407 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1408 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1409 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1410 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1411 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1412 0, 0, NULL, 0, handsfreelpga_event,
1413 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1414 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1415 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1416 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1417 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1418 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1419 0, 0, NULL, 0, handsfreerpga_event,
1420 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1421 /* Vibra */
86139a13
JV		 1422 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1423 &twl4030_dapm_vibra_control, vibramux_event,
1424 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1425 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1426 &twl4030_dapm_vibrapath_control),
5e98a464 1427
276c6222
PU		 1428 /* Introducing four virtual ADC, since TWL4030 have four channel for
1429 capture */
7f51e7d3
PU		 1430 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1431 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1432 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1433 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1434
927a7747
PU		 1435 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1436 TWL4030_REG_VOICE_IF, 5, 0),
1437
276c6222
PU		 1438 /* Analog/Digital mic path selection.
1439 TX1 Left/Right: either analog Left/Right or Digimic0
1440 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1441 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1442 &twl4030_dapm_micpathtx1_control),
1443 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1444 &twl4030_dapm_micpathtx2_control),
276c6222 1445
97b8096d 1446 /* Analog input mixers for the capture amplifiers */
9028935d 1447 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1448 TWL4030_REG_ANAMICL, 4, 0,
1449 &twl4030_dapm_analoglmic_controls[0],
1450 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1451 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1452 TWL4030_REG_ANAMICR, 4, 0,
1453 &twl4030_dapm_analogrmic_controls[0],
1454 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1455
fb2a2f84
PU		 1456 SND_SOC_DAPM_PGA("ADC Physical Left",
1457 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1458 SND_SOC_DAPM_PGA("ADC Physical Right",
1459 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1460
01ea6ba2
PU		 1461 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1462 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1463 digimic_event, SND_SOC_DAPM_POST_PMU),
1464 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1465 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1466 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1467
bda7d2a8
PU		 1468 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1469 NULL, 0),
1470 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1471 NULL, 0),
1472
e04d6e55
PU		 1473 /* Microphone bias */
1474 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1475 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1476 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1477 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1478 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1479 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1480
927a7747 1481 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1482};
1483
1484static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1485 /* Stream -> DAC mapping */
1486 {"DAC Right1", NULL, "HiFi Playback"},
1487 {"DAC Left1", NULL, "HiFi Playback"},
1488 {"DAC Right2", NULL, "HiFi Playback"},
1489 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1490 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1491
1492 /* ADC -> Stream mapping */
1493 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1494 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1495 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1496 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1497 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1498 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1499 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1500
4005d39a
PU		 1501 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1502 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1503 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1504 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1505 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1506
7729cf74 1507 /* Supply for the digital part (APLL) */
7729cf74
PU		 1508 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1509
27eeb1fe
PU		 1510 {"DAC Left1", NULL, "AIF Enable"},
1511 {"DAC Right1", NULL, "AIF Enable"},
1512 {"DAC Left2", NULL, "AIF Enable"},
1513 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1514 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1515
c42a59ea
PU		 1516 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1517 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1518
4005d39a
PU		 1519 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1520 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1521 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1522 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1523 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1524
5e98a464
PU		 1525 /* Internal playback routings */
1526 /* Earpiece */
4005d39a
PU		 1527 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1528 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1529 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1530 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1531 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1532 /* PreDrivL */
4005d39a
PU		 1533 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1534 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1535 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1536 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1537 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1538 /* PreDrivR */
4005d39a
PU		 1539 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1540 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1541 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1542 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1543 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1544 /* HeadsetL */
4005d39a
PU		 1545 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1546 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1547 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1548 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1549 /* HeadsetR */
4005d39a
PU		 1550 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1551 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1552 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1553 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1554 /* CarkitL */
4005d39a
PU		 1555 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1556 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1557 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1558 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1559 /* CarkitR */
4005d39a
PU		 1560 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1561 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1562 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1563 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1564 /* HandsfreeL */
4005d39a
PU		 1565 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1566 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1567 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1568 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1569 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1570 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1571 /* HandsfreeR */
4005d39a
PU		 1572 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1573 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1574 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1575 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1576 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1577 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1578 /* Vibra */
1579 {"Vibra Mux", "AudioL1", "DAC Left1"},
1580 {"Vibra Mux", "AudioR1", "DAC Right1"},
1581 {"Vibra Mux", "AudioL2", "DAC Left2"},
1582 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1583
cc17557e 1584 /* outputs */
7b4c734e 1585 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1586 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1587 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1588 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1589 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1590 /* Must be always connected (for APLL) */
1591 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1592 /* Physical outputs */
9008adf9
PU		 1593 {"EARPIECE", NULL, "Earpiece PGA"},
1594 {"PREDRIVEL", NULL, "PredriveL PGA"},
1595 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1596 {"HSOL", NULL, "HeadsetL PGA"},
1597 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1598 {"CARKITL", NULL, "CarkitL PGA"},
1599 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1600 {"HFL", NULL, "HandsfreeL PGA"},
1601 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1602 {"Vibra Route", "Audio", "Vibra Mux"},
1603 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1604
276c6222 1605 /* Capture path */
7b4c734e
PU		 1606 /* Must be always connected (for AIF and APLL) */
1607 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1608 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1609 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1610 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1611 /* Physical inputs */
9028935d
PU		 1612 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1613 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1614 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1615 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1616
9028935d
PU		 1617 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1618 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1619
9028935d
PU		 1620 {"ADC Physical Left", NULL, "Analog Left"},
1621 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1622
1623 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1624 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1625
bda7d2a8
PU		 1626 {"DIGIMIC0", NULL, "micbias1 select"},
1627 {"DIGIMIC1", NULL, "micbias2 select"},
1628
276c6222 1629 /* TX1 Left capture path */
fb2a2f84 1630 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1631 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1632 /* TX1 Right capture path */
fb2a2f84 1633 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1634 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1635 /* TX2 Left capture path */
fb2a2f84 1636 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1637 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1638 /* TX2 Right capture path */
fb2a2f84 1639 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1640 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1641
1642 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1643 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1644 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1645 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1646
c42a59ea
PU		 1647 {"ADC Virtual Left1", NULL, "AIF Enable"},
1648 {"ADC Virtual Right1", NULL, "AIF Enable"},
1649 {"ADC Virtual Left2", NULL, "AIF Enable"},
1650 {"ADC Virtual Right2", NULL, "AIF Enable"},
1651
7393958f 1652 /* Analog bypass routes */
9028935d
PU		 1653 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1654 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1655 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1656 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1657 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1658
78e08e2f
PU		 1659 /* Supply for the Analog loopbacks */
1660 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1661 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1662 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1663 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1664 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1665
7393958f
PU		 1666 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1667 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1668 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1669 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1670 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1671
6bab83fd
PU		 1672 /* Digital bypass routes */
1673 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1674 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1675 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1676
4005d39a
PU		 1677 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1678 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1679 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1680
cc17557e
SS		 1681};
1682
cc17557e
SS		 1683static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1684 enum snd_soc_bias_level level)
1685{
1686 switch (level) {
1687 case SND_SOC_BIAS_ON:
cc17557e
SS		 1688 break;
1689 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1690 break;
1691 case SND_SOC_BIAS_STANDBY:
ce6120cc 1692 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1693 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1694 break;
1695 case SND_SOC_BIAS_OFF:
cbd2db12 1696 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1697 break;
1698 }
ce6120cc 1699 codec->dapm.bias_level = level;
cc17557e
SS		 1700
1701 return 0;
1702}
1703
6b87a91f
PU		 1704static void twl4030_constraints(struct twl4030_priv *twl4030,
1705 struct snd_pcm_substream *mst_substream)
1706{
1707 struct snd_pcm_substream *slv_substream;
1708
1709 /* Pick the stream, which need to be constrained */
1710 if (mst_substream == twl4030->master_substream)
1711 slv_substream = twl4030->slave_substream;
1712 else if (mst_substream == twl4030->slave_substream)
1713 slv_substream = twl4030->master_substream;
1714 else /* This should not happen.. */
1715 return;
1716
1717 /* Set the constraints according to the already configured stream */
1718 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1719 SNDRV_PCM_HW_PARAM_RATE,
1720 twl4030->rate,
1721 twl4030->rate);
1722
1723 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1724 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1725 twl4030->sample_bits,
1726 twl4030->sample_bits);
1727
1728 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1729 SNDRV_PCM_HW_PARAM_CHANNELS,
1730 twl4030->channels,
1731 twl4030->channels);
1732}
1733
8a1f936a
PU		 1734/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1735 * capture has to be enabled/disabled. */
1736static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1737 int enable)
1738{
1739 u8 reg, mask;
1740
1741 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1742
1743 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1744 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1745 else
1746 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1747
1748 if (enable)
1749 reg |= mask;
1750 else
1751 reg &= ~mask;
1752
1753 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1754}
1755
d6648da1
PU		 1756static int twl4030_startup(struct snd_pcm_substream *substream,
1757 struct snd_soc_dai *dai)
7220b9f4 1758{
e6968a17 1759 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1760 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1761
7220b9f4 1762 if (twl4030->master_substream) {
7220b9f4 1763 twl4030->slave_substream = substream;
6b87a91f
PU		 1764 /* The DAI has one configuration for playback and capture, so
1765 * if the DAI has been already configured then constrain this
1766 * substream to match it. */
1767 if (twl4030->configured)
1768 twl4030_constraints(twl4030, twl4030->master_substream);
1769 } else {
8a1f936a
PU		 1770 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1771 TWL4030_OPTION_1)) {
1772 /* In option2 4 channel is not supported, set the
1773 * constraint for the first stream for channels, the
1774 * second stream will 'inherit' this cosntraint */
1775 snd_pcm_hw_constraint_minmax(substream->runtime,
1776 SNDRV_PCM_HW_PARAM_CHANNELS,
1777 2, 2);
1778 }
7220b9f4 1779 twl4030->master_substream = substream;
6b87a91f 1780 }
7220b9f4
PU		 1781
1782 return 0;
1783}
1784
d6648da1
PU		 1785static void twl4030_shutdown(struct snd_pcm_substream *substream,
1786 struct snd_soc_dai *dai)
7220b9f4 1787{
e6968a17 1788 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1789 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1790
1791 if (twl4030->master_substream == substream)
1792 twl4030->master_substream = twl4030->slave_substream;
1793
1794 twl4030->slave_substream = NULL;
6b87a91f
PU		 1795
1796 /* If all streams are closed, or the remaining stream has not yet
1797 * been configured than set the DAI as not configured. */
1798 if (!twl4030->master_substream)
1799 twl4030->configured = 0;
1800 else if (!twl4030->master_substream->runtime->channels)
1801 twl4030->configured = 0;
8a1f936a
PU		 1802
1803 /* If the closing substream had 4 channel, do the necessary cleanup */
1804 if (substream->runtime->channels == 4)
1805 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1806}
1807
cc17557e 1808static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1809 struct snd_pcm_hw_params *params,
1810 struct snd_soc_dai *dai)
cc17557e 1811{
e6968a17 1812 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1813 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1814 u8 mode, old_mode, format, old_format;
1815
8a1f936a
PU		 1816 /* If the substream has 4 channel, do the necessary setup */
1817 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1818 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1819 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1820
1821 /* Safety check: are we in the correct operating mode and
1822 * the interface is in TDM mode? */
1823 if ((mode & TWL4030_OPTION_1) &&
1824 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1825 twl4030_tdm_enable(codec, substream->stream, 1);
1826 else
1827 return -EINVAL;
1828 }
1829
6b87a91f
PU		 1830 if (twl4030->configured)
1831 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1832 return 0;
1833
cc17557e
SS		 1834 /* bit rate */
1835 old_mode = twl4030_read_reg_cache(codec,
1836 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1837 mode = old_mode & ~TWL4030_APLL_RATE;
1838
1839 switch (params_rate(params)) {
1840 case 8000:
1841 mode |= TWL4030_APLL_RATE_8000;
1842 break;
1843 case 11025:
1844 mode |= TWL4030_APLL_RATE_11025;
1845 break;
1846 case 12000:
1847 mode |= TWL4030_APLL_RATE_12000;
1848 break;
1849 case 16000:
1850 mode |= TWL4030_APLL_RATE_16000;
1851 break;
1852 case 22050:
1853 mode |= TWL4030_APLL_RATE_22050;
1854 break;
1855 case 24000:
1856 mode |= TWL4030_APLL_RATE_24000;
1857 break;
1858 case 32000:
1859 mode |= TWL4030_APLL_RATE_32000;
1860 break;
1861 case 44100:
1862 mode |= TWL4030_APLL_RATE_44100;
1863 break;
1864 case 48000:
1865 mode |= TWL4030_APLL_RATE_48000;
1866 break;
103f211d
PU		 1867 case 96000:
1868 mode |= TWL4030_APLL_RATE_96000;
1869 break;
cc17557e 1870 default:
3b8a0795 1871 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1872 params_rate(params));
1873 return -EINVAL;
1874 }
1875
cc17557e
SS		 1876 /* sample size */
1877 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1878 format = old_format;
1879 format &= ~TWL4030_DATA_WIDTH;
1880 switch (params_format(params)) {
1881 case SNDRV_PCM_FORMAT_S16_LE:
1882 format |= TWL4030_DATA_WIDTH_16S_16W;
1883 break;
dcdeda4a 1884 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1885 format |= TWL4030_DATA_WIDTH_32S_24W;
1886 break;
1887 default:
3b8a0795 1888 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1889 params_format(params));
1890 return -EINVAL;
1891 }
1892
2046f175
PU		 1893 if (format != old_format || mode != old_mode) {
1894 if (twl4030->codec_powered) {
1895 /*
1896 * If the codec is powered, than we need to toggle the
1897 * codec power.
1898 */
1899 twl4030_codec_enable(codec, 0);
1900 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1901 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1902 twl4030_codec_enable(codec, 1);
1903 } else {
1904 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1905 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1906 }
cc17557e 1907 }
6b87a91f
PU		 1908
1909 /* Store the important parameters for the DAI configuration and set
1910 * the DAI as configured */
1911 twl4030->configured = 1;
1912 twl4030->rate = params_rate(params);
1913 twl4030->sample_bits = hw_param_interval(params,
1914 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1915 twl4030->channels = params_channels(params);
1916
1917 /* If both playback and capture streams are open, and one of them
1918 * is setting the hw parameters right now (since we are here), set
1919 * constraints to the other stream to match the current one. */
1920 if (twl4030->slave_substream)
1921 twl4030_constraints(twl4030, substream);
1922
cc17557e
SS		 1923 return 0;
1924}
1925
1926static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1927 int clk_id, unsigned int freq, int dir)
1928{
1929 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1930 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1931
1932 switch (freq) {
1933 case 19200000:
cc17557e 1934 case 26000000:
cc17557e 1935 case 38400000:
cc17557e
SS		 1936 break;
1937 default:
3b8a0795 1938 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1939 return -EINVAL;
1940 }
1941
68d01955
PU		 1942 if ((freq / 1000) != twl4030->sysclk) {
1943 dev_err(codec->dev,
3b8a0795 1944 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1945 freq, twl4030->sysclk * 1000);
1946 return -EINVAL;
1947 }
cc17557e
SS		 1948
1949 return 0;
1950}
1951
1952static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1953 unsigned int fmt)
1954{
1955 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1956 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1957 u8 old_format, format;
1958
1959 /* get format */
1960 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1961 format = old_format;
1962
1963 /* set master/slave audio interface */
1964 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1965 case SND_SOC_DAIFMT_CBM_CFM:
1966 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1967 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1968 break;
1969 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1970 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1971 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1972 break;
1973 default:
1974 return -EINVAL;
1975 }
1976
1977 /* interface format */
1978 format &= ~TWL4030_AIF_FORMAT;
1979 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1980 case SND_SOC_DAIFMT_I2S:
1981 format |= TWL4030_AIF_FORMAT_CODEC;
1982 break;
8a1f936a
PU		 1983 case SND_SOC_DAIFMT_DSP_A:
1984 format |= TWL4030_AIF_FORMAT_TDM;
1985 break;
cc17557e
SS		 1986 default:
1987 return -EINVAL;
1988 }
1989
1990 if (format != old_format) {
2046f175
PU		 1991 if (twl4030->codec_powered) {
1992 /*
1993 * If the codec is powered, than we need to toggle the
1994 * codec power.
1995 */
1996 twl4030_codec_enable(codec, 0);
1997 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1998 twl4030_codec_enable(codec, 1);
1999 } else {
2000 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2001 }
cc17557e
SS		 2002 }
2003
2004 return 0;
2005}
2006
68140443
LCM		 2007static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
2008{
2009 struct snd_soc_codec *codec = dai->codec;
2010 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
2011
2012 if (tristate)
2013 reg |= TWL4030_AIF_TRI_EN;
2014 else
2015 reg &= ~TWL4030_AIF_TRI_EN;
2016
2017 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2018}
2019
b7a755a8
MLC		 2020/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2021 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2022static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2023 int enable)
2024{
2025 u8 reg, mask;
2026
2027 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2028
2029 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2030 mask = TWL4030_ARXL1_VRX_EN;
2031 else
2032 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2033
2034 if (enable)
2035 reg |= mask;
2036 else
2037 reg &= ~mask;
2038
2039 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2040}
2041
7154b3e8
JS		 2042static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2043 struct snd_soc_dai *dai)
2044{
e6968a17 2045 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2046 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2047 u8 mode;
2048
2049 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 2050 * not available.
7154b3e8 2051 */
68d01955 2052 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 2053 dev_err(codec->dev,
2054 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2055 __func__, twl4030->sysclk);
7154b3e8
JS		 2056 return -EINVAL;
2057 }
2058
2059 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 2060 * available.
7154b3e8
JS		 2061 */
2062 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2063 & TWL4030_OPT_MODE;
2064
2065 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 2066 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2067 __func__);
7154b3e8
JS		 2068 return -EINVAL;
2069 }
2070
2071 return 0;
2072}
2073
b7a755a8
MLC		 2074static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2075 struct snd_soc_dai *dai)
2076{
e6968a17 2077 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 2078
2079 /* Enable voice digital filters */
2080 twl4030_voice_enable(codec, substream->stream, 0);
2081}
2082
7154b3e8
JS		 2083static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2084 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2085{
e6968a17 2086 struct snd_soc_codec *codec = dai->codec;
2046f175 2087 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2088 u8 old_mode, mode;
2089
b7a755a8
MLC		 2090 /* Enable voice digital filters */
2091 twl4030_voice_enable(codec, substream->stream, 1);
2092
7154b3e8
JS		 2093 /* bit rate */
2094 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2095 & ~(TWL4030_CODECPDZ);
2096 mode = old_mode;
2097
2098 switch (params_rate(params)) {
2099 case 8000:
2100 mode &= ~(TWL4030_SEL_16K);
2101 break;
2102 case 16000:
2103 mode |= TWL4030_SEL_16K;
2104 break;
2105 default:
3b8a0795 2106 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2107 params_rate(params));
2108 return -EINVAL;
2109 }
2110
2111 if (mode != old_mode) {
2046f175
PU		 2112 if (twl4030->codec_powered) {
2113 /*
2114 * If the codec is powered, than we need to toggle the
2115 * codec power.
2116 */
2117 twl4030_codec_enable(codec, 0);
2118 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2119 twl4030_codec_enable(codec, 1);
2120 } else {
2121 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2122 }
7154b3e8
JS		 2123 }
2124
2125 return 0;
2126}
2127
2128static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2129 int clk_id, unsigned int freq, int dir)
2130{
2131 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2132 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2133
68d01955 2134 if (freq != 26000000) {
3b8a0795
PU		 2135 dev_err(codec->dev,
2136 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2137 __func__, freq / 1000);
68d01955
PU		 2138 return -EINVAL;
2139 }
2140 if ((freq / 1000) != twl4030->sysclk) {
2141 dev_err(codec->dev,
3b8a0795 2142 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2143 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2144 return -EINVAL;
2145 }
7154b3e8
JS		 2146 return 0;
2147}
2148
2149static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2150 unsigned int fmt)
2151{
2152 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2153 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2154 u8 old_format, format;
2155
2156 /* get format */
2157 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2158 format = old_format;
2159
2160 /* set master/slave audio interface */
2161 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2162 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2163 format &= ~(TWL4030_VIF_SLAVE_EN);
2164 break;
2165 case SND_SOC_DAIFMT_CBS_CFS:
2166 format |= TWL4030_VIF_SLAVE_EN;
2167 break;
2168 default:
2169 return -EINVAL;
2170 }
2171
2172 /* clock inversion */
2173 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2174 case SND_SOC_DAIFMT_IB_NF:
2175 format &= ~(TWL4030_VIF_FORMAT);
2176 break;
2177 case SND_SOC_DAIFMT_NB_IF:
2178 format |= TWL4030_VIF_FORMAT;
2179 break;
2180 default:
2181 return -EINVAL;
2182 }
2183
2184 if (format != old_format) {
2046f175
PU		 2185 if (twl4030->codec_powered) {
2186 /*
2187 * If the codec is powered, than we need to toggle the
2188 * codec power.
2189 */
2190 twl4030_codec_enable(codec, 0);
2191 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2192 twl4030_codec_enable(codec, 1);
2193 } else {
2194 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2195 }
7154b3e8
JS		 2196 }
2197
2198 return 0;
2199}
2200
68140443
LCM		 2201static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2202{
2203 struct snd_soc_codec *codec = dai->codec;
2204 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2205
2206 if (tristate)
2207 reg |= TWL4030_VIF_TRI_EN;
2208 else
2209 reg &= ~TWL4030_VIF_TRI_EN;
2210
2211 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2212}
2213
bbba9444 2214#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2215#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2216
85e7652d 2217static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2218 .startup = twl4030_startup,
2219 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2220 .hw_params = twl4030_hw_params,
2221 .set_sysclk = twl4030_set_dai_sysclk,
2222 .set_fmt = twl4030_set_dai_fmt,
68140443 2223 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2224};
2225
85e7652d 2226static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2227 .startup = twl4030_voice_startup,
b7a755a8 2228 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2229 .hw_params = twl4030_voice_hw_params,
2230 .set_sysclk = twl4030_voice_set_dai_sysclk,
2231 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2232 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2233};
2234
f0fba2ad 2235static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2236{
f0fba2ad 2237 .name = "twl4030-hifi",
cc17557e 2238 .playback = {
b4852b79 2239 .stream_name = "HiFi Playback",
cc17557e 2240 .channels_min = 2,
8a1f936a 2241 .channels_max = 4,
31ad0f31 2242 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2243 .formats = TWL4030_FORMATS,
2244 .sig_bits = 24,},
cc17557e 2245 .capture = {
7f51e7d3 2246 .stream_name = "HiFi Capture",
cc17557e 2247 .channels_min = 2,
8a1f936a 2248 .channels_max = 4,
cc17557e 2249 .rates = TWL4030_RATES,
8819f65c
PU		 2250 .formats = TWL4030_FORMATS,
2251 .sig_bits = 24,},
f0fba2ad 2252 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2253},
2254{
f0fba2ad 2255 .name = "twl4030-voice",
7154b3e8 2256 .playback = {
b4852b79 2257 .stream_name = "Voice Playback",
7154b3e8
JS		 2258 .channels_min = 1,
2259 .channels_max = 1,
2260 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2261 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2262 .capture = {
7f51e7d3 2263 .stream_name = "Voice Capture",
7154b3e8
JS		 2264 .channels_min = 1,
2265 .channels_max = 2,
2266 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2267 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2268 .ops = &twl4030_dai_voice_ops,
2269},
cc17557e 2270};
cc17557e 2271
f0fba2ad 2272static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2273{
f0fba2ad 2274 struct twl4030_priv *twl4030;
9da28c7b 2275
f2b1ce49
PU		 2276 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2277 GFP_KERNEL);
f0fba2ad 2278 if (twl4030 == NULL) {
3b8a0795 2279 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2280 return -ENOMEM;
cc17557e 2281 }
f0fba2ad
LG		 2282 snd_soc_codec_set_drvdata(codec, twl4030);
2283 /* Set the defaults, and power up the codec */
57fe7251 2284 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2285
2286 twl4030_init_chip(codec);
cc17557e 2287
7a1fecf5 2288 return 0;
cc17557e
SS		 2289}
2290
f0fba2ad 2291static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2292{
5b3b0fa8 2293 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2294 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2295
7a1fecf5 2296 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2297
2298 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2299 gpio_free(pdata->hs_extmute_gpio);
2300
7a1fecf5
PU		 2301 return 0;
2302}
2303
f0fba2ad
LG		 2304static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2305 .probe = twl4030_soc_probe,
2306 .remove = twl4030_soc_remove,
f0fba2ad
LG		 2307 .read = twl4030_read_reg_cache,
2308 .write = twl4030_write,
2309 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2310 .idle_bias_off = true,
f0fba2ad
LG		 2311 .reg_cache_size = sizeof(twl4030_reg),
2312 .reg_word_size = sizeof(u8),
2313 .reg_cache_default = twl4030_reg,
f7c93f01
PU		 2314
2315 .controls = twl4030_snd_controls,
2316 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2317 .dapm_widgets = twl4030_dapm_widgets,
2318 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2319 .dapm_routes = intercon,
2320 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2321};
2322
05c4c6f7 2323static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2324{
f0fba2ad
LG		 2325 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2326 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2327}
2328
05c4c6f7 2329static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2330{
f0fba2ad 2331 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2332 return 0;
2333}
2334
f0fba2ad 2335MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2336
2337static struct platform_driver twl4030_codec_driver = {
2338 .probe = twl4030_codec_probe,
05c4c6f7 2339 .remove = twl4030_codec_remove,
7a1fecf5 2340 .driver = {
f0fba2ad 2341 .name = "twl4030-codec",
7a1fecf5
PU		 2342 .owner = THIS_MODULE,
2343 },
cc17557e 2344};
cc17557e 2345
5bbcc3c0 2346module_platform_driver(twl4030_codec_driver);
64089b84 2347
cc17557e
SS		 2348MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2349MODULE_AUTHOR("Steve Sakoman");
2350MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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