Commit | Line | Data |
---|---|---|
cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
2d6d649a PU |
29 | #include <linux/of.h> |
30 | #include <linux/of_gpio.h> | |
b07682b6 | 31 | #include <linux/i2c/twl.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
281ecd16 | 33 | #include <linux/gpio.h> |
cc17557e SS |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
cc17557e | 38 | #include <sound/initval.h> |
c10b82cf | 39 | #include <sound/tlv.h> |
cc17557e | 40 | |
f0fba2ad | 41 | /* Register descriptions are here */ |
57fe7251 | 42 | #include <linux/mfd/twl4030-audio.h> |
f0fba2ad | 43 | |
5712ded9 PU |
44 | /* TWL4030 PMBR1 Register */ |
45 | #define TWL4030_PMBR1_REG 0x0D | |
46 | /* TWL4030 PMBR1 Register GPIO6 mux bits */ | |
47 | #define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2) | |
48 | ||
052901f4 | 49 | #define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1) |
cc17557e | 50 | |
7393958f PU |
51 | /* codec private data */ |
52 | struct twl4030_priv { | |
7393958f | 53 | unsigned int codec_powered; |
7b4c734e PU |
54 | |
55 | /* reference counts of AIF/APLL users */ | |
2845fa13 | 56 | unsigned int apll_enabled; |
7220b9f4 PU |
57 | |
58 | struct snd_pcm_substream *master_substream; | |
59 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
60 | |
61 | unsigned int configured; | |
62 | unsigned int rate; | |
63 | unsigned int sample_bits; | |
64 | unsigned int channels; | |
6943c92e PU |
65 | |
66 | unsigned int sysclk; | |
67 | ||
c96907f2 PU |
68 | /* Output (with associated amp) states */ |
69 | u8 hsl_enabled, hsr_enabled; | |
70 | u8 earpiece_enabled; | |
71 | u8 predrivel_enabled, predriver_enabled; | |
72 | u8 carkitl_enabled, carkitr_enabled; | |
8b3bca29 | 73 | u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1]; |
01ea6ba2 | 74 | |
182f73f6 | 75 | struct twl4030_codec_data *pdata; |
7393958f PU |
76 | }; |
77 | ||
8b3bca29 PU |
78 | static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030) |
79 | { | |
80 | int i; | |
81 | u8 byte; | |
82 | ||
83 | for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) { | |
84 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i); | |
85 | twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; | |
86 | } | |
87 | } | |
88 | ||
efc8acff | 89 | static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg) |
cc17557e | 90 | { |
efc8acff PU |
91 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
92 | u8 value = 0; | |
cc17557e SS |
93 | |
94 | if (reg >= TWL4030_CACHEREGNUM) | |
efc8acff PU |
95 | return -EIO; |
96 | ||
97 | switch (reg) { | |
98 | case TWL4030_REG_EAR_CTL: | |
99 | case TWL4030_REG_PREDL_CTL: | |
100 | case TWL4030_REG_PREDR_CTL: | |
101 | case TWL4030_REG_PRECKL_CTL: | |
102 | case TWL4030_REG_PRECKR_CTL: | |
103 | case TWL4030_REG_HS_GAIN_SET: | |
104 | value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; | |
105 | break; | |
106 | default: | |
107 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); | |
108 | break; | |
109 | } | |
110 | ||
111 | return value; | |
cc17557e SS |
112 | } |
113 | ||
b703b504 | 114 | static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030, |
a8fc415c | 115 | unsigned int reg) |
cc17557e | 116 | { |
a8fc415c | 117 | bool write_to_reg = false; |
c96907f2 | 118 | |
052901f4 LPC |
119 | /* Decide if the given register can be written */ |
120 | switch (reg) { | |
121 | case TWL4030_REG_EAR_CTL: | |
122 | if (twl4030->earpiece_enabled) | |
a8fc415c | 123 | write_to_reg = true; |
052901f4 LPC |
124 | break; |
125 | case TWL4030_REG_PREDL_CTL: | |
126 | if (twl4030->predrivel_enabled) | |
a8fc415c | 127 | write_to_reg = true; |
052901f4 LPC |
128 | break; |
129 | case TWL4030_REG_PREDR_CTL: | |
130 | if (twl4030->predriver_enabled) | |
a8fc415c | 131 | write_to_reg = true; |
052901f4 LPC |
132 | break; |
133 | case TWL4030_REG_PRECKL_CTL: | |
134 | if (twl4030->carkitl_enabled) | |
a8fc415c | 135 | write_to_reg = true; |
052901f4 LPC |
136 | break; |
137 | case TWL4030_REG_PRECKR_CTL: | |
138 | if (twl4030->carkitr_enabled) | |
a8fc415c | 139 | write_to_reg = true; |
052901f4 LPC |
140 | break; |
141 | case TWL4030_REG_HS_GAIN_SET: | |
142 | if (twl4030->hsl_enabled || twl4030->hsr_enabled) | |
a8fc415c | 143 | write_to_reg = true; |
052901f4 LPC |
144 | break; |
145 | default: | |
146 | /* All other register can be written */ | |
a8fc415c | 147 | write_to_reg = true; |
052901f4 | 148 | break; |
c96907f2 | 149 | } |
a8fc415c PU |
150 | |
151 | return write_to_reg; | |
152 | } | |
153 | ||
7ded5fe0 PU |
154 | static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg, |
155 | unsigned int value) | |
a8fc415c | 156 | { |
a450aa6f PU |
157 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
158 | ||
159 | /* Update the ctl cache */ | |
160 | switch (reg) { | |
161 | case TWL4030_REG_EAR_CTL: | |
162 | case TWL4030_REG_PREDL_CTL: | |
163 | case TWL4030_REG_PREDR_CTL: | |
164 | case TWL4030_REG_PRECKL_CTL: | |
165 | case TWL4030_REG_PRECKR_CTL: | |
166 | case TWL4030_REG_HS_GAIN_SET: | |
167 | twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value; | |
168 | break; | |
169 | default: | |
170 | break; | |
171 | } | |
172 | ||
b703b504 | 173 | if (twl4030_can_write_to_chip(twl4030, reg)) |
a8fc415c | 174 | return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); |
052901f4 | 175 | |
c96907f2 | 176 | return 0; |
cc17557e SS |
177 | } |
178 | ||
7e6120c5 PU |
179 | static inline void twl4030_wait_ms(int time) |
180 | { | |
181 | if (time < 60) { | |
182 | time *= 1000; | |
183 | usleep_range(time, time + 500); | |
184 | } else { | |
185 | msleep(time); | |
186 | } | |
187 | } | |
188 | ||
db04e2c5 | 189 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 190 | { |
b2c812e2 | 191 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 192 | int mode; |
cc17557e | 193 | |
7393958f PU |
194 | if (enable == twl4030->codec_powered) |
195 | return; | |
196 | ||
db04e2c5 | 197 | if (enable) |
57fe7251 | 198 | mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER); |
db04e2c5 | 199 | else |
57fe7251 | 200 | mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER); |
cc17557e | 201 | |
efc8acff | 202 | if (mode >= 0) |
7a1fecf5 | 203 | twl4030->codec_powered = enable; |
cc17557e SS |
204 | |
205 | /* REVISIT: this delay is present in TI sample drivers */ | |
206 | /* but there seems to be no TRM requirement for it */ | |
207 | udelay(10); | |
208 | } | |
209 | ||
2d6d649a PU |
210 | static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata, |
211 | struct device_node *node) | |
212 | { | |
213 | int value; | |
214 | ||
215 | of_property_read_u32(node, "ti,digimic_delay", | |
216 | &pdata->digimic_delay); | |
217 | of_property_read_u32(node, "ti,ramp_delay_value", | |
218 | &pdata->ramp_delay_value); | |
219 | of_property_read_u32(node, "ti,offset_cncl_path", | |
220 | &pdata->offset_cncl_path); | |
221 | if (!of_property_read_u32(node, "ti,hs_extmute", &value)) | |
222 | pdata->hs_extmute = value; | |
223 | ||
224 | pdata->hs_extmute_gpio = of_get_named_gpio(node, | |
225 | "ti,hs_extmute_gpio", 0); | |
226 | if (gpio_is_valid(pdata->hs_extmute_gpio)) | |
227 | pdata->hs_extmute = 1; | |
228 | } | |
229 | ||
230 | static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec) | |
7393958f | 231 | { |
4ae6df5e | 232 | struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev); |
2d6d649a PU |
233 | struct device_node *twl4030_codec_node = NULL; |
234 | ||
235 | twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node, | |
236 | "codec"); | |
237 | ||
238 | if (!pdata && twl4030_codec_node) { | |
239 | pdata = devm_kzalloc(codec->dev, | |
240 | sizeof(struct twl4030_codec_data), | |
241 | GFP_KERNEL); | |
242 | if (!pdata) { | |
243 | dev_err(codec->dev, "Can not allocate memory\n"); | |
244 | return NULL; | |
245 | } | |
246 | twl4030_setup_pdata_of(pdata, twl4030_codec_node); | |
247 | } | |
248 | ||
249 | return pdata; | |
250 | } | |
251 | ||
252 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
253 | { | |
254 | struct twl4030_codec_data *pdata; | |
b2c812e2 | 255 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
ee4ccac7 PU |
256 | u8 reg, byte; |
257 | int i = 0; | |
7393958f | 258 | |
2d6d649a PU |
259 | pdata = twl4030_get_pdata(codec); |
260 | ||
5712ded9 PU |
261 | if (pdata && pdata->hs_extmute) { |
262 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { | |
263 | int ret; | |
264 | ||
265 | if (!pdata->hs_extmute_gpio) | |
266 | dev_warn(codec->dev, | |
267 | "Extmute GPIO is 0 is this correct?\n"); | |
268 | ||
269 | ret = gpio_request_one(pdata->hs_extmute_gpio, | |
270 | GPIOF_OUT_INIT_LOW, | |
271 | "hs_extmute"); | |
272 | if (ret) { | |
273 | dev_err(codec->dev, | |
274 | "Failed to get hs_extmute GPIO\n"); | |
275 | pdata->hs_extmute_gpio = -1; | |
276 | } | |
277 | } else { | |
278 | u8 pin_mux; | |
279 | ||
280 | /* Set TWL4030 GPIO6 as EXTMUTE signal */ | |
281 | twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux, | |
282 | TWL4030_PMBR1_REG); | |
283 | pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03); | |
284 | pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02); | |
285 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux, | |
286 | TWL4030_PMBR1_REG); | |
281ecd16 PU |
287 | } |
288 | } | |
289 | ||
8b3bca29 PU |
290 | /* Initialize the local ctl register cache */ |
291 | tw4030_init_ctl_cache(twl4030); | |
292 | ||
ee4ccac7 | 293 | /* anti-pop when changing analog gain */ |
efc8acff | 294 | reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1); |
ee4ccac7 | 295 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, |
7ded5fe0 | 296 | reg | TWL4030_SMOOTH_ANAVOL_EN); |
7393958f | 297 | |
ee4ccac7 | 298 | twl4030_write(codec, TWL4030_REG_OPTION, |
7ded5fe0 PU |
299 | TWL4030_ATXL1_EN | TWL4030_ATXR1_EN | |
300 | TWL4030_ARXL2_EN | TWL4030_ARXR2_EN); | |
006f367e | 301 | |
3c36cc68 PU |
302 | /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */ |
303 | twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32); | |
304 | ||
ee4ccac7 | 305 | /* Machine dependent setup */ |
f0fba2ad | 306 | if (!pdata) |
7393958f PU |
307 | return; |
308 | ||
182f73f6 | 309 | twl4030->pdata = pdata; |
ee4ccac7 | 310 | |
efc8acff | 311 | reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET); |
ee4ccac7 | 312 | reg &= ~TWL4030_RAMP_DELAY; |
f0fba2ad | 313 | reg |= (pdata->ramp_delay_value << 2); |
efc8acff | 314 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg); |
006f367e PU |
315 | |
316 | /* initiate offset cancellation */ | |
ee4ccac7 PU |
317 | twl4030_codec_enable(codec, 1); |
318 | ||
efc8acff | 319 | reg = twl4030_read(codec, TWL4030_REG_ANAMICL); |
ee4ccac7 | 320 | reg &= ~TWL4030_OFFSET_CNCL_SEL; |
f0fba2ad | 321 | reg |= pdata->offset_cncl_path; |
006f367e | 322 | twl4030_write(codec, TWL4030_REG_ANAMICL, |
7ded5fe0 | 323 | reg | TWL4030_CNCL_OFFSET_START); |
006f367e | 324 | |
7e6120c5 PU |
325 | /* |
326 | * Wait for offset cancellation to complete. | |
327 | * Since this takes a while, do not slam the i2c. | |
328 | * Start polling the status after ~20ms. | |
329 | */ | |
330 | msleep(20); | |
006f367e | 331 | do { |
7e6120c5 | 332 | usleep_range(1000, 2000); |
efc8acff | 333 | twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true); |
fc7b92fc | 334 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, |
7ded5fe0 | 335 | TWL4030_REG_ANAMICL); |
efc8acff | 336 | twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false); |
006f367e PU |
337 | } while ((i++ < 100) && |
338 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
339 | TWL4030_CNCL_OFFSET_START)); | |
340 | ||
006f367e | 341 | twl4030_codec_enable(codec, 0); |
006f367e PU |
342 | } |
343 | ||
ee4ccac7 | 344 | static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable) |
006f367e | 345 | { |
ee4ccac7 PU |
346 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
347 | int status = -1; | |
348 | ||
349 | if (enable) { | |
350 | twl4030->apll_enabled++; | |
351 | if (twl4030->apll_enabled == 1) | |
57fe7251 PU |
352 | status = twl4030_audio_enable_resource( |
353 | TWL4030_AUDIO_RES_APLL); | |
ee4ccac7 PU |
354 | } else { |
355 | twl4030->apll_enabled--; | |
356 | if (!twl4030->apll_enabled) | |
57fe7251 PU |
357 | status = twl4030_audio_disable_resource( |
358 | TWL4030_AUDIO_RES_APLL); | |
ee4ccac7 | 359 | } |
006f367e PU |
360 | } |
361 | ||
5e98a464 | 362 | /* Earpiece */ |
1a787e7a JS |
363 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
364 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
365 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
366 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
367 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
368 | }; | |
5e98a464 | 369 | |
2a6f5c58 | 370 | /* PreDrive Left */ |
1a787e7a JS |
371 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
372 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
373 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
374 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
375 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
376 | }; | |
2a6f5c58 PU |
377 | |
378 | /* PreDrive Right */ | |
1a787e7a JS |
379 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
380 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
381 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
382 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
383 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
384 | }; | |
2a6f5c58 | 385 | |
dfad21a2 | 386 | /* Headset Left */ |
1a787e7a JS |
387 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
388 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
389 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
390 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
391 | }; | |
dfad21a2 PU |
392 | |
393 | /* Headset Right */ | |
1a787e7a JS |
394 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
395 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
396 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
397 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
398 | }; | |
dfad21a2 | 399 | |
5152d8c2 | 400 | /* Carkit Left */ |
1a787e7a JS |
401 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
402 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
403 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
404 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
405 | }; | |
5152d8c2 PU |
406 | |
407 | /* Carkit Right */ | |
1a787e7a JS |
408 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
409 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
410 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
411 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
412 | }; | |
5152d8c2 | 413 | |
df339804 PU |
414 | /* Handsfree Left */ |
415 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 416 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 PU |
417 | |
418 | static const struct soc_enum twl4030_handsfreel_enum = | |
419 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
420 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
421 | twl4030_handsfreel_texts); | |
422 | ||
423 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
424 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
425 | ||
0f89bdca PU |
426 | /* Handsfree Left virtual mute */ |
427 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
052901f4 | 428 | SOC_DAPM_SINGLE_VIRT("Switch", 1); |
0f89bdca | 429 | |
df339804 PU |
430 | /* Handsfree Right */ |
431 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 432 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 PU |
433 | |
434 | static const struct soc_enum twl4030_handsfreer_enum = | |
435 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
436 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
437 | twl4030_handsfreer_texts); | |
438 | ||
439 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
440 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
441 | ||
0f89bdca PU |
442 | /* Handsfree Right virtual mute */ |
443 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
052901f4 | 444 | SOC_DAPM_SINGLE_VIRT("Switch", 1); |
0f89bdca | 445 | |
376f7839 PU |
446 | /* Vibra */ |
447 | /* Vibra audio path selection */ | |
448 | static const char *twl4030_vibra_texts[] = | |
449 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
450 | ||
451 | static const struct soc_enum twl4030_vibra_enum = | |
452 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, | |
453 | ARRAY_SIZE(twl4030_vibra_texts), | |
454 | twl4030_vibra_texts); | |
455 | ||
456 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
457 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
458 | ||
459 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
460 | static const char *twl4030_vibrapath_texts[] = | |
461 | {"Local vibrator", "Audio"}; | |
462 | ||
463 | static const struct soc_enum twl4030_vibrapath_enum = | |
464 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, | |
465 | ARRAY_SIZE(twl4030_vibrapath_texts), | |
466 | twl4030_vibrapath_texts); | |
467 | ||
468 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
469 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
470 | ||
276c6222 | 471 | /* Left analog microphone selection */ |
97b8096d | 472 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
9028935d PU |
473 | SOC_DAPM_SINGLE("Main Mic Capture Switch", |
474 | TWL4030_REG_ANAMICL, 0, 1, 0), | |
475 | SOC_DAPM_SINGLE("Headset Mic Capture Switch", | |
476 | TWL4030_REG_ANAMICL, 1, 1, 0), | |
477 | SOC_DAPM_SINGLE("AUXL Capture Switch", | |
478 | TWL4030_REG_ANAMICL, 2, 1, 0), | |
479 | SOC_DAPM_SINGLE("Carkit Mic Capture Switch", | |
480 | TWL4030_REG_ANAMICL, 3, 1, 0), | |
97b8096d | 481 | }; |
276c6222 PU |
482 | |
483 | /* Right analog microphone selection */ | |
97b8096d | 484 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
9028935d PU |
485 | SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), |
486 | SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), | |
97b8096d | 487 | }; |
276c6222 PU |
488 | |
489 | /* TX1 L/R Analog/Digital microphone selection */ | |
490 | static const char *twl4030_micpathtx1_texts[] = | |
491 | {"Analog", "Digimic0"}; | |
492 | ||
493 | static const struct soc_enum twl4030_micpathtx1_enum = | |
494 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
495 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
496 | twl4030_micpathtx1_texts); | |
497 | ||
498 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
499 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
500 | ||
501 | /* TX2 L/R Analog/Digital microphone selection */ | |
502 | static const char *twl4030_micpathtx2_texts[] = | |
503 | {"Analog", "Digimic1"}; | |
504 | ||
505 | static const struct soc_enum twl4030_micpathtx2_enum = | |
506 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
507 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
508 | twl4030_micpathtx2_texts); | |
509 | ||
510 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
511 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
512 | ||
7393958f PU |
513 | /* Analog bypass for AudioR1 */ |
514 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
515 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
516 | ||
517 | /* Analog bypass for AudioL1 */ | |
518 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
519 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
520 | ||
521 | /* Analog bypass for AudioR2 */ | |
522 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
523 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
524 | ||
525 | /* Analog bypass for AudioL2 */ | |
526 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
527 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
528 | ||
fcd274a3 LCM |
529 | /* Analog bypass for Voice */ |
530 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
531 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
532 | ||
8b0d3153 | 533 | /* Digital bypass gain, mute instead of -30dB */ |
6bab83fd | 534 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { |
8b0d3153 PU |
535 | TLV_DB_RANGE_HEAD(3), |
536 | 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1), | |
537 | 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0), | |
6bab83fd PU |
538 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), |
539 | }; | |
540 | ||
541 | /* Digital bypass left (TX1L -> RX2L) */ | |
542 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
543 | SOC_DAPM_SINGLE_TLV("Volume", | |
544 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
545 | twl4030_dapm_dbypass_tlv); | |
546 | ||
547 | /* Digital bypass right (TX1R -> RX2R) */ | |
548 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
549 | SOC_DAPM_SINGLE_TLV("Volume", | |
550 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
551 | twl4030_dapm_dbypass_tlv); | |
552 | ||
ee8f6894 LCM |
553 | /* |
554 | * Voice Sidetone GAIN volume control: | |
555 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
556 | */ | |
557 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
558 | ||
559 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
560 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
561 | SOC_DAPM_SINGLE_TLV("Volume", | |
562 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
563 | twl4030_dapm_dbypassv_tlv); | |
564 | ||
9008adf9 PU |
565 | /* |
566 | * Output PGA builder: | |
567 | * Handle the muting and unmuting of the given output (turning off the | |
568 | * amplifier associated with the output pin) | |
c96907f2 PU |
569 | * On mute bypass the reg_cache and write 0 to the register |
570 | * On unmute: restore the register content from the reg_cache | |
9008adf9 PU |
571 | * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R |
572 | */ | |
573 | #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ | |
574 | static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ | |
7ded5fe0 | 575 | struct snd_kcontrol *kcontrol, int event) \ |
9008adf9 | 576 | { \ |
b2c812e2 | 577 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \ |
9008adf9 PU |
578 | \ |
579 | switch (event) { \ | |
580 | case SND_SOC_DAPM_POST_PMU: \ | |
c96907f2 | 581 | twl4030->pin_name##_enabled = 1; \ |
efc8acff | 582 | twl4030_write(w->codec, reg, twl4030_read(w->codec, reg)); \ |
9008adf9 PU |
583 | break; \ |
584 | case SND_SOC_DAPM_POST_PMD: \ | |
c96907f2 | 585 | twl4030->pin_name##_enabled = 0; \ |
7ded5fe0 | 586 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \ |
9008adf9 PU |
587 | break; \ |
588 | } \ | |
589 | return 0; \ | |
590 | } | |
591 | ||
592 | TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); | |
593 | TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); | |
594 | TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); | |
595 | TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); | |
596 | TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); | |
597 | ||
5a2e9a48 | 598 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 599 | { |
49d92c7d SM |
600 | unsigned char hs_ctl; |
601 | ||
efc8acff | 602 | hs_ctl = twl4030_read(codec, reg); |
49d92c7d | 603 | |
5a2e9a48 PU |
604 | if (ramp) { |
605 | /* HF ramp-up */ | |
606 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
607 | twl4030_write(codec, reg, hs_ctl); | |
608 | udelay(10); | |
49d92c7d | 609 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
610 | twl4030_write(codec, reg, hs_ctl); |
611 | udelay(40); | |
49d92c7d | 612 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 613 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 614 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 615 | } else { |
5a2e9a48 PU |
616 | /* HF ramp-down */ |
617 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
618 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
619 | twl4030_write(codec, reg, hs_ctl); | |
620 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
621 | twl4030_write(codec, reg, hs_ctl); | |
622 | udelay(40); | |
623 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
624 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 625 | } |
5a2e9a48 | 626 | } |
49d92c7d | 627 | |
5a2e9a48 | 628 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 629 | struct snd_kcontrol *kcontrol, int event) |
5a2e9a48 PU |
630 | { |
631 | switch (event) { | |
632 | case SND_SOC_DAPM_POST_PMU: | |
633 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); | |
634 | break; | |
635 | case SND_SOC_DAPM_POST_PMD: | |
636 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); | |
637 | break; | |
638 | } | |
639 | return 0; | |
640 | } | |
641 | ||
642 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 643 | struct snd_kcontrol *kcontrol, int event) |
5a2e9a48 PU |
644 | { |
645 | switch (event) { | |
646 | case SND_SOC_DAPM_POST_PMU: | |
647 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); | |
648 | break; | |
649 | case SND_SOC_DAPM_POST_PMD: | |
650 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); | |
651 | break; | |
652 | } | |
49d92c7d SM |
653 | return 0; |
654 | } | |
655 | ||
86139a13 | 656 | static int vibramux_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 657 | struct snd_kcontrol *kcontrol, int event) |
86139a13 JV |
658 | { |
659 | twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff); | |
660 | return 0; | |
661 | } | |
662 | ||
7729cf74 | 663 | static int apll_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 664 | struct snd_kcontrol *kcontrol, int event) |
7729cf74 PU |
665 | { |
666 | switch (event) { | |
667 | case SND_SOC_DAPM_PRE_PMU: | |
668 | twl4030_apll_enable(w->codec, 1); | |
669 | break; | |
670 | case SND_SOC_DAPM_POST_PMD: | |
671 | twl4030_apll_enable(w->codec, 0); | |
672 | break; | |
673 | } | |
674 | return 0; | |
675 | } | |
676 | ||
7b4c734e | 677 | static int aif_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 678 | struct snd_kcontrol *kcontrol, int event) |
7b4c734e PU |
679 | { |
680 | u8 audio_if; | |
681 | ||
efc8acff | 682 | audio_if = twl4030_read(w->codec, TWL4030_REG_AUDIO_IF); |
7b4c734e PU |
683 | switch (event) { |
684 | case SND_SOC_DAPM_PRE_PMU: | |
685 | /* Enable AIF */ | |
686 | /* enable the PLL before we use it to clock the DAI */ | |
687 | twl4030_apll_enable(w->codec, 1); | |
688 | ||
689 | twl4030_write(w->codec, TWL4030_REG_AUDIO_IF, | |
7ded5fe0 | 690 | audio_if | TWL4030_AIF_EN); |
7b4c734e PU |
691 | break; |
692 | case SND_SOC_DAPM_POST_PMD: | |
693 | /* disable the DAI before we stop it's source PLL */ | |
694 | twl4030_write(w->codec, TWL4030_REG_AUDIO_IF, | |
7ded5fe0 | 695 | audio_if & ~TWL4030_AIF_EN); |
7b4c734e PU |
696 | twl4030_apll_enable(w->codec, 0); |
697 | break; | |
698 | } | |
699 | return 0; | |
700 | } | |
701 | ||
6943c92e | 702 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 PU |
703 | { |
704 | unsigned char hs_gain, hs_pop; | |
b2c812e2 | 705 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
182f73f6 | 706 | struct twl4030_codec_data *pdata = twl4030->pdata; |
6943c92e PU |
707 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ |
708 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
709 | 8388608, 16777216, 33554432, 67108864}; | |
7e6120c5 | 710 | unsigned int delay; |
aad749e5 | 711 | |
efc8acff PU |
712 | hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET); |
713 | hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET); | |
7e6120c5 PU |
714 | delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / |
715 | twl4030->sysclk) + 1; | |
aad749e5 | 716 | |
4e49ffd1 CVJ |
717 | /* Enable external mute control, this dramatically reduces |
718 | * the pop-noise */ | |
f0fba2ad | 719 | if (pdata && pdata->hs_extmute) { |
281ecd16 PU |
720 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { |
721 | gpio_set_value(pdata->hs_extmute_gpio, 1); | |
4e49ffd1 CVJ |
722 | } else { |
723 | hs_pop |= TWL4030_EXTMUTE; | |
724 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
725 | } | |
726 | } | |
727 | ||
6943c92e PU |
728 | if (ramp) { |
729 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 730 | hs_pop |= TWL4030_VMID_EN; |
6943c92e | 731 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
c96907f2 | 732 | /* Actually write to the register */ |
7ded5fe0 PU |
733 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain, |
734 | TWL4030_REG_HS_GAIN_SET); | |
aad749e5 | 735 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e | 736 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
4e49ffd1 | 737 | /* Wait ramp delay time + 1, so the VMID can settle */ |
7e6120c5 | 738 | twl4030_wait_ms(delay); |
6943c92e PU |
739 | } else { |
740 | /* Headset ramp-down _not_ according to | |
741 | * the TRM, but in a way that it is working */ | |
aad749e5 | 742 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
743 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
744 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
7e6120c5 | 745 | twl4030_wait_ms(delay); |
aad749e5 | 746 | /* Bypass the reg_cache to mute the headset */ |
7ded5fe0 PU |
747 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f), |
748 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 749 | |
aad749e5 | 750 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
751 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
752 | } | |
4e49ffd1 CVJ |
753 | |
754 | /* Disable external mute */ | |
f0fba2ad | 755 | if (pdata && pdata->hs_extmute) { |
281ecd16 PU |
756 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { |
757 | gpio_set_value(pdata->hs_extmute_gpio, 0); | |
4e49ffd1 CVJ |
758 | } else { |
759 | hs_pop &= ~TWL4030_EXTMUTE; | |
760 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
761 | } | |
762 | } | |
6943c92e PU |
763 | } |
764 | ||
765 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 766 | struct snd_kcontrol *kcontrol, int event) |
6943c92e | 767 | { |
b2c812e2 | 768 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
769 | |
770 | switch (event) { | |
771 | case SND_SOC_DAPM_POST_PMU: | |
772 | /* Do the ramp-up only once */ | |
773 | if (!twl4030->hsr_enabled) | |
774 | headset_ramp(w->codec, 1); | |
775 | ||
776 | twl4030->hsl_enabled = 1; | |
777 | break; | |
778 | case SND_SOC_DAPM_POST_PMD: | |
779 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
780 | if (!twl4030->hsr_enabled) | |
781 | headset_ramp(w->codec, 0); | |
782 | ||
783 | twl4030->hsl_enabled = 0; | |
784 | break; | |
785 | } | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 790 | struct snd_kcontrol *kcontrol, int event) |
6943c92e | 791 | { |
b2c812e2 | 792 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
793 | |
794 | switch (event) { | |
795 | case SND_SOC_DAPM_POST_PMU: | |
796 | /* Do the ramp-up only once */ | |
797 | if (!twl4030->hsl_enabled) | |
798 | headset_ramp(w->codec, 1); | |
799 | ||
800 | twl4030->hsr_enabled = 1; | |
801 | break; | |
802 | case SND_SOC_DAPM_POST_PMD: | |
803 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
804 | if (!twl4030->hsl_enabled) | |
805 | headset_ramp(w->codec, 0); | |
806 | ||
807 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
808 | break; |
809 | } | |
810 | return 0; | |
811 | } | |
812 | ||
01ea6ba2 | 813 | static int digimic_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 814 | struct snd_kcontrol *kcontrol, int event) |
01ea6ba2 PU |
815 | { |
816 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); | |
182f73f6 | 817 | struct twl4030_codec_data *pdata = twl4030->pdata; |
01ea6ba2 | 818 | |
182f73f6 PU |
819 | if (pdata && pdata->digimic_delay) |
820 | twl4030_wait_ms(pdata->digimic_delay); | |
01ea6ba2 PU |
821 | return 0; |
822 | } | |
823 | ||
b0bd53a7 PU |
824 | /* |
825 | * Some of the gain controls in TWL (mostly those which are associated with | |
826 | * the outputs) are implemented in an interesting way: | |
827 | * 0x0 : Power down (mute) | |
828 | * 0x1 : 6dB | |
829 | * 0x2 : 0 dB | |
830 | * 0x3 : -6 dB | |
831 | * Inverting not going to help with these. | |
832 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
833 | */ | |
b0bd53a7 | 834 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, |
7ded5fe0 | 835 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
836 | { |
837 | struct soc_mixer_control *mc = | |
838 | (struct soc_mixer_control *)kcontrol->private_value; | |
839 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
840 | unsigned int reg = mc->reg; | |
841 | unsigned int shift = mc->shift; | |
842 | unsigned int rshift = mc->rshift; | |
843 | int max = mc->max; | |
844 | int mask = (1 << fls(max)) - 1; | |
845 | ||
846 | ucontrol->value.integer.value[0] = | |
847 | (snd_soc_read(codec, reg) >> shift) & mask; | |
848 | if (ucontrol->value.integer.value[0]) | |
849 | ucontrol->value.integer.value[0] = | |
850 | max + 1 - ucontrol->value.integer.value[0]; | |
851 | ||
852 | if (shift != rshift) { | |
853 | ucontrol->value.integer.value[1] = | |
854 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
855 | if (ucontrol->value.integer.value[1]) | |
856 | ucontrol->value.integer.value[1] = | |
857 | max + 1 - ucontrol->value.integer.value[1]; | |
858 | } | |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
863 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 864 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
865 | { |
866 | struct soc_mixer_control *mc = | |
867 | (struct soc_mixer_control *)kcontrol->private_value; | |
868 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
869 | unsigned int reg = mc->reg; | |
870 | unsigned int shift = mc->shift; | |
871 | unsigned int rshift = mc->rshift; | |
872 | int max = mc->max; | |
873 | int mask = (1 << fls(max)) - 1; | |
874 | unsigned short val, val2, val_mask; | |
875 | ||
876 | val = (ucontrol->value.integer.value[0] & mask); | |
877 | ||
878 | val_mask = mask << shift; | |
879 | if (val) | |
880 | val = max + 1 - val; | |
881 | val = val << shift; | |
882 | if (shift != rshift) { | |
883 | val2 = (ucontrol->value.integer.value[1] & mask); | |
884 | val_mask |= mask << rshift; | |
885 | if (val2) | |
886 | val2 = max + 1 - val2; | |
887 | val |= val2 << rshift; | |
888 | } | |
889 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
890 | } | |
891 | ||
892 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 893 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
894 | { |
895 | struct soc_mixer_control *mc = | |
896 | (struct soc_mixer_control *)kcontrol->private_value; | |
897 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
898 | unsigned int reg = mc->reg; | |
899 | unsigned int reg2 = mc->rreg; | |
900 | unsigned int shift = mc->shift; | |
901 | int max = mc->max; | |
902 | int mask = (1<<fls(max))-1; | |
903 | ||
904 | ucontrol->value.integer.value[0] = | |
905 | (snd_soc_read(codec, reg) >> shift) & mask; | |
906 | ucontrol->value.integer.value[1] = | |
907 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
908 | ||
909 | if (ucontrol->value.integer.value[0]) | |
910 | ucontrol->value.integer.value[0] = | |
911 | max + 1 - ucontrol->value.integer.value[0]; | |
912 | if (ucontrol->value.integer.value[1]) | |
913 | ucontrol->value.integer.value[1] = | |
914 | max + 1 - ucontrol->value.integer.value[1]; | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
919 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 920 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
921 | { |
922 | struct soc_mixer_control *mc = | |
923 | (struct soc_mixer_control *)kcontrol->private_value; | |
924 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
925 | unsigned int reg = mc->reg; | |
926 | unsigned int reg2 = mc->rreg; | |
927 | unsigned int shift = mc->shift; | |
928 | int max = mc->max; | |
929 | int mask = (1 << fls(max)) - 1; | |
930 | int err; | |
931 | unsigned short val, val2, val_mask; | |
932 | ||
933 | val_mask = mask << shift; | |
934 | val = (ucontrol->value.integer.value[0] & mask); | |
935 | val2 = (ucontrol->value.integer.value[1] & mask); | |
936 | ||
937 | if (val) | |
938 | val = max + 1 - val; | |
939 | if (val2) | |
940 | val2 = max + 1 - val2; | |
941 | ||
942 | val = val << shift; | |
943 | val2 = val2 << shift; | |
944 | ||
945 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
946 | if (err < 0) | |
947 | return err; | |
948 | ||
949 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
950 | return err; | |
951 | } | |
952 | ||
b74bd40f LCM |
953 | /* Codec operation modes */ |
954 | static const char *twl4030_op_modes_texts[] = { | |
955 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
956 | }; | |
957 | ||
958 | static const struct soc_enum twl4030_op_modes_enum = | |
959 | SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, | |
960 | ARRAY_SIZE(twl4030_op_modes_texts), | |
961 | twl4030_op_modes_texts); | |
962 | ||
423c238d | 963 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
964 | struct snd_ctl_elem_value *ucontrol) |
965 | { | |
966 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 967 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
b74bd40f LCM |
968 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
969 | unsigned short val; | |
86767b7d | 970 | unsigned short mask; |
b74bd40f LCM |
971 | |
972 | if (twl4030->configured) { | |
3b8a0795 PU |
973 | dev_err(codec->dev, |
974 | "operation mode cannot be changed on-the-fly\n"); | |
b74bd40f LCM |
975 | return -EBUSY; |
976 | } | |
977 | ||
9a8d38db | 978 | if (ucontrol->value.enumerated.item[0] >= e->items) |
b74bd40f LCM |
979 | return -EINVAL; |
980 | ||
981 | val = ucontrol->value.enumerated.item[0] << e->shift_l; | |
86767b7d | 982 | mask = e->mask << e->shift_l; |
b74bd40f | 983 | if (e->shift_l != e->shift_r) { |
9a8d38db | 984 | if (ucontrol->value.enumerated.item[1] >= e->items) |
b74bd40f LCM |
985 | return -EINVAL; |
986 | val |= ucontrol->value.enumerated.item[1] << e->shift_r; | |
86767b7d | 987 | mask |= e->mask << e->shift_r; |
b74bd40f LCM |
988 | } |
989 | ||
990 | return snd_soc_update_bits(codec, e->reg, mask, val); | |
991 | } | |
992 | ||
c10b82cf PU |
993 | /* |
994 | * FGAIN volume control: | |
995 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
996 | */ | |
d889a72c | 997 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 998 | |
0d33ea0b PU |
999 | /* |
1000 | * CGAIN volume control: | |
1001 | * 0 dB to 12 dB in 6 dB steps | |
1002 | * value 2 and 3 means 12 dB | |
1003 | */ | |
d889a72c PU |
1004 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
1005 | ||
1a787e7a JS |
1006 | /* |
1007 | * Voice Downlink GAIN volume control: | |
1008 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
1009 | */ | |
1010 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
1011 | ||
d889a72c PU |
1012 | /* |
1013 | * Analog playback gain | |
1014 | * -24 dB to 12 dB in 2 dB steps | |
1015 | */ | |
1016 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 1017 | |
4290239c PU |
1018 | /* |
1019 | * Gain controls tied to outputs | |
1020 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
1021 | */ | |
1022 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
1023 | ||
18cc8d8d JS |
1024 | /* |
1025 | * Gain control for earpiece amplifier | |
1026 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
1027 | */ | |
1028 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
1029 | ||
381a22b5 PU |
1030 | /* |
1031 | * Capture gain after the ADCs | |
1032 | * from 0 dB to 31 dB in 1 dB steps | |
1033 | */ | |
1034 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
1035 | ||
5920b453 GI |
1036 | /* |
1037 | * Gain control for input amplifiers | |
1038 | * 0 dB to 30 dB in 6 dB steps | |
1039 | */ | |
1040 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
1041 | ||
328d0a13 LCM |
1042 | /* AVADC clock priority */ |
1043 | static const char *twl4030_avadc_clk_priority_texts[] = { | |
1044 | "Voice high priority", "HiFi high priority" | |
1045 | }; | |
1046 | ||
1047 | static const struct soc_enum twl4030_avadc_clk_priority_enum = | |
1048 | SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2, | |
1049 | ARRAY_SIZE(twl4030_avadc_clk_priority_texts), | |
1050 | twl4030_avadc_clk_priority_texts); | |
1051 | ||
89492be8 PU |
1052 | static const char *twl4030_rampdelay_texts[] = { |
1053 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1054 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1055 | "3495/2581/1748 ms" | |
1056 | }; | |
1057 | ||
1058 | static const struct soc_enum twl4030_rampdelay_enum = | |
1059 | SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, | |
1060 | ARRAY_SIZE(twl4030_rampdelay_texts), | |
1061 | twl4030_rampdelay_texts); | |
1062 | ||
376f7839 PU |
1063 | /* Vibra H-bridge direction mode */ |
1064 | static const char *twl4030_vibradirmode_texts[] = { | |
1065 | "Vibra H-bridge direction", "Audio data MSB", | |
1066 | }; | |
1067 | ||
1068 | static const struct soc_enum twl4030_vibradirmode_enum = | |
1069 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, | |
1070 | ARRAY_SIZE(twl4030_vibradirmode_texts), | |
1071 | twl4030_vibradirmode_texts); | |
1072 | ||
1073 | /* Vibra H-bridge direction */ | |
1074 | static const char *twl4030_vibradir_texts[] = { | |
1075 | "Positive polarity", "Negative polarity", | |
1076 | }; | |
1077 | ||
1078 | static const struct soc_enum twl4030_vibradir_enum = | |
1079 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, | |
1080 | ARRAY_SIZE(twl4030_vibradir_texts), | |
1081 | twl4030_vibradir_texts); | |
1082 | ||
36aeff61 PU |
1083 | /* Digimic Left and right swapping */ |
1084 | static const char *twl4030_digimicswap_texts[] = { | |
1085 | "Not swapped", "Swapped", | |
1086 | }; | |
1087 | ||
1088 | static const struct soc_enum twl4030_digimicswap_enum = | |
1089 | SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0, | |
1090 | ARRAY_SIZE(twl4030_digimicswap_texts), | |
1091 | twl4030_digimicswap_texts); | |
1092 | ||
cc17557e | 1093 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1094 | /* Codec operation mode control */ |
1095 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1096 | snd_soc_get_enum_double, | |
1097 | snd_soc_put_twl4030_opmode_enum_double), | |
1098 | ||
d889a72c PU |
1099 | /* Common playback gain controls */ |
1100 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1101 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1102 | 0, 0x3f, 0, digital_fine_tlv), | |
1103 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1104 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1105 | 0, 0x3f, 0, digital_fine_tlv), | |
1106 | ||
1107 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1108 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1109 | 6, 0x2, 0, digital_coarse_tlv), | |
1110 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1111 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1112 | 6, 0x2, 0, digital_coarse_tlv), | |
1113 | ||
1114 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1115 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1116 | 3, 0x12, 1, analog_tlv), | |
1117 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1118 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1119 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1120 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1121 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1122 | 1, 1, 0), | |
1123 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1124 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1125 | 1, 1, 0), | |
381a22b5 | 1126 | |
1a787e7a JS |
1127 | /* Common voice downlink gain controls */ |
1128 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1129 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1130 | ||
1131 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1132 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1133 | ||
1134 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1135 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1136 | ||
4290239c | 1137 | /* Separate output gain controls */ |
0f9887d1 | 1138 | SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume", |
4290239c | 1139 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, |
0f9887d1 PU |
1140 | 4, 3, 0, snd_soc_get_volsw_r2_twl4030, |
1141 | snd_soc_put_volsw_r2_twl4030, output_tvl), | |
4290239c | 1142 | |
0f9887d1 PU |
1143 | SOC_DOUBLE_EXT_TLV("Headset Playback Volume", |
1144 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030, | |
1145 | snd_soc_put_volsw_twl4030, output_tvl), | |
4290239c | 1146 | |
0f9887d1 | 1147 | SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume", |
4290239c | 1148 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, |
0f9887d1 PU |
1149 | 4, 3, 0, snd_soc_get_volsw_r2_twl4030, |
1150 | snd_soc_put_volsw_r2_twl4030, output_tvl), | |
4290239c | 1151 | |
0f9887d1 PU |
1152 | SOC_SINGLE_EXT_TLV("Earpiece Playback Volume", |
1153 | TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030, | |
1154 | snd_soc_put_volsw_twl4030, output_ear_tvl), | |
4290239c | 1155 | |
381a22b5 | 1156 | /* Common capture gain controls */ |
276c6222 | 1157 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1158 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1159 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1160 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1161 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1162 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1163 | |
276c6222 | 1164 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1165 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 | 1166 | |
328d0a13 LCM |
1167 | SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), |
1168 | ||
89492be8 | 1169 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), |
376f7839 PU |
1170 | |
1171 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1172 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
36aeff61 PU |
1173 | |
1174 | SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum), | |
cc17557e SS |
1175 | }; |
1176 | ||
cc17557e | 1177 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1178 | /* Left channel inputs */ |
1179 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1180 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1181 | SND_SOC_DAPM_INPUT("AUXL"), | |
1182 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1183 | /* Right channel inputs */ | |
1184 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1185 | SND_SOC_DAPM_INPUT("AUXR"), | |
1186 | /* Digital microphones (Stereo) */ | |
1187 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1188 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1189 | ||
1190 | /* Outputs */ | |
5e98a464 | 1191 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1192 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1193 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1194 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1195 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1196 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1197 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1198 | SND_SOC_DAPM_OUTPUT("HFL"), |
1199 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1200 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1201 | |
7b4c734e PU |
1202 | /* AIF and APLL clocks for running DAIs (including loopback) */ |
1203 | SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"), | |
1204 | SND_SOC_DAPM_INPUT("Virtual HiFi IN"), | |
1205 | SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"), | |
1206 | ||
53b5047d | 1207 | /* DACs */ |
7f51e7d3 PU |
1208 | SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0), |
1209 | SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0), | |
1210 | SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0), | |
1211 | SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0), | |
1212 | SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0), | |
cc17557e | 1213 | |
927a7747 PU |
1214 | SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0, |
1215 | TWL4030_REG_VOICE_IF, 6, 0), | |
1216 | ||
7393958f | 1217 | /* Analog bypasses */ |
78e08e2f PU |
1218 | SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, |
1219 | &twl4030_dapm_abypassr1_control), | |
1220 | SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1221 | &twl4030_dapm_abypassl1_control), | |
1222 | SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1223 | &twl4030_dapm_abypassr2_control), | |
1224 | SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1225 | &twl4030_dapm_abypassl2_control), | |
1226 | SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1227 | &twl4030_dapm_abypassv_control), | |
1228 | ||
1229 | /* Master analog loopback switch */ | |
1230 | SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0, | |
1231 | NULL, 0), | |
7393958f | 1232 | |
6bab83fd | 1233 | /* Digital bypasses */ |
78e08e2f PU |
1234 | SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0, |
1235 | &twl4030_dapm_dbypassl_control), | |
1236 | SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1237 | &twl4030_dapm_dbypassr_control), | |
1238 | SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1239 | &twl4030_dapm_dbypassv_control), | |
6bab83fd | 1240 | |
4005d39a PU |
1241 | /* Digital mixers, power control for the physical DACs */ |
1242 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1243 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1244 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1245 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1246 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1247 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1248 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1249 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1250 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1251 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1252 | ||
1253 | /* Analog mixers, power control for the physical PGAs */ | |
1254 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1255 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1256 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1257 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1258 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1259 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1260 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1261 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1262 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1263 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1264 | |
7729cf74 PU |
1265 | SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event, |
1266 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
1267 | ||
7b4c734e PU |
1268 | SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event, |
1269 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
c42a59ea | 1270 | |
1a787e7a | 1271 | /* Output MIXER controls */ |
5e98a464 | 1272 | /* Earpiece */ |
1a787e7a JS |
1273 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1274 | &twl4030_dapm_earpiece_controls[0], | |
1275 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
9008adf9 PU |
1276 | SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, |
1277 | 0, 0, NULL, 0, earpiecepga_event, | |
1278 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
2a6f5c58 | 1279 | /* PreDrivL/R */ |
1a787e7a JS |
1280 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1281 | &twl4030_dapm_predrivel_controls[0], | |
1282 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
9008adf9 PU |
1283 | SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, |
1284 | 0, 0, NULL, 0, predrivelpga_event, | |
1285 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1286 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, |
1287 | &twl4030_dapm_predriver_controls[0], | |
1288 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
9008adf9 PU |
1289 | SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, |
1290 | 0, 0, NULL, 0, predriverpga_event, | |
1291 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 | 1292 | /* HeadsetL/R */ |
6943c92e | 1293 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1294 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1295 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1296 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1297 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1298 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1299 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1300 | &twl4030_dapm_hsor_controls[0], | |
1301 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1302 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1303 | 0, 0, NULL, 0, headsetrpga_event, | |
1304 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1305 | /* CarkitL/R */ |
1a787e7a JS |
1306 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1307 | &twl4030_dapm_carkitl_controls[0], | |
1308 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
9008adf9 PU |
1309 | SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, |
1310 | 0, 0, NULL, 0, carkitlpga_event, | |
1311 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1312 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, |
1313 | &twl4030_dapm_carkitr_controls[0], | |
1314 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
9008adf9 PU |
1315 | SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, |
1316 | 0, 0, NULL, 0, carkitrpga_event, | |
1317 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1318 | |
1319 | /* Output MUX controls */ | |
df339804 | 1320 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1321 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1322 | &twl4030_dapm_handsfreel_control), | |
e3c7dbb0 | 1323 | SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1324 | &twl4030_dapm_handsfreelmute_control), |
5a2e9a48 PU |
1325 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1326 | 0, 0, NULL, 0, handsfreelpga_event, | |
1327 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1328 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1329 | &twl4030_dapm_handsfreer_control), | |
e3c7dbb0 | 1330 | SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1331 | &twl4030_dapm_handsfreermute_control), |
5a2e9a48 PU |
1332 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1333 | 0, 0, NULL, 0, handsfreerpga_event, | |
1334 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 | 1335 | /* Vibra */ |
86139a13 JV |
1336 | SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, |
1337 | &twl4030_dapm_vibra_control, vibramux_event, | |
1338 | SND_SOC_DAPM_PRE_PMU), | |
376f7839 PU |
1339 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, |
1340 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1341 | |
276c6222 PU |
1342 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1343 | capture */ | |
7f51e7d3 PU |
1344 | SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0), |
1345 | SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0), | |
1346 | SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0), | |
1347 | SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0), | |
276c6222 | 1348 | |
927a7747 PU |
1349 | SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0, |
1350 | TWL4030_REG_VOICE_IF, 5, 0), | |
1351 | ||
276c6222 PU |
1352 | /* Analog/Digital mic path selection. |
1353 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1354 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
bda7d2a8 PU |
1355 | SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0, |
1356 | &twl4030_dapm_micpathtx1_control), | |
1357 | SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1358 | &twl4030_dapm_micpathtx2_control), | |
276c6222 | 1359 | |
97b8096d | 1360 | /* Analog input mixers for the capture amplifiers */ |
9028935d | 1361 | SND_SOC_DAPM_MIXER("Analog Left", |
97b8096d JS |
1362 | TWL4030_REG_ANAMICL, 4, 0, |
1363 | &twl4030_dapm_analoglmic_controls[0], | |
1364 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
9028935d | 1365 | SND_SOC_DAPM_MIXER("Analog Right", |
97b8096d JS |
1366 | TWL4030_REG_ANAMICR, 4, 0, |
1367 | &twl4030_dapm_analogrmic_controls[0], | |
1368 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1369 | |
fb2a2f84 PU |
1370 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1371 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1372 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1373 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 | 1374 | |
01ea6ba2 PU |
1375 | SND_SOC_DAPM_PGA_E("Digimic0 Enable", |
1376 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0, | |
1377 | digimic_event, SND_SOC_DAPM_POST_PMU), | |
1378 | SND_SOC_DAPM_PGA_E("Digimic1 Enable", | |
1379 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0, | |
1380 | digimic_event, SND_SOC_DAPM_POST_PMU), | |
276c6222 | 1381 | |
bda7d2a8 PU |
1382 | SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0, |
1383 | NULL, 0), | |
1384 | SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0, | |
1385 | NULL, 0), | |
1386 | ||
e04d6e55 PU |
1387 | /* Microphone bias */ |
1388 | SND_SOC_DAPM_SUPPLY("Mic Bias 1", | |
1389 | TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0), | |
1390 | SND_SOC_DAPM_SUPPLY("Mic Bias 2", | |
1391 | TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0), | |
1392 | SND_SOC_DAPM_SUPPLY("Headset Mic Bias", | |
1393 | TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0), | |
7393958f | 1394 | |
927a7747 | 1395 | SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0), |
cc17557e SS |
1396 | }; |
1397 | ||
1398 | static const struct snd_soc_dapm_route intercon[] = { | |
7f51e7d3 PU |
1399 | /* Stream -> DAC mapping */ |
1400 | {"DAC Right1", NULL, "HiFi Playback"}, | |
1401 | {"DAC Left1", NULL, "HiFi Playback"}, | |
1402 | {"DAC Right2", NULL, "HiFi Playback"}, | |
1403 | {"DAC Left2", NULL, "HiFi Playback"}, | |
927a7747 | 1404 | {"DAC Voice", NULL, "VAIFIN"}, |
7f51e7d3 PU |
1405 | |
1406 | /* ADC -> Stream mapping */ | |
1407 | {"HiFi Capture", NULL, "ADC Virtual Left1"}, | |
1408 | {"HiFi Capture", NULL, "ADC Virtual Right1"}, | |
1409 | {"HiFi Capture", NULL, "ADC Virtual Left2"}, | |
1410 | {"HiFi Capture", NULL, "ADC Virtual Right2"}, | |
927a7747 PU |
1411 | {"VAIFOUT", NULL, "ADC Virtual Left2"}, |
1412 | {"VAIFOUT", NULL, "ADC Virtual Right2"}, | |
1413 | {"VAIFOUT", NULL, "VIF Enable"}, | |
7f51e7d3 | 1414 | |
4005d39a PU |
1415 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1416 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1417 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1418 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1419 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1420 | ||
7729cf74 | 1421 | /* Supply for the digital part (APLL) */ |
7729cf74 PU |
1422 | {"Digital Voice Playback Mixer", NULL, "APLL Enable"}, |
1423 | ||
27eeb1fe PU |
1424 | {"DAC Left1", NULL, "AIF Enable"}, |
1425 | {"DAC Right1", NULL, "AIF Enable"}, | |
1426 | {"DAC Left2", NULL, "AIF Enable"}, | |
1427 | {"DAC Right1", NULL, "AIF Enable"}, | |
927a7747 | 1428 | {"DAC Voice", NULL, "VIF Enable"}, |
27eeb1fe | 1429 | |
c42a59ea PU |
1430 | {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, |
1431 | {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, | |
1432 | ||
4005d39a PU |
1433 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, |
1434 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1435 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1436 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1437 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1438 | |
5e98a464 PU |
1439 | /* Internal playback routings */ |
1440 | /* Earpiece */ | |
4005d39a PU |
1441 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1442 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1443 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1444 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
9008adf9 | 1445 | {"Earpiece PGA", NULL, "Earpiece Mixer"}, |
2a6f5c58 | 1446 | /* PreDrivL */ |
4005d39a PU |
1447 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1448 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1449 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1450 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1451 | {"PredriveL PGA", NULL, "PredriveL Mixer"}, |
2a6f5c58 | 1452 | /* PreDrivR */ |
4005d39a PU |
1453 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1454 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1455 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1456 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1457 | {"PredriveR PGA", NULL, "PredriveR Mixer"}, |
dfad21a2 | 1458 | /* HeadsetL */ |
4005d39a PU |
1459 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1460 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1461 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1462 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1463 | /* HeadsetR */ |
4005d39a PU |
1464 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1465 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1466 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1467 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1468 | /* CarkitL */ |
4005d39a PU |
1469 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1470 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1471 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1472 | {"CarkitL PGA", NULL, "CarkitL Mixer"}, |
5152d8c2 | 1473 | /* CarkitR */ |
4005d39a PU |
1474 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1475 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1476 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1477 | {"CarkitR PGA", NULL, "CarkitR Mixer"}, |
df339804 | 1478 | /* HandsfreeL */ |
4005d39a PU |
1479 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1480 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1481 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1482 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1483 | {"HandsfreeL", "Switch", "HandsfreeL Mux"}, |
1484 | {"HandsfreeL PGA", NULL, "HandsfreeL"}, | |
df339804 | 1485 | /* HandsfreeR */ |
4005d39a PU |
1486 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1487 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1488 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1489 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1490 | {"HandsfreeR", "Switch", "HandsfreeR Mux"}, |
1491 | {"HandsfreeR PGA", NULL, "HandsfreeR"}, | |
376f7839 PU |
1492 | /* Vibra */ |
1493 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1494 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1495 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1496 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1497 | |
cc17557e | 1498 | /* outputs */ |
7b4c734e | 1499 | /* Must be always connected (for AIF and APLL) */ |
27eeb1fe PU |
1500 | {"Virtual HiFi OUT", NULL, "DAC Left1"}, |
1501 | {"Virtual HiFi OUT", NULL, "DAC Right1"}, | |
1502 | {"Virtual HiFi OUT", NULL, "DAC Left2"}, | |
1503 | {"Virtual HiFi OUT", NULL, "DAC Right2"}, | |
7b4c734e PU |
1504 | /* Must be always connected (for APLL) */ |
1505 | {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"}, | |
1506 | /* Physical outputs */ | |
9008adf9 PU |
1507 | {"EARPIECE", NULL, "Earpiece PGA"}, |
1508 | {"PREDRIVEL", NULL, "PredriveL PGA"}, | |
1509 | {"PREDRIVER", NULL, "PredriveR PGA"}, | |
6943c92e PU |
1510 | {"HSOL", NULL, "HeadsetL PGA"}, |
1511 | {"HSOR", NULL, "HeadsetR PGA"}, | |
9008adf9 PU |
1512 | {"CARKITL", NULL, "CarkitL PGA"}, |
1513 | {"CARKITR", NULL, "CarkitR PGA"}, | |
5a2e9a48 PU |
1514 | {"HFL", NULL, "HandsfreeL PGA"}, |
1515 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1516 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1517 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1518 | |
276c6222 | 1519 | /* Capture path */ |
7b4c734e PU |
1520 | /* Must be always connected (for AIF and APLL) */ |
1521 | {"ADC Virtual Left1", NULL, "Virtual HiFi IN"}, | |
1522 | {"ADC Virtual Right1", NULL, "Virtual HiFi IN"}, | |
1523 | {"ADC Virtual Left2", NULL, "Virtual HiFi IN"}, | |
1524 | {"ADC Virtual Right2", NULL, "Virtual HiFi IN"}, | |
1525 | /* Physical inputs */ | |
9028935d PU |
1526 | {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, |
1527 | {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, | |
1528 | {"Analog Left", "AUXL Capture Switch", "AUXL"}, | |
1529 | {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, | |
276c6222 | 1530 | |
9028935d PU |
1531 | {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, |
1532 | {"Analog Right", "AUXR Capture Switch", "AUXR"}, | |
276c6222 | 1533 | |
9028935d PU |
1534 | {"ADC Physical Left", NULL, "Analog Left"}, |
1535 | {"ADC Physical Right", NULL, "Analog Right"}, | |
276c6222 PU |
1536 | |
1537 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1538 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1539 | ||
bda7d2a8 PU |
1540 | {"DIGIMIC0", NULL, "micbias1 select"}, |
1541 | {"DIGIMIC1", NULL, "micbias2 select"}, | |
1542 | ||
276c6222 | 1543 | /* TX1 Left capture path */ |
fb2a2f84 | 1544 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1545 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1546 | /* TX1 Right capture path */ | |
fb2a2f84 | 1547 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1548 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1549 | /* TX2 Left capture path */ | |
fb2a2f84 | 1550 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1551 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1552 | /* TX2 Right capture path */ | |
fb2a2f84 | 1553 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1554 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1555 | ||
1556 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1557 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1558 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1559 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1560 | ||
c42a59ea PU |
1561 | {"ADC Virtual Left1", NULL, "AIF Enable"}, |
1562 | {"ADC Virtual Right1", NULL, "AIF Enable"}, | |
1563 | {"ADC Virtual Left2", NULL, "AIF Enable"}, | |
1564 | {"ADC Virtual Right2", NULL, "AIF Enable"}, | |
1565 | ||
7393958f | 1566 | /* Analog bypass routes */ |
9028935d PU |
1567 | {"Right1 Analog Loopback", "Switch", "Analog Right"}, |
1568 | {"Left1 Analog Loopback", "Switch", "Analog Left"}, | |
1569 | {"Right2 Analog Loopback", "Switch", "Analog Right"}, | |
1570 | {"Left2 Analog Loopback", "Switch", "Analog Left"}, | |
1571 | {"Voice Analog Loopback", "Switch", "Analog Left"}, | |
7393958f | 1572 | |
78e08e2f PU |
1573 | /* Supply for the Analog loopbacks */ |
1574 | {"Right1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1575 | {"Left1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1576 | {"Right2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1577 | {"Left2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1578 | {"Voice Analog Loopback", NULL, "FM Loop Enable"}, | |
1579 | ||
7393958f PU |
1580 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, |
1581 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1582 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1583 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1584 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1585 | |
6bab83fd PU |
1586 | /* Digital bypass routes */ |
1587 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1588 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1589 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1590 | |
4005d39a PU |
1591 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1592 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1593 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1594 | |
cc17557e SS |
1595 | }; |
1596 | ||
cc17557e SS |
1597 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1598 | enum snd_soc_bias_level level) | |
1599 | { | |
1600 | switch (level) { | |
1601 | case SND_SOC_BIAS_ON: | |
cc17557e SS |
1602 | break; |
1603 | case SND_SOC_BIAS_PREPARE: | |
cc17557e SS |
1604 | break; |
1605 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1606 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
ee4ccac7 | 1607 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1608 | break; |
1609 | case SND_SOC_BIAS_OFF: | |
cbd2db12 | 1610 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1611 | break; |
1612 | } | |
ce6120cc | 1613 | codec->dapm.bias_level = level; |
cc17557e SS |
1614 | |
1615 | return 0; | |
1616 | } | |
1617 | ||
6b87a91f PU |
1618 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1619 | struct snd_pcm_substream *mst_substream) | |
1620 | { | |
1621 | struct snd_pcm_substream *slv_substream; | |
1622 | ||
1623 | /* Pick the stream, which need to be constrained */ | |
1624 | if (mst_substream == twl4030->master_substream) | |
1625 | slv_substream = twl4030->slave_substream; | |
1626 | else if (mst_substream == twl4030->slave_substream) | |
1627 | slv_substream = twl4030->master_substream; | |
1628 | else /* This should not happen.. */ | |
1629 | return; | |
1630 | ||
1631 | /* Set the constraints according to the already configured stream */ | |
1632 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1633 | SNDRV_PCM_HW_PARAM_RATE, | |
1634 | twl4030->rate, | |
1635 | twl4030->rate); | |
1636 | ||
1637 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1638 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1639 | twl4030->sample_bits, | |
1640 | twl4030->sample_bits); | |
1641 | ||
1642 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1643 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1644 | twl4030->channels, | |
1645 | twl4030->channels); | |
1646 | } | |
1647 | ||
8a1f936a PU |
1648 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1649 | * capture has to be enabled/disabled. */ | |
1650 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
7ded5fe0 | 1651 | int enable) |
8a1f936a PU |
1652 | { |
1653 | u8 reg, mask; | |
1654 | ||
efc8acff | 1655 | reg = twl4030_read(codec, TWL4030_REG_OPTION); |
8a1f936a PU |
1656 | |
1657 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1658 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1659 | else | |
1660 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1661 | ||
1662 | if (enable) | |
1663 | reg |= mask; | |
1664 | else | |
1665 | reg &= ~mask; | |
1666 | ||
1667 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1668 | } | |
1669 | ||
d6648da1 PU |
1670 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1671 | struct snd_soc_dai *dai) | |
7220b9f4 | 1672 | { |
e6968a17 | 1673 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1674 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 | 1675 | |
7220b9f4 | 1676 | if (twl4030->master_substream) { |
7220b9f4 | 1677 | twl4030->slave_substream = substream; |
6b87a91f PU |
1678 | /* The DAI has one configuration for playback and capture, so |
1679 | * if the DAI has been already configured then constrain this | |
1680 | * substream to match it. */ | |
1681 | if (twl4030->configured) | |
1682 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1683 | } else { | |
efc8acff | 1684 | if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) & |
8a1f936a PU |
1685 | TWL4030_OPTION_1)) { |
1686 | /* In option2 4 channel is not supported, set the | |
1687 | * constraint for the first stream for channels, the | |
1688 | * second stream will 'inherit' this cosntraint */ | |
1689 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
7ded5fe0 PU |
1690 | SNDRV_PCM_HW_PARAM_CHANNELS, |
1691 | 2, 2); | |
8a1f936a | 1692 | } |
7220b9f4 | 1693 | twl4030->master_substream = substream; |
6b87a91f | 1694 | } |
7220b9f4 PU |
1695 | |
1696 | return 0; | |
1697 | } | |
1698 | ||
d6648da1 PU |
1699 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1700 | struct snd_soc_dai *dai) | |
7220b9f4 | 1701 | { |
e6968a17 | 1702 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1703 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 PU |
1704 | |
1705 | if (twl4030->master_substream == substream) | |
1706 | twl4030->master_substream = twl4030->slave_substream; | |
1707 | ||
1708 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1709 | |
1710 | /* If all streams are closed, or the remaining stream has not yet | |
1711 | * been configured than set the DAI as not configured. */ | |
1712 | if (!twl4030->master_substream) | |
1713 | twl4030->configured = 0; | |
1714 | else if (!twl4030->master_substream->runtime->channels) | |
1715 | twl4030->configured = 0; | |
8a1f936a PU |
1716 | |
1717 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1718 | if (substream->runtime->channels == 4) | |
1719 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1720 | } |
1721 | ||
cc17557e | 1722 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
7ded5fe0 PU |
1723 | struct snd_pcm_hw_params *params, |
1724 | struct snd_soc_dai *dai) | |
cc17557e | 1725 | { |
e6968a17 | 1726 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1727 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1728 | u8 mode, old_mode, format, old_format; |
1729 | ||
8a1f936a PU |
1730 | /* If the substream has 4 channel, do the necessary setup */ |
1731 | if (params_channels(params) == 4) { | |
efc8acff PU |
1732 | format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
1733 | mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE); | |
eaf1ac8b PU |
1734 | |
1735 | /* Safety check: are we in the correct operating mode and | |
1736 | * the interface is in TDM mode? */ | |
1737 | if ((mode & TWL4030_OPTION_1) && | |
1738 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1739 | twl4030_tdm_enable(codec, substream->stream, 1); |
1740 | else | |
1741 | return -EINVAL; | |
1742 | } | |
1743 | ||
6b87a91f PU |
1744 | if (twl4030->configured) |
1745 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1746 | return 0; |
1747 | ||
cc17557e | 1748 | /* bit rate */ |
efc8acff PU |
1749 | old_mode = twl4030_read(codec, |
1750 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
cc17557e SS |
1751 | mode = old_mode & ~TWL4030_APLL_RATE; |
1752 | ||
1753 | switch (params_rate(params)) { | |
1754 | case 8000: | |
1755 | mode |= TWL4030_APLL_RATE_8000; | |
1756 | break; | |
1757 | case 11025: | |
1758 | mode |= TWL4030_APLL_RATE_11025; | |
1759 | break; | |
1760 | case 12000: | |
1761 | mode |= TWL4030_APLL_RATE_12000; | |
1762 | break; | |
1763 | case 16000: | |
1764 | mode |= TWL4030_APLL_RATE_16000; | |
1765 | break; | |
1766 | case 22050: | |
1767 | mode |= TWL4030_APLL_RATE_22050; | |
1768 | break; | |
1769 | case 24000: | |
1770 | mode |= TWL4030_APLL_RATE_24000; | |
1771 | break; | |
1772 | case 32000: | |
1773 | mode |= TWL4030_APLL_RATE_32000; | |
1774 | break; | |
1775 | case 44100: | |
1776 | mode |= TWL4030_APLL_RATE_44100; | |
1777 | break; | |
1778 | case 48000: | |
1779 | mode |= TWL4030_APLL_RATE_48000; | |
1780 | break; | |
103f211d PU |
1781 | case 96000: |
1782 | mode |= TWL4030_APLL_RATE_96000; | |
1783 | break; | |
cc17557e | 1784 | default: |
3b8a0795 | 1785 | dev_err(codec->dev, "%s: unknown rate %d\n", __func__, |
cc17557e SS |
1786 | params_rate(params)); |
1787 | return -EINVAL; | |
1788 | } | |
1789 | ||
cc17557e | 1790 | /* sample size */ |
efc8acff | 1791 | old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
cc17557e SS |
1792 | format = old_format; |
1793 | format &= ~TWL4030_DATA_WIDTH; | |
1794 | switch (params_format(params)) { | |
1795 | case SNDRV_PCM_FORMAT_S16_LE: | |
1796 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1797 | break; | |
dcdeda4a | 1798 | case SNDRV_PCM_FORMAT_S32_LE: |
cc17557e SS |
1799 | format |= TWL4030_DATA_WIDTH_32S_24W; |
1800 | break; | |
1801 | default: | |
3b8a0795 | 1802 | dev_err(codec->dev, "%s: unknown format %d\n", __func__, |
cc17557e SS |
1803 | params_format(params)); |
1804 | return -EINVAL; | |
1805 | } | |
1806 | ||
2046f175 PU |
1807 | if (format != old_format || mode != old_mode) { |
1808 | if (twl4030->codec_powered) { | |
1809 | /* | |
1810 | * If the codec is powered, than we need to toggle the | |
1811 | * codec power. | |
1812 | */ | |
1813 | twl4030_codec_enable(codec, 0); | |
1814 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1815 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1816 | twl4030_codec_enable(codec, 1); | |
1817 | } else { | |
1818 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1819 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1820 | } | |
cc17557e | 1821 | } |
6b87a91f PU |
1822 | |
1823 | /* Store the important parameters for the DAI configuration and set | |
1824 | * the DAI as configured */ | |
1825 | twl4030->configured = 1; | |
1826 | twl4030->rate = params_rate(params); | |
1827 | twl4030->sample_bits = hw_param_interval(params, | |
1828 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1829 | twl4030->channels = params_channels(params); | |
1830 | ||
1831 | /* If both playback and capture streams are open, and one of them | |
1832 | * is setting the hw parameters right now (since we are here), set | |
1833 | * constraints to the other stream to match the current one. */ | |
1834 | if (twl4030->slave_substream) | |
1835 | twl4030_constraints(twl4030, substream); | |
1836 | ||
cc17557e SS |
1837 | return 0; |
1838 | } | |
1839 | ||
7ded5fe0 PU |
1840 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, |
1841 | unsigned int freq, int dir) | |
cc17557e SS |
1842 | { |
1843 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1844 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1845 | |
1846 | switch (freq) { | |
1847 | case 19200000: | |
cc17557e | 1848 | case 26000000: |
cc17557e | 1849 | case 38400000: |
cc17557e SS |
1850 | break; |
1851 | default: | |
3b8a0795 | 1852 | dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq); |
cc17557e SS |
1853 | return -EINVAL; |
1854 | } | |
1855 | ||
68d01955 PU |
1856 | if ((freq / 1000) != twl4030->sysclk) { |
1857 | dev_err(codec->dev, | |
3b8a0795 | 1858 | "Mismatch in HFCLKIN: %u (configured: %u)\n", |
68d01955 PU |
1859 | freq, twl4030->sysclk * 1000); |
1860 | return -EINVAL; | |
1861 | } | |
cc17557e SS |
1862 | |
1863 | return 0; | |
1864 | } | |
1865 | ||
7ded5fe0 | 1866 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
cc17557e SS |
1867 | { |
1868 | struct snd_soc_codec *codec = codec_dai->codec; | |
2046f175 | 1869 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1870 | u8 old_format, format; |
1871 | ||
1872 | /* get format */ | |
efc8acff | 1873 | old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
cc17557e SS |
1874 | format = old_format; |
1875 | ||
1876 | /* set master/slave audio interface */ | |
1877 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1878 | case SND_SOC_DAIFMT_CBM_CFM: | |
1879 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1880 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1881 | break; |
1882 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1883 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1884 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1885 | break; |
1886 | default: | |
1887 | return -EINVAL; | |
1888 | } | |
1889 | ||
1890 | /* interface format */ | |
1891 | format &= ~TWL4030_AIF_FORMAT; | |
1892 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1893 | case SND_SOC_DAIFMT_I2S: | |
1894 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1895 | break; | |
8a1f936a PU |
1896 | case SND_SOC_DAIFMT_DSP_A: |
1897 | format |= TWL4030_AIF_FORMAT_TDM; | |
1898 | break; | |
cc17557e SS |
1899 | default: |
1900 | return -EINVAL; | |
1901 | } | |
1902 | ||
1903 | if (format != old_format) { | |
2046f175 PU |
1904 | if (twl4030->codec_powered) { |
1905 | /* | |
1906 | * If the codec is powered, than we need to toggle the | |
1907 | * codec power. | |
1908 | */ | |
1909 | twl4030_codec_enable(codec, 0); | |
1910 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1911 | twl4030_codec_enable(codec, 1); | |
1912 | } else { | |
1913 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1914 | } | |
cc17557e SS |
1915 | } |
1916 | ||
1917 | return 0; | |
1918 | } | |
1919 | ||
68140443 LCM |
1920 | static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) |
1921 | { | |
1922 | struct snd_soc_codec *codec = dai->codec; | |
efc8acff | 1923 | u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
68140443 LCM |
1924 | |
1925 | if (tristate) | |
1926 | reg |= TWL4030_AIF_TRI_EN; | |
1927 | else | |
1928 | reg &= ~TWL4030_AIF_TRI_EN; | |
1929 | ||
1930 | return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); | |
1931 | } | |
1932 | ||
b7a755a8 MLC |
1933 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1934 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1935 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
7ded5fe0 | 1936 | int enable) |
b7a755a8 MLC |
1937 | { |
1938 | u8 reg, mask; | |
1939 | ||
efc8acff | 1940 | reg = twl4030_read(codec, TWL4030_REG_OPTION); |
b7a755a8 MLC |
1941 | |
1942 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1943 | mask = TWL4030_ARXL1_VRX_EN; | |
1944 | else | |
1945 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1946 | ||
1947 | if (enable) | |
1948 | reg |= mask; | |
1949 | else | |
1950 | reg &= ~mask; | |
1951 | ||
1952 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1953 | } | |
1954 | ||
7154b3e8 | 1955 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
7ded5fe0 | 1956 | struct snd_soc_dai *dai) |
7154b3e8 | 1957 | { |
e6968a17 | 1958 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1959 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
1960 | u8 mode; |
1961 | ||
1962 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
25985edc | 1963 | * not available. |
7154b3e8 | 1964 | */ |
68d01955 | 1965 | if (twl4030->sysclk != 26000) { |
3b8a0795 PU |
1966 | dev_err(codec->dev, |
1967 | "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n", | |
1968 | __func__, twl4030->sysclk); | |
7154b3e8 JS |
1969 | return -EINVAL; |
1970 | } | |
1971 | ||
1972 | /* If the codec mode is not option2, the voice PCM interface is not | |
25985edc | 1973 | * available. |
7154b3e8 | 1974 | */ |
efc8acff | 1975 | mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE) |
7154b3e8 JS |
1976 | & TWL4030_OPT_MODE; |
1977 | ||
1978 | if (mode != TWL4030_OPTION_2) { | |
3b8a0795 PU |
1979 | dev_err(codec->dev, "%s: the codec mode is not option2\n", |
1980 | __func__); | |
7154b3e8 JS |
1981 | return -EINVAL; |
1982 | } | |
1983 | ||
1984 | return 0; | |
1985 | } | |
1986 | ||
b7a755a8 | 1987 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
7ded5fe0 | 1988 | struct snd_soc_dai *dai) |
b7a755a8 | 1989 | { |
e6968a17 | 1990 | struct snd_soc_codec *codec = dai->codec; |
b7a755a8 MLC |
1991 | |
1992 | /* Enable voice digital filters */ | |
1993 | twl4030_voice_enable(codec, substream->stream, 0); | |
1994 | } | |
1995 | ||
7154b3e8 | 1996 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
7ded5fe0 PU |
1997 | struct snd_pcm_hw_params *params, |
1998 | struct snd_soc_dai *dai) | |
7154b3e8 | 1999 | { |
e6968a17 | 2000 | struct snd_soc_codec *codec = dai->codec; |
2046f175 | 2001 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
2002 | u8 old_mode, mode; |
2003 | ||
b7a755a8 MLC |
2004 | /* Enable voice digital filters */ |
2005 | twl4030_voice_enable(codec, substream->stream, 1); | |
2006 | ||
7154b3e8 | 2007 | /* bit rate */ |
7ded5fe0 PU |
2008 | old_mode = twl4030_read(codec, |
2009 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
7154b3e8 JS |
2010 | mode = old_mode; |
2011 | ||
2012 | switch (params_rate(params)) { | |
2013 | case 8000: | |
2014 | mode &= ~(TWL4030_SEL_16K); | |
2015 | break; | |
2016 | case 16000: | |
2017 | mode |= TWL4030_SEL_16K; | |
2018 | break; | |
2019 | default: | |
3b8a0795 | 2020 | dev_err(codec->dev, "%s: unknown rate %d\n", __func__, |
7154b3e8 JS |
2021 | params_rate(params)); |
2022 | return -EINVAL; | |
2023 | } | |
2024 | ||
2025 | if (mode != old_mode) { | |
2046f175 PU |
2026 | if (twl4030->codec_powered) { |
2027 | /* | |
2028 | * If the codec is powered, than we need to toggle the | |
2029 | * codec power. | |
2030 | */ | |
2031 | twl4030_codec_enable(codec, 0); | |
2032 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
2033 | twl4030_codec_enable(codec, 1); | |
2034 | } else { | |
2035 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
2036 | } | |
7154b3e8 JS |
2037 | } |
2038 | ||
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
7ded5fe0 | 2043 | int clk_id, unsigned int freq, int dir) |
7154b3e8 JS |
2044 | { |
2045 | struct snd_soc_codec *codec = codec_dai->codec; | |
d4a8ca24 | 2046 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 | 2047 | |
68d01955 | 2048 | if (freq != 26000000) { |
3b8a0795 PU |
2049 | dev_err(codec->dev, |
2050 | "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n", | |
2051 | __func__, freq / 1000); | |
68d01955 PU |
2052 | return -EINVAL; |
2053 | } | |
2054 | if ((freq / 1000) != twl4030->sysclk) { | |
2055 | dev_err(codec->dev, | |
3b8a0795 | 2056 | "Mismatch in HFCLKIN: %u (configured: %u)\n", |
68d01955 | 2057 | freq, twl4030->sysclk * 1000); |
7154b3e8 JS |
2058 | return -EINVAL; |
2059 | } | |
7154b3e8 JS |
2060 | return 0; |
2061 | } | |
2062 | ||
2063 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
7ded5fe0 | 2064 | unsigned int fmt) |
7154b3e8 JS |
2065 | { |
2066 | struct snd_soc_codec *codec = codec_dai->codec; | |
2046f175 | 2067 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
2068 | u8 old_format, format; |
2069 | ||
2070 | /* get format */ | |
efc8acff | 2071 | old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF); |
7154b3e8 JS |
2072 | format = old_format; |
2073 | ||
2074 | /* set master/slave audio interface */ | |
2075 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 2076 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
2077 | format &= ~(TWL4030_VIF_SLAVE_EN); |
2078 | break; | |
2079 | case SND_SOC_DAIFMT_CBS_CFS: | |
2080 | format |= TWL4030_VIF_SLAVE_EN; | |
2081 | break; | |
2082 | default: | |
2083 | return -EINVAL; | |
2084 | } | |
2085 | ||
2086 | /* clock inversion */ | |
2087 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2088 | case SND_SOC_DAIFMT_IB_NF: | |
2089 | format &= ~(TWL4030_VIF_FORMAT); | |
2090 | break; | |
2091 | case SND_SOC_DAIFMT_NB_IF: | |
2092 | format |= TWL4030_VIF_FORMAT; | |
2093 | break; | |
2094 | default: | |
2095 | return -EINVAL; | |
2096 | } | |
2097 | ||
2098 | if (format != old_format) { | |
2046f175 PU |
2099 | if (twl4030->codec_powered) { |
2100 | /* | |
2101 | * If the codec is powered, than we need to toggle the | |
2102 | * codec power. | |
2103 | */ | |
2104 | twl4030_codec_enable(codec, 0); | |
2105 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2106 | twl4030_codec_enable(codec, 1); | |
2107 | } else { | |
2108 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2109 | } | |
7154b3e8 JS |
2110 | } |
2111 | ||
2112 | return 0; | |
2113 | } | |
2114 | ||
68140443 LCM |
2115 | static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) |
2116 | { | |
2117 | struct snd_soc_codec *codec = dai->codec; | |
efc8acff | 2118 | u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF); |
68140443 LCM |
2119 | |
2120 | if (tristate) | |
2121 | reg |= TWL4030_VIF_TRI_EN; | |
2122 | else | |
2123 | reg &= ~TWL4030_VIF_TRI_EN; | |
2124 | ||
2125 | return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); | |
2126 | } | |
2127 | ||
bbba9444 | 2128 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
dcdeda4a | 2129 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
cc17557e | 2130 | |
85e7652d | 2131 | static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = { |
7220b9f4 PU |
2132 | .startup = twl4030_startup, |
2133 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
2134 | .hw_params = twl4030_hw_params, |
2135 | .set_sysclk = twl4030_set_dai_sysclk, | |
2136 | .set_fmt = twl4030_set_dai_fmt, | |
68140443 | 2137 | .set_tristate = twl4030_set_tristate, |
10d9e3d9 JS |
2138 | }; |
2139 | ||
85e7652d | 2140 | static const struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
7154b3e8 | 2141 | .startup = twl4030_voice_startup, |
b7a755a8 | 2142 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
2143 | .hw_params = twl4030_voice_hw_params, |
2144 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
2145 | .set_fmt = twl4030_voice_set_dai_fmt, | |
68140443 | 2146 | .set_tristate = twl4030_voice_set_tristate, |
7154b3e8 JS |
2147 | }; |
2148 | ||
f0fba2ad | 2149 | static struct snd_soc_dai_driver twl4030_dai[] = { |
7154b3e8 | 2150 | { |
f0fba2ad | 2151 | .name = "twl4030-hifi", |
cc17557e | 2152 | .playback = { |
b4852b79 | 2153 | .stream_name = "HiFi Playback", |
cc17557e | 2154 | .channels_min = 2, |
8a1f936a | 2155 | .channels_max = 4, |
31ad0f31 | 2156 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
8819f65c PU |
2157 | .formats = TWL4030_FORMATS, |
2158 | .sig_bits = 24,}, | |
cc17557e | 2159 | .capture = { |
7f51e7d3 | 2160 | .stream_name = "HiFi Capture", |
cc17557e | 2161 | .channels_min = 2, |
8a1f936a | 2162 | .channels_max = 4, |
cc17557e | 2163 | .rates = TWL4030_RATES, |
8819f65c PU |
2164 | .formats = TWL4030_FORMATS, |
2165 | .sig_bits = 24,}, | |
f0fba2ad | 2166 | .ops = &twl4030_dai_hifi_ops, |
7154b3e8 JS |
2167 | }, |
2168 | { | |
f0fba2ad | 2169 | .name = "twl4030-voice", |
7154b3e8 | 2170 | .playback = { |
b4852b79 | 2171 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2172 | .channels_min = 1, |
2173 | .channels_max = 1, | |
2174 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2175 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2176 | .capture = { | |
7f51e7d3 | 2177 | .stream_name = "Voice Capture", |
7154b3e8 JS |
2178 | .channels_min = 1, |
2179 | .channels_max = 2, | |
2180 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2181 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2182 | .ops = &twl4030_dai_voice_ops, | |
2183 | }, | |
cc17557e | 2184 | }; |
cc17557e | 2185 | |
f0fba2ad | 2186 | static int twl4030_soc_probe(struct snd_soc_codec *codec) |
cc17557e | 2187 | { |
f0fba2ad | 2188 | struct twl4030_priv *twl4030; |
9da28c7b | 2189 | |
f2b1ce49 PU |
2190 | twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv), |
2191 | GFP_KERNEL); | |
f0fba2ad | 2192 | if (twl4030 == NULL) { |
3b8a0795 | 2193 | dev_err(codec->dev, "Can not allocate memory\n"); |
f0fba2ad | 2194 | return -ENOMEM; |
cc17557e | 2195 | } |
f0fba2ad LG |
2196 | snd_soc_codec_set_drvdata(codec, twl4030); |
2197 | /* Set the defaults, and power up the codec */ | |
57fe7251 | 2198 | twl4030->sysclk = twl4030_audio_get_mclk() / 1000; |
f0fba2ad LG |
2199 | |
2200 | twl4030_init_chip(codec); | |
cc17557e | 2201 | |
7a1fecf5 | 2202 | return 0; |
cc17557e SS |
2203 | } |
2204 | ||
f0fba2ad | 2205 | static int twl4030_soc_remove(struct snd_soc_codec *codec) |
cc17557e | 2206 | { |
5b3b0fa8 | 2207 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
182f73f6 | 2208 | struct twl4030_codec_data *pdata = twl4030->pdata; |
5b3b0fa8 | 2209 | |
7a1fecf5 | 2210 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); |
281ecd16 PU |
2211 | |
2212 | if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio)) | |
2213 | gpio_free(pdata->hs_extmute_gpio); | |
2214 | ||
7a1fecf5 PU |
2215 | return 0; |
2216 | } | |
2217 | ||
f0fba2ad LG |
2218 | static struct snd_soc_codec_driver soc_codec_dev_twl4030 = { |
2219 | .probe = twl4030_soc_probe, | |
2220 | .remove = twl4030_soc_remove, | |
efc8acff | 2221 | .read = twl4030_read, |
f0fba2ad LG |
2222 | .write = twl4030_write, |
2223 | .set_bias_level = twl4030_set_bias_level, | |
eb3032f8 | 2224 | .idle_bias_off = true, |
f7c93f01 PU |
2225 | |
2226 | .controls = twl4030_snd_controls, | |
2227 | .num_controls = ARRAY_SIZE(twl4030_snd_controls), | |
2228 | .dapm_widgets = twl4030_dapm_widgets, | |
2229 | .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets), | |
2230 | .dapm_routes = intercon, | |
2231 | .num_dapm_routes = ARRAY_SIZE(intercon), | |
f0fba2ad LG |
2232 | }; |
2233 | ||
05c4c6f7 | 2234 | static int twl4030_codec_probe(struct platform_device *pdev) |
7a1fecf5 | 2235 | { |
f0fba2ad | 2236 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030, |
7ded5fe0 | 2237 | twl4030_dai, ARRAY_SIZE(twl4030_dai)); |
cc17557e SS |
2238 | } |
2239 | ||
05c4c6f7 | 2240 | static int twl4030_codec_remove(struct platform_device *pdev) |
cc17557e | 2241 | { |
f0fba2ad | 2242 | snd_soc_unregister_codec(&pdev->dev); |
cc17557e SS |
2243 | return 0; |
2244 | } | |
2245 | ||
f0fba2ad | 2246 | MODULE_ALIAS("platform:twl4030-codec"); |
7a1fecf5 PU |
2247 | |
2248 | static struct platform_driver twl4030_codec_driver = { | |
2249 | .probe = twl4030_codec_probe, | |
05c4c6f7 | 2250 | .remove = twl4030_codec_remove, |
7a1fecf5 | 2251 | .driver = { |
f0fba2ad | 2252 | .name = "twl4030-codec", |
7a1fecf5 PU |
2253 | .owner = THIS_MODULE, |
2254 | }, | |
cc17557e | 2255 | }; |
cc17557e | 2256 | |
5bbcc3c0 | 2257 | module_platform_driver(twl4030_codec_driver); |
64089b84 | 2258 | |
cc17557e SS |
2259 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2260 | MODULE_AUTHOR("Steve Sakoman"); | |
2261 | MODULE_LICENSE("GPL"); |