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Merge branch 'for-2.6.29' into for-2.6.30
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
125};
126
cc17557e
SS		 127/*
128 * read twl4030 register cache
129 */
130static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
131 unsigned int reg)
132{
133 u8 *cache = codec->reg_cache;
134
91432e97
IM		 135 if (reg >= TWL4030_CACHEREGNUM)
136 return -EIO;
137
cc17557e
SS		 138 return cache[reg];
139}
140
141/*
142 * write twl4030 register cache
143 */
144static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
145 u8 reg, u8 value)
146{
147 u8 *cache = codec->reg_cache;
148
149 if (reg >= TWL4030_CACHEREGNUM)
150 return;
151 cache[reg] = value;
152}
153
154/*
155 * write to the twl4030 register space
156 */
157static int twl4030_write(struct snd_soc_codec *codec,
158 unsigned int reg, unsigned int value)
159{
160 twl4030_write_reg_cache(codec, reg, value);
161 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
162}
163
db04e2c5 164static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 165{
7393958f 166 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 167 u8 mode;
168
7393958f
PU		 169 if (enable == twl4030->codec_powered)
170 return;
171
cc17557e 172 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 173 if (enable)
174 mode |= TWL4030_CODECPDZ;
175 else
176 mode &= ~TWL4030_CODECPDZ;
cc17557e 177
db04e2c5 178 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 179 twl4030->codec_powered = enable;
cc17557e
SS		 180
181 /* REVISIT: this delay is present in TI sample drivers */
182 /* but there seems to be no TRM requirement for it */
183 udelay(10);
184}
185
186static void twl4030_init_chip(struct snd_soc_codec *codec)
187{
188 int i;
189
190 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 191 twl4030_codec_enable(codec, 0);
cc17557e
SS		 192
193 /* set all audio section registers to reasonable defaults */
194 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
195 twl4030_write(codec, i, twl4030_reg[i]);
196
197}
198
7393958f
PU		 199static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
200{
201 struct twl4030_priv *twl4030 = codec->private_data;
202 u8 reg_val;
203
204 if (mute == twl4030->codec_muted)
205 return;
206
207 if (mute) {
208 /* Bypass the reg_cache and mute the volumes
209 * Headset mute is done in it's own event handler
210 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
211 */
212 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
213 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
214 reg_val & (~TWL4030_EAR_GAIN),
215 TWL4030_REG_EAR_CTL);
216
217 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
218 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
219 reg_val & (~TWL4030_PREDL_GAIN),
220 TWL4030_REG_PREDL_CTL);
221 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
222 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
223 reg_val & (~TWL4030_PREDR_GAIN),
224 TWL4030_REG_PREDL_CTL);
225
226 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
227 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
228 reg_val & (~TWL4030_PRECKL_GAIN),
229 TWL4030_REG_PRECKL_CTL);
230 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
231 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
232 reg_val & (~TWL4030_PRECKL_GAIN),
233 TWL4030_REG_PRECKR_CTL);
234
235 /* Disable PLL */
236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
237 reg_val &= ~TWL4030_APLL_EN;
238 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
239 } else {
240 /* Restore the volumes
241 * Headset mute is done in it's own event handler
242 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
243 */
244 twl4030_write(codec, TWL4030_REG_EAR_CTL,
245 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
246
247 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
248 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
249 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
250 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
251
252 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
254 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
255 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
256
257 /* Enable PLL */
258 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
259 reg_val |= TWL4030_APLL_EN;
260 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
261 }
262
263 twl4030->codec_muted = mute;
264}
265
006f367e
PU		 266static void twl4030_power_up(struct snd_soc_codec *codec)
267{
7393958f 268 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 269 u8 anamicl, regmisc1, byte;
270 int i = 0;
271
7393958f
PU		 272 if (twl4030->codec_powered)
273 return;
274
006f367e
PU		 275 /* set CODECPDZ to turn on codec */
276 twl4030_codec_enable(codec, 1);
277
278 /* initiate offset cancellation */
279 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
280 twl4030_write(codec, TWL4030_REG_ANAMICL,
281 anamicl | TWL4030_CNCL_OFFSET_START);
282
283 /* wait for offset cancellation to complete */
284 do {
285 /* this takes a little while, so don't slam i2c */
286 udelay(2000);
287 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
288 TWL4030_REG_ANAMICL);
289 } while ((i++ < 100) &&
290 ((byte & TWL4030_CNCL_OFFSET_START) ==
291 TWL4030_CNCL_OFFSET_START));
292
293 /* Make sure that the reg_cache has the same value as the HW */
294 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
295
296 /* anti-pop when changing analog gain */
297 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
298 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
299 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
300
301 /* toggle CODECPDZ as per TRM */
302 twl4030_codec_enable(codec, 0);
303 twl4030_codec_enable(codec, 1);
304}
305
7393958f
PU		 306/*
307 * Unconditional power down
308 */
006f367e
PU		 309static void twl4030_power_down(struct snd_soc_codec *codec)
310{
311 /* power down */
312 twl4030_codec_enable(codec, 0);
313}
314
5e98a464
PU		 315/* Earpiece */
316static const char *twl4030_earpiece_texts[] =
2f423577 317 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 318
2f423577
PU		 319static const unsigned int twl4030_earpiece_values[] =
320 {0x0, 0x1, 0x2, 0x4};
321
cb1ace04 322static const struct soc_enum twl4030_earpiece_enum =
2f423577 323 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 324 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 325 twl4030_earpiece_texts,
326 twl4030_earpiece_values);
5e98a464
PU		 327
328static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 329SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 330
2a6f5c58
PU		 331/* PreDrive Left */
332static const char *twl4030_predrivel_texts[] =
2f423577
PU		 333 {"Off", "DACL1", "DACL2", "DACR2"};
334
335static const unsigned int twl4030_predrivel_values[] =
336 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 337
cb1ace04 338static const struct soc_enum twl4030_predrivel_enum =
2f423577 339 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 340 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 341 twl4030_predrivel_texts,
342 twl4030_predrivel_values);
2a6f5c58
PU		 343
344static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 345SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 346
347/* PreDrive Right */
348static const char *twl4030_predriver_texts[] =
2f423577 349 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 350
2f423577
PU		 351static const unsigned int twl4030_predriver_values[] =
352 {0x0, 0x1, 0x2, 0x4};
353
cb1ace04 354static const struct soc_enum twl4030_predriver_enum =
2f423577 355 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 356 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 357 twl4030_predriver_texts,
358 twl4030_predriver_values);
2a6f5c58
PU		 359
360static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 361SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 362
dfad21a2
PU		 363/* Headset Left */
364static const char *twl4030_hsol_texts[] =
365 {"Off", "DACL1", "DACL2"};
366
367static const struct soc_enum twl4030_hsol_enum =
368 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
369 ARRAY_SIZE(twl4030_hsol_texts),
370 twl4030_hsol_texts);
371
372static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
373SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
374
375/* Headset Right */
376static const char *twl4030_hsor_texts[] =
377 {"Off", "DACR1", "DACR2"};
378
379static const struct soc_enum twl4030_hsor_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
381 ARRAY_SIZE(twl4030_hsor_texts),
382 twl4030_hsor_texts);
383
384static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
385SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
386
5152d8c2
PU		 387/* Carkit Left */
388static const char *twl4030_carkitl_texts[] =
389 {"Off", "DACL1", "DACL2"};
390
391static const struct soc_enum twl4030_carkitl_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
393 ARRAY_SIZE(twl4030_carkitl_texts),
394 twl4030_carkitl_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
397SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
398
399/* Carkit Right */
400static const char *twl4030_carkitr_texts[] =
401 {"Off", "DACR1", "DACR2"};
402
403static const struct soc_enum twl4030_carkitr_enum =
404 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
405 ARRAY_SIZE(twl4030_carkitr_texts),
406 twl4030_carkitr_texts);
407
408static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
409SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
410
df339804
PU		 411/* Handsfree Left */
412static const char *twl4030_handsfreel_texts[] =
413 {"Voice", "DACL1", "DACL2", "DACR2"};
414
415static const struct soc_enum twl4030_handsfreel_enum =
416 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
417 ARRAY_SIZE(twl4030_handsfreel_texts),
418 twl4030_handsfreel_texts);
419
420static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
421SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
422
423/* Handsfree Right */
424static const char *twl4030_handsfreer_texts[] =
425 {"Voice", "DACR1", "DACR2", "DACL2"};
426
427static const struct soc_enum twl4030_handsfreer_enum =
428 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
429 ARRAY_SIZE(twl4030_handsfreer_texts),
430 twl4030_handsfreer_texts);
431
432static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
433SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
434
276c6222
PU		 435/* Left analog microphone selection */
436static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 437 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
438
439static const unsigned int twl4030_analoglmic_values[] =
440 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 441
cb1ace04 442static const struct soc_enum twl4030_analoglmic_enum =
2f423577 443 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 444 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 445 twl4030_analoglmic_texts,
446 twl4030_analoglmic_values);
276c6222
PU		 447
448static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 449SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 450
451/* Right analog microphone selection */
452static const char *twl4030_analogrmic_texts[] =
2f423577 453 {"Off", "Sub mic", "AUXR"};
276c6222 454
2f423577
PU		 455static const unsigned int twl4030_analogrmic_values[] =
456 {0x0, 0x1, 0x4};
457
cb1ace04 458static const struct soc_enum twl4030_analogrmic_enum =
2f423577 459 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 460 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 461 twl4030_analogrmic_texts,
462 twl4030_analogrmic_values);
276c6222
PU		 463
464static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 465SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 466
467/* TX1 L/R Analog/Digital microphone selection */
468static const char *twl4030_micpathtx1_texts[] =
469 {"Analog", "Digimic0"};
470
471static const struct soc_enum twl4030_micpathtx1_enum =
472 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
473 ARRAY_SIZE(twl4030_micpathtx1_texts),
474 twl4030_micpathtx1_texts);
475
476static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
477SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
478
479/* TX2 L/R Analog/Digital microphone selection */
480static const char *twl4030_micpathtx2_texts[] =
481 {"Analog", "Digimic1"};
482
483static const struct soc_enum twl4030_micpathtx2_enum =
484 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
485 ARRAY_SIZE(twl4030_micpathtx2_texts),
486 twl4030_micpathtx2_texts);
487
488static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
489SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
490
7393958f
PU		 491/* Analog bypass for AudioR1 */
492static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
493 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
494
495/* Analog bypass for AudioL1 */
496static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
497 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
498
499/* Analog bypass for AudioR2 */
500static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
501 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
502
503/* Analog bypass for AudioL2 */
504static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
505 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
506
276c6222
PU		 507static int micpath_event(struct snd_soc_dapm_widget *w,
508 struct snd_kcontrol *kcontrol, int event)
509{
510 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
511 unsigned char adcmicsel, micbias_ctl;
512
513 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
514 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
515 /* Prepare the bits for the given TX path:
516 * shift_l == 0: TX1 microphone path
517 * shift_l == 2: TX2 microphone path */
518 if (e->shift_l) {
519 /* TX2 microphone path */
520 if (adcmicsel & TWL4030_TX2IN_SEL)
521 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
522 else
523 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
524 } else {
525 /* TX1 microphone path */
526 if (adcmicsel & TWL4030_TX1IN_SEL)
527 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
528 else
529 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
530 }
531
532 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
533
534 return 0;
535}
536
49d92c7d
SM		 537static int handsfree_event(struct snd_soc_dapm_widget *w,
538 struct snd_kcontrol *kcontrol, int event)
539{
540 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
541 unsigned char hs_ctl;
542
543 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
544
545 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
546 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
547 twl4030_write(w->codec, e->reg, hs_ctl);
548 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
549 twl4030_write(w->codec, e->reg, hs_ctl);
550 hs_ctl |= TWL4030_HF_CTL_HB_EN;
551 twl4030_write(w->codec, e->reg, hs_ctl);
552 } else {
553 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
554 | TWL4030_HF_CTL_HB_EN);
555 twl4030_write(w->codec, e->reg, hs_ctl);
556 }
557
558 return 0;
559}
560
aad749e5
PU		 561static int headsetl_event(struct snd_soc_dapm_widget *w,
562 struct snd_kcontrol *kcontrol, int event)
563{
564 unsigned char hs_gain, hs_pop;
565
566 /* Save the current volume */
567 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
568
569 switch (event) {
570 case SND_SOC_DAPM_POST_PMU:
571 /* Do the anti-pop/bias ramp enable according to the TRM */
572 hs_pop = TWL4030_RAMP_DELAY_645MS;
573 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
574 hs_pop |= TWL4030_VMID_EN;
575 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
576 /* Is this needed? Can we just use whatever gain here? */
577 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
578 (hs_gain & (~0x0f)) | 0x0a);
579 hs_pop |= TWL4030_RAMP_EN;
580 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
581
582 /* Restore the original volume */
583 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
584 break;
585 case SND_SOC_DAPM_POST_PMD:
586 /* Do the anti-pop/bias ramp disable according to the TRM */
587 hs_pop = twl4030_read_reg_cache(w->codec,
588 TWL4030_REG_HS_POPN_SET);
589 hs_pop &= ~TWL4030_RAMP_EN;
590 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
591 /* Bypass the reg_cache to mute the headset */
592 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
593 hs_gain & (~0x0f),
594 TWL4030_REG_HS_GAIN_SET);
595 hs_pop &= ~TWL4030_VMID_EN;
596 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
597 break;
598 }
599 return 0;
600}
601
7393958f
PU		 602static int bypass_event(struct snd_soc_dapm_widget *w,
603 struct snd_kcontrol *kcontrol, int event)
604{
605 struct soc_mixer_control *m =
606 (struct soc_mixer_control *)w->kcontrols->private_value;
607 struct twl4030_priv *twl4030 = w->codec->private_data;
608 unsigned char reg;
609
610 reg = twl4030_read_reg_cache(w->codec, m->reg);
611 if (reg & (1 << m->shift))
612 twl4030->bypass_state |=
613 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
614 else
615 twl4030->bypass_state &=
616 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
617
618 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
619 if (twl4030->bypass_state)
620 twl4030_codec_mute(w->codec, 0);
621 else
622 twl4030_codec_mute(w->codec, 1);
623 }
624 return 0;
625}
626
b0bd53a7
PU		 627/*
628 * Some of the gain controls in TWL (mostly those which are associated with
629 * the outputs) are implemented in an interesting way:
630 * 0x0 : Power down (mute)
631 * 0x1 : 6dB
632 * 0x2 : 0 dB
633 * 0x3 : -6 dB
634 * Inverting not going to help with these.
635 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
636 */
637#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
638 xinvert, tlv_array) \
639{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
640 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
641 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
642 .tlv.p = (tlv_array), \
643 .info = snd_soc_info_volsw, \
644 .get = snd_soc_get_volsw_twl4030, \
645 .put = snd_soc_put_volsw_twl4030, \
646 .private_value = (unsigned long)&(struct soc_mixer_control) \
647 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
648 .max = xmax, .invert = xinvert} }
649#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
650 xinvert, tlv_array) \
651{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
652 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
653 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
654 .tlv.p = (tlv_array), \
655 .info = snd_soc_info_volsw_2r, \
656 .get = snd_soc_get_volsw_r2_twl4030,\
657 .put = snd_soc_put_volsw_r2_twl4030, \
658 .private_value = (unsigned long)&(struct soc_mixer_control) \
659 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 660 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 661#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
662 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
663 xinvert, tlv_array)
664
665static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
666 struct snd_ctl_elem_value *ucontrol)
667{
668 struct soc_mixer_control *mc =
669 (struct soc_mixer_control *)kcontrol->private_value;
670 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
671 unsigned int reg = mc->reg;
672 unsigned int shift = mc->shift;
673 unsigned int rshift = mc->rshift;
674 int max = mc->max;
675 int mask = (1 << fls(max)) - 1;
676
677 ucontrol->value.integer.value[0] =
678 (snd_soc_read(codec, reg) >> shift) & mask;
679 if (ucontrol->value.integer.value[0])
680 ucontrol->value.integer.value[0] =
681 max + 1 - ucontrol->value.integer.value[0];
682
683 if (shift != rshift) {
684 ucontrol->value.integer.value[1] =
685 (snd_soc_read(codec, reg) >> rshift) & mask;
686 if (ucontrol->value.integer.value[1])
687 ucontrol->value.integer.value[1] =
688 max + 1 - ucontrol->value.integer.value[1];
689 }
690
691 return 0;
692}
693
694static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct soc_mixer_control *mc =
698 (struct soc_mixer_control *)kcontrol->private_value;
699 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
700 unsigned int reg = mc->reg;
701 unsigned int shift = mc->shift;
702 unsigned int rshift = mc->rshift;
703 int max = mc->max;
704 int mask = (1 << fls(max)) - 1;
705 unsigned short val, val2, val_mask;
706
707 val = (ucontrol->value.integer.value[0] & mask);
708
709 val_mask = mask << shift;
710 if (val)
711 val = max + 1 - val;
712 val = val << shift;
713 if (shift != rshift) {
714 val2 = (ucontrol->value.integer.value[1] & mask);
715 val_mask |= mask << rshift;
716 if (val2)
717 val2 = max + 1 - val2;
718 val |= val2 << rshift;
719 }
720 return snd_soc_update_bits(codec, reg, val_mask, val);
721}
722
723static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
724 struct snd_ctl_elem_value *ucontrol)
725{
726 struct soc_mixer_control *mc =
727 (struct soc_mixer_control *)kcontrol->private_value;
728 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
729 unsigned int reg = mc->reg;
730 unsigned int reg2 = mc->rreg;
731 unsigned int shift = mc->shift;
732 int max = mc->max;
733 int mask = (1<<fls(max))-1;
734
735 ucontrol->value.integer.value[0] =
736 (snd_soc_read(codec, reg) >> shift) & mask;
737 ucontrol->value.integer.value[1] =
738 (snd_soc_read(codec, reg2) >> shift) & mask;
739
740 if (ucontrol->value.integer.value[0])
741 ucontrol->value.integer.value[0] =
742 max + 1 - ucontrol->value.integer.value[0];
743 if (ucontrol->value.integer.value[1])
744 ucontrol->value.integer.value[1] =
745 max + 1 - ucontrol->value.integer.value[1];
746
747 return 0;
748}
749
750static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
752{
753 struct soc_mixer_control *mc =
754 (struct soc_mixer_control *)kcontrol->private_value;
755 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
756 unsigned int reg = mc->reg;
757 unsigned int reg2 = mc->rreg;
758 unsigned int shift = mc->shift;
759 int max = mc->max;
760 int mask = (1 << fls(max)) - 1;
761 int err;
762 unsigned short val, val2, val_mask;
763
764 val_mask = mask << shift;
765 val = (ucontrol->value.integer.value[0] & mask);
766 val2 = (ucontrol->value.integer.value[1] & mask);
767
768 if (val)
769 val = max + 1 - val;
770 if (val2)
771 val2 = max + 1 - val2;
772
773 val = val << shift;
774 val2 = val2 << shift;
775
776 err = snd_soc_update_bits(codec, reg, val_mask, val);
777 if (err < 0)
778 return err;
779
780 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
781 return err;
782}
783
c10b82cf
PU		 784/*
785 * FGAIN volume control:
786 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
787 */
d889a72c 788static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 789
0d33ea0b
PU		 790/*
791 * CGAIN volume control:
792 * 0 dB to 12 dB in 6 dB steps
793 * value 2 and 3 means 12 dB
794 */
d889a72c
PU		 795static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
796
797/*
798 * Analog playback gain
799 * -24 dB to 12 dB in 2 dB steps
800 */
801static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 802
4290239c
PU		 803/*
804 * Gain controls tied to outputs
805 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
806 */
807static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
808
381a22b5
PU		 809/*
810 * Capture gain after the ADCs
811 * from 0 dB to 31 dB in 1 dB steps
812 */
813static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
814
5920b453
GI		 815/*
816 * Gain control for input amplifiers
817 * 0 dB to 30 dB in 6 dB steps
818 */
819static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
820
cc17557e 821static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 822 /* Common playback gain controls */
823 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
824 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
825 0, 0x3f, 0, digital_fine_tlv),
826 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
827 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
828 0, 0x3f, 0, digital_fine_tlv),
829
830 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
831 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
832 6, 0x2, 0, digital_coarse_tlv),
833 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
834 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
835 6, 0x2, 0, digital_coarse_tlv),
836
837 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
838 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
839 3, 0x12, 1, analog_tlv),
840 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
841 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
842 3, 0x12, 1, analog_tlv),
44c55870
PU		 843 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
844 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
845 1, 1, 0),
846 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
847 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
848 1, 1, 0),
381a22b5 849
4290239c
PU		 850 /* Separate output gain controls */
851 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
852 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
853 4, 3, 0, output_tvl),
854
855 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
856 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
857
858 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
859 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
860 4, 3, 0, output_tvl),
861
862 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
863 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
864
381a22b5 865 /* Common capture gain controls */
276c6222 866 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 867 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
868 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 869 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
870 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
871 0, 0x1f, 0, digital_capture_tlv),
5920b453 872
276c6222 873 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 874 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 875};
876
cc17557e 877static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 878 /* Left channel inputs */
879 SND_SOC_DAPM_INPUT("MAINMIC"),
880 SND_SOC_DAPM_INPUT("HSMIC"),
881 SND_SOC_DAPM_INPUT("AUXL"),
882 SND_SOC_DAPM_INPUT("CARKITMIC"),
883 /* Right channel inputs */
884 SND_SOC_DAPM_INPUT("SUBMIC"),
885 SND_SOC_DAPM_INPUT("AUXR"),
886 /* Digital microphones (Stereo) */
887 SND_SOC_DAPM_INPUT("DIGIMIC0"),
888 SND_SOC_DAPM_INPUT("DIGIMIC1"),
889
890 /* Outputs */
cc17557e
SS		 891 SND_SOC_DAPM_OUTPUT("OUTL"),
892 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 893 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 894 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
895 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 896 SND_SOC_DAPM_OUTPUT("HSOL"),
897 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 898 SND_SOC_DAPM_OUTPUT("CARKITL"),
899 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 900 SND_SOC_DAPM_OUTPUT("HFL"),
901 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 902
53b5047d 903 /* DACs */
1e5fa31f 904 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 905 SND_SOC_NOPM, 0, 0),
1e5fa31f 906 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 907 SND_SOC_NOPM, 0, 0),
1e5fa31f 908 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 909 SND_SOC_NOPM, 0, 0),
1e5fa31f 910 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 911 SND_SOC_NOPM, 0, 0),
cc17557e 912
44c55870
PU		 913 /* Analog PGAs */
914 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
915 0, 0, NULL, 0),
916 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
917 0, 0, NULL, 0),
918 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
919 0, 0, NULL, 0),
920 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
921 0, 0, NULL, 0),
922
7393958f
PU		 923 /* Analog bypasses */
924 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
925 &twl4030_dapm_abypassr1_control, bypass_event,
926 SND_SOC_DAPM_POST_REG),
927 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
928 &twl4030_dapm_abypassl1_control,
929 bypass_event, SND_SOC_DAPM_POST_REG),
930 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
931 &twl4030_dapm_abypassr2_control,
932 bypass_event, SND_SOC_DAPM_POST_REG),
933 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
934 &twl4030_dapm_abypassl2_control,
935 bypass_event, SND_SOC_DAPM_POST_REG),
936
937 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
938 0, 0, NULL, 0),
939 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
940 1, 0, NULL, 0),
941 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
942 2, 0, NULL, 0),
943 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
944 3, 0, NULL, 0),
945
5e98a464
PU		 946 /* Output MUX controls */
947 /* Earpiece */
2f423577
PU		 948 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
949 &twl4030_dapm_earpiece_control),
2a6f5c58 950 /* PreDrivL/R */
2f423577
PU		 951 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
952 &twl4030_dapm_predrivel_control),
953 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
954 &twl4030_dapm_predriver_control),
dfad21a2 955 /* HeadsetL/R */
aad749e5
PU		 956 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
957 &twl4030_dapm_hsol_control, headsetl_event,
958 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2
PU		 959 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
960 &twl4030_dapm_hsor_control),
5152d8c2
PU		 961 /* CarkitL/R */
962 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
963 &twl4030_dapm_carkitl_control),
964 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
965 &twl4030_dapm_carkitr_control),
df339804 966 /* HandsfreeL/R */
49d92c7d
SM		 967 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
968 &twl4030_dapm_handsfreel_control, handsfree_event,
969 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
970 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
971 &twl4030_dapm_handsfreer_control, handsfree_event,
972 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 973
276c6222
PU		 974 /* Introducing four virtual ADC, since TWL4030 have four channel for
975 capture */
976 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
977 SND_SOC_NOPM, 0, 0),
978 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
979 SND_SOC_NOPM, 0, 0),
980 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
981 SND_SOC_NOPM, 0, 0),
982 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
983 SND_SOC_NOPM, 0, 0),
984
985 /* Analog/Digital mic path selection.
986 TX1 Left/Right: either analog Left/Right or Digimic0
987 TX2 Left/Right: either analog Left/Right or Digimic1 */
988 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
989 &twl4030_dapm_micpathtx1_control, micpath_event,
990 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
991 SND_SOC_DAPM_POST_REG),
992 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
993 &twl4030_dapm_micpathtx2_control, micpath_event,
994 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
995 SND_SOC_DAPM_POST_REG),
996
fb2a2f84 997 /* Analog input muxes with switch for the capture amplifiers */
2f423577 998 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 999 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1000 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1001 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1002
fb2a2f84
PU		 1003 SND_SOC_DAPM_PGA("ADC Physical Left",
1004 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1005 SND_SOC_DAPM_PGA("ADC Physical Right",
1006 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1007
1008 SND_SOC_DAPM_PGA("Digimic0 Enable",
1009 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1010 SND_SOC_DAPM_PGA("Digimic1 Enable",
1011 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1012
1013 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1014 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1015 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1016
cc17557e
SS		 1017};
1018
1019static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1020 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1021 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1022 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1023 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1024
1025 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1026 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1027 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1028 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
44c55870 1029
5e98a464
PU		 1030 /* Internal playback routings */
1031 /* Earpiece */
1032 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
1033 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
1034 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 1035 /* PreDrivL */
1036 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
1037 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
1038 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
1039 /* PreDrivR */
1040 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
1041 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
1042 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 1043 /* HeadsetL */
1044 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
1045 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
1046 /* HeadsetR */
1047 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
1048 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 1049 /* CarkitL */
1050 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
1051 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
1052 /* CarkitR */
1053 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
1054 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 1055 /* HandsfreeL */
1056 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
1057 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
1058 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
1059 /* HandsfreeR */
1060 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
1061 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
1062 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 1063
cc17557e 1064 /* outputs */
44c55870
PU		 1065 {"OUTL", NULL, "ARXL2_APGA"},
1066 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 1067 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 1068 {"PREDRIVEL", NULL, "PredriveL Mux"},
1069 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 1070 {"HSOL", NULL, "HeadsetL Mux"},
1071 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 1072 {"CARKITL", NULL, "CarkitL Mux"},
1073 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 1074 {"HFL", NULL, "HandsfreeL Mux"},
1075 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 1076
276c6222
PU		 1077 /* Capture path */
1078 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1079 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1080 {"Analog Left Capture Route", "AUXL", "AUXL"},
1081 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1082
1083 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1084 {"Analog Right Capture Route", "AUXR", "AUXR"},
1085
fb2a2f84
PU		 1086 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1087 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1088
1089 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1090 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1091
1092 /* TX1 Left capture path */
fb2a2f84 1093 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1094 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1095 /* TX1 Right capture path */
fb2a2f84 1096 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1097 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1098 /* TX2 Left capture path */
fb2a2f84 1099 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1100 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1101 /* TX2 Right capture path */
fb2a2f84 1102 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1103 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1104
1105 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1106 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1107 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1108 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1109
7393958f
PU		 1110 /* Analog bypass routes */
1111 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1112 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1113 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1114 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1115
1116 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1117 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1118 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1119 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1120
cc17557e
SS		 1121};
1122
1123static int twl4030_add_widgets(struct snd_soc_codec *codec)
1124{
1125 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1126 ARRAY_SIZE(twl4030_dapm_widgets));
1127
1128 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1129
1130 snd_soc_dapm_new_widgets(codec);
1131 return 0;
1132}
1133
cc17557e
SS		 1134static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1135 enum snd_soc_bias_level level)
1136{
7393958f
PU		 1137 struct twl4030_priv *twl4030 = codec->private_data;
1138
cc17557e
SS		 1139 switch (level) {
1140 case SND_SOC_BIAS_ON:
7393958f 1141 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1142 break;
1143 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1144 twl4030_power_up(codec);
1145 if (twl4030->bypass_state)
1146 twl4030_codec_mute(codec, 0);
1147 else
1148 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1149 break;
1150 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1151 twl4030_power_up(codec);
1152 if (twl4030->bypass_state)
1153 twl4030_codec_mute(codec, 0);
1154 else
1155 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1156 break;
1157 case SND_SOC_BIAS_OFF:
1158 twl4030_power_down(codec);
1159 break;
1160 }
1161 codec->bias_level = level;
1162
1163 return 0;
1164}
1165
1166static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1167 struct snd_pcm_hw_params *params,
1168 struct snd_soc_dai *dai)
cc17557e
SS		 1169{
1170 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1171 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1172 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1173 u8 mode, old_mode, format, old_format;
1174
cc17557e
SS		 1175 /* bit rate */
1176 old_mode = twl4030_read_reg_cache(codec,
1177 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1178 mode = old_mode & ~TWL4030_APLL_RATE;
1179
1180 switch (params_rate(params)) {
1181 case 8000:
1182 mode |= TWL4030_APLL_RATE_8000;
1183 break;
1184 case 11025:
1185 mode |= TWL4030_APLL_RATE_11025;
1186 break;
1187 case 12000:
1188 mode |= TWL4030_APLL_RATE_12000;
1189 break;
1190 case 16000:
1191 mode |= TWL4030_APLL_RATE_16000;
1192 break;
1193 case 22050:
1194 mode |= TWL4030_APLL_RATE_22050;
1195 break;
1196 case 24000:
1197 mode |= TWL4030_APLL_RATE_24000;
1198 break;
1199 case 32000:
1200 mode |= TWL4030_APLL_RATE_32000;
1201 break;
1202 case 44100:
1203 mode |= TWL4030_APLL_RATE_44100;
1204 break;
1205 case 48000:
1206 mode |= TWL4030_APLL_RATE_48000;
1207 break;
1208 default:
1209 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1210 params_rate(params));
1211 return -EINVAL;
1212 }
1213
1214 if (mode != old_mode) {
1215 /* change rate and set CODECPDZ */
7393958f 1216 twl4030_codec_enable(codec, 0);
cc17557e 1217 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1218 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1219 }
1220
1221 /* sample size */
1222 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1223 format = old_format;
1224 format &= ~TWL4030_DATA_WIDTH;
1225 switch (params_format(params)) {
1226 case SNDRV_PCM_FORMAT_S16_LE:
1227 format |= TWL4030_DATA_WIDTH_16S_16W;
1228 break;
1229 case SNDRV_PCM_FORMAT_S24_LE:
1230 format |= TWL4030_DATA_WIDTH_32S_24W;
1231 break;
1232 default:
1233 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1234 params_format(params));
1235 return -EINVAL;
1236 }
1237
1238 if (format != old_format) {
1239
1240 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1241 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1242
1243 /* change format */
1244 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1245
1246 /* set CODECPDZ afterwards */
db04e2c5 1247 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1248 }
1249 return 0;
1250}
1251
1252static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1253 int clk_id, unsigned int freq, int dir)
1254{
1255 struct snd_soc_codec *codec = codec_dai->codec;
1256 u8 infreq;
1257
1258 switch (freq) {
1259 case 19200000:
1260 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1261 break;
1262 case 26000000:
1263 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1264 break;
1265 case 38400000:
1266 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1267 break;
1268 default:
1269 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1270 freq);
1271 return -EINVAL;
1272 }
1273
1274 infreq |= TWL4030_APLL_EN;
1275 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1276
1277 return 0;
1278}
1279
1280static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1281 unsigned int fmt)
1282{
1283 struct snd_soc_codec *codec = codec_dai->codec;
1284 u8 old_format, format;
1285
1286 /* get format */
1287 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1288 format = old_format;
1289
1290 /* set master/slave audio interface */
1291 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1292 case SND_SOC_DAIFMT_CBM_CFM:
1293 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1294 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1295 break;
1296 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1297 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1298 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1299 break;
1300 default:
1301 return -EINVAL;
1302 }
1303
1304 /* interface format */
1305 format &= ~TWL4030_AIF_FORMAT;
1306 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1307 case SND_SOC_DAIFMT_I2S:
1308 format |= TWL4030_AIF_FORMAT_CODEC;
1309 break;
1310 default:
1311 return -EINVAL;
1312 }
1313
1314 if (format != old_format) {
1315
1316 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1317 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1318
1319 /* change format */
1320 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1321
1322 /* set CODECPDZ afterwards */
db04e2c5 1323 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1324 }
1325
1326 return 0;
1327}
1328
bbba9444 1329#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1330#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1331
1332struct snd_soc_dai twl4030_dai = {
1333 .name = "twl4030",
1334 .playback = {
1335 .stream_name = "Playback",
1336 .channels_min = 2,
1337 .channels_max = 2,
1338 .rates = TWL4030_RATES,
1339 .formats = TWL4030_FORMATS,},
1340 .capture = {
1341 .stream_name = "Capture",
1342 .channels_min = 2,
1343 .channels_max = 2,
1344 .rates = TWL4030_RATES,
1345 .formats = TWL4030_FORMATS,},
1346 .ops = {
1347 .hw_params = twl4030_hw_params,
cc17557e
SS		 1348 .set_sysclk = twl4030_set_dai_sysclk,
1349 .set_fmt = twl4030_set_dai_fmt,
1350 }
1351};
1352EXPORT_SYMBOL_GPL(twl4030_dai);
1353
1354static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1355{
1356 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1357 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1358
1359 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1360
1361 return 0;
1362}
1363
1364static int twl4030_resume(struct platform_device *pdev)
1365{
1366 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1367 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1368
1369 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1370 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1371 return 0;
1372}
1373
1374/*
1375 * initialize the driver
1376 * register the mixer and dsp interfaces with the kernel
1377 */
1378
1379static int twl4030_init(struct snd_soc_device *socdev)
1380{
6627a653 1381 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1382 int ret = 0;
1383
1384 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1385
1386 codec->name = "twl4030";
1387 codec->owner = THIS_MODULE;
1388 codec->read = twl4030_read_reg_cache;
1389 codec->write = twl4030_write;
1390 codec->set_bias_level = twl4030_set_bias_level;
1391 codec->dai = &twl4030_dai;
1392 codec->num_dai = 1;
1393 codec->reg_cache_size = sizeof(twl4030_reg);
1394 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1395 GFP_KERNEL);
1396 if (codec->reg_cache == NULL)
1397 return -ENOMEM;
1398
1399 /* register pcms */
1400 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1401 if (ret < 0) {
1402 printk(KERN_ERR "twl4030: failed to create pcms\n");
1403 goto pcm_err;
1404 }
1405
1406 twl4030_init_chip(codec);
1407
1408 /* power on device */
1409 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1410
3e8e1952
IM		 1411 snd_soc_add_controls(codec, twl4030_snd_controls,
1412 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1413 twl4030_add_widgets(codec);
1414
968a6025 1415 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1416 if (ret < 0) {
1417 printk(KERN_ERR "twl4030: failed to register card\n");
1418 goto card_err;
1419 }
1420
1421 return ret;
1422
1423card_err:
1424 snd_soc_free_pcms(socdev);
1425 snd_soc_dapm_free(socdev);
1426pcm_err:
1427 kfree(codec->reg_cache);
1428 return ret;
1429}
1430
1431static struct snd_soc_device *twl4030_socdev;
1432
1433static int twl4030_probe(struct platform_device *pdev)
1434{
1435 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1436 struct snd_soc_codec *codec;
7393958f 1437 struct twl4030_priv *twl4030;
cc17557e
SS		 1438
1439 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1440 if (codec == NULL)
1441 return -ENOMEM;
1442
7393958f
PU		 1443 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1444 if (twl4030 == NULL) {
1445 kfree(codec);
1446 return -ENOMEM;
1447 }
1448
1449 codec->private_data = twl4030;
6627a653 1450 socdev->card->codec = codec;
cc17557e
SS		 1451 mutex_init(&codec->mutex);
1452 INIT_LIST_HEAD(&codec->dapm_widgets);
1453 INIT_LIST_HEAD(&codec->dapm_paths);
1454
1455 twl4030_socdev = socdev;
1456 twl4030_init(socdev);
1457
1458 return 0;
1459}
1460
1461static int twl4030_remove(struct platform_device *pdev)
1462{
1463 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1464 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1465
1466 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1467 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1468 snd_soc_free_pcms(socdev);
1469 snd_soc_dapm_free(socdev);
7393958f 1470 kfree(codec->private_data);
cc17557e
SS		 1471 kfree(codec);
1472
1473 return 0;
1474}
1475
1476struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1477 .probe = twl4030_probe,
1478 .remove = twl4030_remove,
1479 .suspend = twl4030_suspend,
1480 .resume = twl4030_resume,
1481};
1482EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1483
24e07db8 1484static int __init twl4030_modinit(void)
64089b84
MB		 1485{
1486 return snd_soc_register_dai(&twl4030_dai);
1487}
24e07db8 1488module_init(twl4030_modinit);
64089b84
MB		 1489
1490static void __exit twl4030_exit(void)
1491{
1492 snd_soc_unregister_dai(&twl4030_dai);
1493}
1494module_exit(twl4030_exit);
1495
cc17557e
SS		 1496MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1497MODULE_AUTHOR("Steve Sakoman");
1498MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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