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cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/i2c/twl4030.h> | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
db04e2c5 | 45 | 0x91, /* REG_CODEC_MODE (0x1) */ |
cc17557e SS |
46 | 0xc3, /* REG_OPTION (0x2) */ |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
5920b453 GI |
49 | 0x20, /* REG_ANAMICL (0x5) */ |
50 | 0x00, /* REG_ANAMICR (0x6) */ | |
51 | 0x00, /* REG_AVADC_CTL (0x7) */ | |
cc17557e SS |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
58 | 0x01, /* REG_AUDIO_IF (0xE) */ | |
59 | 0x00, /* REG_VOICE_IF (0xF) */ | |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
67 | 0x0c, /* REG_AVDAC_CTL (0x17) */ | |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ | |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
71 | 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ | |
72 | 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ | |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
78 | 0x24, /* REG_HS_SEL (0x22) */ | |
79 | 0x0a, /* REG_HS_GAIN_SET (0x23) */ | |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ | |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
102 | 0x16, /* REG_APLL_CTL (0x3A) */ | |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ | |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
f3b5d300 | 118 | 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */ |
cc17557e SS |
119 | }; |
120 | ||
7393958f PU |
121 | /* codec private data */ |
122 | struct twl4030_priv { | |
123 | unsigned int bypass_state; | |
124 | unsigned int codec_powered; | |
125 | unsigned int codec_muted; | |
7220b9f4 PU |
126 | |
127 | struct snd_pcm_substream *master_substream; | |
128 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
129 | |
130 | unsigned int configured; | |
131 | unsigned int rate; | |
132 | unsigned int sample_bits; | |
133 | unsigned int channels; | |
6943c92e PU |
134 | |
135 | unsigned int sysclk; | |
136 | ||
137 | /* Headset output state handling */ | |
138 | unsigned int hsl_enabled; | |
139 | unsigned int hsr_enabled; | |
7393958f PU |
140 | }; |
141 | ||
cc17557e SS |
142 | /* |
143 | * read twl4030 register cache | |
144 | */ | |
145 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
146 | unsigned int reg) | |
147 | { | |
d08664fd | 148 | u8 *cache = codec->reg_cache; |
cc17557e | 149 | |
91432e97 IM |
150 | if (reg >= TWL4030_CACHEREGNUM) |
151 | return -EIO; | |
152 | ||
cc17557e SS |
153 | return cache[reg]; |
154 | } | |
155 | ||
156 | /* | |
157 | * write twl4030 register cache | |
158 | */ | |
159 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
160 | u8 reg, u8 value) | |
161 | { | |
162 | u8 *cache = codec->reg_cache; | |
163 | ||
164 | if (reg >= TWL4030_CACHEREGNUM) | |
165 | return; | |
166 | cache[reg] = value; | |
167 | } | |
168 | ||
169 | /* | |
170 | * write to the twl4030 register space | |
171 | */ | |
172 | static int twl4030_write(struct snd_soc_codec *codec, | |
173 | unsigned int reg, unsigned int value) | |
174 | { | |
175 | twl4030_write_reg_cache(codec, reg, value); | |
f3b5d300 PU |
176 | if (likely(reg < TWL4030_REG_SW_SHADOW)) |
177 | return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, | |
178 | reg); | |
179 | else | |
180 | return 0; | |
cc17557e SS |
181 | } |
182 | ||
db04e2c5 | 183 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 184 | { |
7393958f | 185 | struct twl4030_priv *twl4030 = codec->private_data; |
cc17557e SS |
186 | u8 mode; |
187 | ||
7393958f PU |
188 | if (enable == twl4030->codec_powered) |
189 | return; | |
190 | ||
cc17557e | 191 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); |
db04e2c5 PU |
192 | if (enable) |
193 | mode |= TWL4030_CODECPDZ; | |
194 | else | |
195 | mode &= ~TWL4030_CODECPDZ; | |
cc17557e | 196 | |
db04e2c5 | 197 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
7393958f | 198 | twl4030->codec_powered = enable; |
cc17557e SS |
199 | |
200 | /* REVISIT: this delay is present in TI sample drivers */ | |
201 | /* but there seems to be no TRM requirement for it */ | |
202 | udelay(10); | |
203 | } | |
204 | ||
205 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
206 | { | |
16a30fbb | 207 | u8 *cache = codec->reg_cache; |
cc17557e SS |
208 | int i; |
209 | ||
210 | /* clear CODECPDZ prior to setting register defaults */ | |
db04e2c5 | 211 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
212 | |
213 | /* set all audio section registers to reasonable defaults */ | |
214 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
16a30fbb | 215 | twl4030_write(codec, i, cache[i]); |
cc17557e SS |
216 | |
217 | } | |
218 | ||
7393958f PU |
219 | static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute) |
220 | { | |
221 | struct twl4030_priv *twl4030 = codec->private_data; | |
222 | u8 reg_val; | |
223 | ||
224 | if (mute == twl4030->codec_muted) | |
225 | return; | |
226 | ||
227 | if (mute) { | |
228 | /* Bypass the reg_cache and mute the volumes | |
229 | * Headset mute is done in it's own event handler | |
230 | * Things to mute: Earpiece, PreDrivL/R, CarkitL/R | |
231 | */ | |
232 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL); | |
233 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
234 | reg_val & (~TWL4030_EAR_GAIN), | |
235 | TWL4030_REG_EAR_CTL); | |
236 | ||
237 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL); | |
238 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
239 | reg_val & (~TWL4030_PREDL_GAIN), | |
240 | TWL4030_REG_PREDL_CTL); | |
241 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL); | |
242 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
243 | reg_val & (~TWL4030_PREDR_GAIN), | |
244 | TWL4030_REG_PREDL_CTL); | |
245 | ||
246 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL); | |
247 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
248 | reg_val & (~TWL4030_PRECKL_GAIN), | |
249 | TWL4030_REG_PRECKL_CTL); | |
250 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL); | |
251 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
c198d811 | 252 | reg_val & (~TWL4030_PRECKR_GAIN), |
7393958f PU |
253 | TWL4030_REG_PRECKR_CTL); |
254 | ||
255 | /* Disable PLL */ | |
256 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); | |
257 | reg_val &= ~TWL4030_APLL_EN; | |
258 | twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); | |
259 | } else { | |
260 | /* Restore the volumes | |
261 | * Headset mute is done in it's own event handler | |
262 | * Things to restore: Earpiece, PreDrivL/R, CarkitL/R | |
263 | */ | |
264 | twl4030_write(codec, TWL4030_REG_EAR_CTL, | |
265 | twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL)); | |
266 | ||
267 | twl4030_write(codec, TWL4030_REG_PREDL_CTL, | |
268 | twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL)); | |
269 | twl4030_write(codec, TWL4030_REG_PREDR_CTL, | |
270 | twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL)); | |
271 | ||
272 | twl4030_write(codec, TWL4030_REG_PRECKL_CTL, | |
273 | twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL)); | |
274 | twl4030_write(codec, TWL4030_REG_PRECKR_CTL, | |
275 | twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL)); | |
276 | ||
277 | /* Enable PLL */ | |
278 | reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); | |
279 | reg_val |= TWL4030_APLL_EN; | |
280 | twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); | |
281 | } | |
282 | ||
283 | twl4030->codec_muted = mute; | |
284 | } | |
285 | ||
006f367e PU |
286 | static void twl4030_power_up(struct snd_soc_codec *codec) |
287 | { | |
7393958f | 288 | struct twl4030_priv *twl4030 = codec->private_data; |
006f367e PU |
289 | u8 anamicl, regmisc1, byte; |
290 | int i = 0; | |
291 | ||
7393958f PU |
292 | if (twl4030->codec_powered) |
293 | return; | |
294 | ||
006f367e PU |
295 | /* set CODECPDZ to turn on codec */ |
296 | twl4030_codec_enable(codec, 1); | |
297 | ||
298 | /* initiate offset cancellation */ | |
299 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
300 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
301 | anamicl | TWL4030_CNCL_OFFSET_START); | |
302 | ||
303 | /* wait for offset cancellation to complete */ | |
304 | do { | |
305 | /* this takes a little while, so don't slam i2c */ | |
306 | udelay(2000); | |
307 | twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, | |
308 | TWL4030_REG_ANAMICL); | |
309 | } while ((i++ < 100) && | |
310 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
311 | TWL4030_CNCL_OFFSET_START)); | |
312 | ||
313 | /* Make sure that the reg_cache has the same value as the HW */ | |
314 | twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); | |
315 | ||
316 | /* anti-pop when changing analog gain */ | |
317 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
318 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
319 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
320 | ||
321 | /* toggle CODECPDZ as per TRM */ | |
322 | twl4030_codec_enable(codec, 0); | |
323 | twl4030_codec_enable(codec, 1); | |
324 | } | |
325 | ||
7393958f PU |
326 | /* |
327 | * Unconditional power down | |
328 | */ | |
006f367e PU |
329 | static void twl4030_power_down(struct snd_soc_codec *codec) |
330 | { | |
331 | /* power down */ | |
332 | twl4030_codec_enable(codec, 0); | |
333 | } | |
334 | ||
5e98a464 | 335 | /* Earpiece */ |
1a787e7a JS |
336 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
337 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
338 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
339 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
340 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
341 | }; | |
5e98a464 | 342 | |
2a6f5c58 | 343 | /* PreDrive Left */ |
1a787e7a JS |
344 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
345 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
346 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
347 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
348 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
349 | }; | |
2a6f5c58 PU |
350 | |
351 | /* PreDrive Right */ | |
1a787e7a JS |
352 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
353 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
354 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
355 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
356 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
357 | }; | |
2a6f5c58 | 358 | |
dfad21a2 | 359 | /* Headset Left */ |
1a787e7a JS |
360 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
361 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
362 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
363 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
364 | }; | |
dfad21a2 PU |
365 | |
366 | /* Headset Right */ | |
1a787e7a JS |
367 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
368 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
369 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
370 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
371 | }; | |
dfad21a2 | 372 | |
5152d8c2 | 373 | /* Carkit Left */ |
1a787e7a JS |
374 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
375 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
376 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
377 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
378 | }; | |
5152d8c2 PU |
379 | |
380 | /* Carkit Right */ | |
1a787e7a JS |
381 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
382 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
383 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
384 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
385 | }; | |
5152d8c2 | 386 | |
df339804 PU |
387 | /* Handsfree Left */ |
388 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 389 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 PU |
390 | |
391 | static const struct soc_enum twl4030_handsfreel_enum = | |
392 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
393 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
394 | twl4030_handsfreel_texts); | |
395 | ||
396 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
397 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
398 | ||
0f89bdca PU |
399 | /* Handsfree Left virtual mute */ |
400 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
401 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0); | |
402 | ||
df339804 PU |
403 | /* Handsfree Right */ |
404 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 405 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 PU |
406 | |
407 | static const struct soc_enum twl4030_handsfreer_enum = | |
408 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
409 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
410 | twl4030_handsfreer_texts); | |
411 | ||
412 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
413 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
414 | ||
0f89bdca PU |
415 | /* Handsfree Right virtual mute */ |
416 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
417 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0); | |
418 | ||
376f7839 PU |
419 | /* Vibra */ |
420 | /* Vibra audio path selection */ | |
421 | static const char *twl4030_vibra_texts[] = | |
422 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
423 | ||
424 | static const struct soc_enum twl4030_vibra_enum = | |
425 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, | |
426 | ARRAY_SIZE(twl4030_vibra_texts), | |
427 | twl4030_vibra_texts); | |
428 | ||
429 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
430 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
431 | ||
432 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
433 | static const char *twl4030_vibrapath_texts[] = | |
434 | {"Local vibrator", "Audio"}; | |
435 | ||
436 | static const struct soc_enum twl4030_vibrapath_enum = | |
437 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, | |
438 | ARRAY_SIZE(twl4030_vibrapath_texts), | |
439 | twl4030_vibrapath_texts); | |
440 | ||
441 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
442 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
443 | ||
276c6222 | 444 | /* Left analog microphone selection */ |
97b8096d JS |
445 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
446 | SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0), | |
447 | SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0), | |
448 | SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0), | |
449 | SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0), | |
450 | }; | |
276c6222 PU |
451 | |
452 | /* Right analog microphone selection */ | |
97b8096d JS |
453 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
454 | SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0), | |
181da78c | 455 | SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0), |
97b8096d | 456 | }; |
276c6222 PU |
457 | |
458 | /* TX1 L/R Analog/Digital microphone selection */ | |
459 | static const char *twl4030_micpathtx1_texts[] = | |
460 | {"Analog", "Digimic0"}; | |
461 | ||
462 | static const struct soc_enum twl4030_micpathtx1_enum = | |
463 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
464 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
465 | twl4030_micpathtx1_texts); | |
466 | ||
467 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
468 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
469 | ||
470 | /* TX2 L/R Analog/Digital microphone selection */ | |
471 | static const char *twl4030_micpathtx2_texts[] = | |
472 | {"Analog", "Digimic1"}; | |
473 | ||
474 | static const struct soc_enum twl4030_micpathtx2_enum = | |
475 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
476 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
477 | twl4030_micpathtx2_texts); | |
478 | ||
479 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
480 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
481 | ||
7393958f PU |
482 | /* Analog bypass for AudioR1 */ |
483 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
484 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
485 | ||
486 | /* Analog bypass for AudioL1 */ | |
487 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
488 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
489 | ||
490 | /* Analog bypass for AudioR2 */ | |
491 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
492 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
493 | ||
494 | /* Analog bypass for AudioL2 */ | |
495 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
496 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
497 | ||
fcd274a3 LCM |
498 | /* Analog bypass for Voice */ |
499 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
500 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
501 | ||
6bab83fd PU |
502 | /* Digital bypass gain, 0 mutes the bypass */ |
503 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { | |
504 | TLV_DB_RANGE_HEAD(2), | |
505 | 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), | |
506 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), | |
507 | }; | |
508 | ||
509 | /* Digital bypass left (TX1L -> RX2L) */ | |
510 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
511 | SOC_DAPM_SINGLE_TLV("Volume", | |
512 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
513 | twl4030_dapm_dbypass_tlv); | |
514 | ||
515 | /* Digital bypass right (TX1R -> RX2R) */ | |
516 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
517 | SOC_DAPM_SINGLE_TLV("Volume", | |
518 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
519 | twl4030_dapm_dbypass_tlv); | |
520 | ||
ee8f6894 LCM |
521 | /* |
522 | * Voice Sidetone GAIN volume control: | |
523 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
524 | */ | |
525 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
526 | ||
527 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
528 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
529 | SOC_DAPM_SINGLE_TLV("Volume", | |
530 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
531 | twl4030_dapm_dbypassv_tlv); | |
532 | ||
276c6222 PU |
533 | static int micpath_event(struct snd_soc_dapm_widget *w, |
534 | struct snd_kcontrol *kcontrol, int event) | |
535 | { | |
536 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
537 | unsigned char adcmicsel, micbias_ctl; | |
538 | ||
539 | adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); | |
540 | micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); | |
541 | /* Prepare the bits for the given TX path: | |
542 | * shift_l == 0: TX1 microphone path | |
543 | * shift_l == 2: TX2 microphone path */ | |
544 | if (e->shift_l) { | |
545 | /* TX2 microphone path */ | |
546 | if (adcmicsel & TWL4030_TX2IN_SEL) | |
547 | micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ | |
548 | else | |
549 | micbias_ctl &= ~TWL4030_MICBIAS2_CTL; | |
550 | } else { | |
551 | /* TX1 microphone path */ | |
552 | if (adcmicsel & TWL4030_TX1IN_SEL) | |
553 | micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ | |
554 | else | |
555 | micbias_ctl &= ~TWL4030_MICBIAS1_CTL; | |
556 | } | |
557 | ||
558 | twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
5a2e9a48 | 563 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 564 | { |
49d92c7d SM |
565 | unsigned char hs_ctl; |
566 | ||
5a2e9a48 | 567 | hs_ctl = twl4030_read_reg_cache(codec, reg); |
49d92c7d | 568 | |
5a2e9a48 PU |
569 | if (ramp) { |
570 | /* HF ramp-up */ | |
571 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
572 | twl4030_write(codec, reg, hs_ctl); | |
573 | udelay(10); | |
49d92c7d | 574 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
575 | twl4030_write(codec, reg, hs_ctl); |
576 | udelay(40); | |
49d92c7d | 577 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 578 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 579 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 580 | } else { |
5a2e9a48 PU |
581 | /* HF ramp-down */ |
582 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
583 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
584 | twl4030_write(codec, reg, hs_ctl); | |
585 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
586 | twl4030_write(codec, reg, hs_ctl); | |
587 | udelay(40); | |
588 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
589 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 590 | } |
5a2e9a48 | 591 | } |
49d92c7d | 592 | |
5a2e9a48 PU |
593 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
594 | struct snd_kcontrol *kcontrol, int event) | |
595 | { | |
596 | switch (event) { | |
597 | case SND_SOC_DAPM_POST_PMU: | |
598 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); | |
599 | break; | |
600 | case SND_SOC_DAPM_POST_PMD: | |
601 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); | |
602 | break; | |
603 | } | |
604 | return 0; | |
605 | } | |
606 | ||
607 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
608 | struct snd_kcontrol *kcontrol, int event) | |
609 | { | |
610 | switch (event) { | |
611 | case SND_SOC_DAPM_POST_PMU: | |
612 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); | |
613 | break; | |
614 | case SND_SOC_DAPM_POST_PMD: | |
615 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); | |
616 | break; | |
617 | } | |
49d92c7d SM |
618 | return 0; |
619 | } | |
620 | ||
6943c92e | 621 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 PU |
622 | { |
623 | unsigned char hs_gain, hs_pop; | |
6943c92e PU |
624 | struct twl4030_priv *twl4030 = codec->private_data; |
625 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ | |
626 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
627 | 8388608, 16777216, 33554432, 67108864}; | |
aad749e5 | 628 | |
6943c92e PU |
629 | hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); |
630 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
aad749e5 | 631 | |
6943c92e PU |
632 | if (ramp) { |
633 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 634 | hs_pop |= TWL4030_VMID_EN; |
6943c92e PU |
635 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
636 | twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain); | |
aad749e5 | 637 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e PU |
638 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
639 | } else { | |
640 | /* Headset ramp-down _not_ according to | |
641 | * the TRM, but in a way that it is working */ | |
aad749e5 | 642 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
643 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
644 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
645 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
646 | twl4030->sysclk) + 1); | |
aad749e5 PU |
647 | /* Bypass the reg_cache to mute the headset */ |
648 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
649 | hs_gain & (~0x0f), | |
650 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 651 | |
aad749e5 | 652 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
653 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
654 | } | |
655 | } | |
656 | ||
657 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
658 | struct snd_kcontrol *kcontrol, int event) | |
659 | { | |
660 | struct twl4030_priv *twl4030 = w->codec->private_data; | |
661 | ||
662 | switch (event) { | |
663 | case SND_SOC_DAPM_POST_PMU: | |
664 | /* Do the ramp-up only once */ | |
665 | if (!twl4030->hsr_enabled) | |
666 | headset_ramp(w->codec, 1); | |
667 | ||
668 | twl4030->hsl_enabled = 1; | |
669 | break; | |
670 | case SND_SOC_DAPM_POST_PMD: | |
671 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
672 | if (!twl4030->hsr_enabled) | |
673 | headset_ramp(w->codec, 0); | |
674 | ||
675 | twl4030->hsl_enabled = 0; | |
676 | break; | |
677 | } | |
678 | return 0; | |
679 | } | |
680 | ||
681 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
682 | struct snd_kcontrol *kcontrol, int event) | |
683 | { | |
684 | struct twl4030_priv *twl4030 = w->codec->private_data; | |
685 | ||
686 | switch (event) { | |
687 | case SND_SOC_DAPM_POST_PMU: | |
688 | /* Do the ramp-up only once */ | |
689 | if (!twl4030->hsl_enabled) | |
690 | headset_ramp(w->codec, 1); | |
691 | ||
692 | twl4030->hsr_enabled = 1; | |
693 | break; | |
694 | case SND_SOC_DAPM_POST_PMD: | |
695 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
696 | if (!twl4030->hsl_enabled) | |
697 | headset_ramp(w->codec, 0); | |
698 | ||
699 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
700 | break; |
701 | } | |
702 | return 0; | |
703 | } | |
704 | ||
7393958f PU |
705 | static int bypass_event(struct snd_soc_dapm_widget *w, |
706 | struct snd_kcontrol *kcontrol, int event) | |
707 | { | |
708 | struct soc_mixer_control *m = | |
709 | (struct soc_mixer_control *)w->kcontrols->private_value; | |
710 | struct twl4030_priv *twl4030 = w->codec->private_data; | |
fcd274a3 | 711 | unsigned char reg, misc; |
7393958f PU |
712 | |
713 | reg = twl4030_read_reg_cache(w->codec, m->reg); | |
6bab83fd PU |
714 | |
715 | if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) { | |
716 | /* Analog bypass */ | |
717 | if (reg & (1 << m->shift)) | |
718 | twl4030->bypass_state |= | |
719 | (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); | |
720 | else | |
721 | twl4030->bypass_state &= | |
722 | ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); | |
fcd274a3 LCM |
723 | } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) { |
724 | /* Analog voice bypass */ | |
725 | if (reg & (1 << m->shift)) | |
726 | twl4030->bypass_state |= (1 << 4); | |
727 | else | |
728 | twl4030->bypass_state &= ~(1 << 4); | |
ee8f6894 LCM |
729 | } else if (m->reg == TWL4030_REG_VSTPGA) { |
730 | /* Voice digital bypass */ | |
731 | if (reg) | |
732 | twl4030->bypass_state |= (1 << 5); | |
733 | else | |
734 | twl4030->bypass_state &= ~(1 << 5); | |
6bab83fd PU |
735 | } else { |
736 | /* Digital bypass */ | |
737 | if (reg & (0x7 << m->shift)) | |
ee8f6894 | 738 | twl4030->bypass_state |= (1 << (m->shift ? 7 : 6)); |
6bab83fd | 739 | else |
ee8f6894 | 740 | twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6)); |
6bab83fd | 741 | } |
7393958f | 742 | |
fcd274a3 LCM |
743 | /* Enable master analog loopback mode if any analog switch is enabled*/ |
744 | misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1); | |
745 | if (twl4030->bypass_state & 0x1F) | |
746 | misc |= TWL4030_FMLOOP_EN; | |
747 | else | |
748 | misc &= ~TWL4030_FMLOOP_EN; | |
749 | twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc); | |
750 | ||
7393958f PU |
751 | if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) { |
752 | if (twl4030->bypass_state) | |
753 | twl4030_codec_mute(w->codec, 0); | |
754 | else | |
755 | twl4030_codec_mute(w->codec, 1); | |
756 | } | |
757 | return 0; | |
758 | } | |
759 | ||
b0bd53a7 PU |
760 | /* |
761 | * Some of the gain controls in TWL (mostly those which are associated with | |
762 | * the outputs) are implemented in an interesting way: | |
763 | * 0x0 : Power down (mute) | |
764 | * 0x1 : 6dB | |
765 | * 0x2 : 0 dB | |
766 | * 0x3 : -6 dB | |
767 | * Inverting not going to help with these. | |
768 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
769 | */ | |
770 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
771 | xinvert, tlv_array) \ | |
772 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
773 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
774 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
775 | .tlv.p = (tlv_array), \ | |
776 | .info = snd_soc_info_volsw, \ | |
777 | .get = snd_soc_get_volsw_twl4030, \ | |
778 | .put = snd_soc_put_volsw_twl4030, \ | |
779 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
780 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
781 | .max = xmax, .invert = xinvert} } | |
782 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
783 | xinvert, tlv_array) \ | |
784 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
785 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
786 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
787 | .tlv.p = (tlv_array), \ | |
788 | .info = snd_soc_info_volsw_2r, \ | |
789 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
790 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
791 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
792 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
64089b84 | 793 | .rshift = xshift, .max = xmax, .invert = xinvert} } |
b0bd53a7 PU |
794 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ |
795 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
796 | xinvert, tlv_array) | |
797 | ||
798 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
799 | struct snd_ctl_elem_value *ucontrol) | |
800 | { | |
801 | struct soc_mixer_control *mc = | |
802 | (struct soc_mixer_control *)kcontrol->private_value; | |
803 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
804 | unsigned int reg = mc->reg; | |
805 | unsigned int shift = mc->shift; | |
806 | unsigned int rshift = mc->rshift; | |
807 | int max = mc->max; | |
808 | int mask = (1 << fls(max)) - 1; | |
809 | ||
810 | ucontrol->value.integer.value[0] = | |
811 | (snd_soc_read(codec, reg) >> shift) & mask; | |
812 | if (ucontrol->value.integer.value[0]) | |
813 | ucontrol->value.integer.value[0] = | |
814 | max + 1 - ucontrol->value.integer.value[0]; | |
815 | ||
816 | if (shift != rshift) { | |
817 | ucontrol->value.integer.value[1] = | |
818 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
819 | if (ucontrol->value.integer.value[1]) | |
820 | ucontrol->value.integer.value[1] = | |
821 | max + 1 - ucontrol->value.integer.value[1]; | |
822 | } | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
828 | struct snd_ctl_elem_value *ucontrol) | |
829 | { | |
830 | struct soc_mixer_control *mc = | |
831 | (struct soc_mixer_control *)kcontrol->private_value; | |
832 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
833 | unsigned int reg = mc->reg; | |
834 | unsigned int shift = mc->shift; | |
835 | unsigned int rshift = mc->rshift; | |
836 | int max = mc->max; | |
837 | int mask = (1 << fls(max)) - 1; | |
838 | unsigned short val, val2, val_mask; | |
839 | ||
840 | val = (ucontrol->value.integer.value[0] & mask); | |
841 | ||
842 | val_mask = mask << shift; | |
843 | if (val) | |
844 | val = max + 1 - val; | |
845 | val = val << shift; | |
846 | if (shift != rshift) { | |
847 | val2 = (ucontrol->value.integer.value[1] & mask); | |
848 | val_mask |= mask << rshift; | |
849 | if (val2) | |
850 | val2 = max + 1 - val2; | |
851 | val |= val2 << rshift; | |
852 | } | |
853 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
854 | } | |
855 | ||
856 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
857 | struct snd_ctl_elem_value *ucontrol) | |
858 | { | |
859 | struct soc_mixer_control *mc = | |
860 | (struct soc_mixer_control *)kcontrol->private_value; | |
861 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
862 | unsigned int reg = mc->reg; | |
863 | unsigned int reg2 = mc->rreg; | |
864 | unsigned int shift = mc->shift; | |
865 | int max = mc->max; | |
866 | int mask = (1<<fls(max))-1; | |
867 | ||
868 | ucontrol->value.integer.value[0] = | |
869 | (snd_soc_read(codec, reg) >> shift) & mask; | |
870 | ucontrol->value.integer.value[1] = | |
871 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
872 | ||
873 | if (ucontrol->value.integer.value[0]) | |
874 | ucontrol->value.integer.value[0] = | |
875 | max + 1 - ucontrol->value.integer.value[0]; | |
876 | if (ucontrol->value.integer.value[1]) | |
877 | ucontrol->value.integer.value[1] = | |
878 | max + 1 - ucontrol->value.integer.value[1]; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
884 | struct snd_ctl_elem_value *ucontrol) | |
885 | { | |
886 | struct soc_mixer_control *mc = | |
887 | (struct soc_mixer_control *)kcontrol->private_value; | |
888 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
889 | unsigned int reg = mc->reg; | |
890 | unsigned int reg2 = mc->rreg; | |
891 | unsigned int shift = mc->shift; | |
892 | int max = mc->max; | |
893 | int mask = (1 << fls(max)) - 1; | |
894 | int err; | |
895 | unsigned short val, val2, val_mask; | |
896 | ||
897 | val_mask = mask << shift; | |
898 | val = (ucontrol->value.integer.value[0] & mask); | |
899 | val2 = (ucontrol->value.integer.value[1] & mask); | |
900 | ||
901 | if (val) | |
902 | val = max + 1 - val; | |
903 | if (val2) | |
904 | val2 = max + 1 - val2; | |
905 | ||
906 | val = val << shift; | |
907 | val2 = val2 << shift; | |
908 | ||
909 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
910 | if (err < 0) | |
911 | return err; | |
912 | ||
913 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
914 | return err; | |
915 | } | |
916 | ||
b74bd40f LCM |
917 | /* Codec operation modes */ |
918 | static const char *twl4030_op_modes_texts[] = { | |
919 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
920 | }; | |
921 | ||
922 | static const struct soc_enum twl4030_op_modes_enum = | |
923 | SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, | |
924 | ARRAY_SIZE(twl4030_op_modes_texts), | |
925 | twl4030_op_modes_texts); | |
926 | ||
423c238d | 927 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
928 | struct snd_ctl_elem_value *ucontrol) |
929 | { | |
930 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
931 | struct twl4030_priv *twl4030 = codec->private_data; | |
932 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
933 | unsigned short val; | |
934 | unsigned short mask, bitmask; | |
935 | ||
936 | if (twl4030->configured) { | |
937 | printk(KERN_ERR "twl4030 operation mode cannot be " | |
938 | "changed on-the-fly\n"); | |
939 | return -EBUSY; | |
940 | } | |
941 | ||
942 | for (bitmask = 1; bitmask < e->max; bitmask <<= 1) | |
943 | ; | |
944 | if (ucontrol->value.enumerated.item[0] > e->max - 1) | |
945 | return -EINVAL; | |
946 | ||
947 | val = ucontrol->value.enumerated.item[0] << e->shift_l; | |
948 | mask = (bitmask - 1) << e->shift_l; | |
949 | if (e->shift_l != e->shift_r) { | |
950 | if (ucontrol->value.enumerated.item[1] > e->max - 1) | |
951 | return -EINVAL; | |
952 | val |= ucontrol->value.enumerated.item[1] << e->shift_r; | |
953 | mask |= (bitmask - 1) << e->shift_r; | |
954 | } | |
955 | ||
956 | return snd_soc_update_bits(codec, e->reg, mask, val); | |
957 | } | |
958 | ||
c10b82cf PU |
959 | /* |
960 | * FGAIN volume control: | |
961 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
962 | */ | |
d889a72c | 963 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 964 | |
0d33ea0b PU |
965 | /* |
966 | * CGAIN volume control: | |
967 | * 0 dB to 12 dB in 6 dB steps | |
968 | * value 2 and 3 means 12 dB | |
969 | */ | |
d889a72c PU |
970 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
971 | ||
1a787e7a JS |
972 | /* |
973 | * Voice Downlink GAIN volume control: | |
974 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
975 | */ | |
976 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
977 | ||
d889a72c PU |
978 | /* |
979 | * Analog playback gain | |
980 | * -24 dB to 12 dB in 2 dB steps | |
981 | */ | |
982 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 983 | |
4290239c PU |
984 | /* |
985 | * Gain controls tied to outputs | |
986 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
987 | */ | |
988 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
989 | ||
18cc8d8d JS |
990 | /* |
991 | * Gain control for earpiece amplifier | |
992 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
993 | */ | |
994 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
995 | ||
381a22b5 PU |
996 | /* |
997 | * Capture gain after the ADCs | |
998 | * from 0 dB to 31 dB in 1 dB steps | |
999 | */ | |
1000 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
1001 | ||
5920b453 GI |
1002 | /* |
1003 | * Gain control for input amplifiers | |
1004 | * 0 dB to 30 dB in 6 dB steps | |
1005 | */ | |
1006 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
1007 | ||
89492be8 PU |
1008 | static const char *twl4030_rampdelay_texts[] = { |
1009 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1010 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1011 | "3495/2581/1748 ms" | |
1012 | }; | |
1013 | ||
1014 | static const struct soc_enum twl4030_rampdelay_enum = | |
1015 | SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, | |
1016 | ARRAY_SIZE(twl4030_rampdelay_texts), | |
1017 | twl4030_rampdelay_texts); | |
1018 | ||
376f7839 PU |
1019 | /* Vibra H-bridge direction mode */ |
1020 | static const char *twl4030_vibradirmode_texts[] = { | |
1021 | "Vibra H-bridge direction", "Audio data MSB", | |
1022 | }; | |
1023 | ||
1024 | static const struct soc_enum twl4030_vibradirmode_enum = | |
1025 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, | |
1026 | ARRAY_SIZE(twl4030_vibradirmode_texts), | |
1027 | twl4030_vibradirmode_texts); | |
1028 | ||
1029 | /* Vibra H-bridge direction */ | |
1030 | static const char *twl4030_vibradir_texts[] = { | |
1031 | "Positive polarity", "Negative polarity", | |
1032 | }; | |
1033 | ||
1034 | static const struct soc_enum twl4030_vibradir_enum = | |
1035 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, | |
1036 | ARRAY_SIZE(twl4030_vibradir_texts), | |
1037 | twl4030_vibradir_texts); | |
1038 | ||
cc17557e | 1039 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1040 | /* Codec operation mode control */ |
1041 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1042 | snd_soc_get_enum_double, | |
1043 | snd_soc_put_twl4030_opmode_enum_double), | |
1044 | ||
d889a72c PU |
1045 | /* Common playback gain controls */ |
1046 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1047 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1048 | 0, 0x3f, 0, digital_fine_tlv), | |
1049 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1050 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1051 | 0, 0x3f, 0, digital_fine_tlv), | |
1052 | ||
1053 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1054 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1055 | 6, 0x2, 0, digital_coarse_tlv), | |
1056 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1057 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1058 | 6, 0x2, 0, digital_coarse_tlv), | |
1059 | ||
1060 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1061 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1062 | 3, 0x12, 1, analog_tlv), | |
1063 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1064 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1065 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1066 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1067 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1068 | 1, 1, 0), | |
1069 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1070 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1071 | 1, 1, 0), | |
381a22b5 | 1072 | |
1a787e7a JS |
1073 | /* Common voice downlink gain controls */ |
1074 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1075 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1076 | ||
1077 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1078 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1079 | ||
1080 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1081 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1082 | ||
4290239c PU |
1083 | /* Separate output gain controls */ |
1084 | SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", | |
1085 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, | |
1086 | 4, 3, 0, output_tvl), | |
1087 | ||
1088 | SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", | |
1089 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), | |
1090 | ||
1091 | SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", | |
1092 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, | |
1093 | 4, 3, 0, output_tvl), | |
1094 | ||
1095 | SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", | |
18cc8d8d | 1096 | TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl), |
4290239c | 1097 | |
381a22b5 | 1098 | /* Common capture gain controls */ |
276c6222 | 1099 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1100 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1101 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1102 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1103 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1104 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1105 | |
276c6222 | 1106 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1107 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 PU |
1108 | |
1109 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), | |
376f7839 PU |
1110 | |
1111 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1112 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
cc17557e SS |
1113 | }; |
1114 | ||
cc17557e | 1115 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1116 | /* Left channel inputs */ |
1117 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1118 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1119 | SND_SOC_DAPM_INPUT("AUXL"), | |
1120 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1121 | /* Right channel inputs */ | |
1122 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1123 | SND_SOC_DAPM_INPUT("AUXR"), | |
1124 | /* Digital microphones (Stereo) */ | |
1125 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1126 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1127 | ||
1128 | /* Outputs */ | |
cc17557e SS |
1129 | SND_SOC_DAPM_OUTPUT("OUTL"), |
1130 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
5e98a464 | 1131 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1132 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1133 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1134 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1135 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1136 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1137 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1138 | SND_SOC_DAPM_OUTPUT("HFL"), |
1139 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1140 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1141 | |
53b5047d | 1142 | /* DACs */ |
b4852b79 | 1143 | SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback", |
7393958f | 1144 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1145 | SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback", |
7393958f | 1146 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1147 | SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback", |
7393958f | 1148 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1149 | SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback", |
7393958f | 1150 | SND_SOC_NOPM, 0, 0), |
1a787e7a | 1151 | SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback", |
fcd274a3 | 1152 | SND_SOC_NOPM, 0, 0), |
cc17557e | 1153 | |
7393958f PU |
1154 | /* Analog bypasses */ |
1155 | SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1156 | &twl4030_dapm_abypassr1_control, bypass_event, | |
1157 | SND_SOC_DAPM_POST_REG), | |
1158 | SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1159 | &twl4030_dapm_abypassl1_control, | |
1160 | bypass_event, SND_SOC_DAPM_POST_REG), | |
1161 | SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1162 | &twl4030_dapm_abypassr2_control, | |
1163 | bypass_event, SND_SOC_DAPM_POST_REG), | |
1164 | SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1165 | &twl4030_dapm_abypassl2_control, | |
1166 | bypass_event, SND_SOC_DAPM_POST_REG), | |
fcd274a3 LCM |
1167 | SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, |
1168 | &twl4030_dapm_abypassv_control, | |
1169 | bypass_event, SND_SOC_DAPM_POST_REG), | |
7393958f | 1170 | |
6bab83fd PU |
1171 | /* Digital bypasses */ |
1172 | SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1173 | &twl4030_dapm_dbypassl_control, bypass_event, | |
1174 | SND_SOC_DAPM_POST_REG), | |
1175 | SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1176 | &twl4030_dapm_dbypassr_control, bypass_event, | |
1177 | SND_SOC_DAPM_POST_REG), | |
ee8f6894 LCM |
1178 | SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, |
1179 | &twl4030_dapm_dbypassv_control, bypass_event, | |
1180 | SND_SOC_DAPM_POST_REG), | |
6bab83fd | 1181 | |
4005d39a PU |
1182 | /* Digital mixers, power control for the physical DACs */ |
1183 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1184 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1185 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1186 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1187 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1188 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1189 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1190 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1191 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1192 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1193 | ||
1194 | /* Analog mixers, power control for the physical PGAs */ | |
1195 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1196 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1197 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1198 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1199 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1200 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1201 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1202 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1203 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1204 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1205 | |
1a787e7a | 1206 | /* Output MIXER controls */ |
5e98a464 | 1207 | /* Earpiece */ |
1a787e7a JS |
1208 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1209 | &twl4030_dapm_earpiece_controls[0], | |
1210 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
2a6f5c58 | 1211 | /* PreDrivL/R */ |
1a787e7a JS |
1212 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1213 | &twl4030_dapm_predrivel_controls[0], | |
1214 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
1215 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, | |
1216 | &twl4030_dapm_predriver_controls[0], | |
1217 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
dfad21a2 | 1218 | /* HeadsetL/R */ |
6943c92e | 1219 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1220 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1221 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1222 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1223 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1224 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1225 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1226 | &twl4030_dapm_hsor_controls[0], | |
1227 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1228 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1229 | 0, 0, NULL, 0, headsetrpga_event, | |
1230 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1231 | /* CarkitL/R */ |
1a787e7a JS |
1232 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1233 | &twl4030_dapm_carkitl_controls[0], | |
1234 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
1235 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, | |
1236 | &twl4030_dapm_carkitr_controls[0], | |
1237 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
1238 | ||
1239 | /* Output MUX controls */ | |
df339804 | 1240 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1241 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1242 | &twl4030_dapm_handsfreel_control), | |
0f89bdca PU |
1243 | SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0, |
1244 | &twl4030_dapm_handsfreelmute_control), | |
5a2e9a48 PU |
1245 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1246 | 0, 0, NULL, 0, handsfreelpga_event, | |
1247 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1248 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1249 | &twl4030_dapm_handsfreer_control), | |
0f89bdca PU |
1250 | SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0, |
1251 | &twl4030_dapm_handsfreermute_control), | |
5a2e9a48 PU |
1252 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1253 | 0, 0, NULL, 0, handsfreerpga_event, | |
1254 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 PU |
1255 | /* Vibra */ |
1256 | SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, | |
1257 | &twl4030_dapm_vibra_control), | |
1258 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, | |
1259 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1260 | |
276c6222 PU |
1261 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1262 | capture */ | |
1263 | SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", | |
1264 | SND_SOC_NOPM, 0, 0), | |
1265 | SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", | |
1266 | SND_SOC_NOPM, 0, 0), | |
1267 | SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", | |
1268 | SND_SOC_NOPM, 0, 0), | |
1269 | SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", | |
1270 | SND_SOC_NOPM, 0, 0), | |
1271 | ||
1272 | /* Analog/Digital mic path selection. | |
1273 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1274 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
1275 | SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, | |
1276 | &twl4030_dapm_micpathtx1_control, micpath_event, | |
1277 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1278 | SND_SOC_DAPM_POST_REG), | |
1279 | SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1280 | &twl4030_dapm_micpathtx2_control, micpath_event, | |
1281 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1282 | SND_SOC_DAPM_POST_REG), | |
1283 | ||
97b8096d JS |
1284 | /* Analog input mixers for the capture amplifiers */ |
1285 | SND_SOC_DAPM_MIXER("Analog Left Capture Route", | |
1286 | TWL4030_REG_ANAMICL, 4, 0, | |
1287 | &twl4030_dapm_analoglmic_controls[0], | |
1288 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
1289 | SND_SOC_DAPM_MIXER("Analog Right Capture Route", | |
1290 | TWL4030_REG_ANAMICR, 4, 0, | |
1291 | &twl4030_dapm_analogrmic_controls[0], | |
1292 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1293 | |
fb2a2f84 PU |
1294 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1295 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1296 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1297 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 PU |
1298 | |
1299 | SND_SOC_DAPM_PGA("Digimic0 Enable", | |
1300 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), | |
1301 | SND_SOC_DAPM_PGA("Digimic1 Enable", | |
1302 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), | |
1303 | ||
1304 | SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), | |
1305 | SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), | |
1306 | SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), | |
7393958f | 1307 | |
cc17557e SS |
1308 | }; |
1309 | ||
1310 | static const struct snd_soc_dapm_route intercon[] = { | |
4005d39a PU |
1311 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1312 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1313 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1314 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1315 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1316 | ||
1317 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, | |
1318 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1319 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1320 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1321 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1322 | |
5e98a464 PU |
1323 | /* Internal playback routings */ |
1324 | /* Earpiece */ | |
4005d39a PU |
1325 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1326 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1327 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1328 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
2a6f5c58 | 1329 | /* PreDrivL */ |
4005d39a PU |
1330 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1331 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1332 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1333 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
2a6f5c58 | 1334 | /* PreDrivR */ |
4005d39a PU |
1335 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1336 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1337 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1338 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
dfad21a2 | 1339 | /* HeadsetL */ |
4005d39a PU |
1340 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1341 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1342 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1343 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1344 | /* HeadsetR */ |
4005d39a PU |
1345 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1346 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1347 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1348 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1349 | /* CarkitL */ |
4005d39a PU |
1350 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1351 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1352 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
5152d8c2 | 1353 | /* CarkitR */ |
4005d39a PU |
1354 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1355 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1356 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
df339804 | 1357 | /* HandsfreeL */ |
4005d39a PU |
1358 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1359 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1360 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1361 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
0f89bdca PU |
1362 | {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"}, |
1363 | {"HandsfreeL PGA", NULL, "HandsfreeL Switch"}, | |
df339804 | 1364 | /* HandsfreeR */ |
4005d39a PU |
1365 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1366 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1367 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1368 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
0f89bdca PU |
1369 | {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"}, |
1370 | {"HandsfreeR PGA", NULL, "HandsfreeR Switch"}, | |
376f7839 PU |
1371 | /* Vibra */ |
1372 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1373 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1374 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1375 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1376 | |
cc17557e | 1377 | /* outputs */ |
4005d39a PU |
1378 | {"OUTL", NULL, "Analog L2 Playback Mixer"}, |
1379 | {"OUTR", NULL, "Analog R2 Playback Mixer"}, | |
1a787e7a JS |
1380 | {"EARPIECE", NULL, "Earpiece Mixer"}, |
1381 | {"PREDRIVEL", NULL, "PredriveL Mixer"}, | |
1382 | {"PREDRIVER", NULL, "PredriveR Mixer"}, | |
6943c92e PU |
1383 | {"HSOL", NULL, "HeadsetL PGA"}, |
1384 | {"HSOR", NULL, "HeadsetR PGA"}, | |
1a787e7a JS |
1385 | {"CARKITL", NULL, "CarkitL Mixer"}, |
1386 | {"CARKITR", NULL, "CarkitR Mixer"}, | |
5a2e9a48 PU |
1387 | {"HFL", NULL, "HandsfreeL PGA"}, |
1388 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1389 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1390 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1391 | |
276c6222 PU |
1392 | /* Capture path */ |
1393 | {"Analog Left Capture Route", "Main mic", "MAINMIC"}, | |
1394 | {"Analog Left Capture Route", "Headset mic", "HSMIC"}, | |
1395 | {"Analog Left Capture Route", "AUXL", "AUXL"}, | |
1396 | {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"}, | |
1397 | ||
1398 | {"Analog Right Capture Route", "Sub mic", "SUBMIC"}, | |
1399 | {"Analog Right Capture Route", "AUXR", "AUXR"}, | |
1400 | ||
fb2a2f84 PU |
1401 | {"ADC Physical Left", NULL, "Analog Left Capture Route"}, |
1402 | {"ADC Physical Right", NULL, "Analog Right Capture Route"}, | |
276c6222 PU |
1403 | |
1404 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1405 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1406 | ||
1407 | /* TX1 Left capture path */ | |
fb2a2f84 | 1408 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1409 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1410 | /* TX1 Right capture path */ | |
fb2a2f84 | 1411 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1412 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1413 | /* TX2 Left capture path */ | |
fb2a2f84 | 1414 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1415 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1416 | /* TX2 Right capture path */ | |
fb2a2f84 | 1417 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1418 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1419 | ||
1420 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1421 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1422 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1423 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1424 | ||
7393958f PU |
1425 | /* Analog bypass routes */ |
1426 | {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"}, | |
1427 | {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"}, | |
1428 | {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"}, | |
1429 | {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"}, | |
fcd274a3 | 1430 | {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"}, |
7393958f PU |
1431 | |
1432 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, | |
1433 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1434 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1435 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1436 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1437 | |
6bab83fd PU |
1438 | /* Digital bypass routes */ |
1439 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1440 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1441 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1442 | |
4005d39a PU |
1443 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1444 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1445 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1446 | |
cc17557e SS |
1447 | }; |
1448 | ||
1449 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
1450 | { | |
1451 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
1452 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
1453 | ||
1454 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
1455 | ||
1456 | snd_soc_dapm_new_widgets(codec); | |
1457 | return 0; | |
1458 | } | |
1459 | ||
cc17557e SS |
1460 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1461 | enum snd_soc_bias_level level) | |
1462 | { | |
7393958f PU |
1463 | struct twl4030_priv *twl4030 = codec->private_data; |
1464 | ||
cc17557e SS |
1465 | switch (level) { |
1466 | case SND_SOC_BIAS_ON: | |
7393958f | 1467 | twl4030_codec_mute(codec, 0); |
cc17557e SS |
1468 | break; |
1469 | case SND_SOC_BIAS_PREPARE: | |
7393958f PU |
1470 | twl4030_power_up(codec); |
1471 | if (twl4030->bypass_state) | |
1472 | twl4030_codec_mute(codec, 0); | |
1473 | else | |
1474 | twl4030_codec_mute(codec, 1); | |
cc17557e SS |
1475 | break; |
1476 | case SND_SOC_BIAS_STANDBY: | |
7393958f PU |
1477 | twl4030_power_up(codec); |
1478 | if (twl4030->bypass_state) | |
1479 | twl4030_codec_mute(codec, 0); | |
1480 | else | |
1481 | twl4030_codec_mute(codec, 1); | |
cc17557e SS |
1482 | break; |
1483 | case SND_SOC_BIAS_OFF: | |
1484 | twl4030_power_down(codec); | |
1485 | break; | |
1486 | } | |
1487 | codec->bias_level = level; | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
6b87a91f PU |
1492 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1493 | struct snd_pcm_substream *mst_substream) | |
1494 | { | |
1495 | struct snd_pcm_substream *slv_substream; | |
1496 | ||
1497 | /* Pick the stream, which need to be constrained */ | |
1498 | if (mst_substream == twl4030->master_substream) | |
1499 | slv_substream = twl4030->slave_substream; | |
1500 | else if (mst_substream == twl4030->slave_substream) | |
1501 | slv_substream = twl4030->master_substream; | |
1502 | else /* This should not happen.. */ | |
1503 | return; | |
1504 | ||
1505 | /* Set the constraints according to the already configured stream */ | |
1506 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1507 | SNDRV_PCM_HW_PARAM_RATE, | |
1508 | twl4030->rate, | |
1509 | twl4030->rate); | |
1510 | ||
1511 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1512 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1513 | twl4030->sample_bits, | |
1514 | twl4030->sample_bits); | |
1515 | ||
1516 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1517 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1518 | twl4030->channels, | |
1519 | twl4030->channels); | |
1520 | } | |
1521 | ||
8a1f936a PU |
1522 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1523 | * capture has to be enabled/disabled. */ | |
1524 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
1525 | int enable) | |
1526 | { | |
1527 | u8 reg, mask; | |
1528 | ||
1529 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1530 | ||
1531 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1532 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1533 | else | |
1534 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1535 | ||
1536 | if (enable) | |
1537 | reg |= mask; | |
1538 | else | |
1539 | reg &= ~mask; | |
1540 | ||
1541 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1542 | } | |
1543 | ||
d6648da1 PU |
1544 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1545 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1546 | { |
1547 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1548 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1549 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 PU |
1550 | struct twl4030_priv *twl4030 = codec->private_data; |
1551 | ||
7220b9f4 | 1552 | if (twl4030->master_substream) { |
7220b9f4 | 1553 | twl4030->slave_substream = substream; |
6b87a91f PU |
1554 | /* The DAI has one configuration for playback and capture, so |
1555 | * if the DAI has been already configured then constrain this | |
1556 | * substream to match it. */ | |
1557 | if (twl4030->configured) | |
1558 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1559 | } else { | |
8a1f936a PU |
1560 | if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) & |
1561 | TWL4030_OPTION_1)) { | |
1562 | /* In option2 4 channel is not supported, set the | |
1563 | * constraint for the first stream for channels, the | |
1564 | * second stream will 'inherit' this cosntraint */ | |
1565 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1566 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1567 | 2, 2); | |
1568 | } | |
7220b9f4 | 1569 | twl4030->master_substream = substream; |
6b87a91f | 1570 | } |
7220b9f4 PU |
1571 | |
1572 | return 0; | |
1573 | } | |
1574 | ||
d6648da1 PU |
1575 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1576 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1577 | { |
1578 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1579 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1580 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 PU |
1581 | struct twl4030_priv *twl4030 = codec->private_data; |
1582 | ||
1583 | if (twl4030->master_substream == substream) | |
1584 | twl4030->master_substream = twl4030->slave_substream; | |
1585 | ||
1586 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1587 | |
1588 | /* If all streams are closed, or the remaining stream has not yet | |
1589 | * been configured than set the DAI as not configured. */ | |
1590 | if (!twl4030->master_substream) | |
1591 | twl4030->configured = 0; | |
1592 | else if (!twl4030->master_substream->runtime->channels) | |
1593 | twl4030->configured = 0; | |
8a1f936a PU |
1594 | |
1595 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1596 | if (substream->runtime->channels == 4) | |
1597 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1598 | } |
1599 | ||
cc17557e | 1600 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1601 | struct snd_pcm_hw_params *params, |
1602 | struct snd_soc_dai *dai) | |
cc17557e SS |
1603 | { |
1604 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1605 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1606 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 | 1607 | struct twl4030_priv *twl4030 = codec->private_data; |
cc17557e SS |
1608 | u8 mode, old_mode, format, old_format; |
1609 | ||
8a1f936a PU |
1610 | /* If the substream has 4 channel, do the necessary setup */ |
1611 | if (params_channels(params) == 4) { | |
eaf1ac8b PU |
1612 | format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); |
1613 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
1614 | ||
1615 | /* Safety check: are we in the correct operating mode and | |
1616 | * the interface is in TDM mode? */ | |
1617 | if ((mode & TWL4030_OPTION_1) && | |
1618 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1619 | twl4030_tdm_enable(codec, substream->stream, 1); |
1620 | else | |
1621 | return -EINVAL; | |
1622 | } | |
1623 | ||
6b87a91f PU |
1624 | if (twl4030->configured) |
1625 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1626 | return 0; |
1627 | ||
cc17557e SS |
1628 | /* bit rate */ |
1629 | old_mode = twl4030_read_reg_cache(codec, | |
1630 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
1631 | mode = old_mode & ~TWL4030_APLL_RATE; | |
1632 | ||
1633 | switch (params_rate(params)) { | |
1634 | case 8000: | |
1635 | mode |= TWL4030_APLL_RATE_8000; | |
1636 | break; | |
1637 | case 11025: | |
1638 | mode |= TWL4030_APLL_RATE_11025; | |
1639 | break; | |
1640 | case 12000: | |
1641 | mode |= TWL4030_APLL_RATE_12000; | |
1642 | break; | |
1643 | case 16000: | |
1644 | mode |= TWL4030_APLL_RATE_16000; | |
1645 | break; | |
1646 | case 22050: | |
1647 | mode |= TWL4030_APLL_RATE_22050; | |
1648 | break; | |
1649 | case 24000: | |
1650 | mode |= TWL4030_APLL_RATE_24000; | |
1651 | break; | |
1652 | case 32000: | |
1653 | mode |= TWL4030_APLL_RATE_32000; | |
1654 | break; | |
1655 | case 44100: | |
1656 | mode |= TWL4030_APLL_RATE_44100; | |
1657 | break; | |
1658 | case 48000: | |
1659 | mode |= TWL4030_APLL_RATE_48000; | |
1660 | break; | |
103f211d PU |
1661 | case 96000: |
1662 | mode |= TWL4030_APLL_RATE_96000; | |
1663 | break; | |
cc17557e SS |
1664 | default: |
1665 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
1666 | params_rate(params)); | |
1667 | return -EINVAL; | |
1668 | } | |
1669 | ||
1670 | if (mode != old_mode) { | |
1671 | /* change rate and set CODECPDZ */ | |
7393958f | 1672 | twl4030_codec_enable(codec, 0); |
cc17557e | 1673 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
db04e2c5 | 1674 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1675 | } |
1676 | ||
1677 | /* sample size */ | |
1678 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1679 | format = old_format; | |
1680 | format &= ~TWL4030_DATA_WIDTH; | |
1681 | switch (params_format(params)) { | |
1682 | case SNDRV_PCM_FORMAT_S16_LE: | |
1683 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1684 | break; | |
1685 | case SNDRV_PCM_FORMAT_S24_LE: | |
1686 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
1687 | break; | |
1688 | default: | |
1689 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
1690 | params_format(params)); | |
1691 | return -EINVAL; | |
1692 | } | |
1693 | ||
1694 | if (format != old_format) { | |
1695 | ||
1696 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1697 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1698 | |
1699 | /* change format */ | |
1700 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1701 | ||
1702 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1703 | twl4030_codec_enable(codec, 1); |
cc17557e | 1704 | } |
6b87a91f PU |
1705 | |
1706 | /* Store the important parameters for the DAI configuration and set | |
1707 | * the DAI as configured */ | |
1708 | twl4030->configured = 1; | |
1709 | twl4030->rate = params_rate(params); | |
1710 | twl4030->sample_bits = hw_param_interval(params, | |
1711 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1712 | twl4030->channels = params_channels(params); | |
1713 | ||
1714 | /* If both playback and capture streams are open, and one of them | |
1715 | * is setting the hw parameters right now (since we are here), set | |
1716 | * constraints to the other stream to match the current one. */ | |
1717 | if (twl4030->slave_substream) | |
1718 | twl4030_constraints(twl4030, substream); | |
1719 | ||
cc17557e SS |
1720 | return 0; |
1721 | } | |
1722 | ||
1723 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1724 | int clk_id, unsigned int freq, int dir) | |
1725 | { | |
1726 | struct snd_soc_codec *codec = codec_dai->codec; | |
6943c92e | 1727 | struct twl4030_priv *twl4030 = codec->private_data; |
cc17557e SS |
1728 | u8 infreq; |
1729 | ||
1730 | switch (freq) { | |
1731 | case 19200000: | |
1732 | infreq = TWL4030_APLL_INFREQ_19200KHZ; | |
6943c92e | 1733 | twl4030->sysclk = 19200; |
cc17557e SS |
1734 | break; |
1735 | case 26000000: | |
1736 | infreq = TWL4030_APLL_INFREQ_26000KHZ; | |
6943c92e | 1737 | twl4030->sysclk = 26000; |
cc17557e SS |
1738 | break; |
1739 | case 38400000: | |
1740 | infreq = TWL4030_APLL_INFREQ_38400KHZ; | |
6943c92e | 1741 | twl4030->sysclk = 38400; |
cc17557e SS |
1742 | break; |
1743 | default: | |
1744 | printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", | |
1745 | freq); | |
1746 | return -EINVAL; | |
1747 | } | |
1748 | ||
1749 | infreq |= TWL4030_APLL_EN; | |
1750 | twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); | |
1751 | ||
1752 | return 0; | |
1753 | } | |
1754 | ||
1755 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1756 | unsigned int fmt) | |
1757 | { | |
1758 | struct snd_soc_codec *codec = codec_dai->codec; | |
1759 | u8 old_format, format; | |
1760 | ||
1761 | /* get format */ | |
1762 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1763 | format = old_format; | |
1764 | ||
1765 | /* set master/slave audio interface */ | |
1766 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1767 | case SND_SOC_DAIFMT_CBM_CFM: | |
1768 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1769 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1770 | break; |
1771 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1772 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1773 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1774 | break; |
1775 | default: | |
1776 | return -EINVAL; | |
1777 | } | |
1778 | ||
1779 | /* interface format */ | |
1780 | format &= ~TWL4030_AIF_FORMAT; | |
1781 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1782 | case SND_SOC_DAIFMT_I2S: | |
1783 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1784 | break; | |
8a1f936a PU |
1785 | case SND_SOC_DAIFMT_DSP_A: |
1786 | format |= TWL4030_AIF_FORMAT_TDM; | |
1787 | break; | |
cc17557e SS |
1788 | default: |
1789 | return -EINVAL; | |
1790 | } | |
1791 | ||
1792 | if (format != old_format) { | |
1793 | ||
1794 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1795 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1796 | |
1797 | /* change format */ | |
1798 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1799 | ||
1800 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1801 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1802 | } |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
b7a755a8 MLC |
1807 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1808 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1809 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
1810 | int enable) | |
1811 | { | |
1812 | u8 reg, mask; | |
1813 | ||
1814 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1815 | ||
1816 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1817 | mask = TWL4030_ARXL1_VRX_EN; | |
1818 | else | |
1819 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1820 | ||
1821 | if (enable) | |
1822 | reg |= mask; | |
1823 | else | |
1824 | reg &= ~mask; | |
1825 | ||
1826 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1827 | } | |
1828 | ||
7154b3e8 JS |
1829 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
1830 | struct snd_soc_dai *dai) | |
1831 | { | |
1832 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1833 | struct snd_soc_device *socdev = rtd->socdev; | |
1834 | struct snd_soc_codec *codec = socdev->card->codec; | |
1835 | u8 infreq; | |
1836 | u8 mode; | |
1837 | ||
1838 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
1839 | * not avilable. | |
1840 | */ | |
1841 | infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL) | |
1842 | & TWL4030_APLL_INFREQ; | |
1843 | ||
1844 | if (infreq != TWL4030_APLL_INFREQ_26000KHZ) { | |
1845 | printk(KERN_ERR "TWL4030 voice startup: " | |
1846 | "MCLK is not 26MHz, call set_sysclk() on init\n"); | |
1847 | return -EINVAL; | |
1848 | } | |
1849 | ||
1850 | /* If the codec mode is not option2, the voice PCM interface is not | |
1851 | * avilable. | |
1852 | */ | |
1853 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1854 | & TWL4030_OPT_MODE; | |
1855 | ||
1856 | if (mode != TWL4030_OPTION_2) { | |
1857 | printk(KERN_ERR "TWL4030 voice startup: " | |
1858 | "the codec mode is not option2\n"); | |
1859 | return -EINVAL; | |
1860 | } | |
1861 | ||
1862 | return 0; | |
1863 | } | |
1864 | ||
b7a755a8 MLC |
1865 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
1866 | struct snd_soc_dai *dai) | |
1867 | { | |
1868 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1869 | struct snd_soc_device *socdev = rtd->socdev; | |
1870 | struct snd_soc_codec *codec = socdev->card->codec; | |
1871 | ||
1872 | /* Enable voice digital filters */ | |
1873 | twl4030_voice_enable(codec, substream->stream, 0); | |
1874 | } | |
1875 | ||
7154b3e8 JS |
1876 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
1877 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1878 | { | |
1879 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1880 | struct snd_soc_device *socdev = rtd->socdev; | |
1881 | struct snd_soc_codec *codec = socdev->card->codec; | |
1882 | u8 old_mode, mode; | |
1883 | ||
b7a755a8 MLC |
1884 | /* Enable voice digital filters */ |
1885 | twl4030_voice_enable(codec, substream->stream, 1); | |
1886 | ||
7154b3e8 JS |
1887 | /* bit rate */ |
1888 | old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1889 | & ~(TWL4030_CODECPDZ); | |
1890 | mode = old_mode; | |
1891 | ||
1892 | switch (params_rate(params)) { | |
1893 | case 8000: | |
1894 | mode &= ~(TWL4030_SEL_16K); | |
1895 | break; | |
1896 | case 16000: | |
1897 | mode |= TWL4030_SEL_16K; | |
1898 | break; | |
1899 | default: | |
1900 | printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n", | |
1901 | params_rate(params)); | |
1902 | return -EINVAL; | |
1903 | } | |
1904 | ||
1905 | if (mode != old_mode) { | |
1906 | /* change rate and set CODECPDZ */ | |
1907 | twl4030_codec_enable(codec, 0); | |
1908 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1909 | twl4030_codec_enable(codec, 1); | |
1910 | } | |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
1915 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1916 | int clk_id, unsigned int freq, int dir) | |
1917 | { | |
1918 | struct snd_soc_codec *codec = codec_dai->codec; | |
1919 | u8 infreq; | |
1920 | ||
1921 | switch (freq) { | |
1922 | case 26000000: | |
1923 | infreq = TWL4030_APLL_INFREQ_26000KHZ; | |
1924 | break; | |
1925 | default: | |
1926 | printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n", | |
1927 | freq); | |
1928 | return -EINVAL; | |
1929 | } | |
1930 | ||
1931 | infreq |= TWL4030_APLL_EN; | |
1932 | twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1938 | unsigned int fmt) | |
1939 | { | |
1940 | struct snd_soc_codec *codec = codec_dai->codec; | |
1941 | u8 old_format, format; | |
1942 | ||
1943 | /* get format */ | |
1944 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
1945 | format = old_format; | |
1946 | ||
1947 | /* set master/slave audio interface */ | |
1948 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 1949 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
1950 | format &= ~(TWL4030_VIF_SLAVE_EN); |
1951 | break; | |
1952 | case SND_SOC_DAIFMT_CBS_CFS: | |
1953 | format |= TWL4030_VIF_SLAVE_EN; | |
1954 | break; | |
1955 | default: | |
1956 | return -EINVAL; | |
1957 | } | |
1958 | ||
1959 | /* clock inversion */ | |
1960 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1961 | case SND_SOC_DAIFMT_IB_NF: | |
1962 | format &= ~(TWL4030_VIF_FORMAT); | |
1963 | break; | |
1964 | case SND_SOC_DAIFMT_NB_IF: | |
1965 | format |= TWL4030_VIF_FORMAT; | |
1966 | break; | |
1967 | default: | |
1968 | return -EINVAL; | |
1969 | } | |
1970 | ||
1971 | if (format != old_format) { | |
1972 | /* change format and set CODECPDZ */ | |
1973 | twl4030_codec_enable(codec, 0); | |
1974 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
1975 | twl4030_codec_enable(codec, 1); | |
1976 | } | |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
bbba9444 | 1981 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
1982 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
1983 | ||
10d9e3d9 | 1984 | static struct snd_soc_dai_ops twl4030_dai_ops = { |
7220b9f4 PU |
1985 | .startup = twl4030_startup, |
1986 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
1987 | .hw_params = twl4030_hw_params, |
1988 | .set_sysclk = twl4030_set_dai_sysclk, | |
1989 | .set_fmt = twl4030_set_dai_fmt, | |
1990 | }; | |
1991 | ||
7154b3e8 JS |
1992 | static struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
1993 | .startup = twl4030_voice_startup, | |
b7a755a8 | 1994 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
1995 | .hw_params = twl4030_voice_hw_params, |
1996 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
1997 | .set_fmt = twl4030_voice_set_dai_fmt, | |
1998 | }; | |
1999 | ||
2000 | struct snd_soc_dai twl4030_dai[] = { | |
2001 | { | |
cc17557e SS |
2002 | .name = "twl4030", |
2003 | .playback = { | |
b4852b79 | 2004 | .stream_name = "HiFi Playback", |
cc17557e | 2005 | .channels_min = 2, |
8a1f936a | 2006 | .channels_max = 4, |
31ad0f31 | 2007 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
cc17557e SS |
2008 | .formats = TWL4030_FORMATS,}, |
2009 | .capture = { | |
2010 | .stream_name = "Capture", | |
2011 | .channels_min = 2, | |
8a1f936a | 2012 | .channels_max = 4, |
cc17557e SS |
2013 | .rates = TWL4030_RATES, |
2014 | .formats = TWL4030_FORMATS,}, | |
10d9e3d9 | 2015 | .ops = &twl4030_dai_ops, |
7154b3e8 JS |
2016 | }, |
2017 | { | |
2018 | .name = "twl4030 Voice", | |
2019 | .playback = { | |
b4852b79 | 2020 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2021 | .channels_min = 1, |
2022 | .channels_max = 1, | |
2023 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2024 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2025 | .capture = { | |
2026 | .stream_name = "Capture", | |
2027 | .channels_min = 1, | |
2028 | .channels_max = 2, | |
2029 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2030 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2031 | .ops = &twl4030_dai_voice_ops, | |
2032 | }, | |
cc17557e SS |
2033 | }; |
2034 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
2035 | ||
2036 | static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) | |
2037 | { | |
2038 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2039 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2040 | |
2041 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2042 | ||
2043 | return 0; | |
2044 | } | |
2045 | ||
2046 | static int twl4030_resume(struct platform_device *pdev) | |
2047 | { | |
2048 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2049 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2050 | |
2051 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2052 | twl4030_set_bias_level(codec, codec->suspend_bias_level); | |
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | /* | |
2057 | * initialize the driver | |
2058 | * register the mixer and dsp interfaces with the kernel | |
2059 | */ | |
2060 | ||
2061 | static int twl4030_init(struct snd_soc_device *socdev) | |
2062 | { | |
6627a653 | 2063 | struct snd_soc_codec *codec = socdev->card->codec; |
9da28c7b PU |
2064 | struct twl4030_setup_data *setup = socdev->codec_data; |
2065 | struct twl4030_priv *twl4030 = codec->private_data; | |
cc17557e SS |
2066 | int ret = 0; |
2067 | ||
2068 | printk(KERN_INFO "TWL4030 Audio Codec init \n"); | |
2069 | ||
2070 | codec->name = "twl4030"; | |
2071 | codec->owner = THIS_MODULE; | |
2072 | codec->read = twl4030_read_reg_cache; | |
2073 | codec->write = twl4030_write; | |
2074 | codec->set_bias_level = twl4030_set_bias_level; | |
7154b3e8 JS |
2075 | codec->dai = twl4030_dai; |
2076 | codec->num_dai = ARRAY_SIZE(twl4030_dai), | |
cc17557e SS |
2077 | codec->reg_cache_size = sizeof(twl4030_reg); |
2078 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
2079 | GFP_KERNEL); | |
2080 | if (codec->reg_cache == NULL) | |
2081 | return -ENOMEM; | |
2082 | ||
9da28c7b PU |
2083 | /* Configuration for headset ramp delay from setup data */ |
2084 | if (setup) { | |
2085 | unsigned char hs_pop; | |
2086 | ||
2087 | if (setup->sysclk) | |
2088 | twl4030->sysclk = setup->sysclk; | |
2089 | else | |
2090 | twl4030->sysclk = 26000; | |
2091 | ||
2092 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
2093 | hs_pop &= ~TWL4030_RAMP_DELAY; | |
2094 | hs_pop |= (setup->ramp_delay_value << 2); | |
2095 | twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
2096 | } else { | |
2097 | twl4030->sysclk = 26000; | |
2098 | } | |
2099 | ||
cc17557e SS |
2100 | /* register pcms */ |
2101 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
2102 | if (ret < 0) { | |
2103 | printk(KERN_ERR "twl4030: failed to create pcms\n"); | |
2104 | goto pcm_err; | |
2105 | } | |
2106 | ||
2107 | twl4030_init_chip(codec); | |
2108 | ||
2109 | /* power on device */ | |
2110 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2111 | ||
3e8e1952 IM |
2112 | snd_soc_add_controls(codec, twl4030_snd_controls, |
2113 | ARRAY_SIZE(twl4030_snd_controls)); | |
cc17557e SS |
2114 | twl4030_add_widgets(codec); |
2115 | ||
968a6025 | 2116 | ret = snd_soc_init_card(socdev); |
cc17557e SS |
2117 | if (ret < 0) { |
2118 | printk(KERN_ERR "twl4030: failed to register card\n"); | |
2119 | goto card_err; | |
2120 | } | |
2121 | ||
2122 | return ret; | |
2123 | ||
2124 | card_err: | |
2125 | snd_soc_free_pcms(socdev); | |
2126 | snd_soc_dapm_free(socdev); | |
2127 | pcm_err: | |
2128 | kfree(codec->reg_cache); | |
2129 | return ret; | |
2130 | } | |
2131 | ||
2132 | static struct snd_soc_device *twl4030_socdev; | |
2133 | ||
2134 | static int twl4030_probe(struct platform_device *pdev) | |
2135 | { | |
2136 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
2137 | struct snd_soc_codec *codec; | |
7393958f | 2138 | struct twl4030_priv *twl4030; |
cc17557e SS |
2139 | |
2140 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | |
2141 | if (codec == NULL) | |
2142 | return -ENOMEM; | |
2143 | ||
7393958f PU |
2144 | twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); |
2145 | if (twl4030 == NULL) { | |
2146 | kfree(codec); | |
2147 | return -ENOMEM; | |
2148 | } | |
2149 | ||
2150 | codec->private_data = twl4030; | |
6627a653 | 2151 | socdev->card->codec = codec; |
cc17557e SS |
2152 | mutex_init(&codec->mutex); |
2153 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
2154 | INIT_LIST_HEAD(&codec->dapm_paths); | |
2155 | ||
2156 | twl4030_socdev = socdev; | |
2157 | twl4030_init(socdev); | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
2162 | static int twl4030_remove(struct platform_device *pdev) | |
2163 | { | |
2164 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2165 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2166 | |
2167 | printk(KERN_INFO "TWL4030 Audio Codec remove\n"); | |
7393958f | 2168 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); |
c6d1662b PU |
2169 | snd_soc_free_pcms(socdev); |
2170 | snd_soc_dapm_free(socdev); | |
7393958f | 2171 | kfree(codec->private_data); |
cc17557e SS |
2172 | kfree(codec); |
2173 | ||
2174 | return 0; | |
2175 | } | |
2176 | ||
2177 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { | |
2178 | .probe = twl4030_probe, | |
2179 | .remove = twl4030_remove, | |
2180 | .suspend = twl4030_suspend, | |
2181 | .resume = twl4030_resume, | |
2182 | }; | |
2183 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
2184 | ||
24e07db8 | 2185 | static int __init twl4030_modinit(void) |
64089b84 | 2186 | { |
7154b3e8 | 2187 | return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); |
64089b84 | 2188 | } |
24e07db8 | 2189 | module_init(twl4030_modinit); |
64089b84 MB |
2190 | |
2191 | static void __exit twl4030_exit(void) | |
2192 | { | |
7154b3e8 | 2193 | snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); |
64089b84 MB |
2194 | } |
2195 | module_exit(twl4030_exit); | |
2196 | ||
cc17557e SS |
2197 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2198 | MODULE_AUTHOR("Steve Sakoman"); | |
2199 | MODULE_LICENSE("GPL"); |