Commit | Line | Data |
---|---|---|
cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
b07682b6 | 29 | #include <linux/i2c/twl.h> |
cc17557e SS |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
db04e2c5 | 45 | 0x91, /* REG_CODEC_MODE (0x1) */ |
cc17557e SS |
46 | 0xc3, /* REG_OPTION (0x2) */ |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
5920b453 GI |
49 | 0x20, /* REG_ANAMICL (0x5) */ |
50 | 0x00, /* REG_ANAMICR (0x6) */ | |
51 | 0x00, /* REG_AVADC_CTL (0x7) */ | |
cc17557e SS |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
c42a59ea | 58 | 0x00, /* REG_AUDIO_IF (0xE) */ |
cc17557e SS |
59 | 0x00, /* REG_VOICE_IF (0xF) */ |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
c8124593 | 67 | 0x00, /* REG_AVDAC_CTL (0x17) */ |
cc17557e SS |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
c8124593 PU |
71 | 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */ |
72 | 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
cc17557e SS |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
78 | 0x24, /* REG_HS_SEL (0x22) */ | |
79 | 0x0a, /* REG_HS_GAIN_SET (0x23) */ | |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ | |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
c8124593 | 102 | 0x06, /* REG_APLL_CTL (0x3A) */ |
cc17557e SS |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
f3b5d300 | 118 | 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */ |
cc17557e SS |
119 | }; |
120 | ||
7393958f PU |
121 | /* codec private data */ |
122 | struct twl4030_priv { | |
7a1fecf5 PU |
123 | struct snd_soc_codec codec; |
124 | ||
7393958f | 125 | unsigned int codec_powered; |
2845fa13 | 126 | unsigned int apll_enabled; |
7220b9f4 PU |
127 | |
128 | struct snd_pcm_substream *master_substream; | |
129 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
130 | |
131 | unsigned int configured; | |
132 | unsigned int rate; | |
133 | unsigned int sample_bits; | |
134 | unsigned int channels; | |
6943c92e PU |
135 | |
136 | unsigned int sysclk; | |
137 | ||
138 | /* Headset output state handling */ | |
139 | unsigned int hsl_enabled; | |
140 | unsigned int hsr_enabled; | |
7393958f PU |
141 | }; |
142 | ||
cc17557e SS |
143 | /* |
144 | * read twl4030 register cache | |
145 | */ | |
146 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
147 | unsigned int reg) | |
148 | { | |
d08664fd | 149 | u8 *cache = codec->reg_cache; |
cc17557e | 150 | |
91432e97 IM |
151 | if (reg >= TWL4030_CACHEREGNUM) |
152 | return -EIO; | |
153 | ||
cc17557e SS |
154 | return cache[reg]; |
155 | } | |
156 | ||
157 | /* | |
158 | * write twl4030 register cache | |
159 | */ | |
160 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
161 | u8 reg, u8 value) | |
162 | { | |
163 | u8 *cache = codec->reg_cache; | |
164 | ||
165 | if (reg >= TWL4030_CACHEREGNUM) | |
166 | return; | |
167 | cache[reg] = value; | |
168 | } | |
169 | ||
170 | /* | |
171 | * write to the twl4030 register space | |
172 | */ | |
173 | static int twl4030_write(struct snd_soc_codec *codec, | |
174 | unsigned int reg, unsigned int value) | |
175 | { | |
176 | twl4030_write_reg_cache(codec, reg, value); | |
f3b5d300 | 177 | if (likely(reg < TWL4030_REG_SW_SHADOW)) |
fc7b92fc | 178 | return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, |
f3b5d300 PU |
179 | reg); |
180 | else | |
181 | return 0; | |
cc17557e SS |
182 | } |
183 | ||
db04e2c5 | 184 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 185 | { |
7393958f | 186 | struct twl4030_priv *twl4030 = codec->private_data; |
7a1fecf5 | 187 | int mode; |
cc17557e | 188 | |
7393958f PU |
189 | if (enable == twl4030->codec_powered) |
190 | return; | |
191 | ||
db04e2c5 | 192 | if (enable) |
7a1fecf5 | 193 | mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER); |
db04e2c5 | 194 | else |
7a1fecf5 | 195 | mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER); |
cc17557e | 196 | |
7a1fecf5 PU |
197 | if (mode >= 0) { |
198 | twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode); | |
199 | twl4030->codec_powered = enable; | |
200 | } | |
cc17557e SS |
201 | |
202 | /* REVISIT: this delay is present in TI sample drivers */ | |
203 | /* but there seems to be no TRM requirement for it */ | |
204 | udelay(10); | |
205 | } | |
206 | ||
207 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
208 | { | |
16a30fbb | 209 | u8 *cache = codec->reg_cache; |
cc17557e SS |
210 | int i; |
211 | ||
212 | /* clear CODECPDZ prior to setting register defaults */ | |
db04e2c5 | 213 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
214 | |
215 | /* set all audio section registers to reasonable defaults */ | |
216 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
68d01955 PU |
217 | if (i != TWL4030_REG_APLL_CTL) |
218 | twl4030_write(codec, i, cache[i]); | |
cc17557e SS |
219 | |
220 | } | |
221 | ||
2845fa13 | 222 | static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable) |
7393958f PU |
223 | { |
224 | struct twl4030_priv *twl4030 = codec->private_data; | |
7a1fecf5 | 225 | int status; |
7393958f | 226 | |
2845fa13 | 227 | if (enable == twl4030->apll_enabled) |
7393958f PU |
228 | return; |
229 | ||
2845fa13 | 230 | if (enable) |
7393958f | 231 | /* Enable PLL */ |
7a1fecf5 | 232 | status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL); |
2845fa13 PU |
233 | else |
234 | /* Disable PLL */ | |
235 | status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL); | |
7a1fecf5 PU |
236 | |
237 | if (status >= 0) | |
238 | twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status); | |
7393958f | 239 | |
2845fa13 | 240 | twl4030->apll_enabled = enable; |
7393958f PU |
241 | } |
242 | ||
006f367e PU |
243 | static void twl4030_power_up(struct snd_soc_codec *codec) |
244 | { | |
7393958f | 245 | struct twl4030_priv *twl4030 = codec->private_data; |
006f367e PU |
246 | u8 anamicl, regmisc1, byte; |
247 | int i = 0; | |
248 | ||
7393958f PU |
249 | if (twl4030->codec_powered) |
250 | return; | |
251 | ||
006f367e PU |
252 | /* set CODECPDZ to turn on codec */ |
253 | twl4030_codec_enable(codec, 1); | |
254 | ||
255 | /* initiate offset cancellation */ | |
256 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
257 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
258 | anamicl | TWL4030_CNCL_OFFSET_START); | |
259 | ||
260 | /* wait for offset cancellation to complete */ | |
261 | do { | |
262 | /* this takes a little while, so don't slam i2c */ | |
263 | udelay(2000); | |
fc7b92fc | 264 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, |
006f367e PU |
265 | TWL4030_REG_ANAMICL); |
266 | } while ((i++ < 100) && | |
267 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
268 | TWL4030_CNCL_OFFSET_START)); | |
269 | ||
270 | /* Make sure that the reg_cache has the same value as the HW */ | |
271 | twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); | |
272 | ||
273 | /* anti-pop when changing analog gain */ | |
274 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
275 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
276 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
277 | ||
278 | /* toggle CODECPDZ as per TRM */ | |
279 | twl4030_codec_enable(codec, 0); | |
280 | twl4030_codec_enable(codec, 1); | |
281 | } | |
282 | ||
7393958f PU |
283 | /* |
284 | * Unconditional power down | |
285 | */ | |
006f367e PU |
286 | static void twl4030_power_down(struct snd_soc_codec *codec) |
287 | { | |
288 | /* power down */ | |
289 | twl4030_codec_enable(codec, 0); | |
290 | } | |
291 | ||
5e98a464 | 292 | /* Earpiece */ |
1a787e7a JS |
293 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
294 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
295 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
296 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
297 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
298 | }; | |
5e98a464 | 299 | |
2a6f5c58 | 300 | /* PreDrive Left */ |
1a787e7a JS |
301 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
302 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
303 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
304 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
305 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
306 | }; | |
2a6f5c58 PU |
307 | |
308 | /* PreDrive Right */ | |
1a787e7a JS |
309 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
310 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
311 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
312 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
313 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
314 | }; | |
2a6f5c58 | 315 | |
dfad21a2 | 316 | /* Headset Left */ |
1a787e7a JS |
317 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
318 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
319 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
320 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
321 | }; | |
dfad21a2 PU |
322 | |
323 | /* Headset Right */ | |
1a787e7a JS |
324 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
325 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
326 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
327 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
328 | }; | |
dfad21a2 | 329 | |
5152d8c2 | 330 | /* Carkit Left */ |
1a787e7a JS |
331 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
332 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
333 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
334 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
335 | }; | |
5152d8c2 PU |
336 | |
337 | /* Carkit Right */ | |
1a787e7a JS |
338 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
339 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
340 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
341 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
342 | }; | |
5152d8c2 | 343 | |
df339804 PU |
344 | /* Handsfree Left */ |
345 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 346 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 PU |
347 | |
348 | static const struct soc_enum twl4030_handsfreel_enum = | |
349 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
350 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
351 | twl4030_handsfreel_texts); | |
352 | ||
353 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
354 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
355 | ||
0f89bdca PU |
356 | /* Handsfree Left virtual mute */ |
357 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
358 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0); | |
359 | ||
df339804 PU |
360 | /* Handsfree Right */ |
361 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 362 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 PU |
363 | |
364 | static const struct soc_enum twl4030_handsfreer_enum = | |
365 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
366 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
367 | twl4030_handsfreer_texts); | |
368 | ||
369 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
370 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
371 | ||
0f89bdca PU |
372 | /* Handsfree Right virtual mute */ |
373 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
374 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0); | |
375 | ||
376f7839 PU |
376 | /* Vibra */ |
377 | /* Vibra audio path selection */ | |
378 | static const char *twl4030_vibra_texts[] = | |
379 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
380 | ||
381 | static const struct soc_enum twl4030_vibra_enum = | |
382 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, | |
383 | ARRAY_SIZE(twl4030_vibra_texts), | |
384 | twl4030_vibra_texts); | |
385 | ||
386 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
387 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
388 | ||
389 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
390 | static const char *twl4030_vibrapath_texts[] = | |
391 | {"Local vibrator", "Audio"}; | |
392 | ||
393 | static const struct soc_enum twl4030_vibrapath_enum = | |
394 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, | |
395 | ARRAY_SIZE(twl4030_vibrapath_texts), | |
396 | twl4030_vibrapath_texts); | |
397 | ||
398 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
399 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
400 | ||
276c6222 | 401 | /* Left analog microphone selection */ |
97b8096d | 402 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
9028935d PU |
403 | SOC_DAPM_SINGLE("Main Mic Capture Switch", |
404 | TWL4030_REG_ANAMICL, 0, 1, 0), | |
405 | SOC_DAPM_SINGLE("Headset Mic Capture Switch", | |
406 | TWL4030_REG_ANAMICL, 1, 1, 0), | |
407 | SOC_DAPM_SINGLE("AUXL Capture Switch", | |
408 | TWL4030_REG_ANAMICL, 2, 1, 0), | |
409 | SOC_DAPM_SINGLE("Carkit Mic Capture Switch", | |
410 | TWL4030_REG_ANAMICL, 3, 1, 0), | |
97b8096d | 411 | }; |
276c6222 PU |
412 | |
413 | /* Right analog microphone selection */ | |
97b8096d | 414 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
9028935d PU |
415 | SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), |
416 | SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), | |
97b8096d | 417 | }; |
276c6222 PU |
418 | |
419 | /* TX1 L/R Analog/Digital microphone selection */ | |
420 | static const char *twl4030_micpathtx1_texts[] = | |
421 | {"Analog", "Digimic0"}; | |
422 | ||
423 | static const struct soc_enum twl4030_micpathtx1_enum = | |
424 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
425 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
426 | twl4030_micpathtx1_texts); | |
427 | ||
428 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
429 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
430 | ||
431 | /* TX2 L/R Analog/Digital microphone selection */ | |
432 | static const char *twl4030_micpathtx2_texts[] = | |
433 | {"Analog", "Digimic1"}; | |
434 | ||
435 | static const struct soc_enum twl4030_micpathtx2_enum = | |
436 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
437 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
438 | twl4030_micpathtx2_texts); | |
439 | ||
440 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
441 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
442 | ||
7393958f PU |
443 | /* Analog bypass for AudioR1 */ |
444 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
445 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
446 | ||
447 | /* Analog bypass for AudioL1 */ | |
448 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
449 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
450 | ||
451 | /* Analog bypass for AudioR2 */ | |
452 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
453 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
454 | ||
455 | /* Analog bypass for AudioL2 */ | |
456 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
457 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
458 | ||
fcd274a3 LCM |
459 | /* Analog bypass for Voice */ |
460 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
461 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
462 | ||
6bab83fd PU |
463 | /* Digital bypass gain, 0 mutes the bypass */ |
464 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { | |
465 | TLV_DB_RANGE_HEAD(2), | |
466 | 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), | |
467 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), | |
468 | }; | |
469 | ||
470 | /* Digital bypass left (TX1L -> RX2L) */ | |
471 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
472 | SOC_DAPM_SINGLE_TLV("Volume", | |
473 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
474 | twl4030_dapm_dbypass_tlv); | |
475 | ||
476 | /* Digital bypass right (TX1R -> RX2R) */ | |
477 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
478 | SOC_DAPM_SINGLE_TLV("Volume", | |
479 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
480 | twl4030_dapm_dbypass_tlv); | |
481 | ||
ee8f6894 LCM |
482 | /* |
483 | * Voice Sidetone GAIN volume control: | |
484 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
485 | */ | |
486 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
487 | ||
488 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
489 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
490 | SOC_DAPM_SINGLE_TLV("Volume", | |
491 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
492 | twl4030_dapm_dbypassv_tlv); | |
493 | ||
276c6222 PU |
494 | static int micpath_event(struct snd_soc_dapm_widget *w, |
495 | struct snd_kcontrol *kcontrol, int event) | |
496 | { | |
497 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
498 | unsigned char adcmicsel, micbias_ctl; | |
499 | ||
500 | adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); | |
501 | micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); | |
502 | /* Prepare the bits for the given TX path: | |
503 | * shift_l == 0: TX1 microphone path | |
504 | * shift_l == 2: TX2 microphone path */ | |
505 | if (e->shift_l) { | |
506 | /* TX2 microphone path */ | |
507 | if (adcmicsel & TWL4030_TX2IN_SEL) | |
508 | micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ | |
509 | else | |
510 | micbias_ctl &= ~TWL4030_MICBIAS2_CTL; | |
511 | } else { | |
512 | /* TX1 microphone path */ | |
513 | if (adcmicsel & TWL4030_TX1IN_SEL) | |
514 | micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ | |
515 | else | |
516 | micbias_ctl &= ~TWL4030_MICBIAS1_CTL; | |
517 | } | |
518 | ||
519 | twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
9008adf9 PU |
524 | /* |
525 | * Output PGA builder: | |
526 | * Handle the muting and unmuting of the given output (turning off the | |
527 | * amplifier associated with the output pin) | |
528 | * On mute bypass the reg_cache and mute the volume | |
529 | * On unmute: restore the register content | |
530 | * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R | |
531 | */ | |
532 | #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ | |
533 | static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ | |
534 | struct snd_kcontrol *kcontrol, int event) \ | |
535 | { \ | |
536 | u8 reg_val; \ | |
537 | \ | |
538 | switch (event) { \ | |
539 | case SND_SOC_DAPM_POST_PMU: \ | |
540 | twl4030_write(w->codec, reg, \ | |
541 | twl4030_read_reg_cache(w->codec, reg)); \ | |
542 | break; \ | |
543 | case SND_SOC_DAPM_POST_PMD: \ | |
544 | reg_val = twl4030_read_reg_cache(w->codec, reg); \ | |
fc7b92fc | 545 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \ |
9008adf9 PU |
546 | reg_val & (~mask), \ |
547 | reg); \ | |
548 | break; \ | |
549 | } \ | |
550 | return 0; \ | |
551 | } | |
552 | ||
553 | TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); | |
554 | TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); | |
555 | TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); | |
556 | TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); | |
557 | TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); | |
558 | ||
5a2e9a48 | 559 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 560 | { |
49d92c7d SM |
561 | unsigned char hs_ctl; |
562 | ||
5a2e9a48 | 563 | hs_ctl = twl4030_read_reg_cache(codec, reg); |
49d92c7d | 564 | |
5a2e9a48 PU |
565 | if (ramp) { |
566 | /* HF ramp-up */ | |
567 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
568 | twl4030_write(codec, reg, hs_ctl); | |
569 | udelay(10); | |
49d92c7d | 570 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
571 | twl4030_write(codec, reg, hs_ctl); |
572 | udelay(40); | |
49d92c7d | 573 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 574 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 575 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 576 | } else { |
5a2e9a48 PU |
577 | /* HF ramp-down */ |
578 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
579 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
580 | twl4030_write(codec, reg, hs_ctl); | |
581 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
582 | twl4030_write(codec, reg, hs_ctl); | |
583 | udelay(40); | |
584 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
585 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 586 | } |
5a2e9a48 | 587 | } |
49d92c7d | 588 | |
5a2e9a48 PU |
589 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
590 | struct snd_kcontrol *kcontrol, int event) | |
591 | { | |
592 | switch (event) { | |
593 | case SND_SOC_DAPM_POST_PMU: | |
594 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); | |
595 | break; | |
596 | case SND_SOC_DAPM_POST_PMD: | |
597 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); | |
598 | break; | |
599 | } | |
600 | return 0; | |
601 | } | |
602 | ||
603 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
604 | struct snd_kcontrol *kcontrol, int event) | |
605 | { | |
606 | switch (event) { | |
607 | case SND_SOC_DAPM_POST_PMU: | |
608 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); | |
609 | break; | |
610 | case SND_SOC_DAPM_POST_PMD: | |
611 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); | |
612 | break; | |
613 | } | |
49d92c7d SM |
614 | return 0; |
615 | } | |
616 | ||
86139a13 JV |
617 | static int vibramux_event(struct snd_soc_dapm_widget *w, |
618 | struct snd_kcontrol *kcontrol, int event) | |
619 | { | |
620 | twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff); | |
621 | return 0; | |
622 | } | |
623 | ||
7729cf74 PU |
624 | static int apll_event(struct snd_soc_dapm_widget *w, |
625 | struct snd_kcontrol *kcontrol, int event) | |
626 | { | |
627 | switch (event) { | |
628 | case SND_SOC_DAPM_PRE_PMU: | |
629 | twl4030_apll_enable(w->codec, 1); | |
630 | break; | |
631 | case SND_SOC_DAPM_POST_PMD: | |
632 | twl4030_apll_enable(w->codec, 0); | |
633 | break; | |
634 | } | |
635 | return 0; | |
636 | } | |
637 | ||
6943c92e | 638 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 | 639 | { |
4e49ffd1 CVJ |
640 | struct snd_soc_device *socdev = codec->socdev; |
641 | struct twl4030_setup_data *setup = socdev->codec_data; | |
642 | ||
aad749e5 | 643 | unsigned char hs_gain, hs_pop; |
6943c92e PU |
644 | struct twl4030_priv *twl4030 = codec->private_data; |
645 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ | |
646 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
647 | 8388608, 16777216, 33554432, 67108864}; | |
aad749e5 | 648 | |
6943c92e PU |
649 | hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); |
650 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
aad749e5 | 651 | |
4e49ffd1 CVJ |
652 | /* Enable external mute control, this dramatically reduces |
653 | * the pop-noise */ | |
654 | if (setup && setup->hs_extmute) { | |
655 | if (setup->set_hs_extmute) { | |
656 | setup->set_hs_extmute(1); | |
657 | } else { | |
658 | hs_pop |= TWL4030_EXTMUTE; | |
659 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
660 | } | |
661 | } | |
662 | ||
6943c92e PU |
663 | if (ramp) { |
664 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 665 | hs_pop |= TWL4030_VMID_EN; |
6943c92e PU |
666 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
667 | twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain); | |
aad749e5 | 668 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e | 669 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
4e49ffd1 CVJ |
670 | /* Wait ramp delay time + 1, so the VMID can settle */ |
671 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
672 | twl4030->sysclk) + 1); | |
6943c92e PU |
673 | } else { |
674 | /* Headset ramp-down _not_ according to | |
675 | * the TRM, but in a way that it is working */ | |
aad749e5 | 676 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
677 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
678 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
679 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
680 | twl4030->sysclk) + 1); | |
aad749e5 | 681 | /* Bypass the reg_cache to mute the headset */ |
fc7b92fc | 682 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, |
aad749e5 PU |
683 | hs_gain & (~0x0f), |
684 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 685 | |
aad749e5 | 686 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
687 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
688 | } | |
4e49ffd1 CVJ |
689 | |
690 | /* Disable external mute */ | |
691 | if (setup && setup->hs_extmute) { | |
692 | if (setup->set_hs_extmute) { | |
693 | setup->set_hs_extmute(0); | |
694 | } else { | |
695 | hs_pop &= ~TWL4030_EXTMUTE; | |
696 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
697 | } | |
698 | } | |
6943c92e PU |
699 | } |
700 | ||
701 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
702 | struct snd_kcontrol *kcontrol, int event) | |
703 | { | |
704 | struct twl4030_priv *twl4030 = w->codec->private_data; | |
705 | ||
706 | switch (event) { | |
707 | case SND_SOC_DAPM_POST_PMU: | |
708 | /* Do the ramp-up only once */ | |
709 | if (!twl4030->hsr_enabled) | |
710 | headset_ramp(w->codec, 1); | |
711 | ||
712 | twl4030->hsl_enabled = 1; | |
713 | break; | |
714 | case SND_SOC_DAPM_POST_PMD: | |
715 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
716 | if (!twl4030->hsr_enabled) | |
717 | headset_ramp(w->codec, 0); | |
718 | ||
719 | twl4030->hsl_enabled = 0; | |
720 | break; | |
721 | } | |
722 | return 0; | |
723 | } | |
724 | ||
725 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
726 | struct snd_kcontrol *kcontrol, int event) | |
727 | { | |
728 | struct twl4030_priv *twl4030 = w->codec->private_data; | |
729 | ||
730 | switch (event) { | |
731 | case SND_SOC_DAPM_POST_PMU: | |
732 | /* Do the ramp-up only once */ | |
733 | if (!twl4030->hsl_enabled) | |
734 | headset_ramp(w->codec, 1); | |
735 | ||
736 | twl4030->hsr_enabled = 1; | |
737 | break; | |
738 | case SND_SOC_DAPM_POST_PMD: | |
739 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
740 | if (!twl4030->hsl_enabled) | |
741 | headset_ramp(w->codec, 0); | |
742 | ||
743 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
744 | break; |
745 | } | |
746 | return 0; | |
747 | } | |
748 | ||
b0bd53a7 PU |
749 | /* |
750 | * Some of the gain controls in TWL (mostly those which are associated with | |
751 | * the outputs) are implemented in an interesting way: | |
752 | * 0x0 : Power down (mute) | |
753 | * 0x1 : 6dB | |
754 | * 0x2 : 0 dB | |
755 | * 0x3 : -6 dB | |
756 | * Inverting not going to help with these. | |
757 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
758 | */ | |
759 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
760 | xinvert, tlv_array) \ | |
761 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
762 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
763 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
764 | .tlv.p = (tlv_array), \ | |
765 | .info = snd_soc_info_volsw, \ | |
766 | .get = snd_soc_get_volsw_twl4030, \ | |
767 | .put = snd_soc_put_volsw_twl4030, \ | |
768 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
769 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
770 | .max = xmax, .invert = xinvert} } | |
771 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
772 | xinvert, tlv_array) \ | |
773 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
774 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
775 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
776 | .tlv.p = (tlv_array), \ | |
777 | .info = snd_soc_info_volsw_2r, \ | |
778 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
779 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
780 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
781 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
64089b84 | 782 | .rshift = xshift, .max = xmax, .invert = xinvert} } |
b0bd53a7 PU |
783 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ |
784 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
785 | xinvert, tlv_array) | |
786 | ||
787 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
788 | struct snd_ctl_elem_value *ucontrol) | |
789 | { | |
790 | struct soc_mixer_control *mc = | |
791 | (struct soc_mixer_control *)kcontrol->private_value; | |
792 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
793 | unsigned int reg = mc->reg; | |
794 | unsigned int shift = mc->shift; | |
795 | unsigned int rshift = mc->rshift; | |
796 | int max = mc->max; | |
797 | int mask = (1 << fls(max)) - 1; | |
798 | ||
799 | ucontrol->value.integer.value[0] = | |
800 | (snd_soc_read(codec, reg) >> shift) & mask; | |
801 | if (ucontrol->value.integer.value[0]) | |
802 | ucontrol->value.integer.value[0] = | |
803 | max + 1 - ucontrol->value.integer.value[0]; | |
804 | ||
805 | if (shift != rshift) { | |
806 | ucontrol->value.integer.value[1] = | |
807 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
808 | if (ucontrol->value.integer.value[1]) | |
809 | ucontrol->value.integer.value[1] = | |
810 | max + 1 - ucontrol->value.integer.value[1]; | |
811 | } | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
817 | struct snd_ctl_elem_value *ucontrol) | |
818 | { | |
819 | struct soc_mixer_control *mc = | |
820 | (struct soc_mixer_control *)kcontrol->private_value; | |
821 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
822 | unsigned int reg = mc->reg; | |
823 | unsigned int shift = mc->shift; | |
824 | unsigned int rshift = mc->rshift; | |
825 | int max = mc->max; | |
826 | int mask = (1 << fls(max)) - 1; | |
827 | unsigned short val, val2, val_mask; | |
828 | ||
829 | val = (ucontrol->value.integer.value[0] & mask); | |
830 | ||
831 | val_mask = mask << shift; | |
832 | if (val) | |
833 | val = max + 1 - val; | |
834 | val = val << shift; | |
835 | if (shift != rshift) { | |
836 | val2 = (ucontrol->value.integer.value[1] & mask); | |
837 | val_mask |= mask << rshift; | |
838 | if (val2) | |
839 | val2 = max + 1 - val2; | |
840 | val |= val2 << rshift; | |
841 | } | |
842 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
843 | } | |
844 | ||
845 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
846 | struct snd_ctl_elem_value *ucontrol) | |
847 | { | |
848 | struct soc_mixer_control *mc = | |
849 | (struct soc_mixer_control *)kcontrol->private_value; | |
850 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
851 | unsigned int reg = mc->reg; | |
852 | unsigned int reg2 = mc->rreg; | |
853 | unsigned int shift = mc->shift; | |
854 | int max = mc->max; | |
855 | int mask = (1<<fls(max))-1; | |
856 | ||
857 | ucontrol->value.integer.value[0] = | |
858 | (snd_soc_read(codec, reg) >> shift) & mask; | |
859 | ucontrol->value.integer.value[1] = | |
860 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
861 | ||
862 | if (ucontrol->value.integer.value[0]) | |
863 | ucontrol->value.integer.value[0] = | |
864 | max + 1 - ucontrol->value.integer.value[0]; | |
865 | if (ucontrol->value.integer.value[1]) | |
866 | ucontrol->value.integer.value[1] = | |
867 | max + 1 - ucontrol->value.integer.value[1]; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
873 | struct snd_ctl_elem_value *ucontrol) | |
874 | { | |
875 | struct soc_mixer_control *mc = | |
876 | (struct soc_mixer_control *)kcontrol->private_value; | |
877 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
878 | unsigned int reg = mc->reg; | |
879 | unsigned int reg2 = mc->rreg; | |
880 | unsigned int shift = mc->shift; | |
881 | int max = mc->max; | |
882 | int mask = (1 << fls(max)) - 1; | |
883 | int err; | |
884 | unsigned short val, val2, val_mask; | |
885 | ||
886 | val_mask = mask << shift; | |
887 | val = (ucontrol->value.integer.value[0] & mask); | |
888 | val2 = (ucontrol->value.integer.value[1] & mask); | |
889 | ||
890 | if (val) | |
891 | val = max + 1 - val; | |
892 | if (val2) | |
893 | val2 = max + 1 - val2; | |
894 | ||
895 | val = val << shift; | |
896 | val2 = val2 << shift; | |
897 | ||
898 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
899 | if (err < 0) | |
900 | return err; | |
901 | ||
902 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
903 | return err; | |
904 | } | |
905 | ||
b74bd40f LCM |
906 | /* Codec operation modes */ |
907 | static const char *twl4030_op_modes_texts[] = { | |
908 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
909 | }; | |
910 | ||
911 | static const struct soc_enum twl4030_op_modes_enum = | |
912 | SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, | |
913 | ARRAY_SIZE(twl4030_op_modes_texts), | |
914 | twl4030_op_modes_texts); | |
915 | ||
423c238d | 916 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
917 | struct snd_ctl_elem_value *ucontrol) |
918 | { | |
919 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
920 | struct twl4030_priv *twl4030 = codec->private_data; | |
921 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
922 | unsigned short val; | |
923 | unsigned short mask, bitmask; | |
924 | ||
925 | if (twl4030->configured) { | |
926 | printk(KERN_ERR "twl4030 operation mode cannot be " | |
927 | "changed on-the-fly\n"); | |
928 | return -EBUSY; | |
929 | } | |
930 | ||
931 | for (bitmask = 1; bitmask < e->max; bitmask <<= 1) | |
932 | ; | |
933 | if (ucontrol->value.enumerated.item[0] > e->max - 1) | |
934 | return -EINVAL; | |
935 | ||
936 | val = ucontrol->value.enumerated.item[0] << e->shift_l; | |
937 | mask = (bitmask - 1) << e->shift_l; | |
938 | if (e->shift_l != e->shift_r) { | |
939 | if (ucontrol->value.enumerated.item[1] > e->max - 1) | |
940 | return -EINVAL; | |
941 | val |= ucontrol->value.enumerated.item[1] << e->shift_r; | |
942 | mask |= (bitmask - 1) << e->shift_r; | |
943 | } | |
944 | ||
945 | return snd_soc_update_bits(codec, e->reg, mask, val); | |
946 | } | |
947 | ||
c10b82cf PU |
948 | /* |
949 | * FGAIN volume control: | |
950 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
951 | */ | |
d889a72c | 952 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 953 | |
0d33ea0b PU |
954 | /* |
955 | * CGAIN volume control: | |
956 | * 0 dB to 12 dB in 6 dB steps | |
957 | * value 2 and 3 means 12 dB | |
958 | */ | |
d889a72c PU |
959 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
960 | ||
1a787e7a JS |
961 | /* |
962 | * Voice Downlink GAIN volume control: | |
963 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
964 | */ | |
965 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
966 | ||
d889a72c PU |
967 | /* |
968 | * Analog playback gain | |
969 | * -24 dB to 12 dB in 2 dB steps | |
970 | */ | |
971 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 972 | |
4290239c PU |
973 | /* |
974 | * Gain controls tied to outputs | |
975 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
976 | */ | |
977 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
978 | ||
18cc8d8d JS |
979 | /* |
980 | * Gain control for earpiece amplifier | |
981 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
982 | */ | |
983 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
984 | ||
381a22b5 PU |
985 | /* |
986 | * Capture gain after the ADCs | |
987 | * from 0 dB to 31 dB in 1 dB steps | |
988 | */ | |
989 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
990 | ||
5920b453 GI |
991 | /* |
992 | * Gain control for input amplifiers | |
993 | * 0 dB to 30 dB in 6 dB steps | |
994 | */ | |
995 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
996 | ||
328d0a13 LCM |
997 | /* AVADC clock priority */ |
998 | static const char *twl4030_avadc_clk_priority_texts[] = { | |
999 | "Voice high priority", "HiFi high priority" | |
1000 | }; | |
1001 | ||
1002 | static const struct soc_enum twl4030_avadc_clk_priority_enum = | |
1003 | SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2, | |
1004 | ARRAY_SIZE(twl4030_avadc_clk_priority_texts), | |
1005 | twl4030_avadc_clk_priority_texts); | |
1006 | ||
89492be8 PU |
1007 | static const char *twl4030_rampdelay_texts[] = { |
1008 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1009 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1010 | "3495/2581/1748 ms" | |
1011 | }; | |
1012 | ||
1013 | static const struct soc_enum twl4030_rampdelay_enum = | |
1014 | SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, | |
1015 | ARRAY_SIZE(twl4030_rampdelay_texts), | |
1016 | twl4030_rampdelay_texts); | |
1017 | ||
376f7839 PU |
1018 | /* Vibra H-bridge direction mode */ |
1019 | static const char *twl4030_vibradirmode_texts[] = { | |
1020 | "Vibra H-bridge direction", "Audio data MSB", | |
1021 | }; | |
1022 | ||
1023 | static const struct soc_enum twl4030_vibradirmode_enum = | |
1024 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, | |
1025 | ARRAY_SIZE(twl4030_vibradirmode_texts), | |
1026 | twl4030_vibradirmode_texts); | |
1027 | ||
1028 | /* Vibra H-bridge direction */ | |
1029 | static const char *twl4030_vibradir_texts[] = { | |
1030 | "Positive polarity", "Negative polarity", | |
1031 | }; | |
1032 | ||
1033 | static const struct soc_enum twl4030_vibradir_enum = | |
1034 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, | |
1035 | ARRAY_SIZE(twl4030_vibradir_texts), | |
1036 | twl4030_vibradir_texts); | |
1037 | ||
cc17557e | 1038 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1039 | /* Codec operation mode control */ |
1040 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1041 | snd_soc_get_enum_double, | |
1042 | snd_soc_put_twl4030_opmode_enum_double), | |
1043 | ||
d889a72c PU |
1044 | /* Common playback gain controls */ |
1045 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1046 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1047 | 0, 0x3f, 0, digital_fine_tlv), | |
1048 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1049 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1050 | 0, 0x3f, 0, digital_fine_tlv), | |
1051 | ||
1052 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1053 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1054 | 6, 0x2, 0, digital_coarse_tlv), | |
1055 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1056 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1057 | 6, 0x2, 0, digital_coarse_tlv), | |
1058 | ||
1059 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1060 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1061 | 3, 0x12, 1, analog_tlv), | |
1062 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1063 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1064 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1065 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1066 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1067 | 1, 1, 0), | |
1068 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1069 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1070 | 1, 1, 0), | |
381a22b5 | 1071 | |
1a787e7a JS |
1072 | /* Common voice downlink gain controls */ |
1073 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1074 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1075 | ||
1076 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1077 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1078 | ||
1079 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1080 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1081 | ||
4290239c PU |
1082 | /* Separate output gain controls */ |
1083 | SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", | |
1084 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, | |
1085 | 4, 3, 0, output_tvl), | |
1086 | ||
1087 | SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", | |
1088 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), | |
1089 | ||
1090 | SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", | |
1091 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, | |
1092 | 4, 3, 0, output_tvl), | |
1093 | ||
1094 | SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", | |
18cc8d8d | 1095 | TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl), |
4290239c | 1096 | |
381a22b5 | 1097 | /* Common capture gain controls */ |
276c6222 | 1098 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1099 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1100 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1101 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1102 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1103 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1104 | |
276c6222 | 1105 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1106 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 | 1107 | |
328d0a13 LCM |
1108 | SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), |
1109 | ||
89492be8 | 1110 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), |
376f7839 PU |
1111 | |
1112 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1113 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
cc17557e SS |
1114 | }; |
1115 | ||
cc17557e | 1116 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1117 | /* Left channel inputs */ |
1118 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1119 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1120 | SND_SOC_DAPM_INPUT("AUXL"), | |
1121 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1122 | /* Right channel inputs */ | |
1123 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1124 | SND_SOC_DAPM_INPUT("AUXR"), | |
1125 | /* Digital microphones (Stereo) */ | |
1126 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1127 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1128 | ||
1129 | /* Outputs */ | |
cc17557e SS |
1130 | SND_SOC_DAPM_OUTPUT("OUTL"), |
1131 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
5e98a464 | 1132 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1133 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1134 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1135 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1136 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1137 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1138 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1139 | SND_SOC_DAPM_OUTPUT("HFL"), |
1140 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1141 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1142 | |
53b5047d | 1143 | /* DACs */ |
b4852b79 | 1144 | SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback", |
7393958f | 1145 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1146 | SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback", |
7393958f | 1147 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1148 | SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback", |
7393958f | 1149 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1150 | SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback", |
7393958f | 1151 | SND_SOC_NOPM, 0, 0), |
1a787e7a | 1152 | SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback", |
fcd274a3 | 1153 | SND_SOC_NOPM, 0, 0), |
cc17557e | 1154 | |
7393958f | 1155 | /* Analog bypasses */ |
78e08e2f PU |
1156 | SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, |
1157 | &twl4030_dapm_abypassr1_control), | |
1158 | SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1159 | &twl4030_dapm_abypassl1_control), | |
1160 | SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1161 | &twl4030_dapm_abypassr2_control), | |
1162 | SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1163 | &twl4030_dapm_abypassl2_control), | |
1164 | SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1165 | &twl4030_dapm_abypassv_control), | |
1166 | ||
1167 | /* Master analog loopback switch */ | |
1168 | SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0, | |
1169 | NULL, 0), | |
7393958f | 1170 | |
6bab83fd | 1171 | /* Digital bypasses */ |
78e08e2f PU |
1172 | SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0, |
1173 | &twl4030_dapm_dbypassl_control), | |
1174 | SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1175 | &twl4030_dapm_dbypassr_control), | |
1176 | SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1177 | &twl4030_dapm_dbypassv_control), | |
6bab83fd | 1178 | |
4005d39a PU |
1179 | /* Digital mixers, power control for the physical DACs */ |
1180 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1181 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1182 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1183 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1184 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1185 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1186 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1187 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1188 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1189 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1190 | ||
1191 | /* Analog mixers, power control for the physical PGAs */ | |
1192 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1193 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1194 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1195 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1196 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1197 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1198 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1199 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1200 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1201 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1202 | |
7729cf74 PU |
1203 | SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event, |
1204 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
1205 | ||
c42a59ea PU |
1206 | SND_SOC_DAPM_SUPPLY("AIF Enable", TWL4030_REG_AUDIO_IF, 0, 0, NULL, 0), |
1207 | ||
1a787e7a | 1208 | /* Output MIXER controls */ |
5e98a464 | 1209 | /* Earpiece */ |
1a787e7a JS |
1210 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1211 | &twl4030_dapm_earpiece_controls[0], | |
1212 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
9008adf9 PU |
1213 | SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, |
1214 | 0, 0, NULL, 0, earpiecepga_event, | |
1215 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
2a6f5c58 | 1216 | /* PreDrivL/R */ |
1a787e7a JS |
1217 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1218 | &twl4030_dapm_predrivel_controls[0], | |
1219 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
9008adf9 PU |
1220 | SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, |
1221 | 0, 0, NULL, 0, predrivelpga_event, | |
1222 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1223 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, |
1224 | &twl4030_dapm_predriver_controls[0], | |
1225 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
9008adf9 PU |
1226 | SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, |
1227 | 0, 0, NULL, 0, predriverpga_event, | |
1228 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 | 1229 | /* HeadsetL/R */ |
6943c92e | 1230 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1231 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1232 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1233 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1234 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1235 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1236 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1237 | &twl4030_dapm_hsor_controls[0], | |
1238 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1239 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1240 | 0, 0, NULL, 0, headsetrpga_event, | |
1241 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1242 | /* CarkitL/R */ |
1a787e7a JS |
1243 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1244 | &twl4030_dapm_carkitl_controls[0], | |
1245 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
9008adf9 PU |
1246 | SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, |
1247 | 0, 0, NULL, 0, carkitlpga_event, | |
1248 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1249 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, |
1250 | &twl4030_dapm_carkitr_controls[0], | |
1251 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
9008adf9 PU |
1252 | SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, |
1253 | 0, 0, NULL, 0, carkitrpga_event, | |
1254 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1255 | |
1256 | /* Output MUX controls */ | |
df339804 | 1257 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1258 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1259 | &twl4030_dapm_handsfreel_control), | |
e3c7dbb0 | 1260 | SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1261 | &twl4030_dapm_handsfreelmute_control), |
5a2e9a48 PU |
1262 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1263 | 0, 0, NULL, 0, handsfreelpga_event, | |
1264 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1265 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1266 | &twl4030_dapm_handsfreer_control), | |
e3c7dbb0 | 1267 | SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1268 | &twl4030_dapm_handsfreermute_control), |
5a2e9a48 PU |
1269 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1270 | 0, 0, NULL, 0, handsfreerpga_event, | |
1271 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 | 1272 | /* Vibra */ |
86139a13 JV |
1273 | SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, |
1274 | &twl4030_dapm_vibra_control, vibramux_event, | |
1275 | SND_SOC_DAPM_PRE_PMU), | |
376f7839 PU |
1276 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, |
1277 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1278 | |
276c6222 PU |
1279 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1280 | capture */ | |
1281 | SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", | |
1282 | SND_SOC_NOPM, 0, 0), | |
1283 | SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", | |
1284 | SND_SOC_NOPM, 0, 0), | |
1285 | SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", | |
1286 | SND_SOC_NOPM, 0, 0), | |
1287 | SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", | |
1288 | SND_SOC_NOPM, 0, 0), | |
1289 | ||
1290 | /* Analog/Digital mic path selection. | |
1291 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1292 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
1293 | SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, | |
1294 | &twl4030_dapm_micpathtx1_control, micpath_event, | |
1295 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1296 | SND_SOC_DAPM_POST_REG), | |
1297 | SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1298 | &twl4030_dapm_micpathtx2_control, micpath_event, | |
1299 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1300 | SND_SOC_DAPM_POST_REG), | |
1301 | ||
97b8096d | 1302 | /* Analog input mixers for the capture amplifiers */ |
9028935d | 1303 | SND_SOC_DAPM_MIXER("Analog Left", |
97b8096d JS |
1304 | TWL4030_REG_ANAMICL, 4, 0, |
1305 | &twl4030_dapm_analoglmic_controls[0], | |
1306 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
9028935d | 1307 | SND_SOC_DAPM_MIXER("Analog Right", |
97b8096d JS |
1308 | TWL4030_REG_ANAMICR, 4, 0, |
1309 | &twl4030_dapm_analogrmic_controls[0], | |
1310 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1311 | |
fb2a2f84 PU |
1312 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1313 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1314 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1315 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 PU |
1316 | |
1317 | SND_SOC_DAPM_PGA("Digimic0 Enable", | |
1318 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), | |
1319 | SND_SOC_DAPM_PGA("Digimic1 Enable", | |
1320 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), | |
1321 | ||
1322 | SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), | |
1323 | SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), | |
1324 | SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), | |
7393958f | 1325 | |
cc17557e SS |
1326 | }; |
1327 | ||
1328 | static const struct snd_soc_dapm_route intercon[] = { | |
4005d39a PU |
1329 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1330 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1331 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1332 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1333 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1334 | ||
7729cf74 PU |
1335 | /* Supply for the digital part (APLL) */ |
1336 | {"Digital R1 Playback Mixer", NULL, "APLL Enable"}, | |
1337 | {"Digital L1 Playback Mixer", NULL, "APLL Enable"}, | |
1338 | {"Digital R2 Playback Mixer", NULL, "APLL Enable"}, | |
1339 | {"Digital L2 Playback Mixer", NULL, "APLL Enable"}, | |
1340 | {"Digital Voice Playback Mixer", NULL, "APLL Enable"}, | |
1341 | ||
c42a59ea PU |
1342 | {"Digital R1 Playback Mixer", NULL, "AIF Enable"}, |
1343 | {"Digital L1 Playback Mixer", NULL, "AIF Enable"}, | |
1344 | {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, | |
1345 | {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, | |
1346 | ||
4005d39a PU |
1347 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, |
1348 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1349 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1350 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1351 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1352 | |
5e98a464 PU |
1353 | /* Internal playback routings */ |
1354 | /* Earpiece */ | |
4005d39a PU |
1355 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1356 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1357 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1358 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
9008adf9 | 1359 | {"Earpiece PGA", NULL, "Earpiece Mixer"}, |
2a6f5c58 | 1360 | /* PreDrivL */ |
4005d39a PU |
1361 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1362 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1363 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1364 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1365 | {"PredriveL PGA", NULL, "PredriveL Mixer"}, |
2a6f5c58 | 1366 | /* PreDrivR */ |
4005d39a PU |
1367 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1368 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1369 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1370 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1371 | {"PredriveR PGA", NULL, "PredriveR Mixer"}, |
dfad21a2 | 1372 | /* HeadsetL */ |
4005d39a PU |
1373 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1374 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1375 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1376 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1377 | /* HeadsetR */ |
4005d39a PU |
1378 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1379 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1380 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1381 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1382 | /* CarkitL */ |
4005d39a PU |
1383 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1384 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1385 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1386 | {"CarkitL PGA", NULL, "CarkitL Mixer"}, |
5152d8c2 | 1387 | /* CarkitR */ |
4005d39a PU |
1388 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1389 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1390 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1391 | {"CarkitR PGA", NULL, "CarkitR Mixer"}, |
df339804 | 1392 | /* HandsfreeL */ |
4005d39a PU |
1393 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1394 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1395 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1396 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1397 | {"HandsfreeL", "Switch", "HandsfreeL Mux"}, |
1398 | {"HandsfreeL PGA", NULL, "HandsfreeL"}, | |
df339804 | 1399 | /* HandsfreeR */ |
4005d39a PU |
1400 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1401 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1402 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1403 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1404 | {"HandsfreeR", "Switch", "HandsfreeR Mux"}, |
1405 | {"HandsfreeR PGA", NULL, "HandsfreeR"}, | |
376f7839 PU |
1406 | /* Vibra */ |
1407 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1408 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1409 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1410 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1411 | |
cc17557e | 1412 | /* outputs */ |
4005d39a PU |
1413 | {"OUTL", NULL, "Analog L2 Playback Mixer"}, |
1414 | {"OUTR", NULL, "Analog R2 Playback Mixer"}, | |
9008adf9 PU |
1415 | {"EARPIECE", NULL, "Earpiece PGA"}, |
1416 | {"PREDRIVEL", NULL, "PredriveL PGA"}, | |
1417 | {"PREDRIVER", NULL, "PredriveR PGA"}, | |
6943c92e PU |
1418 | {"HSOL", NULL, "HeadsetL PGA"}, |
1419 | {"HSOR", NULL, "HeadsetR PGA"}, | |
9008adf9 PU |
1420 | {"CARKITL", NULL, "CarkitL PGA"}, |
1421 | {"CARKITR", NULL, "CarkitR PGA"}, | |
5a2e9a48 PU |
1422 | {"HFL", NULL, "HandsfreeL PGA"}, |
1423 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1424 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1425 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1426 | |
276c6222 | 1427 | /* Capture path */ |
9028935d PU |
1428 | {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, |
1429 | {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, | |
1430 | {"Analog Left", "AUXL Capture Switch", "AUXL"}, | |
1431 | {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, | |
276c6222 | 1432 | |
9028935d PU |
1433 | {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, |
1434 | {"Analog Right", "AUXR Capture Switch", "AUXR"}, | |
276c6222 | 1435 | |
9028935d PU |
1436 | {"ADC Physical Left", NULL, "Analog Left"}, |
1437 | {"ADC Physical Right", NULL, "Analog Right"}, | |
276c6222 PU |
1438 | |
1439 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1440 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1441 | ||
1442 | /* TX1 Left capture path */ | |
fb2a2f84 | 1443 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1444 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1445 | /* TX1 Right capture path */ | |
fb2a2f84 | 1446 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1447 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1448 | /* TX2 Left capture path */ | |
fb2a2f84 | 1449 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1450 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1451 | /* TX2 Right capture path */ | |
fb2a2f84 | 1452 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1453 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1454 | ||
1455 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1456 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1457 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1458 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1459 | ||
1c3d2002 PU |
1460 | {"ADC Virtual Left1", NULL, "APLL Enable"}, |
1461 | {"ADC Virtual Right1", NULL, "APLL Enable"}, | |
1462 | {"ADC Virtual Left2", NULL, "APLL Enable"}, | |
1463 | {"ADC Virtual Right2", NULL, "APLL Enable"}, | |
1464 | ||
c42a59ea PU |
1465 | {"ADC Virtual Left1", NULL, "AIF Enable"}, |
1466 | {"ADC Virtual Right1", NULL, "AIF Enable"}, | |
1467 | {"ADC Virtual Left2", NULL, "AIF Enable"}, | |
1468 | {"ADC Virtual Right2", NULL, "AIF Enable"}, | |
1469 | ||
7393958f | 1470 | /* Analog bypass routes */ |
9028935d PU |
1471 | {"Right1 Analog Loopback", "Switch", "Analog Right"}, |
1472 | {"Left1 Analog Loopback", "Switch", "Analog Left"}, | |
1473 | {"Right2 Analog Loopback", "Switch", "Analog Right"}, | |
1474 | {"Left2 Analog Loopback", "Switch", "Analog Left"}, | |
1475 | {"Voice Analog Loopback", "Switch", "Analog Left"}, | |
7393958f | 1476 | |
78e08e2f PU |
1477 | /* Supply for the Analog loopbacks */ |
1478 | {"Right1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1479 | {"Left1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1480 | {"Right2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1481 | {"Left2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1482 | {"Voice Analog Loopback", NULL, "FM Loop Enable"}, | |
1483 | ||
7393958f PU |
1484 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, |
1485 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1486 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1487 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1488 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1489 | |
6bab83fd PU |
1490 | /* Digital bypass routes */ |
1491 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1492 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1493 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1494 | |
4005d39a PU |
1495 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1496 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1497 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1498 | |
cc17557e SS |
1499 | }; |
1500 | ||
1501 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
1502 | { | |
1503 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
1504 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
1505 | ||
1506 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
1507 | ||
cc17557e SS |
1508 | return 0; |
1509 | } | |
1510 | ||
cc17557e SS |
1511 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1512 | enum snd_soc_bias_level level) | |
1513 | { | |
1514 | switch (level) { | |
1515 | case SND_SOC_BIAS_ON: | |
cc17557e SS |
1516 | break; |
1517 | case SND_SOC_BIAS_PREPARE: | |
cc17557e SS |
1518 | break; |
1519 | case SND_SOC_BIAS_STANDBY: | |
78e08e2f PU |
1520 | if (codec->bias_level == SND_SOC_BIAS_OFF) |
1521 | twl4030_power_up(codec); | |
cc17557e SS |
1522 | break; |
1523 | case SND_SOC_BIAS_OFF: | |
1524 | twl4030_power_down(codec); | |
1525 | break; | |
1526 | } | |
1527 | codec->bias_level = level; | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
6b87a91f PU |
1532 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1533 | struct snd_pcm_substream *mst_substream) | |
1534 | { | |
1535 | struct snd_pcm_substream *slv_substream; | |
1536 | ||
1537 | /* Pick the stream, which need to be constrained */ | |
1538 | if (mst_substream == twl4030->master_substream) | |
1539 | slv_substream = twl4030->slave_substream; | |
1540 | else if (mst_substream == twl4030->slave_substream) | |
1541 | slv_substream = twl4030->master_substream; | |
1542 | else /* This should not happen.. */ | |
1543 | return; | |
1544 | ||
1545 | /* Set the constraints according to the already configured stream */ | |
1546 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1547 | SNDRV_PCM_HW_PARAM_RATE, | |
1548 | twl4030->rate, | |
1549 | twl4030->rate); | |
1550 | ||
1551 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1552 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1553 | twl4030->sample_bits, | |
1554 | twl4030->sample_bits); | |
1555 | ||
1556 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1557 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1558 | twl4030->channels, | |
1559 | twl4030->channels); | |
1560 | } | |
1561 | ||
8a1f936a PU |
1562 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1563 | * capture has to be enabled/disabled. */ | |
1564 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
1565 | int enable) | |
1566 | { | |
1567 | u8 reg, mask; | |
1568 | ||
1569 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1570 | ||
1571 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1572 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1573 | else | |
1574 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1575 | ||
1576 | if (enable) | |
1577 | reg |= mask; | |
1578 | else | |
1579 | reg &= ~mask; | |
1580 | ||
1581 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1582 | } | |
1583 | ||
d6648da1 PU |
1584 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1585 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1586 | { |
1587 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1588 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1589 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 PU |
1590 | struct twl4030_priv *twl4030 = codec->private_data; |
1591 | ||
7220b9f4 | 1592 | if (twl4030->master_substream) { |
7220b9f4 | 1593 | twl4030->slave_substream = substream; |
6b87a91f PU |
1594 | /* The DAI has one configuration for playback and capture, so |
1595 | * if the DAI has been already configured then constrain this | |
1596 | * substream to match it. */ | |
1597 | if (twl4030->configured) | |
1598 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1599 | } else { | |
8a1f936a PU |
1600 | if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) & |
1601 | TWL4030_OPTION_1)) { | |
1602 | /* In option2 4 channel is not supported, set the | |
1603 | * constraint for the first stream for channels, the | |
1604 | * second stream will 'inherit' this cosntraint */ | |
1605 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1606 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1607 | 2, 2); | |
1608 | } | |
7220b9f4 | 1609 | twl4030->master_substream = substream; |
6b87a91f | 1610 | } |
7220b9f4 PU |
1611 | |
1612 | return 0; | |
1613 | } | |
1614 | ||
d6648da1 PU |
1615 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1616 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1617 | { |
1618 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1619 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1620 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 PU |
1621 | struct twl4030_priv *twl4030 = codec->private_data; |
1622 | ||
1623 | if (twl4030->master_substream == substream) | |
1624 | twl4030->master_substream = twl4030->slave_substream; | |
1625 | ||
1626 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1627 | |
1628 | /* If all streams are closed, or the remaining stream has not yet | |
1629 | * been configured than set the DAI as not configured. */ | |
1630 | if (!twl4030->master_substream) | |
1631 | twl4030->configured = 0; | |
1632 | else if (!twl4030->master_substream->runtime->channels) | |
1633 | twl4030->configured = 0; | |
8a1f936a PU |
1634 | |
1635 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1636 | if (substream->runtime->channels == 4) | |
1637 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1638 | } |
1639 | ||
cc17557e | 1640 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1641 | struct snd_pcm_hw_params *params, |
1642 | struct snd_soc_dai *dai) | |
cc17557e SS |
1643 | { |
1644 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1645 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1646 | struct snd_soc_codec *codec = socdev->card->codec; |
7220b9f4 | 1647 | struct twl4030_priv *twl4030 = codec->private_data; |
cc17557e SS |
1648 | u8 mode, old_mode, format, old_format; |
1649 | ||
8a1f936a PU |
1650 | /* If the substream has 4 channel, do the necessary setup */ |
1651 | if (params_channels(params) == 4) { | |
eaf1ac8b PU |
1652 | format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); |
1653 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
1654 | ||
1655 | /* Safety check: are we in the correct operating mode and | |
1656 | * the interface is in TDM mode? */ | |
1657 | if ((mode & TWL4030_OPTION_1) && | |
1658 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1659 | twl4030_tdm_enable(codec, substream->stream, 1); |
1660 | else | |
1661 | return -EINVAL; | |
1662 | } | |
1663 | ||
6b87a91f PU |
1664 | if (twl4030->configured) |
1665 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1666 | return 0; |
1667 | ||
cc17557e SS |
1668 | /* bit rate */ |
1669 | old_mode = twl4030_read_reg_cache(codec, | |
1670 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
1671 | mode = old_mode & ~TWL4030_APLL_RATE; | |
1672 | ||
1673 | switch (params_rate(params)) { | |
1674 | case 8000: | |
1675 | mode |= TWL4030_APLL_RATE_8000; | |
1676 | break; | |
1677 | case 11025: | |
1678 | mode |= TWL4030_APLL_RATE_11025; | |
1679 | break; | |
1680 | case 12000: | |
1681 | mode |= TWL4030_APLL_RATE_12000; | |
1682 | break; | |
1683 | case 16000: | |
1684 | mode |= TWL4030_APLL_RATE_16000; | |
1685 | break; | |
1686 | case 22050: | |
1687 | mode |= TWL4030_APLL_RATE_22050; | |
1688 | break; | |
1689 | case 24000: | |
1690 | mode |= TWL4030_APLL_RATE_24000; | |
1691 | break; | |
1692 | case 32000: | |
1693 | mode |= TWL4030_APLL_RATE_32000; | |
1694 | break; | |
1695 | case 44100: | |
1696 | mode |= TWL4030_APLL_RATE_44100; | |
1697 | break; | |
1698 | case 48000: | |
1699 | mode |= TWL4030_APLL_RATE_48000; | |
1700 | break; | |
103f211d PU |
1701 | case 96000: |
1702 | mode |= TWL4030_APLL_RATE_96000; | |
1703 | break; | |
cc17557e SS |
1704 | default: |
1705 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
1706 | params_rate(params)); | |
1707 | return -EINVAL; | |
1708 | } | |
1709 | ||
1710 | if (mode != old_mode) { | |
1711 | /* change rate and set CODECPDZ */ | |
7393958f | 1712 | twl4030_codec_enable(codec, 0); |
cc17557e | 1713 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
db04e2c5 | 1714 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1715 | } |
1716 | ||
1717 | /* sample size */ | |
1718 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1719 | format = old_format; | |
1720 | format &= ~TWL4030_DATA_WIDTH; | |
1721 | switch (params_format(params)) { | |
1722 | case SNDRV_PCM_FORMAT_S16_LE: | |
1723 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1724 | break; | |
1725 | case SNDRV_PCM_FORMAT_S24_LE: | |
1726 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
1727 | break; | |
1728 | default: | |
1729 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
1730 | params_format(params)); | |
1731 | return -EINVAL; | |
1732 | } | |
1733 | ||
1734 | if (format != old_format) { | |
1735 | ||
1736 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1737 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1738 | |
1739 | /* change format */ | |
1740 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1741 | ||
1742 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1743 | twl4030_codec_enable(codec, 1); |
cc17557e | 1744 | } |
6b87a91f PU |
1745 | |
1746 | /* Store the important parameters for the DAI configuration and set | |
1747 | * the DAI as configured */ | |
1748 | twl4030->configured = 1; | |
1749 | twl4030->rate = params_rate(params); | |
1750 | twl4030->sample_bits = hw_param_interval(params, | |
1751 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1752 | twl4030->channels = params_channels(params); | |
1753 | ||
1754 | /* If both playback and capture streams are open, and one of them | |
1755 | * is setting the hw parameters right now (since we are here), set | |
1756 | * constraints to the other stream to match the current one. */ | |
1757 | if (twl4030->slave_substream) | |
1758 | twl4030_constraints(twl4030, substream); | |
1759 | ||
cc17557e SS |
1760 | return 0; |
1761 | } | |
1762 | ||
1763 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1764 | int clk_id, unsigned int freq, int dir) | |
1765 | { | |
1766 | struct snd_soc_codec *codec = codec_dai->codec; | |
6943c92e | 1767 | struct twl4030_priv *twl4030 = codec->private_data; |
cc17557e SS |
1768 | |
1769 | switch (freq) { | |
1770 | case 19200000: | |
cc17557e | 1771 | case 26000000: |
cc17557e | 1772 | case 38400000: |
cc17557e SS |
1773 | break; |
1774 | default: | |
68d01955 | 1775 | dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq); |
cc17557e SS |
1776 | return -EINVAL; |
1777 | } | |
1778 | ||
68d01955 PU |
1779 | if ((freq / 1000) != twl4030->sysclk) { |
1780 | dev_err(codec->dev, | |
1781 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
1782 | freq, twl4030->sysclk * 1000); | |
1783 | return -EINVAL; | |
1784 | } | |
cc17557e SS |
1785 | |
1786 | return 0; | |
1787 | } | |
1788 | ||
1789 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1790 | unsigned int fmt) | |
1791 | { | |
1792 | struct snd_soc_codec *codec = codec_dai->codec; | |
1793 | u8 old_format, format; | |
1794 | ||
1795 | /* get format */ | |
1796 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1797 | format = old_format; | |
1798 | ||
1799 | /* set master/slave audio interface */ | |
1800 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1801 | case SND_SOC_DAIFMT_CBM_CFM: | |
1802 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1803 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1804 | break; |
1805 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1806 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1807 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1808 | break; |
1809 | default: | |
1810 | return -EINVAL; | |
1811 | } | |
1812 | ||
1813 | /* interface format */ | |
1814 | format &= ~TWL4030_AIF_FORMAT; | |
1815 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1816 | case SND_SOC_DAIFMT_I2S: | |
1817 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1818 | break; | |
8a1f936a PU |
1819 | case SND_SOC_DAIFMT_DSP_A: |
1820 | format |= TWL4030_AIF_FORMAT_TDM; | |
1821 | break; | |
cc17557e SS |
1822 | default: |
1823 | return -EINVAL; | |
1824 | } | |
1825 | ||
1826 | if (format != old_format) { | |
1827 | ||
1828 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1829 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1830 | |
1831 | /* change format */ | |
1832 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1833 | ||
1834 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1835 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1836 | } |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
68140443 LCM |
1841 | static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) |
1842 | { | |
1843 | struct snd_soc_codec *codec = dai->codec; | |
1844 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1845 | ||
1846 | if (tristate) | |
1847 | reg |= TWL4030_AIF_TRI_EN; | |
1848 | else | |
1849 | reg &= ~TWL4030_AIF_TRI_EN; | |
1850 | ||
1851 | return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); | |
1852 | } | |
1853 | ||
b7a755a8 MLC |
1854 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1855 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1856 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
1857 | int enable) | |
1858 | { | |
1859 | u8 reg, mask; | |
1860 | ||
1861 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1862 | ||
1863 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1864 | mask = TWL4030_ARXL1_VRX_EN; | |
1865 | else | |
1866 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1867 | ||
1868 | if (enable) | |
1869 | reg |= mask; | |
1870 | else | |
1871 | reg &= ~mask; | |
1872 | ||
1873 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1874 | } | |
1875 | ||
7154b3e8 JS |
1876 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
1877 | struct snd_soc_dai *dai) | |
1878 | { | |
1879 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1880 | struct snd_soc_device *socdev = rtd->socdev; | |
1881 | struct snd_soc_codec *codec = socdev->card->codec; | |
68d01955 | 1882 | struct twl4030_priv *twl4030 = codec->private_data; |
7154b3e8 JS |
1883 | u8 mode; |
1884 | ||
1885 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
1886 | * not avilable. | |
1887 | */ | |
68d01955 PU |
1888 | if (twl4030->sysclk != 26000) { |
1889 | dev_err(codec->dev, "The board is configured for %u Hz, while" | |
1890 | "the Voice interface needs 26MHz APLL mclk\n", | |
1891 | twl4030->sysclk * 1000); | |
7154b3e8 JS |
1892 | return -EINVAL; |
1893 | } | |
1894 | ||
1895 | /* If the codec mode is not option2, the voice PCM interface is not | |
1896 | * avilable. | |
1897 | */ | |
1898 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1899 | & TWL4030_OPT_MODE; | |
1900 | ||
1901 | if (mode != TWL4030_OPTION_2) { | |
1902 | printk(KERN_ERR "TWL4030 voice startup: " | |
1903 | "the codec mode is not option2\n"); | |
1904 | return -EINVAL; | |
1905 | } | |
1906 | ||
1907 | return 0; | |
1908 | } | |
1909 | ||
b7a755a8 MLC |
1910 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
1911 | struct snd_soc_dai *dai) | |
1912 | { | |
1913 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1914 | struct snd_soc_device *socdev = rtd->socdev; | |
1915 | struct snd_soc_codec *codec = socdev->card->codec; | |
1916 | ||
1917 | /* Enable voice digital filters */ | |
1918 | twl4030_voice_enable(codec, substream->stream, 0); | |
1919 | } | |
1920 | ||
7154b3e8 JS |
1921 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
1922 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1923 | { | |
1924 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1925 | struct snd_soc_device *socdev = rtd->socdev; | |
1926 | struct snd_soc_codec *codec = socdev->card->codec; | |
1927 | u8 old_mode, mode; | |
1928 | ||
b7a755a8 MLC |
1929 | /* Enable voice digital filters */ |
1930 | twl4030_voice_enable(codec, substream->stream, 1); | |
1931 | ||
7154b3e8 JS |
1932 | /* bit rate */ |
1933 | old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1934 | & ~(TWL4030_CODECPDZ); | |
1935 | mode = old_mode; | |
1936 | ||
1937 | switch (params_rate(params)) { | |
1938 | case 8000: | |
1939 | mode &= ~(TWL4030_SEL_16K); | |
1940 | break; | |
1941 | case 16000: | |
1942 | mode |= TWL4030_SEL_16K; | |
1943 | break; | |
1944 | default: | |
1945 | printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n", | |
1946 | params_rate(params)); | |
1947 | return -EINVAL; | |
1948 | } | |
1949 | ||
1950 | if (mode != old_mode) { | |
1951 | /* change rate and set CODECPDZ */ | |
1952 | twl4030_codec_enable(codec, 0); | |
1953 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1954 | twl4030_codec_enable(codec, 1); | |
1955 | } | |
1956 | ||
1957 | return 0; | |
1958 | } | |
1959 | ||
1960 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1961 | int clk_id, unsigned int freq, int dir) | |
1962 | { | |
1963 | struct snd_soc_codec *codec = codec_dai->codec; | |
68d01955 | 1964 | struct twl4030_priv *twl4030 = codec->private_data; |
7154b3e8 | 1965 | |
68d01955 PU |
1966 | if (freq != 26000000) { |
1967 | dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice" | |
1968 | "interface needs 26MHz APLL mclk\n", freq); | |
1969 | return -EINVAL; | |
1970 | } | |
1971 | if ((freq / 1000) != twl4030->sysclk) { | |
1972 | dev_err(codec->dev, | |
1973 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
1974 | freq, twl4030->sysclk * 1000); | |
7154b3e8 JS |
1975 | return -EINVAL; |
1976 | } | |
7154b3e8 JS |
1977 | return 0; |
1978 | } | |
1979 | ||
1980 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1981 | unsigned int fmt) | |
1982 | { | |
1983 | struct snd_soc_codec *codec = codec_dai->codec; | |
1984 | u8 old_format, format; | |
1985 | ||
1986 | /* get format */ | |
1987 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
1988 | format = old_format; | |
1989 | ||
1990 | /* set master/slave audio interface */ | |
1991 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 1992 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
1993 | format &= ~(TWL4030_VIF_SLAVE_EN); |
1994 | break; | |
1995 | case SND_SOC_DAIFMT_CBS_CFS: | |
1996 | format |= TWL4030_VIF_SLAVE_EN; | |
1997 | break; | |
1998 | default: | |
1999 | return -EINVAL; | |
2000 | } | |
2001 | ||
2002 | /* clock inversion */ | |
2003 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2004 | case SND_SOC_DAIFMT_IB_NF: | |
2005 | format &= ~(TWL4030_VIF_FORMAT); | |
2006 | break; | |
2007 | case SND_SOC_DAIFMT_NB_IF: | |
2008 | format |= TWL4030_VIF_FORMAT; | |
2009 | break; | |
2010 | default: | |
2011 | return -EINVAL; | |
2012 | } | |
2013 | ||
2014 | if (format != old_format) { | |
2015 | /* change format and set CODECPDZ */ | |
2016 | twl4030_codec_enable(codec, 0); | |
2017 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2018 | twl4030_codec_enable(codec, 1); | |
2019 | } | |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
68140443 LCM |
2024 | static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) |
2025 | { | |
2026 | struct snd_soc_codec *codec = dai->codec; | |
2027 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
2028 | ||
2029 | if (tristate) | |
2030 | reg |= TWL4030_VIF_TRI_EN; | |
2031 | else | |
2032 | reg &= ~TWL4030_VIF_TRI_EN; | |
2033 | ||
2034 | return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); | |
2035 | } | |
2036 | ||
bbba9444 | 2037 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
2038 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
2039 | ||
10d9e3d9 | 2040 | static struct snd_soc_dai_ops twl4030_dai_ops = { |
7220b9f4 PU |
2041 | .startup = twl4030_startup, |
2042 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
2043 | .hw_params = twl4030_hw_params, |
2044 | .set_sysclk = twl4030_set_dai_sysclk, | |
2045 | .set_fmt = twl4030_set_dai_fmt, | |
68140443 | 2046 | .set_tristate = twl4030_set_tristate, |
10d9e3d9 JS |
2047 | }; |
2048 | ||
7154b3e8 JS |
2049 | static struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
2050 | .startup = twl4030_voice_startup, | |
b7a755a8 | 2051 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
2052 | .hw_params = twl4030_voice_hw_params, |
2053 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
2054 | .set_fmt = twl4030_voice_set_dai_fmt, | |
68140443 | 2055 | .set_tristate = twl4030_voice_set_tristate, |
7154b3e8 JS |
2056 | }; |
2057 | ||
2058 | struct snd_soc_dai twl4030_dai[] = { | |
2059 | { | |
cc17557e SS |
2060 | .name = "twl4030", |
2061 | .playback = { | |
b4852b79 | 2062 | .stream_name = "HiFi Playback", |
cc17557e | 2063 | .channels_min = 2, |
8a1f936a | 2064 | .channels_max = 4, |
31ad0f31 | 2065 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
cc17557e SS |
2066 | .formats = TWL4030_FORMATS,}, |
2067 | .capture = { | |
2068 | .stream_name = "Capture", | |
2069 | .channels_min = 2, | |
8a1f936a | 2070 | .channels_max = 4, |
cc17557e SS |
2071 | .rates = TWL4030_RATES, |
2072 | .formats = TWL4030_FORMATS,}, | |
10d9e3d9 | 2073 | .ops = &twl4030_dai_ops, |
7154b3e8 JS |
2074 | }, |
2075 | { | |
2076 | .name = "twl4030 Voice", | |
2077 | .playback = { | |
b4852b79 | 2078 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2079 | .channels_min = 1, |
2080 | .channels_max = 1, | |
2081 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2082 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2083 | .capture = { | |
2084 | .stream_name = "Capture", | |
2085 | .channels_min = 1, | |
2086 | .channels_max = 2, | |
2087 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2088 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2089 | .ops = &twl4030_dai_voice_ops, | |
2090 | }, | |
cc17557e SS |
2091 | }; |
2092 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
2093 | ||
7a1fecf5 | 2094 | static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state) |
cc17557e SS |
2095 | { |
2096 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2097 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2098 | |
2099 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2100 | ||
2101 | return 0; | |
2102 | } | |
2103 | ||
7a1fecf5 | 2104 | static int twl4030_soc_resume(struct platform_device *pdev) |
cc17557e SS |
2105 | { |
2106 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2107 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2108 | |
2109 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2110 | twl4030_set_bias_level(codec, codec->suspend_bias_level); | |
2111 | return 0; | |
2112 | } | |
2113 | ||
7a1fecf5 | 2114 | static struct snd_soc_codec *twl4030_codec; |
cc17557e | 2115 | |
7a1fecf5 | 2116 | static int twl4030_soc_probe(struct platform_device *pdev) |
cc17557e | 2117 | { |
7a1fecf5 | 2118 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
9da28c7b | 2119 | struct twl4030_setup_data *setup = socdev->codec_data; |
7a1fecf5 PU |
2120 | struct snd_soc_codec *codec; |
2121 | struct twl4030_priv *twl4030; | |
2122 | int ret; | |
cc17557e | 2123 | |
7a1fecf5 | 2124 | BUG_ON(!twl4030_codec); |
cc17557e | 2125 | |
7a1fecf5 PU |
2126 | codec = twl4030_codec; |
2127 | twl4030 = codec->private_data; | |
2128 | socdev->card->codec = codec; | |
cc17557e | 2129 | |
9da28c7b PU |
2130 | /* Configuration for headset ramp delay from setup data */ |
2131 | if (setup) { | |
2132 | unsigned char hs_pop; | |
2133 | ||
68d01955 PU |
2134 | if (setup->sysclk != twl4030->sysclk) |
2135 | dev_warn(&pdev->dev, | |
2136 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
2137 | setup->sysclk, twl4030->sysclk); | |
9da28c7b PU |
2138 | |
2139 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
2140 | hs_pop &= ~TWL4030_RAMP_DELAY; | |
2141 | hs_pop |= (setup->ramp_delay_value << 2); | |
2142 | twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
9da28c7b PU |
2143 | } |
2144 | ||
cc17557e SS |
2145 | /* register pcms */ |
2146 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
2147 | if (ret < 0) { | |
7a1fecf5 PU |
2148 | dev_err(&pdev->dev, "failed to create pcms\n"); |
2149 | return ret; | |
cc17557e SS |
2150 | } |
2151 | ||
3e8e1952 IM |
2152 | snd_soc_add_controls(codec, twl4030_snd_controls, |
2153 | ARRAY_SIZE(twl4030_snd_controls)); | |
cc17557e SS |
2154 | twl4030_add_widgets(codec); |
2155 | ||
7a1fecf5 | 2156 | return 0; |
cc17557e SS |
2157 | } |
2158 | ||
7a1fecf5 | 2159 | static int twl4030_soc_remove(struct platform_device *pdev) |
cc17557e SS |
2160 | { |
2161 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
7a1fecf5 PU |
2162 | struct snd_soc_codec *codec = socdev->card->codec; |
2163 | ||
2164 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2165 | snd_soc_free_pcms(socdev); | |
2166 | snd_soc_dapm_free(socdev); | |
7a1fecf5 PU |
2167 | |
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | static int __devinit twl4030_codec_probe(struct platform_device *pdev) | |
2172 | { | |
2173 | struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data; | |
cc17557e | 2174 | struct snd_soc_codec *codec; |
7393958f | 2175 | struct twl4030_priv *twl4030; |
7a1fecf5 | 2176 | int ret; |
cc17557e | 2177 | |
68d01955 PU |
2178 | if (!pdata) { |
2179 | dev_err(&pdev->dev, "platform_data is missing\n"); | |
7a1fecf5 PU |
2180 | return -EINVAL; |
2181 | } | |
cc17557e | 2182 | |
7393958f PU |
2183 | twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); |
2184 | if (twl4030 == NULL) { | |
7a1fecf5 | 2185 | dev_err(&pdev->dev, "Can not allocate memroy\n"); |
7393958f PU |
2186 | return -ENOMEM; |
2187 | } | |
2188 | ||
7a1fecf5 | 2189 | codec = &twl4030->codec; |
7393958f | 2190 | codec->private_data = twl4030; |
7a1fecf5 PU |
2191 | codec->dev = &pdev->dev; |
2192 | twl4030_dai[0].dev = &pdev->dev; | |
2193 | twl4030_dai[1].dev = &pdev->dev; | |
2194 | ||
cc17557e SS |
2195 | mutex_init(&codec->mutex); |
2196 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
2197 | INIT_LIST_HEAD(&codec->dapm_paths); | |
2198 | ||
7a1fecf5 PU |
2199 | codec->name = "twl4030"; |
2200 | codec->owner = THIS_MODULE; | |
2201 | codec->read = twl4030_read_reg_cache; | |
2202 | codec->write = twl4030_write; | |
2203 | codec->set_bias_level = twl4030_set_bias_level; | |
2204 | codec->dai = twl4030_dai; | |
fd63df22 | 2205 | codec->num_dai = ARRAY_SIZE(twl4030_dai); |
7a1fecf5 PU |
2206 | codec->reg_cache_size = sizeof(twl4030_reg); |
2207 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
2208 | GFP_KERNEL); | |
2209 | if (codec->reg_cache == NULL) { | |
2210 | ret = -ENOMEM; | |
2211 | goto error_cache; | |
2212 | } | |
2213 | ||
2214 | platform_set_drvdata(pdev, twl4030); | |
2215 | twl4030_codec = codec; | |
2216 | ||
2217 | /* Set the defaults, and power up the codec */ | |
68d01955 | 2218 | twl4030->sysclk = twl4030_codec_get_mclk() / 1000; |
7a1fecf5 | 2219 | twl4030_init_chip(codec); |
b3f5a272 | 2220 | codec->bias_level = SND_SOC_BIAS_OFF; |
7a1fecf5 PU |
2221 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2222 | ||
2223 | ret = snd_soc_register_codec(codec); | |
2224 | if (ret != 0) { | |
2225 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
2226 | goto error_codec; | |
2227 | } | |
2228 | ||
2229 | ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); | |
2230 | if (ret != 0) { | |
2231 | dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); | |
2232 | snd_soc_unregister_codec(codec); | |
2233 | goto error_codec; | |
2234 | } | |
cc17557e SS |
2235 | |
2236 | return 0; | |
7a1fecf5 PU |
2237 | |
2238 | error_codec: | |
2239 | twl4030_power_down(codec); | |
2240 | kfree(codec->reg_cache); | |
2241 | error_cache: | |
2242 | kfree(twl4030); | |
2243 | return ret; | |
cc17557e SS |
2244 | } |
2245 | ||
7a1fecf5 | 2246 | static int __devexit twl4030_codec_remove(struct platform_device *pdev) |
cc17557e | 2247 | { |
7a1fecf5 | 2248 | struct twl4030_priv *twl4030 = platform_get_drvdata(pdev); |
cc17557e | 2249 | |
cb67286d PU |
2250 | snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); |
2251 | snd_soc_unregister_codec(&twl4030->codec); | |
2252 | kfree(twl4030->codec.reg_cache); | |
7a1fecf5 | 2253 | kfree(twl4030); |
cc17557e | 2254 | |
7a1fecf5 | 2255 | twl4030_codec = NULL; |
cc17557e SS |
2256 | return 0; |
2257 | } | |
2258 | ||
7a1fecf5 PU |
2259 | MODULE_ALIAS("platform:twl4030_codec_audio"); |
2260 | ||
2261 | static struct platform_driver twl4030_codec_driver = { | |
2262 | .probe = twl4030_codec_probe, | |
2263 | .remove = __devexit_p(twl4030_codec_remove), | |
2264 | .driver = { | |
2265 | .name = "twl4030_codec_audio", | |
2266 | .owner = THIS_MODULE, | |
2267 | }, | |
cc17557e | 2268 | }; |
cc17557e | 2269 | |
24e07db8 | 2270 | static int __init twl4030_modinit(void) |
64089b84 | 2271 | { |
7a1fecf5 | 2272 | return platform_driver_register(&twl4030_codec_driver); |
64089b84 | 2273 | } |
24e07db8 | 2274 | module_init(twl4030_modinit); |
64089b84 MB |
2275 | |
2276 | static void __exit twl4030_exit(void) | |
2277 | { | |
7a1fecf5 | 2278 | platform_driver_unregister(&twl4030_codec_driver); |
64089b84 MB |
2279 | } |
2280 | module_exit(twl4030_exit); | |
2281 | ||
7a1fecf5 PU |
2282 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { |
2283 | .probe = twl4030_soc_probe, | |
2284 | .remove = twl4030_soc_remove, | |
2285 | .suspend = twl4030_soc_suspend, | |
2286 | .resume = twl4030_soc_resume, | |
2287 | }; | |
2288 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
2289 | ||
cc17557e SS |
2290 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2291 | MODULE_AUTHOR("Steve Sakoman"); | |
2292 | MODULE_LICENSE("GPL"); |