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ASoC: add output/input widgets in ad1938 to make dac/adc dynamic PM work
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
d08664fd 148 u8 *cache = codec->reg_cache;
cc17557e 149
91432e97
IM		 150 if (reg >= TWL4030_CACHEREGNUM)
151 return -EIO;
152
cc17557e
SS		 153 return cache[reg];
154}
155
156/*
157 * write twl4030 register cache
158 */
159static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
160 u8 reg, u8 value)
161{
162 u8 *cache = codec->reg_cache;
163
164 if (reg >= TWL4030_CACHEREGNUM)
165 return;
166 cache[reg] = value;
167}
168
169/*
170 * write to the twl4030 register space
171 */
172static int twl4030_write(struct snd_soc_codec *codec,
173 unsigned int reg, unsigned int value)
174{
175 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
cc17557e
SS		 181}
182
db04e2c5 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 184{
7393958f 185 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 186 u8 mode;
187
7393958f
PU		 188 if (enable == twl4030->codec_powered)
189 return;
190
cc17557e 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 192 if (enable)
193 mode |= TWL4030_CODECPDZ;
194 else
195 mode &= ~TWL4030_CODECPDZ;
cc17557e 196
db04e2c5 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 198 twl4030->codec_powered = enable;
cc17557e
SS		 199
200 /* REVISIT: this delay is present in TI sample drivers */
201 /* but there seems to be no TRM requirement for it */
202 udelay(10);
203}
204
205static void twl4030_init_chip(struct snd_soc_codec *codec)
206{
16a30fbb 207 u8 *cache = codec->reg_cache;
cc17557e
SS		 208 int i;
209
210 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 211 twl4030_codec_enable(codec, 0);
cc17557e
SS		 212
213 /* set all audio section registers to reasonable defaults */
214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 215 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 216
217}
218
7393958f
PU		 219static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
220{
221 struct twl4030_priv *twl4030 = codec->private_data;
222 u8 reg_val;
223
224 if (mute == twl4030->codec_muted)
225 return;
226
227 if (mute) {
228 /* Bypass the reg_cache and mute the volumes
229 * Headset mute is done in it's own event handler
230 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
231 */
232 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
233 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
234 reg_val & (~TWL4030_EAR_GAIN),
235 TWL4030_REG_EAR_CTL);
236
237 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
238 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
239 reg_val & (~TWL4030_PREDL_GAIN),
240 TWL4030_REG_PREDL_CTL);
241 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
242 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
243 reg_val & (~TWL4030_PREDR_GAIN),
244 TWL4030_REG_PREDL_CTL);
245
246 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
247 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
248 reg_val & (~TWL4030_PRECKL_GAIN),
249 TWL4030_REG_PRECKL_CTL);
250 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
251 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 252 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 253 TWL4030_REG_PRECKR_CTL);
254
255 /* Disable PLL */
256 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
257 reg_val &= ~TWL4030_APLL_EN;
258 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
259 } else {
260 /* Restore the volumes
261 * Headset mute is done in it's own event handler
262 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
263 */
264 twl4030_write(codec, TWL4030_REG_EAR_CTL,
265 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
266
267 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
268 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
269 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
270 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
271
272 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
273 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
274 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
275 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
276
277 /* Enable PLL */
278 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
279 reg_val |= TWL4030_APLL_EN;
280 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
281 }
282
283 twl4030->codec_muted = mute;
284}
285
006f367e
PU		 286static void twl4030_power_up(struct snd_soc_codec *codec)
287{
7393958f 288 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 289 u8 anamicl, regmisc1, byte;
290 int i = 0;
291
7393958f
PU		 292 if (twl4030->codec_powered)
293 return;
294
006f367e
PU		 295 /* set CODECPDZ to turn on codec */
296 twl4030_codec_enable(codec, 1);
297
298 /* initiate offset cancellation */
299 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
300 twl4030_write(codec, TWL4030_REG_ANAMICL,
301 anamicl | TWL4030_CNCL_OFFSET_START);
302
303 /* wait for offset cancellation to complete */
304 do {
305 /* this takes a little while, so don't slam i2c */
306 udelay(2000);
307 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
308 TWL4030_REG_ANAMICL);
309 } while ((i++ < 100) &&
310 ((byte & TWL4030_CNCL_OFFSET_START) ==
311 TWL4030_CNCL_OFFSET_START));
312
313 /* Make sure that the reg_cache has the same value as the HW */
314 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
315
316 /* anti-pop when changing analog gain */
317 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
318 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
319 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
320
321 /* toggle CODECPDZ as per TRM */
322 twl4030_codec_enable(codec, 0);
323 twl4030_codec_enable(codec, 1);
324}
325
7393958f
PU		 326/*
327 * Unconditional power down
328 */
006f367e
PU		 329static void twl4030_power_down(struct snd_soc_codec *codec)
330{
331 /* power down */
332 twl4030_codec_enable(codec, 0);
333}
334
5e98a464 335/* Earpiece */
1a787e7a
JS		 336static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
337 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
338 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
339 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
341};
5e98a464 342
2a6f5c58 343/* PreDrive Left */
1a787e7a
JS		 344static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
345 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
346 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
347 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
348 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
349};
2a6f5c58
PU		 350
351/* PreDrive Right */
1a787e7a
JS		 352static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
353 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
354 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
355 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
356 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
357};
2a6f5c58 358
dfad21a2 359/* Headset Left */
1a787e7a
JS		 360static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
361 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
362 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
363 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
364};
dfad21a2
PU		 365
366/* Headset Right */
1a787e7a
JS		 367static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
368 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
369 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
370 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
371};
dfad21a2 372
5152d8c2 373/* Carkit Left */
1a787e7a
JS		 374static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
375 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
376 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
377 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
378};
5152d8c2
PU		 379
380/* Carkit Right */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
385};
5152d8c2 386
df339804
PU		 387/* Handsfree Left */
388static const char *twl4030_handsfreel_texts[] =
1a787e7a 389 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 390
391static const struct soc_enum twl4030_handsfreel_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreel_texts),
394 twl4030_handsfreel_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
397SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
398
0f89bdca
PU		 399/* Handsfree Left virtual mute */
400static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
401 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
402
df339804
PU		 403/* Handsfree Right */
404static const char *twl4030_handsfreer_texts[] =
1a787e7a 405 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 406
407static const struct soc_enum twl4030_handsfreer_enum =
408 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
409 ARRAY_SIZE(twl4030_handsfreer_texts),
410 twl4030_handsfreer_texts);
411
412static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
413SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
414
0f89bdca
PU		 415/* Handsfree Right virtual mute */
416static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
417 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
418
376f7839
PU		 419/* Vibra */
420/* Vibra audio path selection */
421static const char *twl4030_vibra_texts[] =
422 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
423
424static const struct soc_enum twl4030_vibra_enum =
425 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
426 ARRAY_SIZE(twl4030_vibra_texts),
427 twl4030_vibra_texts);
428
429static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
430SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
431
432/* Vibra path selection: local vibrator (PWM) or audio driven */
433static const char *twl4030_vibrapath_texts[] =
434 {"Local vibrator", "Audio"};
435
436static const struct soc_enum twl4030_vibrapath_enum =
437 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
438 ARRAY_SIZE(twl4030_vibrapath_texts),
439 twl4030_vibrapath_texts);
440
441static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
442SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
443
276c6222 444/* Left analog microphone selection */
97b8096d
JS		 445static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
446 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
447 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
448 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
449 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
450};
276c6222
PU		 451
452/* Right analog microphone selection */
97b8096d
JS		 453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
454 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 455 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 456};
276c6222
PU		 457
458/* TX1 L/R Analog/Digital microphone selection */
459static const char *twl4030_micpathtx1_texts[] =
460 {"Analog", "Digimic0"};
461
462static const struct soc_enum twl4030_micpathtx1_enum =
463 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
464 ARRAY_SIZE(twl4030_micpathtx1_texts),
465 twl4030_micpathtx1_texts);
466
467static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
468SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
469
470/* TX2 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx2_texts[] =
472 {"Analog", "Digimic1"};
473
474static const struct soc_enum twl4030_micpathtx2_enum =
475 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
476 ARRAY_SIZE(twl4030_micpathtx2_texts),
477 twl4030_micpathtx2_texts);
478
479static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
480SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
481
7393958f
PU		 482/* Analog bypass for AudioR1 */
483static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
484 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
485
486/* Analog bypass for AudioL1 */
487static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
488 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
489
490/* Analog bypass for AudioR2 */
491static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
492 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
493
494/* Analog bypass for AudioL2 */
495static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
497
fcd274a3
LCM		 498/* Analog bypass for Voice */
499static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
501
6bab83fd
PU		 502/* Digital bypass gain, 0 mutes the bypass */
503static const unsigned int twl4030_dapm_dbypass_tlv[] = {
504 TLV_DB_RANGE_HEAD(2),
505 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
506 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
507};
508
509/* Digital bypass left (TX1L -> RX2L) */
510static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
511 SOC_DAPM_SINGLE_TLV("Volume",
512 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
513 twl4030_dapm_dbypass_tlv);
514
515/* Digital bypass right (TX1R -> RX2R) */
516static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
517 SOC_DAPM_SINGLE_TLV("Volume",
518 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
519 twl4030_dapm_dbypass_tlv);
520
ee8f6894
LCM		 521/*
522 * Voice Sidetone GAIN volume control:
523 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
524 */
525static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
526
527/* Digital bypass voice: sidetone (VUL -> VDL)*/
528static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
529 SOC_DAPM_SINGLE_TLV("Volume",
530 TWL4030_REG_VSTPGA, 0, 0x29, 0,
531 twl4030_dapm_dbypassv_tlv);
532
276c6222
PU		 533static int micpath_event(struct snd_soc_dapm_widget *w,
534 struct snd_kcontrol *kcontrol, int event)
535{
536 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
537 unsigned char adcmicsel, micbias_ctl;
538
539 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
540 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
541 /* Prepare the bits for the given TX path:
542 * shift_l == 0: TX1 microphone path
543 * shift_l == 2: TX2 microphone path */
544 if (e->shift_l) {
545 /* TX2 microphone path */
546 if (adcmicsel & TWL4030_TX2IN_SEL)
547 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
548 else
549 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
550 } else {
551 /* TX1 microphone path */
552 if (adcmicsel & TWL4030_TX1IN_SEL)
553 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
554 else
555 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
556 }
557
558 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
559
560 return 0;
561}
562
5a2e9a48 563static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 564{
49d92c7d
SM		 565 unsigned char hs_ctl;
566
5a2e9a48 567 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 568
5a2e9a48
PU		 569 if (ramp) {
570 /* HF ramp-up */
571 hs_ctl |= TWL4030_HF_CTL_REF_EN;
572 twl4030_write(codec, reg, hs_ctl);
573 udelay(10);
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 575 twl4030_write(codec, reg, hs_ctl);
576 udelay(40);
49d92c7d 577 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 578 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 579 twl4030_write(codec, reg, hs_ctl);
49d92c7d 580 } else {
5a2e9a48
PU		 581 /* HF ramp-down */
582 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
583 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
584 twl4030_write(codec, reg, hs_ctl);
585 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
586 twl4030_write(codec, reg, hs_ctl);
587 udelay(40);
588 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
589 twl4030_write(codec, reg, hs_ctl);
49d92c7d 590 }
5a2e9a48 591}
49d92c7d 592
5a2e9a48
PU		 593static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
594 struct snd_kcontrol *kcontrol, int event)
595{
596 switch (event) {
597 case SND_SOC_DAPM_POST_PMU:
598 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
599 break;
600 case SND_SOC_DAPM_POST_PMD:
601 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
602 break;
603 }
604 return 0;
605}
606
607static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
608 struct snd_kcontrol *kcontrol, int event)
609{
610 switch (event) {
611 case SND_SOC_DAPM_POST_PMU:
612 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
613 break;
614 case SND_SOC_DAPM_POST_PMD:
615 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
616 break;
617 }
49d92c7d
SM		 618 return 0;
619}
620
6943c92e 621static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 622{
4e49ffd1
CVJ		 623 struct snd_soc_device *socdev = codec->socdev;
624 struct twl4030_setup_data *setup = socdev->codec_data;
625
aad749e5 626 unsigned char hs_gain, hs_pop;
6943c92e
PU		 627 struct twl4030_priv *twl4030 = codec->private_data;
628 /* Base values for ramp delay calculation: 2^19 - 2^26 */
629 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
630 8388608, 16777216, 33554432, 67108864};
aad749e5 631
6943c92e
PU		 632 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
633 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 634
4e49ffd1
CVJ		 635 /* Enable external mute control, this dramatically reduces
636 * the pop-noise */
637 if (setup && setup->hs_extmute) {
638 if (setup->set_hs_extmute) {
639 setup->set_hs_extmute(1);
640 } else {
641 hs_pop |= TWL4030_EXTMUTE;
642 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
643 }
644 }
645
6943c92e
PU		 646 if (ramp) {
647 /* Headset ramp-up according to the TRM */
aad749e5 648 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 649 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
650 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 651 hs_pop |= TWL4030_RAMP_EN;
6943c92e 652 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 653 /* Wait ramp delay time + 1, so the VMID can settle */
654 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
655 twl4030->sysclk) + 1);
6943c92e
PU		 656 } else {
657 /* Headset ramp-down _not_ according to
658 * the TRM, but in a way that it is working */
aad749e5 659 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 660 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
661 /* Wait ramp delay time + 1, so the VMID can settle */
662 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
663 twl4030->sysclk) + 1);
aad749e5
PU		 664 /* Bypass the reg_cache to mute the headset */
665 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
666 hs_gain & (~0x0f),
667 TWL4030_REG_HS_GAIN_SET);
6943c92e 668
aad749e5 669 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 670 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
671 }
4e49ffd1
CVJ		 672
673 /* Disable external mute */
674 if (setup && setup->hs_extmute) {
675 if (setup->set_hs_extmute) {
676 setup->set_hs_extmute(0);
677 } else {
678 hs_pop &= ~TWL4030_EXTMUTE;
679 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
680 }
681 }
6943c92e
PU		 682}
683
684static int headsetlpga_event(struct snd_soc_dapm_widget *w,
685 struct snd_kcontrol *kcontrol, int event)
686{
687 struct twl4030_priv *twl4030 = w->codec->private_data;
688
689 switch (event) {
690 case SND_SOC_DAPM_POST_PMU:
691 /* Do the ramp-up only once */
692 if (!twl4030->hsr_enabled)
693 headset_ramp(w->codec, 1);
694
695 twl4030->hsl_enabled = 1;
696 break;
697 case SND_SOC_DAPM_POST_PMD:
698 /* Do the ramp-down only if both headsetL/R is disabled */
699 if (!twl4030->hsr_enabled)
700 headset_ramp(w->codec, 0);
701
702 twl4030->hsl_enabled = 0;
703 break;
704 }
705 return 0;
706}
707
708static int headsetrpga_event(struct snd_soc_dapm_widget *w,
709 struct snd_kcontrol *kcontrol, int event)
710{
711 struct twl4030_priv *twl4030 = w->codec->private_data;
712
713 switch (event) {
714 case SND_SOC_DAPM_POST_PMU:
715 /* Do the ramp-up only once */
716 if (!twl4030->hsl_enabled)
717 headset_ramp(w->codec, 1);
718
719 twl4030->hsr_enabled = 1;
720 break;
721 case SND_SOC_DAPM_POST_PMD:
722 /* Do the ramp-down only if both headsetL/R is disabled */
723 if (!twl4030->hsl_enabled)
724 headset_ramp(w->codec, 0);
725
726 twl4030->hsr_enabled = 0;
aad749e5
PU		 727 break;
728 }
729 return 0;
730}
731
7393958f
PU		 732static int bypass_event(struct snd_soc_dapm_widget *w,
733 struct snd_kcontrol *kcontrol, int event)
734{
735 struct soc_mixer_control *m =
736 (struct soc_mixer_control *)w->kcontrols->private_value;
737 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 738 unsigned char reg, misc;
7393958f
PU		 739
740 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd 741
30808ca7
LCM		 742 /*
743 * bypass_state[0:3] - analog HiFi bypass
744 * bypass_state[4] - analog voice bypass
745 * bypass_state[5] - digital voice bypass
746 * bypass_state[6:7] - digital HiFi bypass
747 */
748 if (m->reg == TWL4030_REG_VSTPGA) {
749 /* Voice digital bypass */
750 if (reg)
751 twl4030->bypass_state |= (1 << 5);
752 else
753 twl4030->bypass_state &= ~(1 << 5);
754 } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
6bab83fd
PU		 755 /* Analog bypass */
756 if (reg & (1 << m->shift))
757 twl4030->bypass_state |=
758 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
759 else
760 twl4030->bypass_state &=
761 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 762 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
763 /* Analog voice bypass */
764 if (reg & (1 << m->shift))
765 twl4030->bypass_state |= (1 << 4);
766 else
767 twl4030->bypass_state &= ~(1 << 4);
6bab83fd
PU		 768 } else {
769 /* Digital bypass */
770 if (reg & (0x7 << m->shift))
ee8f6894 771 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 772 else
ee8f6894 773 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 774 }
7393958f 775
fcd274a3
LCM		 776 /* Enable master analog loopback mode if any analog switch is enabled*/
777 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
778 if (twl4030->bypass_state & 0x1F)
779 misc |= TWL4030_FMLOOP_EN;
780 else
781 misc &= ~TWL4030_FMLOOP_EN;
782 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
783
7393958f
PU		 784 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
785 if (twl4030->bypass_state)
786 twl4030_codec_mute(w->codec, 0);
787 else
788 twl4030_codec_mute(w->codec, 1);
789 }
790 return 0;
791}
792
b0bd53a7
PU		 793/*
794 * Some of the gain controls in TWL (mostly those which are associated with
795 * the outputs) are implemented in an interesting way:
796 * 0x0 : Power down (mute)
797 * 0x1 : 6dB
798 * 0x2 : 0 dB
799 * 0x3 : -6 dB
800 * Inverting not going to help with these.
801 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
802 */
803#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
804 xinvert, tlv_array) \
805{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
806 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
807 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
808 .tlv.p = (tlv_array), \
809 .info = snd_soc_info_volsw, \
810 .get = snd_soc_get_volsw_twl4030, \
811 .put = snd_soc_put_volsw_twl4030, \
812 .private_value = (unsigned long)&(struct soc_mixer_control) \
813 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
814 .max = xmax, .invert = xinvert} }
815#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
816 xinvert, tlv_array) \
817{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
818 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
819 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
820 .tlv.p = (tlv_array), \
821 .info = snd_soc_info_volsw_2r, \
822 .get = snd_soc_get_volsw_r2_twl4030,\
823 .put = snd_soc_put_volsw_r2_twl4030, \
824 .private_value = (unsigned long)&(struct soc_mixer_control) \
825 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 826 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 827#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
828 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
829 xinvert, tlv_array)
830
831static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
832 struct snd_ctl_elem_value *ucontrol)
833{
834 struct soc_mixer_control *mc =
835 (struct soc_mixer_control *)kcontrol->private_value;
836 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
837 unsigned int reg = mc->reg;
838 unsigned int shift = mc->shift;
839 unsigned int rshift = mc->rshift;
840 int max = mc->max;
841 int mask = (1 << fls(max)) - 1;
842
843 ucontrol->value.integer.value[0] =
844 (snd_soc_read(codec, reg) >> shift) & mask;
845 if (ucontrol->value.integer.value[0])
846 ucontrol->value.integer.value[0] =
847 max + 1 - ucontrol->value.integer.value[0];
848
849 if (shift != rshift) {
850 ucontrol->value.integer.value[1] =
851 (snd_soc_read(codec, reg) >> rshift) & mask;
852 if (ucontrol->value.integer.value[1])
853 ucontrol->value.integer.value[1] =
854 max + 1 - ucontrol->value.integer.value[1];
855 }
856
857 return 0;
858}
859
860static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
861 struct snd_ctl_elem_value *ucontrol)
862{
863 struct soc_mixer_control *mc =
864 (struct soc_mixer_control *)kcontrol->private_value;
865 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
866 unsigned int reg = mc->reg;
867 unsigned int shift = mc->shift;
868 unsigned int rshift = mc->rshift;
869 int max = mc->max;
870 int mask = (1 << fls(max)) - 1;
871 unsigned short val, val2, val_mask;
872
873 val = (ucontrol->value.integer.value[0] & mask);
874
875 val_mask = mask << shift;
876 if (val)
877 val = max + 1 - val;
878 val = val << shift;
879 if (shift != rshift) {
880 val2 = (ucontrol->value.integer.value[1] & mask);
881 val_mask |= mask << rshift;
882 if (val2)
883 val2 = max + 1 - val2;
884 val |= val2 << rshift;
885 }
886 return snd_soc_update_bits(codec, reg, val_mask, val);
887}
888
889static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
890 struct snd_ctl_elem_value *ucontrol)
891{
892 struct soc_mixer_control *mc =
893 (struct soc_mixer_control *)kcontrol->private_value;
894 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
895 unsigned int reg = mc->reg;
896 unsigned int reg2 = mc->rreg;
897 unsigned int shift = mc->shift;
898 int max = mc->max;
899 int mask = (1<<fls(max))-1;
900
901 ucontrol->value.integer.value[0] =
902 (snd_soc_read(codec, reg) >> shift) & mask;
903 ucontrol->value.integer.value[1] =
904 (snd_soc_read(codec, reg2) >> shift) & mask;
905
906 if (ucontrol->value.integer.value[0])
907 ucontrol->value.integer.value[0] =
908 max + 1 - ucontrol->value.integer.value[0];
909 if (ucontrol->value.integer.value[1])
910 ucontrol->value.integer.value[1] =
911 max + 1 - ucontrol->value.integer.value[1];
912
913 return 0;
914}
915
916static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
917 struct snd_ctl_elem_value *ucontrol)
918{
919 struct soc_mixer_control *mc =
920 (struct soc_mixer_control *)kcontrol->private_value;
921 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
922 unsigned int reg = mc->reg;
923 unsigned int reg2 = mc->rreg;
924 unsigned int shift = mc->shift;
925 int max = mc->max;
926 int mask = (1 << fls(max)) - 1;
927 int err;
928 unsigned short val, val2, val_mask;
929
930 val_mask = mask << shift;
931 val = (ucontrol->value.integer.value[0] & mask);
932 val2 = (ucontrol->value.integer.value[1] & mask);
933
934 if (val)
935 val = max + 1 - val;
936 if (val2)
937 val2 = max + 1 - val2;
938
939 val = val << shift;
940 val2 = val2 << shift;
941
942 err = snd_soc_update_bits(codec, reg, val_mask, val);
943 if (err < 0)
944 return err;
945
946 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
947 return err;
948}
949
b74bd40f
LCM		 950/* Codec operation modes */
951static const char *twl4030_op_modes_texts[] = {
952 "Option 2 (voice/audio)", "Option 1 (audio)"
953};
954
955static const struct soc_enum twl4030_op_modes_enum =
956 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
957 ARRAY_SIZE(twl4030_op_modes_texts),
958 twl4030_op_modes_texts);
959
423c238d 960static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 961 struct snd_ctl_elem_value *ucontrol)
962{
963 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
964 struct twl4030_priv *twl4030 = codec->private_data;
965 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
966 unsigned short val;
967 unsigned short mask, bitmask;
968
969 if (twl4030->configured) {
970 printk(KERN_ERR "twl4030 operation mode cannot be "
971 "changed on-the-fly\n");
972 return -EBUSY;
973 }
974
975 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
976 ;
977 if (ucontrol->value.enumerated.item[0] > e->max - 1)
978 return -EINVAL;
979
980 val = ucontrol->value.enumerated.item[0] << e->shift_l;
981 mask = (bitmask - 1) << e->shift_l;
982 if (e->shift_l != e->shift_r) {
983 if (ucontrol->value.enumerated.item[1] > e->max - 1)
984 return -EINVAL;
985 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
986 mask |= (bitmask - 1) << e->shift_r;
987 }
988
989 return snd_soc_update_bits(codec, e->reg, mask, val);
990}
991
c10b82cf
PU		 992/*
993 * FGAIN volume control:
994 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
995 */
d889a72c 996static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 997
0d33ea0b
PU		 998/*
999 * CGAIN volume control:
1000 * 0 dB to 12 dB in 6 dB steps
1001 * value 2 and 3 means 12 dB
1002 */
d889a72c
PU		 1003static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1004
1a787e7a
JS		 1005/*
1006 * Voice Downlink GAIN volume control:
1007 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1008 */
1009static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1010
d889a72c
PU		 1011/*
1012 * Analog playback gain
1013 * -24 dB to 12 dB in 2 dB steps
1014 */
1015static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1016
4290239c
PU		 1017/*
1018 * Gain controls tied to outputs
1019 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1020 */
1021static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1022
18cc8d8d
JS		 1023/*
1024 * Gain control for earpiece amplifier
1025 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1026 */
1027static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1028
381a22b5
PU		 1029/*
1030 * Capture gain after the ADCs
1031 * from 0 dB to 31 dB in 1 dB steps
1032 */
1033static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1034
5920b453
GI		 1035/*
1036 * Gain control for input amplifiers
1037 * 0 dB to 30 dB in 6 dB steps
1038 */
1039static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1040
328d0a13
LCM		 1041/* AVADC clock priority */
1042static const char *twl4030_avadc_clk_priority_texts[] = {
1043 "Voice high priority", "HiFi high priority"
1044};
1045
1046static const struct soc_enum twl4030_avadc_clk_priority_enum =
1047 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1048 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1049 twl4030_avadc_clk_priority_texts);
1050
89492be8
PU		 1051static const char *twl4030_rampdelay_texts[] = {
1052 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1053 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1054 "3495/2581/1748 ms"
1055};
1056
1057static const struct soc_enum twl4030_rampdelay_enum =
1058 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1059 ARRAY_SIZE(twl4030_rampdelay_texts),
1060 twl4030_rampdelay_texts);
1061
376f7839
PU		 1062/* Vibra H-bridge direction mode */
1063static const char *twl4030_vibradirmode_texts[] = {
1064 "Vibra H-bridge direction", "Audio data MSB",
1065};
1066
1067static const struct soc_enum twl4030_vibradirmode_enum =
1068 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1069 ARRAY_SIZE(twl4030_vibradirmode_texts),
1070 twl4030_vibradirmode_texts);
1071
1072/* Vibra H-bridge direction */
1073static const char *twl4030_vibradir_texts[] = {
1074 "Positive polarity", "Negative polarity",
1075};
1076
1077static const struct soc_enum twl4030_vibradir_enum =
1078 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1079 ARRAY_SIZE(twl4030_vibradir_texts),
1080 twl4030_vibradir_texts);
1081
cc17557e 1082static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1083 /* Codec operation mode control */
1084 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1085 snd_soc_get_enum_double,
1086 snd_soc_put_twl4030_opmode_enum_double),
1087
d889a72c
PU		 1088 /* Common playback gain controls */
1089 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1090 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1091 0, 0x3f, 0, digital_fine_tlv),
1092 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1093 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1094 0, 0x3f, 0, digital_fine_tlv),
1095
1096 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1097 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1098 6, 0x2, 0, digital_coarse_tlv),
1099 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1100 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1101 6, 0x2, 0, digital_coarse_tlv),
1102
1103 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1104 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1105 3, 0x12, 1, analog_tlv),
1106 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1107 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1108 3, 0x12, 1, analog_tlv),
44c55870
PU		 1109 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1110 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1111 1, 1, 0),
1112 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1113 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1114 1, 1, 0),
381a22b5 1115
1a787e7a
JS		 1116 /* Common voice downlink gain controls */
1117 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1118 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1119
1120 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1121 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1122
1123 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1124 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1125
4290239c
PU		 1126 /* Separate output gain controls */
1127 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1128 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1129 4, 3, 0, output_tvl),
1130
1131 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1132 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1133
1134 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1135 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1136 4, 3, 0, output_tvl),
1137
1138 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1139 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1140
381a22b5 1141 /* Common capture gain controls */
276c6222 1142 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1143 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1144 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1145 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1146 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1147 0, 0x1f, 0, digital_capture_tlv),
5920b453 1148
276c6222 1149 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1150 0, 3, 5, 0, input_gain_tlv),
89492be8 1151
328d0a13
LCM		 1152 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1153
89492be8 1154 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1155
1156 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1157 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1158};
1159
cc17557e 1160static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1161 /* Left channel inputs */
1162 SND_SOC_DAPM_INPUT("MAINMIC"),
1163 SND_SOC_DAPM_INPUT("HSMIC"),
1164 SND_SOC_DAPM_INPUT("AUXL"),
1165 SND_SOC_DAPM_INPUT("CARKITMIC"),
1166 /* Right channel inputs */
1167 SND_SOC_DAPM_INPUT("SUBMIC"),
1168 SND_SOC_DAPM_INPUT("AUXR"),
1169 /* Digital microphones (Stereo) */
1170 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1171 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1172
1173 /* Outputs */
cc17557e
SS		 1174 SND_SOC_DAPM_OUTPUT("OUTL"),
1175 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1176 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1177 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1178 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1179 SND_SOC_DAPM_OUTPUT("HSOL"),
1180 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1181 SND_SOC_DAPM_OUTPUT("CARKITL"),
1182 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1183 SND_SOC_DAPM_OUTPUT("HFL"),
1184 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1185 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1186
53b5047d 1187 /* DACs */
b4852b79 1188 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1189 SND_SOC_NOPM, 0, 0),
b4852b79 1190 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1191 SND_SOC_NOPM, 0, 0),
b4852b79 1192 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1193 SND_SOC_NOPM, 0, 0),
b4852b79 1194 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1195 SND_SOC_NOPM, 0, 0),
1a787e7a 1196 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1197 SND_SOC_NOPM, 0, 0),
cc17557e 1198
7393958f
PU		 1199 /* Analog bypasses */
1200 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1201 &twl4030_dapm_abypassr1_control, bypass_event,
1202 SND_SOC_DAPM_POST_REG),
1203 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1204 &twl4030_dapm_abypassl1_control,
1205 bypass_event, SND_SOC_DAPM_POST_REG),
1206 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1207 &twl4030_dapm_abypassr2_control,
1208 bypass_event, SND_SOC_DAPM_POST_REG),
1209 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1210 &twl4030_dapm_abypassl2_control,
1211 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1212 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1213 &twl4030_dapm_abypassv_control,
1214 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1215
6bab83fd
PU		 1216 /* Digital bypasses */
1217 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1218 &twl4030_dapm_dbypassl_control, bypass_event,
1219 SND_SOC_DAPM_POST_REG),
1220 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1221 &twl4030_dapm_dbypassr_control, bypass_event,
1222 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1223 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1224 &twl4030_dapm_dbypassv_control, bypass_event,
1225 SND_SOC_DAPM_POST_REG),
6bab83fd 1226
4005d39a
PU		 1227 /* Digital mixers, power control for the physical DACs */
1228 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1229 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1230 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1231 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1232 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1233 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1234 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1235 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1236 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1237 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1238
1239 /* Analog mixers, power control for the physical PGAs */
1240 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1241 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1242 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1243 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1244 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1245 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1246 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1247 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1248 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1249 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1250
1a787e7a 1251 /* Output MIXER controls */
5e98a464 1252 /* Earpiece */
1a787e7a
JS		 1253 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1254 &twl4030_dapm_earpiece_controls[0],
1255 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1256 /* PreDrivL/R */
1a787e7a
JS		 1257 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_predrivel_controls[0],
1259 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1260 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1261 &twl4030_dapm_predriver_controls[0],
1262 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1263 /* HeadsetL/R */
6943c92e 1264 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1265 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1266 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1267 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1268 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1269 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1270 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_hsor_controls[0],
1272 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1273 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1274 0, 0, NULL, 0, headsetrpga_event,
1275 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1276 /* CarkitL/R */
1a787e7a
JS		 1277 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1278 &twl4030_dapm_carkitl_controls[0],
1279 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1280 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_carkitr_controls[0],
1282 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1283
1284 /* Output MUX controls */
df339804 1285 /* HandsfreeL/R */
5a2e9a48
PU		 1286 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1287 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1288 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1289 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1290 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1291 0, 0, NULL, 0, handsfreelpga_event,
1292 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1293 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1294 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1295 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1296 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1297 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1298 0, 0, NULL, 0, handsfreerpga_event,
1299 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1300 /* Vibra */
1301 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1302 &twl4030_dapm_vibra_control),
1303 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1304 &twl4030_dapm_vibrapath_control),
5e98a464 1305
276c6222
PU		 1306 /* Introducing four virtual ADC, since TWL4030 have four channel for
1307 capture */
1308 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1309 SND_SOC_NOPM, 0, 0),
1310 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1311 SND_SOC_NOPM, 0, 0),
1312 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1313 SND_SOC_NOPM, 0, 0),
1314 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1315 SND_SOC_NOPM, 0, 0),
1316
1317 /* Analog/Digital mic path selection.
1318 TX1 Left/Right: either analog Left/Right or Digimic0
1319 TX2 Left/Right: either analog Left/Right or Digimic1 */
1320 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1321 &twl4030_dapm_micpathtx1_control, micpath_event,
1322 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1323 SND_SOC_DAPM_POST_REG),
1324 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1325 &twl4030_dapm_micpathtx2_control, micpath_event,
1326 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1327 SND_SOC_DAPM_POST_REG),
1328
97b8096d
JS		 1329 /* Analog input mixers for the capture amplifiers */
1330 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1331 TWL4030_REG_ANAMICL, 4, 0,
1332 &twl4030_dapm_analoglmic_controls[0],
1333 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1334 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1335 TWL4030_REG_ANAMICR, 4, 0,
1336 &twl4030_dapm_analogrmic_controls[0],
1337 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1338
fb2a2f84
PU		 1339 SND_SOC_DAPM_PGA("ADC Physical Left",
1340 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1341 SND_SOC_DAPM_PGA("ADC Physical Right",
1342 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1343
1344 SND_SOC_DAPM_PGA("Digimic0 Enable",
1345 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1346 SND_SOC_DAPM_PGA("Digimic1 Enable",
1347 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1348
1349 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1350 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1351 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1352
cc17557e
SS		 1353};
1354
1355static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1356 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1357 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1358 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1359 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1360 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1361
1362 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1363 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1364 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1365 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1366 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1367
5e98a464
PU		 1368 /* Internal playback routings */
1369 /* Earpiece */
4005d39a
PU		 1370 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1371 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1372 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1373 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1374 /* PreDrivL */
4005d39a
PU		 1375 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1376 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1377 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1378 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1379 /* PreDrivR */
4005d39a
PU		 1380 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1381 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1382 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1383 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1384 /* HeadsetL */
4005d39a
PU		 1385 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1386 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1387 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1388 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1389 /* HeadsetR */
4005d39a
PU		 1390 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1391 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1392 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1393 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1394 /* CarkitL */
4005d39a
PU		 1395 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1396 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1397 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1398 /* CarkitR */
4005d39a
PU		 1399 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1400 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1401 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1402 /* HandsfreeL */
4005d39a
PU		 1403 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1404 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1405 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1406 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1407 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1408 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1409 /* HandsfreeR */
4005d39a
PU		 1410 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1411 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1412 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1413 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1414 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1415 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1416 /* Vibra */
1417 {"Vibra Mux", "AudioL1", "DAC Left1"},
1418 {"Vibra Mux", "AudioR1", "DAC Right1"},
1419 {"Vibra Mux", "AudioL2", "DAC Left2"},
1420 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1421
cc17557e 1422 /* outputs */
4005d39a
PU		 1423 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1424 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1425 {"EARPIECE", NULL, "Earpiece Mixer"},
1426 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1427 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1428 {"HSOL", NULL, "HeadsetL PGA"},
1429 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1430 {"CARKITL", NULL, "CarkitL Mixer"},
1431 {"CARKITR", NULL, "CarkitR Mixer"},
5a2e9a48
PU		 1432 {"HFL", NULL, "HandsfreeL PGA"},
1433 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1434 {"Vibra Route", "Audio", "Vibra Mux"},
1435 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1436
276c6222
PU		 1437 /* Capture path */
1438 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1439 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1440 {"Analog Left Capture Route", "AUXL", "AUXL"},
1441 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1442
1443 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1444 {"Analog Right Capture Route", "AUXR", "AUXR"},
1445
fb2a2f84
PU		 1446 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1447 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1448
1449 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1450 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1451
1452 /* TX1 Left capture path */
fb2a2f84 1453 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1454 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1455 /* TX1 Right capture path */
fb2a2f84 1456 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1457 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1458 /* TX2 Left capture path */
fb2a2f84 1459 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1460 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1461 /* TX2 Right capture path */
fb2a2f84 1462 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1463 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1464
1465 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1466 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1467 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1468 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1469
7393958f
PU		 1470 /* Analog bypass routes */
1471 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1472 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1473 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1474 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1475 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1476
1477 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1478 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1479 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1480 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1481 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1482
6bab83fd
PU		 1483 /* Digital bypass routes */
1484 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1485 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1486 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1487
4005d39a
PU		 1488 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1489 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1490 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1491
cc17557e
SS		 1492};
1493
1494static int twl4030_add_widgets(struct snd_soc_codec *codec)
1495{
1496 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1497 ARRAY_SIZE(twl4030_dapm_widgets));
1498
1499 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1500
1501 snd_soc_dapm_new_widgets(codec);
1502 return 0;
1503}
1504
cc17557e
SS		 1505static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1506 enum snd_soc_bias_level level)
1507{
7393958f
PU		 1508 struct twl4030_priv *twl4030 = codec->private_data;
1509
cc17557e
SS		 1510 switch (level) {
1511 case SND_SOC_BIAS_ON:
7393958f 1512 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1513 break;
1514 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1515 twl4030_power_up(codec);
1516 if (twl4030->bypass_state)
1517 twl4030_codec_mute(codec, 0);
1518 else
1519 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1520 break;
1521 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1522 twl4030_power_up(codec);
1523 if (twl4030->bypass_state)
1524 twl4030_codec_mute(codec, 0);
1525 else
1526 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1527 break;
1528 case SND_SOC_BIAS_OFF:
1529 twl4030_power_down(codec);
1530 break;
1531 }
1532 codec->bias_level = level;
1533
1534 return 0;
1535}
1536
6b87a91f
PU		 1537static void twl4030_constraints(struct twl4030_priv *twl4030,
1538 struct snd_pcm_substream *mst_substream)
1539{
1540 struct snd_pcm_substream *slv_substream;
1541
1542 /* Pick the stream, which need to be constrained */
1543 if (mst_substream == twl4030->master_substream)
1544 slv_substream = twl4030->slave_substream;
1545 else if (mst_substream == twl4030->slave_substream)
1546 slv_substream = twl4030->master_substream;
1547 else /* This should not happen.. */
1548 return;
1549
1550 /* Set the constraints according to the already configured stream */
1551 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1552 SNDRV_PCM_HW_PARAM_RATE,
1553 twl4030->rate,
1554 twl4030->rate);
1555
1556 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1557 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1558 twl4030->sample_bits,
1559 twl4030->sample_bits);
1560
1561 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1562 SNDRV_PCM_HW_PARAM_CHANNELS,
1563 twl4030->channels,
1564 twl4030->channels);
1565}
1566
8a1f936a
PU		 1567/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1568 * capture has to be enabled/disabled. */
1569static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1570 int enable)
1571{
1572 u8 reg, mask;
1573
1574 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1575
1576 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1577 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1578 else
1579 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1580
1581 if (enable)
1582 reg |= mask;
1583 else
1584 reg &= ~mask;
1585
1586 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1587}
1588
d6648da1
PU		 1589static int twl4030_startup(struct snd_pcm_substream *substream,
1590 struct snd_soc_dai *dai)
7220b9f4
PU		 1591{
1592 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1593 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1594 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1595 struct twl4030_priv *twl4030 = codec->private_data;
1596
7220b9f4 1597 if (twl4030->master_substream) {
7220b9f4 1598 twl4030->slave_substream = substream;
6b87a91f
PU		 1599 /* The DAI has one configuration for playback and capture, so
1600 * if the DAI has been already configured then constrain this
1601 * substream to match it. */
1602 if (twl4030->configured)
1603 twl4030_constraints(twl4030, twl4030->master_substream);
1604 } else {
8a1f936a
PU		 1605 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1606 TWL4030_OPTION_1)) {
1607 /* In option2 4 channel is not supported, set the
1608 * constraint for the first stream for channels, the
1609 * second stream will 'inherit' this cosntraint */
1610 snd_pcm_hw_constraint_minmax(substream->runtime,
1611 SNDRV_PCM_HW_PARAM_CHANNELS,
1612 2, 2);
1613 }
7220b9f4 1614 twl4030->master_substream = substream;
6b87a91f 1615 }
7220b9f4
PU		 1616
1617 return 0;
1618}
1619
d6648da1
PU		 1620static void twl4030_shutdown(struct snd_pcm_substream *substream,
1621 struct snd_soc_dai *dai)
7220b9f4
PU		 1622{
1623 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1624 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1625 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1626 struct twl4030_priv *twl4030 = codec->private_data;
1627
1628 if (twl4030->master_substream == substream)
1629 twl4030->master_substream = twl4030->slave_substream;
1630
1631 twl4030->slave_substream = NULL;
6b87a91f
PU		 1632
1633 /* If all streams are closed, or the remaining stream has not yet
1634 * been configured than set the DAI as not configured. */
1635 if (!twl4030->master_substream)
1636 twl4030->configured = 0;
1637 else if (!twl4030->master_substream->runtime->channels)
1638 twl4030->configured = 0;
8a1f936a
PU		 1639
1640 /* If the closing substream had 4 channel, do the necessary cleanup */
1641 if (substream->runtime->channels == 4)
1642 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1643}
1644
cc17557e 1645static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1646 struct snd_pcm_hw_params *params,
1647 struct snd_soc_dai *dai)
cc17557e
SS		 1648{
1649 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1650 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1651 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1652 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1653 u8 mode, old_mode, format, old_format;
1654
8a1f936a
PU		 1655 /* If the substream has 4 channel, do the necessary setup */
1656 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1657 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1658 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1659
1660 /* Safety check: are we in the correct operating mode and
1661 * the interface is in TDM mode? */
1662 if ((mode & TWL4030_OPTION_1) &&
1663 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1664 twl4030_tdm_enable(codec, substream->stream, 1);
1665 else
1666 return -EINVAL;
1667 }
1668
6b87a91f
PU		 1669 if (twl4030->configured)
1670 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1671 return 0;
1672
cc17557e
SS		 1673 /* bit rate */
1674 old_mode = twl4030_read_reg_cache(codec,
1675 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1676 mode = old_mode & ~TWL4030_APLL_RATE;
1677
1678 switch (params_rate(params)) {
1679 case 8000:
1680 mode |= TWL4030_APLL_RATE_8000;
1681 break;
1682 case 11025:
1683 mode |= TWL4030_APLL_RATE_11025;
1684 break;
1685 case 12000:
1686 mode |= TWL4030_APLL_RATE_12000;
1687 break;
1688 case 16000:
1689 mode |= TWL4030_APLL_RATE_16000;
1690 break;
1691 case 22050:
1692 mode |= TWL4030_APLL_RATE_22050;
1693 break;
1694 case 24000:
1695 mode |= TWL4030_APLL_RATE_24000;
1696 break;
1697 case 32000:
1698 mode |= TWL4030_APLL_RATE_32000;
1699 break;
1700 case 44100:
1701 mode |= TWL4030_APLL_RATE_44100;
1702 break;
1703 case 48000:
1704 mode |= TWL4030_APLL_RATE_48000;
1705 break;
103f211d
PU		 1706 case 96000:
1707 mode |= TWL4030_APLL_RATE_96000;
1708 break;
cc17557e
SS		 1709 default:
1710 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1711 params_rate(params));
1712 return -EINVAL;
1713 }
1714
1715 if (mode != old_mode) {
1716 /* change rate and set CODECPDZ */
7393958f 1717 twl4030_codec_enable(codec, 0);
cc17557e 1718 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1719 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1720 }
1721
1722 /* sample size */
1723 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1724 format = old_format;
1725 format &= ~TWL4030_DATA_WIDTH;
1726 switch (params_format(params)) {
1727 case SNDRV_PCM_FORMAT_S16_LE:
1728 format |= TWL4030_DATA_WIDTH_16S_16W;
1729 break;
1730 case SNDRV_PCM_FORMAT_S24_LE:
1731 format |= TWL4030_DATA_WIDTH_32S_24W;
1732 break;
1733 default:
1734 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1735 params_format(params));
1736 return -EINVAL;
1737 }
1738
1739 if (format != old_format) {
1740
1741 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1742 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1743
1744 /* change format */
1745 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1746
1747 /* set CODECPDZ afterwards */
db04e2c5 1748 twl4030_codec_enable(codec, 1);
cc17557e 1749 }
6b87a91f
PU		 1750
1751 /* Store the important parameters for the DAI configuration and set
1752 * the DAI as configured */
1753 twl4030->configured = 1;
1754 twl4030->rate = params_rate(params);
1755 twl4030->sample_bits = hw_param_interval(params,
1756 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1757 twl4030->channels = params_channels(params);
1758
1759 /* If both playback and capture streams are open, and one of them
1760 * is setting the hw parameters right now (since we are here), set
1761 * constraints to the other stream to match the current one. */
1762 if (twl4030->slave_substream)
1763 twl4030_constraints(twl4030, substream);
1764
cc17557e
SS		 1765 return 0;
1766}
1767
1768static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1769 int clk_id, unsigned int freq, int dir)
1770{
1771 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1772 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1773 u8 infreq;
1774
1775 switch (freq) {
1776 case 19200000:
1777 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1778 twl4030->sysclk = 19200;
cc17557e
SS		 1779 break;
1780 case 26000000:
1781 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1782 twl4030->sysclk = 26000;
cc17557e
SS		 1783 break;
1784 case 38400000:
1785 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1786 twl4030->sysclk = 38400;
cc17557e
SS		 1787 break;
1788 default:
1789 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1790 freq);
1791 return -EINVAL;
1792 }
1793
1794 infreq |= TWL4030_APLL_EN;
1795 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1796
1797 return 0;
1798}
1799
1800static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1801 unsigned int fmt)
1802{
1803 struct snd_soc_codec *codec = codec_dai->codec;
1804 u8 old_format, format;
1805
1806 /* get format */
1807 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1808 format = old_format;
1809
1810 /* set master/slave audio interface */
1811 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1812 case SND_SOC_DAIFMT_CBM_CFM:
1813 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1814 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1815 break;
1816 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1817 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1818 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1819 break;
1820 default:
1821 return -EINVAL;
1822 }
1823
1824 /* interface format */
1825 format &= ~TWL4030_AIF_FORMAT;
1826 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1827 case SND_SOC_DAIFMT_I2S:
1828 format |= TWL4030_AIF_FORMAT_CODEC;
1829 break;
8a1f936a
PU		 1830 case SND_SOC_DAIFMT_DSP_A:
1831 format |= TWL4030_AIF_FORMAT_TDM;
1832 break;
cc17557e
SS		 1833 default:
1834 return -EINVAL;
1835 }
1836
1837 if (format != old_format) {
1838
1839 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1840 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1841
1842 /* change format */
1843 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1844
1845 /* set CODECPDZ afterwards */
db04e2c5 1846 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1847 }
1848
1849 return 0;
1850}
1851
68140443
LCM		 1852static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1853{
1854 struct snd_soc_codec *codec = dai->codec;
1855 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1856
1857 if (tristate)
1858 reg |= TWL4030_AIF_TRI_EN;
1859 else
1860 reg &= ~TWL4030_AIF_TRI_EN;
1861
1862 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1863}
1864
b7a755a8
MLC		 1865/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1866 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1867static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1868 int enable)
1869{
1870 u8 reg, mask;
1871
1872 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1873
1874 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1875 mask = TWL4030_ARXL1_VRX_EN;
1876 else
1877 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1878
1879 if (enable)
1880 reg |= mask;
1881 else
1882 reg &= ~mask;
1883
1884 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1885}
1886
7154b3e8
JS		 1887static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1888 struct snd_soc_dai *dai)
1889{
1890 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1891 struct snd_soc_device *socdev = rtd->socdev;
1892 struct snd_soc_codec *codec = socdev->card->codec;
1893 u8 infreq;
1894 u8 mode;
1895
1896 /* If the system master clock is not 26MHz, the voice PCM interface is
1897 * not avilable.
1898 */
1899 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1900 & TWL4030_APLL_INFREQ;
1901
1902 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1903 printk(KERN_ERR "TWL4030 voice startup: "
1904 "MCLK is not 26MHz, call set_sysclk() on init\n");
1905 return -EINVAL;
1906 }
1907
1908 /* If the codec mode is not option2, the voice PCM interface is not
1909 * avilable.
1910 */
1911 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1912 & TWL4030_OPT_MODE;
1913
1914 if (mode != TWL4030_OPTION_2) {
1915 printk(KERN_ERR "TWL4030 voice startup: "
1916 "the codec mode is not option2\n");
1917 return -EINVAL;
1918 }
1919
1920 return 0;
1921}
1922
b7a755a8
MLC		 1923static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1924 struct snd_soc_dai *dai)
1925{
1926 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1927 struct snd_soc_device *socdev = rtd->socdev;
1928 struct snd_soc_codec *codec = socdev->card->codec;
1929
1930 /* Enable voice digital filters */
1931 twl4030_voice_enable(codec, substream->stream, 0);
1932}
1933
7154b3e8
JS		 1934static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1935 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1936{
1937 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1938 struct snd_soc_device *socdev = rtd->socdev;
1939 struct snd_soc_codec *codec = socdev->card->codec;
1940 u8 old_mode, mode;
1941
b7a755a8
MLC		 1942 /* Enable voice digital filters */
1943 twl4030_voice_enable(codec, substream->stream, 1);
1944
7154b3e8
JS		 1945 /* bit rate */
1946 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1947 & ~(TWL4030_CODECPDZ);
1948 mode = old_mode;
1949
1950 switch (params_rate(params)) {
1951 case 8000:
1952 mode &= ~(TWL4030_SEL_16K);
1953 break;
1954 case 16000:
1955 mode |= TWL4030_SEL_16K;
1956 break;
1957 default:
1958 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1959 params_rate(params));
1960 return -EINVAL;
1961 }
1962
1963 if (mode != old_mode) {
1964 /* change rate and set CODECPDZ */
1965 twl4030_codec_enable(codec, 0);
1966 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1967 twl4030_codec_enable(codec, 1);
1968 }
1969
1970 return 0;
1971}
1972
1973static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1974 int clk_id, unsigned int freq, int dir)
1975{
1976 struct snd_soc_codec *codec = codec_dai->codec;
1977 u8 infreq;
1978
1979 switch (freq) {
1980 case 26000000:
1981 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1982 break;
1983 default:
1984 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1985 freq);
1986 return -EINVAL;
1987 }
1988
1989 infreq |= TWL4030_APLL_EN;
1990 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1991
1992 return 0;
1993}
1994
1995static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1996 unsigned int fmt)
1997{
1998 struct snd_soc_codec *codec = codec_dai->codec;
1999 u8 old_format, format;
2000
2001 /* get format */
2002 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2003 format = old_format;
2004
2005 /* set master/slave audio interface */
2006 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2007 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2008 format &= ~(TWL4030_VIF_SLAVE_EN);
2009 break;
2010 case SND_SOC_DAIFMT_CBS_CFS:
2011 format |= TWL4030_VIF_SLAVE_EN;
2012 break;
2013 default:
2014 return -EINVAL;
2015 }
2016
2017 /* clock inversion */
2018 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2019 case SND_SOC_DAIFMT_IB_NF:
2020 format &= ~(TWL4030_VIF_FORMAT);
2021 break;
2022 case SND_SOC_DAIFMT_NB_IF:
2023 format |= TWL4030_VIF_FORMAT;
2024 break;
2025 default:
2026 return -EINVAL;
2027 }
2028
2029 if (format != old_format) {
2030 /* change format and set CODECPDZ */
2031 twl4030_codec_enable(codec, 0);
2032 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2033 twl4030_codec_enable(codec, 1);
2034 }
2035
2036 return 0;
2037}
2038
68140443
LCM		 2039static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2040{
2041 struct snd_soc_codec *codec = dai->codec;
2042 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2043
2044 if (tristate)
2045 reg |= TWL4030_VIF_TRI_EN;
2046 else
2047 reg &= ~TWL4030_VIF_TRI_EN;
2048
2049 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2050}
2051
bbba9444 2052#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2053#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2054
10d9e3d9 2055static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2056 .startup = twl4030_startup,
2057 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2058 .hw_params = twl4030_hw_params,
2059 .set_sysclk = twl4030_set_dai_sysclk,
2060 .set_fmt = twl4030_set_dai_fmt,
68140443 2061 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2062};
2063
7154b3e8
JS		 2064static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2065 .startup = twl4030_voice_startup,
b7a755a8 2066 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2067 .hw_params = twl4030_voice_hw_params,
2068 .set_sysclk = twl4030_voice_set_dai_sysclk,
2069 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2070 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2071};
2072
2073struct snd_soc_dai twl4030_dai[] = {
2074{
cc17557e
SS		 2075 .name = "twl4030",
2076 .playback = {
b4852b79 2077 .stream_name = "HiFi Playback",
cc17557e 2078 .channels_min = 2,
8a1f936a 2079 .channels_max = 4,
31ad0f31 2080 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2081 .formats = TWL4030_FORMATS,},
2082 .capture = {
2083 .stream_name = "Capture",
2084 .channels_min = 2,
8a1f936a 2085 .channels_max = 4,
cc17557e
SS		 2086 .rates = TWL4030_RATES,
2087 .formats = TWL4030_FORMATS,},
10d9e3d9 2088 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2089},
2090{
2091 .name = "twl4030 Voice",
2092 .playback = {
b4852b79 2093 .stream_name = "Voice Playback",
7154b3e8
JS		 2094 .channels_min = 1,
2095 .channels_max = 1,
2096 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2097 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2098 .capture = {
2099 .stream_name = "Capture",
2100 .channels_min = 1,
2101 .channels_max = 2,
2102 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2103 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2104 .ops = &twl4030_dai_voice_ops,
2105},
cc17557e
SS		 2106};
2107EXPORT_SYMBOL_GPL(twl4030_dai);
2108
2109static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2110{
2111 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2112 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2113
2114 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2115
2116 return 0;
2117}
2118
2119static int twl4030_resume(struct platform_device *pdev)
2120{
2121 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2122 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2123
2124 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2125 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2126 return 0;
2127}
2128
2129/*
2130 * initialize the driver
2131 * register the mixer and dsp interfaces with the kernel
2132 */
2133
2134static int twl4030_init(struct snd_soc_device *socdev)
2135{
6627a653 2136 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2137 struct twl4030_setup_data *setup = socdev->codec_data;
2138 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2139 int ret = 0;
2140
2141 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2142
2143 codec->name = "twl4030";
2144 codec->owner = THIS_MODULE;
2145 codec->read = twl4030_read_reg_cache;
2146 codec->write = twl4030_write;
2147 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2148 codec->dai = twl4030_dai;
2149 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2150 codec->reg_cache_size = sizeof(twl4030_reg);
2151 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2152 GFP_KERNEL);
2153 if (codec->reg_cache == NULL)
2154 return -ENOMEM;
2155
9da28c7b
PU		 2156 /* Configuration for headset ramp delay from setup data */
2157 if (setup) {
2158 unsigned char hs_pop;
2159
2160 if (setup->sysclk)
2161 twl4030->sysclk = setup->sysclk;
2162 else
2163 twl4030->sysclk = 26000;
2164
2165 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2166 hs_pop &= ~TWL4030_RAMP_DELAY;
2167 hs_pop |= (setup->ramp_delay_value << 2);
2168 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2169 } else {
2170 twl4030->sysclk = 26000;
2171 }
2172
cc17557e
SS		 2173 /* register pcms */
2174 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2175 if (ret < 0) {
2176 printk(KERN_ERR "twl4030: failed to create pcms\n");
2177 goto pcm_err;
2178 }
2179
2180 twl4030_init_chip(codec);
2181
2182 /* power on device */
2183 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2184
3e8e1952
IM		 2185 snd_soc_add_controls(codec, twl4030_snd_controls,
2186 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2187 twl4030_add_widgets(codec);
2188
968a6025 2189 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2190 if (ret < 0) {
2191 printk(KERN_ERR "twl4030: failed to register card\n");
2192 goto card_err;
2193 }
2194
2195 return ret;
2196
2197card_err:
2198 snd_soc_free_pcms(socdev);
2199 snd_soc_dapm_free(socdev);
2200pcm_err:
2201 kfree(codec->reg_cache);
2202 return ret;
2203}
2204
2205static struct snd_soc_device *twl4030_socdev;
2206
2207static int twl4030_probe(struct platform_device *pdev)
2208{
2209 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2210 struct snd_soc_codec *codec;
7393958f 2211 struct twl4030_priv *twl4030;
cc17557e
SS		 2212
2213 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2214 if (codec == NULL)
2215 return -ENOMEM;
2216
7393958f
PU		 2217 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2218 if (twl4030 == NULL) {
2219 kfree(codec);
2220 return -ENOMEM;
2221 }
2222
2223 codec->private_data = twl4030;
6627a653 2224 socdev->card->codec = codec;
cc17557e
SS		 2225 mutex_init(&codec->mutex);
2226 INIT_LIST_HEAD(&codec->dapm_widgets);
2227 INIT_LIST_HEAD(&codec->dapm_paths);
2228
2229 twl4030_socdev = socdev;
2230 twl4030_init(socdev);
2231
2232 return 0;
2233}
2234
2235static int twl4030_remove(struct platform_device *pdev)
2236{
2237 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2238 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2239
2240 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2241 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2242 snd_soc_free_pcms(socdev);
2243 snd_soc_dapm_free(socdev);
7393958f 2244 kfree(codec->private_data);
cc17557e
SS		 2245 kfree(codec);
2246
2247 return 0;
2248}
2249
2250struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2251 .probe = twl4030_probe,
2252 .remove = twl4030_remove,
2253 .suspend = twl4030_suspend,
2254 .resume = twl4030_resume,
2255};
2256EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2257
24e07db8 2258static int __init twl4030_modinit(void)
64089b84 2259{
7154b3e8 2260 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2261}
24e07db8 2262module_init(twl4030_modinit);
64089b84
MB		 2263
2264static void __exit twl4030_exit(void)
2265{
7154b3e8 2266 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2267}
2268module_exit(twl4030_exit);
2269
cc17557e
SS		 2270MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2271MODULE_AUTHOR("Steve Sakoman");
2272MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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