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ASoC: tlv320dac33: Replace w->codec snd_soc_dapm_to_codec(w->dapm)
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e 50
7393958f
PU		 51/* codec private data */
52struct twl4030_priv {
7393958f 53 unsigned int codec_powered;
7b4c734e
PU		 54
55 /* reference counts of AIF/APLL users */
2845fa13 56 unsigned int apll_enabled;
7220b9f4
PU		 57
58 struct snd_pcm_substream *master_substream;
59 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 60
61 unsigned int configured;
62 unsigned int rate;
63 unsigned int sample_bits;
64 unsigned int channels;
6943c92e
PU		 65
66 unsigned int sysclk;
67
c96907f2
PU		 68 /* Output (with associated amp) states */
69 u8 hsl_enabled, hsr_enabled;
70 u8 earpiece_enabled;
71 u8 predrivel_enabled, predriver_enabled;
72 u8 carkitl_enabled, carkitr_enabled;
8b3bca29 73 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
01ea6ba2 74
182f73f6 75 struct twl4030_codec_data *pdata;
7393958f
PU		 76};
77
8b3bca29
PU		 78static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
79{
80 int i;
81 u8 byte;
82
83 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
84 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
85 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
86 }
87}
88
efc8acff 89static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg)
cc17557e 90{
efc8acff
PU		 91 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
92 u8 value = 0;
cc17557e
SS		 93
94 if (reg >= TWL4030_CACHEREGNUM)
efc8acff
PU		 95 return -EIO;
96
97 switch (reg) {
98 case TWL4030_REG_EAR_CTL:
99 case TWL4030_REG_PREDL_CTL:
100 case TWL4030_REG_PREDR_CTL:
101 case TWL4030_REG_PRECKL_CTL:
102 case TWL4030_REG_PRECKR_CTL:
103 case TWL4030_REG_HS_GAIN_SET:
104 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
105 break;
106 default:
107 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
108 break;
109 }
110
111 return value;
cc17557e
SS		 112}
113
b703b504 114static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,
a8fc415c 115 unsigned int reg)
cc17557e 116{
a8fc415c 117 bool write_to_reg = false;
c96907f2 118
052901f4
LPC		 119 /* Decide if the given register can be written */
120 switch (reg) {
121 case TWL4030_REG_EAR_CTL:
122 if (twl4030->earpiece_enabled)
a8fc415c 123 write_to_reg = true;
052901f4
LPC		 124 break;
125 case TWL4030_REG_PREDL_CTL:
126 if (twl4030->predrivel_enabled)
a8fc415c 127 write_to_reg = true;
052901f4
LPC		 128 break;
129 case TWL4030_REG_PREDR_CTL:
130 if (twl4030->predriver_enabled)
a8fc415c 131 write_to_reg = true;
052901f4
LPC		 132 break;
133 case TWL4030_REG_PRECKL_CTL:
134 if (twl4030->carkitl_enabled)
a8fc415c 135 write_to_reg = true;
052901f4
LPC		 136 break;
137 case TWL4030_REG_PRECKR_CTL:
138 if (twl4030->carkitr_enabled)
a8fc415c 139 write_to_reg = true;
052901f4
LPC		 140 break;
141 case TWL4030_REG_HS_GAIN_SET:
142 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 143 write_to_reg = true;
052901f4
LPC		 144 break;
145 default:
146 /* All other register can be written */
a8fc415c 147 write_to_reg = true;
052901f4 148 break;
c96907f2 149 }
a8fc415c
PU		 150
151 return write_to_reg;
152}
153
7ded5fe0
PU		 154static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg,
155 unsigned int value)
a8fc415c 156{
a450aa6f
PU		 157 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
158
159 /* Update the ctl cache */
160 switch (reg) {
161 case TWL4030_REG_EAR_CTL:
162 case TWL4030_REG_PREDL_CTL:
163 case TWL4030_REG_PREDR_CTL:
164 case TWL4030_REG_PRECKL_CTL:
165 case TWL4030_REG_PRECKR_CTL:
166 case TWL4030_REG_HS_GAIN_SET:
167 twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
168 break;
169 default:
170 break;
171 }
172
b703b504 173 if (twl4030_can_write_to_chip(twl4030, reg))
a8fc415c 174 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 175
c96907f2 176 return 0;
cc17557e
SS		 177}
178
7e6120c5
PU		 179static inline void twl4030_wait_ms(int time)
180{
181 if (time < 60) {
182 time *= 1000;
183 usleep_range(time, time + 500);
184 } else {
185 msleep(time);
186 }
187}
188
db04e2c5 189static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 190{
b2c812e2 191 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 192 int mode;
cc17557e 193
7393958f
PU		 194 if (enable == twl4030->codec_powered)
195 return;
196
db04e2c5 197 if (enable)
57fe7251 198 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 199 else
57fe7251 200 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 201
efc8acff 202 if (mode >= 0)
7a1fecf5 203 twl4030->codec_powered = enable;
cc17557e
SS		 204
205 /* REVISIT: this delay is present in TI sample drivers */
206 /* but there seems to be no TRM requirement for it */
207 udelay(10);
208}
209
2d6d649a
PU		 210static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
211 struct device_node *node)
212{
213 int value;
214
215 of_property_read_u32(node, "ti,digimic_delay",
216 &pdata->digimic_delay);
217 of_property_read_u32(node, "ti,ramp_delay_value",
218 &pdata->ramp_delay_value);
219 of_property_read_u32(node, "ti,offset_cncl_path",
220 &pdata->offset_cncl_path);
221 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
222 pdata->hs_extmute = value;
223
224 pdata->hs_extmute_gpio = of_get_named_gpio(node,
225 "ti,hs_extmute_gpio", 0);
226 if (gpio_is_valid(pdata->hs_extmute_gpio))
227 pdata->hs_extmute = 1;
228}
229
230static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 231{
4ae6df5e 232 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 233 struct device_node *twl4030_codec_node = NULL;
234
235 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
236 "codec");
237
238 if (!pdata && twl4030_codec_node) {
239 pdata = devm_kzalloc(codec->dev,
240 sizeof(struct twl4030_codec_data),
241 GFP_KERNEL);
242 if (!pdata) {
243 dev_err(codec->dev, "Can not allocate memory\n");
244 return NULL;
245 }
246 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
247 }
248
249 return pdata;
250}
251
252static void twl4030_init_chip(struct snd_soc_codec *codec)
253{
254 struct twl4030_codec_data *pdata;
b2c812e2 255 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 256 u8 reg, byte;
257 int i = 0;
7393958f 258
2d6d649a
PU		 259 pdata = twl4030_get_pdata(codec);
260
5712ded9
PU		 261 if (pdata && pdata->hs_extmute) {
262 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
263 int ret;
264
265 if (!pdata->hs_extmute_gpio)
266 dev_warn(codec->dev,
267 "Extmute GPIO is 0 is this correct?\n");
268
269 ret = gpio_request_one(pdata->hs_extmute_gpio,
270 GPIOF_OUT_INIT_LOW,
271 "hs_extmute");
272 if (ret) {
273 dev_err(codec->dev,
274 "Failed to get hs_extmute GPIO\n");
275 pdata->hs_extmute_gpio = -1;
276 }
277 } else {
278 u8 pin_mux;
279
280 /* Set TWL4030 GPIO6 as EXTMUTE signal */
281 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
282 TWL4030_PMBR1_REG);
283 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
284 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
285 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
286 TWL4030_PMBR1_REG);
281ecd16
PU		 287 }
288 }
289
8b3bca29
PU		 290 /* Initialize the local ctl register cache */
291 tw4030_init_ctl_cache(twl4030);
292
ee4ccac7 293 /* anti-pop when changing analog gain */
efc8acff 294 reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1);
ee4ccac7 295 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
7ded5fe0 296 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 297
ee4ccac7 298 twl4030_write(codec, TWL4030_REG_OPTION,
7ded5fe0
PU		 299 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
300 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 301
3c36cc68
PU		 302 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
303 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
304
ee4ccac7 305 /* Machine dependent setup */
f0fba2ad 306 if (!pdata)
7393958f
PU		 307 return;
308
182f73f6 309 twl4030->pdata = pdata;
ee4ccac7 310
efc8acff 311 reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
ee4ccac7 312 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 313 reg |= (pdata->ramp_delay_value << 2);
efc8acff 314 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 315
316 /* initiate offset cancellation */
ee4ccac7
PU		 317 twl4030_codec_enable(codec, 1);
318
efc8acff 319 reg = twl4030_read(codec, TWL4030_REG_ANAMICL);
ee4ccac7 320 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 321 reg |= pdata->offset_cncl_path;
006f367e 322 twl4030_write(codec, TWL4030_REG_ANAMICL,
7ded5fe0 323 reg | TWL4030_CNCL_OFFSET_START);
006f367e 324
7e6120c5
PU		 325 /*
326 * Wait for offset cancellation to complete.
327 * Since this takes a while, do not slam the i2c.
328 * Start polling the status after ~20ms.
329 */
330 msleep(20);
006f367e 331 do {
7e6120c5 332 usleep_range(1000, 2000);
efc8acff 333 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
fc7b92fc 334 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
7ded5fe0 335 TWL4030_REG_ANAMICL);
efc8acff 336 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
006f367e
PU		 337 } while ((i++ < 100) &&
338 ((byte & TWL4030_CNCL_OFFSET_START) ==
339 TWL4030_CNCL_OFFSET_START));
340
006f367e 341 twl4030_codec_enable(codec, 0);
006f367e
PU		 342}
343
ee4ccac7 344static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 345{
ee4ccac7 346 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 347
348 if (enable) {
349 twl4030->apll_enabled++;
350 if (twl4030->apll_enabled == 1)
bb17bc78 351 twl4030_audio_enable_resource(
57fe7251 352 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 353 } else {
354 twl4030->apll_enabled--;
355 if (!twl4030->apll_enabled)
bb17bc78 356 twl4030_audio_disable_resource(
57fe7251 357 TWL4030_AUDIO_RES_APLL);
ee4ccac7 358 }
006f367e
PU		 359}
360
5e98a464 361/* Earpiece */
1a787e7a
JS		 362static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
366 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
367};
5e98a464 368
2a6f5c58 369/* PreDrive Left */
1a787e7a
JS		 370static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
371 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
372 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
373 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
374 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
375};
2a6f5c58
PU		 376
377/* PreDrive Right */
1a787e7a
JS		 378static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
379 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
380 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
381 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
382 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
383};
2a6f5c58 384
dfad21a2 385/* Headset Left */
1a787e7a
JS		 386static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
387 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
388 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
389 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
390};
dfad21a2
PU		 391
392/* Headset Right */
1a787e7a
JS		 393static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
394 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
395 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
396 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
397};
dfad21a2 398
5152d8c2 399/* Carkit Left */
1a787e7a
JS		 400static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
401 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
402 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
403 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
404};
5152d8c2
PU		 405
406/* Carkit Right */
1a787e7a
JS		 407static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
408 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
409 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
410 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
411};
5152d8c2 412
df339804
PU		 413/* Handsfree Left */
414static const char *twl4030_handsfreel_texts[] =
1a787e7a 415 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804 416
9f04fba7
TI		 417static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,
418 TWL4030_REG_HFL_CTL, 0,
419 twl4030_handsfreel_texts);
df339804
PU		 420
421static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
422SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
423
0f89bdca
PU		 424/* Handsfree Left virtual mute */
425static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 426 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 427
df339804
PU		 428/* Handsfree Right */
429static const char *twl4030_handsfreer_texts[] =
1a787e7a 430 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804 431
9f04fba7
TI		 432static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,
433 TWL4030_REG_HFR_CTL, 0,
434 twl4030_handsfreer_texts);
df339804
PU		 435
436static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
437SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
438
0f89bdca
PU		 439/* Handsfree Right virtual mute */
440static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 441 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 442
376f7839
PU		 443/* Vibra */
444/* Vibra audio path selection */
445static const char *twl4030_vibra_texts[] =
446 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
447
9f04fba7
TI		 448static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,
449 TWL4030_REG_VIBRA_CTL, 2,
450 twl4030_vibra_texts);
376f7839
PU		 451
452static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
453SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
454
455/* Vibra path selection: local vibrator (PWM) or audio driven */
456static const char *twl4030_vibrapath_texts[] =
457 {"Local vibrator", "Audio"};
458
9f04fba7
TI		 459static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,
460 TWL4030_REG_VIBRA_CTL, 4,
461 twl4030_vibrapath_texts);
376f7839
PU		 462
463static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
464SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
465
276c6222 466/* Left analog microphone selection */
97b8096d 467static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 468 SOC_DAPM_SINGLE("Main Mic Capture Switch",
469 TWL4030_REG_ANAMICL, 0, 1, 0),
470 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
471 TWL4030_REG_ANAMICL, 1, 1, 0),
472 SOC_DAPM_SINGLE("AUXL Capture Switch",
473 TWL4030_REG_ANAMICL, 2, 1, 0),
474 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
475 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 476};
276c6222
PU		 477
478/* Right analog microphone selection */
97b8096d 479static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 480 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
481 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 482};
276c6222
PU		 483
484/* TX1 L/R Analog/Digital microphone selection */
485static const char *twl4030_micpathtx1_texts[] =
486 {"Analog", "Digimic0"};
487
9f04fba7
TI		 488static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,
489 TWL4030_REG_ADCMICSEL, 0,
490 twl4030_micpathtx1_texts);
276c6222
PU		 491
492static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
493SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
494
495/* TX2 L/R Analog/Digital microphone selection */
496static const char *twl4030_micpathtx2_texts[] =
497 {"Analog", "Digimic1"};
498
9f04fba7
TI		 499static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,
500 TWL4030_REG_ADCMICSEL, 2,
501 twl4030_micpathtx2_texts);
276c6222
PU		 502
503static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
504SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
505
7393958f
PU		 506/* Analog bypass for AudioR1 */
507static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
508 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
509
510/* Analog bypass for AudioL1 */
511static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
512 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
513
514/* Analog bypass for AudioR2 */
515static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
516 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
517
518/* Analog bypass for AudioL2 */
519static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
520 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
521
fcd274a3
LCM		 522/* Analog bypass for Voice */
523static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
524 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
525
8b0d3153 526/* Digital bypass gain, mute instead of -30dB */
6bab83fd 527static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 528 TLV_DB_RANGE_HEAD(3),
529 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
530 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 531 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
532};
533
534/* Digital bypass left (TX1L -> RX2L) */
535static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
536 SOC_DAPM_SINGLE_TLV("Volume",
537 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
538 twl4030_dapm_dbypass_tlv);
539
540/* Digital bypass right (TX1R -> RX2R) */
541static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
542 SOC_DAPM_SINGLE_TLV("Volume",
543 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
544 twl4030_dapm_dbypass_tlv);
545
ee8f6894
LCM		 546/*
547 * Voice Sidetone GAIN volume control:
548 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
549 */
550static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
551
552/* Digital bypass voice: sidetone (VUL -> VDL)*/
553static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
554 SOC_DAPM_SINGLE_TLV("Volume",
555 TWL4030_REG_VSTPGA, 0, 0x29, 0,
556 twl4030_dapm_dbypassv_tlv);
557
9008adf9
PU		 558/*
559 * Output PGA builder:
560 * Handle the muting and unmuting of the given output (turning off the
561 * amplifier associated with the output pin)
c96907f2
PU		 562 * On mute bypass the reg_cache and write 0 to the register
563 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 564 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
565 */
566#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
567static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
7ded5fe0 568 struct snd_kcontrol *kcontrol, int event) \
9008adf9 569{ \
b2c812e2 570 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 571 \
572 switch (event) { \
573 case SND_SOC_DAPM_POST_PMU: \
c96907f2 574 twl4030->pin_name##_enabled = 1; \
efc8acff 575 twl4030_write(w->codec, reg, twl4030_read(w->codec, reg)); \
9008adf9
PU		 576 break; \
577 case SND_SOC_DAPM_POST_PMD: \
c96907f2 578 twl4030->pin_name##_enabled = 0; \
7ded5fe0 579 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \
9008adf9
PU		 580 break; \
581 } \
582 return 0; \
583}
584
585TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
586TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
587TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
588TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
589TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
590
5a2e9a48 591static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 592{
49d92c7d
SM		 593 unsigned char hs_ctl;
594
efc8acff 595 hs_ctl = twl4030_read(codec, reg);
49d92c7d 596
5a2e9a48
PU		 597 if (ramp) {
598 /* HF ramp-up */
599 hs_ctl |= TWL4030_HF_CTL_REF_EN;
600 twl4030_write(codec, reg, hs_ctl);
601 udelay(10);
49d92c7d 602 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 603 twl4030_write(codec, reg, hs_ctl);
604 udelay(40);
49d92c7d 605 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 606 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 607 twl4030_write(codec, reg, hs_ctl);
49d92c7d 608 } else {
5a2e9a48
PU		 609 /* HF ramp-down */
610 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
611 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
612 twl4030_write(codec, reg, hs_ctl);
613 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
614 twl4030_write(codec, reg, hs_ctl);
615 udelay(40);
616 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
617 twl4030_write(codec, reg, hs_ctl);
49d92c7d 618 }
5a2e9a48 619}
49d92c7d 620
5a2e9a48 621static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 622 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 623{
624 switch (event) {
625 case SND_SOC_DAPM_POST_PMU:
626 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
627 break;
628 case SND_SOC_DAPM_POST_PMD:
629 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
630 break;
631 }
632 return 0;
633}
634
635static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 636 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 637{
638 switch (event) {
639 case SND_SOC_DAPM_POST_PMU:
640 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
641 break;
642 case SND_SOC_DAPM_POST_PMD:
643 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
644 break;
645 }
49d92c7d
SM		 646 return 0;
647}
648
86139a13 649static int vibramux_event(struct snd_soc_dapm_widget *w,
7ded5fe0 650 struct snd_kcontrol *kcontrol, int event)
86139a13
JV		 651{
652 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
653 return 0;
654}
655
7729cf74 656static int apll_event(struct snd_soc_dapm_widget *w,
7ded5fe0 657 struct snd_kcontrol *kcontrol, int event)
7729cf74
PU		 658{
659 switch (event) {
660 case SND_SOC_DAPM_PRE_PMU:
661 twl4030_apll_enable(w->codec, 1);
662 break;
663 case SND_SOC_DAPM_POST_PMD:
664 twl4030_apll_enable(w->codec, 0);
665 break;
666 }
667 return 0;
668}
669
7b4c734e 670static int aif_event(struct snd_soc_dapm_widget *w,
7ded5fe0 671 struct snd_kcontrol *kcontrol, int event)
7b4c734e
PU		 672{
673 u8 audio_if;
674
efc8acff 675 audio_if = twl4030_read(w->codec, TWL4030_REG_AUDIO_IF);
7b4c734e
PU		 676 switch (event) {
677 case SND_SOC_DAPM_PRE_PMU:
678 /* Enable AIF */
679 /* enable the PLL before we use it to clock the DAI */
680 twl4030_apll_enable(w->codec, 1);
681
682 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 683 audio_if | TWL4030_AIF_EN);
7b4c734e
PU		 684 break;
685 case SND_SOC_DAPM_POST_PMD:
686 /* disable the DAI before we stop it's source PLL */
687 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 688 audio_if & ~TWL4030_AIF_EN);
7b4c734e
PU		 689 twl4030_apll_enable(w->codec, 0);
690 break;
691 }
692 return 0;
693}
694
6943c92e 695static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 696{
697 unsigned char hs_gain, hs_pop;
b2c812e2 698 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 699 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 700 /* Base values for ramp delay calculation: 2^19 - 2^26 */
701 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
702 8388608, 16777216, 33554432, 67108864};
7e6120c5 703 unsigned int delay;
aad749e5 704
efc8acff
PU		 705 hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET);
706 hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 707 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
708 twl4030->sysclk) + 1;
aad749e5 709
4e49ffd1
CVJ		 710 /* Enable external mute control, this dramatically reduces
711 * the pop-noise */
f0fba2ad 712 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 713 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
714 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 715 } else {
716 hs_pop |= TWL4030_EXTMUTE;
717 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
718 }
719 }
720
6943c92e
PU		 721 if (ramp) {
722 /* Headset ramp-up according to the TRM */
aad749e5 723 hs_pop |= TWL4030_VMID_EN;
6943c92e 724 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2 725 /* Actually write to the register */
7ded5fe0
PU		 726 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
727 TWL4030_REG_HS_GAIN_SET);
aad749e5 728 hs_pop |= TWL4030_RAMP_EN;
6943c92e 729 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 730 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 731 twl4030_wait_ms(delay);
6943c92e
PU		 732 } else {
733 /* Headset ramp-down _not_ according to
734 * the TRM, but in a way that it is working */
aad749e5 735 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 736 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
737 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 738 twl4030_wait_ms(delay);
aad749e5 739 /* Bypass the reg_cache to mute the headset */
7ded5fe0
PU		 740 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
741 TWL4030_REG_HS_GAIN_SET);
6943c92e 742
aad749e5 743 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 744 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
745 }
4e49ffd1
CVJ		 746
747 /* Disable external mute */
f0fba2ad 748 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 749 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
750 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 751 } else {
752 hs_pop &= ~TWL4030_EXTMUTE;
753 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
754 }
755 }
6943c92e
PU		 756}
757
758static int headsetlpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 759 struct snd_kcontrol *kcontrol, int event)
6943c92e 760{
b2c812e2 761 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 762
763 switch (event) {
764 case SND_SOC_DAPM_POST_PMU:
765 /* Do the ramp-up only once */
766 if (!twl4030->hsr_enabled)
767 headset_ramp(w->codec, 1);
768
769 twl4030->hsl_enabled = 1;
770 break;
771 case SND_SOC_DAPM_POST_PMD:
772 /* Do the ramp-down only if both headsetL/R is disabled */
773 if (!twl4030->hsr_enabled)
774 headset_ramp(w->codec, 0);
775
776 twl4030->hsl_enabled = 0;
777 break;
778 }
779 return 0;
780}
781
782static int headsetrpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 783 struct snd_kcontrol *kcontrol, int event)
6943c92e 784{
b2c812e2 785 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 786
787 switch (event) {
788 case SND_SOC_DAPM_POST_PMU:
789 /* Do the ramp-up only once */
790 if (!twl4030->hsl_enabled)
791 headset_ramp(w->codec, 1);
792
793 twl4030->hsr_enabled = 1;
794 break;
795 case SND_SOC_DAPM_POST_PMD:
796 /* Do the ramp-down only if both headsetL/R is disabled */
797 if (!twl4030->hsl_enabled)
798 headset_ramp(w->codec, 0);
799
800 twl4030->hsr_enabled = 0;
aad749e5
PU		 801 break;
802 }
803 return 0;
804}
805
01ea6ba2 806static int digimic_event(struct snd_soc_dapm_widget *w,
7ded5fe0 807 struct snd_kcontrol *kcontrol, int event)
01ea6ba2
PU		 808{
809 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 810 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 811
182f73f6
PU		 812 if (pdata && pdata->digimic_delay)
813 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 814 return 0;
815}
816
b0bd53a7
PU		 817/*
818 * Some of the gain controls in TWL (mostly those which are associated with
819 * the outputs) are implemented in an interesting way:
820 * 0x0 : Power down (mute)
821 * 0x1 : 6dB
822 * 0x2 : 0 dB
823 * 0x3 : -6 dB
824 * Inverting not going to help with these.
825 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
826 */
b0bd53a7 827static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 828 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 829{
830 struct soc_mixer_control *mc =
831 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 832 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 833 unsigned int reg = mc->reg;
834 unsigned int shift = mc->shift;
835 unsigned int rshift = mc->rshift;
836 int max = mc->max;
837 int mask = (1 << fls(max)) - 1;
838
839 ucontrol->value.integer.value[0] =
840 (snd_soc_read(codec, reg) >> shift) & mask;
841 if (ucontrol->value.integer.value[0])
842 ucontrol->value.integer.value[0] =
843 max + 1 - ucontrol->value.integer.value[0];
844
845 if (shift != rshift) {
846 ucontrol->value.integer.value[1] =
847 (snd_soc_read(codec, reg) >> rshift) & mask;
848 if (ucontrol->value.integer.value[1])
849 ucontrol->value.integer.value[1] =
850 max + 1 - ucontrol->value.integer.value[1];
851 }
852
853 return 0;
854}
855
856static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 857 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 858{
859 struct soc_mixer_control *mc =
860 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 861 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 862 unsigned int reg = mc->reg;
863 unsigned int shift = mc->shift;
864 unsigned int rshift = mc->rshift;
865 int max = mc->max;
866 int mask = (1 << fls(max)) - 1;
867 unsigned short val, val2, val_mask;
868
869 val = (ucontrol->value.integer.value[0] & mask);
870
871 val_mask = mask << shift;
872 if (val)
873 val = max + 1 - val;
874 val = val << shift;
875 if (shift != rshift) {
876 val2 = (ucontrol->value.integer.value[1] & mask);
877 val_mask |= mask << rshift;
878 if (val2)
879 val2 = max + 1 - val2;
880 val |= val2 << rshift;
881 }
882 return snd_soc_update_bits(codec, reg, val_mask, val);
883}
884
885static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 886 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 887{
888 struct soc_mixer_control *mc =
889 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 890 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 891 unsigned int reg = mc->reg;
892 unsigned int reg2 = mc->rreg;
893 unsigned int shift = mc->shift;
894 int max = mc->max;
895 int mask = (1<<fls(max))-1;
896
897 ucontrol->value.integer.value[0] =
898 (snd_soc_read(codec, reg) >> shift) & mask;
899 ucontrol->value.integer.value[1] =
900 (snd_soc_read(codec, reg2) >> shift) & mask;
901
902 if (ucontrol->value.integer.value[0])
903 ucontrol->value.integer.value[0] =
904 max + 1 - ucontrol->value.integer.value[0];
905 if (ucontrol->value.integer.value[1])
906 ucontrol->value.integer.value[1] =
907 max + 1 - ucontrol->value.integer.value[1];
908
909 return 0;
910}
911
912static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 913 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 914{
915 struct soc_mixer_control *mc =
916 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 917 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 918 unsigned int reg = mc->reg;
919 unsigned int reg2 = mc->rreg;
920 unsigned int shift = mc->shift;
921 int max = mc->max;
922 int mask = (1 << fls(max)) - 1;
923 int err;
924 unsigned short val, val2, val_mask;
925
926 val_mask = mask << shift;
927 val = (ucontrol->value.integer.value[0] & mask);
928 val2 = (ucontrol->value.integer.value[1] & mask);
929
930 if (val)
931 val = max + 1 - val;
932 if (val2)
933 val2 = max + 1 - val2;
934
935 val = val << shift;
936 val2 = val2 << shift;
937
938 err = snd_soc_update_bits(codec, reg, val_mask, val);
939 if (err < 0)
940 return err;
941
942 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
943 return err;
944}
945
b74bd40f
LCM		 946/* Codec operation modes */
947static const char *twl4030_op_modes_texts[] = {
948 "Option 2 (voice/audio)", "Option 1 (audio)"
949};
950
9f04fba7
TI		 951static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
952 TWL4030_REG_CODEC_MODE, 0,
953 twl4030_op_modes_texts);
b74bd40f 954
423c238d 955static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 956 struct snd_ctl_elem_value *ucontrol)
957{
ea53bf77 958 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 959 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 960
961 if (twl4030->configured) {
3b8a0795
PU		 962 dev_err(codec->dev,
963 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 964 return -EBUSY;
965 }
966
6b207c0f 967 return snd_soc_put_enum_double(kcontrol, ucontrol);
b74bd40f
LCM		 968}
969
c10b82cf
PU		 970/*
971 * FGAIN volume control:
972 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
973 */
d889a72c 974static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 975
0d33ea0b
PU		 976/*
977 * CGAIN volume control:
978 * 0 dB to 12 dB in 6 dB steps
979 * value 2 and 3 means 12 dB
980 */
d889a72c
PU		 981static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
982
1a787e7a
JS		 983/*
984 * Voice Downlink GAIN volume control:
985 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
986 */
987static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
988
d889a72c
PU		 989/*
990 * Analog playback gain
991 * -24 dB to 12 dB in 2 dB steps
992 */
993static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 994
4290239c
PU		 995/*
996 * Gain controls tied to outputs
997 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
998 */
999static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1000
18cc8d8d
JS		 1001/*
1002 * Gain control for earpiece amplifier
1003 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1004 */
1005static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1006
381a22b5
PU		 1007/*
1008 * Capture gain after the ADCs
1009 * from 0 dB to 31 dB in 1 dB steps
1010 */
1011static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1012
5920b453
GI		 1013/*
1014 * Gain control for input amplifiers
1015 * 0 dB to 30 dB in 6 dB steps
1016 */
1017static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1018
328d0a13
LCM		 1019/* AVADC clock priority */
1020static const char *twl4030_avadc_clk_priority_texts[] = {
1021 "Voice high priority", "HiFi high priority"
1022};
1023
9f04fba7
TI		 1024static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,
1025 TWL4030_REG_AVADC_CTL, 2,
1026 twl4030_avadc_clk_priority_texts);
328d0a13 1027
89492be8
PU		 1028static const char *twl4030_rampdelay_texts[] = {
1029 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1030 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1031 "3495/2581/1748 ms"
1032};
1033
9f04fba7
TI		 1034static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,
1035 TWL4030_REG_HS_POPN_SET, 2,
1036 twl4030_rampdelay_texts);
89492be8 1037
376f7839
PU		 1038/* Vibra H-bridge direction mode */
1039static const char *twl4030_vibradirmode_texts[] = {
1040 "Vibra H-bridge direction", "Audio data MSB",
1041};
1042
9f04fba7
TI		 1043static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,
1044 TWL4030_REG_VIBRA_CTL, 5,
1045 twl4030_vibradirmode_texts);
376f7839
PU		 1046
1047/* Vibra H-bridge direction */
1048static const char *twl4030_vibradir_texts[] = {
1049 "Positive polarity", "Negative polarity",
1050};
1051
9f04fba7
TI		 1052static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,
1053 TWL4030_REG_VIBRA_CTL, 1,
1054 twl4030_vibradir_texts);
376f7839 1055
36aeff61
PU		 1056/* Digimic Left and right swapping */
1057static const char *twl4030_digimicswap_texts[] = {
1058 "Not swapped", "Swapped",
1059};
1060
9f04fba7
TI		 1061static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,
1062 TWL4030_REG_MISC_SET_1, 0,
1063 twl4030_digimicswap_texts);
36aeff61 1064
cc17557e 1065static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1066 /* Codec operation mode control */
1067 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1068 snd_soc_get_enum_double,
1069 snd_soc_put_twl4030_opmode_enum_double),
1070
d889a72c
PU		 1071 /* Common playback gain controls */
1072 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1073 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1074 0, 0x3f, 0, digital_fine_tlv),
1075 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1076 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1077 0, 0x3f, 0, digital_fine_tlv),
1078
1079 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1080 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1081 6, 0x2, 0, digital_coarse_tlv),
1082 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1083 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1084 6, 0x2, 0, digital_coarse_tlv),
1085
1086 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1087 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1088 3, 0x12, 1, analog_tlv),
1089 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1090 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1091 3, 0x12, 1, analog_tlv),
44c55870
PU		 1092 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1093 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1094 1, 1, 0),
1095 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1096 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1097 1, 1, 0),
381a22b5 1098
1a787e7a
JS		 1099 /* Common voice downlink gain controls */
1100 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1101 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1102
1103 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1104 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1105
1106 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1107 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1108
4290239c 1109 /* Separate output gain controls */
0f9887d1 1110 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1111 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1112 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1113 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1114
0f9887d1
PU		 1115 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1116 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1117 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1118
0f9887d1 1119 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1120 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1121 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1122 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1123
0f9887d1
PU		 1124 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1125 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1126 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1127
381a22b5 1128 /* Common capture gain controls */
276c6222 1129 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1130 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1131 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1132 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1133 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1134 0, 0x1f, 0, digital_capture_tlv),
5920b453 1135
276c6222 1136 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1137 0, 3, 5, 0, input_gain_tlv),
89492be8 1138
328d0a13
LCM		 1139 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1140
89492be8 1141 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1142
1143 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1144 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1145
1146 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1147};
1148
cc17557e 1149static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1150 /* Left channel inputs */
1151 SND_SOC_DAPM_INPUT("MAINMIC"),
1152 SND_SOC_DAPM_INPUT("HSMIC"),
1153 SND_SOC_DAPM_INPUT("AUXL"),
1154 SND_SOC_DAPM_INPUT("CARKITMIC"),
1155 /* Right channel inputs */
1156 SND_SOC_DAPM_INPUT("SUBMIC"),
1157 SND_SOC_DAPM_INPUT("AUXR"),
1158 /* Digital microphones (Stereo) */
1159 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1160 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1161
1162 /* Outputs */
5e98a464 1163 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1164 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1165 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1166 SND_SOC_DAPM_OUTPUT("HSOL"),
1167 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1168 SND_SOC_DAPM_OUTPUT("CARKITL"),
1169 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1170 SND_SOC_DAPM_OUTPUT("HFL"),
1171 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1172 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1173
7b4c734e
PU		 1174 /* AIF and APLL clocks for running DAIs (including loopback) */
1175 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1176 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1177 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1178
53b5047d 1179 /* DACs */
7f51e7d3
PU		 1180 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1181 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1182 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1183 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1184 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1185
927a7747
PU		 1186 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1187 TWL4030_REG_VOICE_IF, 6, 0),
1188
7393958f 1189 /* Analog bypasses */
78e08e2f
PU		 1190 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1191 &twl4030_dapm_abypassr1_control),
1192 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1193 &twl4030_dapm_abypassl1_control),
1194 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1195 &twl4030_dapm_abypassr2_control),
1196 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1197 &twl4030_dapm_abypassl2_control),
1198 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1199 &twl4030_dapm_abypassv_control),
1200
1201 /* Master analog loopback switch */
1202 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1203 NULL, 0),
7393958f 1204
6bab83fd 1205 /* Digital bypasses */
78e08e2f
PU		 1206 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1207 &twl4030_dapm_dbypassl_control),
1208 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1209 &twl4030_dapm_dbypassr_control),
1210 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1211 &twl4030_dapm_dbypassv_control),
6bab83fd 1212
4005d39a
PU		 1213 /* Digital mixers, power control for the physical DACs */
1214 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1215 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1216 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1217 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1218 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1219 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1220 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1221 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1222 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1223 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1224
1225 /* Analog mixers, power control for the physical PGAs */
1226 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1227 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1228 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1229 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1230 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1231 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1232 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1233 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1234 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1235 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1236
7729cf74
PU		 1237 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1238 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1239
7b4c734e
PU		 1240 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1241 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1242
1a787e7a 1243 /* Output MIXER controls */
5e98a464 1244 /* Earpiece */
1a787e7a
JS		 1245 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1246 &twl4030_dapm_earpiece_controls[0],
1247 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1248 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1249 0, 0, NULL, 0, earpiecepga_event,
1250 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1251 /* PreDrivL/R */
1a787e7a
JS		 1252 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1253 &twl4030_dapm_predrivel_controls[0],
1254 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1255 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1256 0, 0, NULL, 0, predrivelpga_event,
1257 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1258 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1259 &twl4030_dapm_predriver_controls[0],
1260 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1261 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1262 0, 0, NULL, 0, predriverpga_event,
1263 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1264 /* HeadsetL/R */
6943c92e 1265 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1266 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1267 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1268 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1269 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1270 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1271 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1272 &twl4030_dapm_hsor_controls[0],
1273 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1274 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1275 0, 0, NULL, 0, headsetrpga_event,
1276 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1277 /* CarkitL/R */
1a787e7a
JS		 1278 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_carkitl_controls[0],
1280 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1281 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1282 0, 0, NULL, 0, carkitlpga_event,
1283 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1284 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_carkitr_controls[0],
1286 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1287 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1288 0, 0, NULL, 0, carkitrpga_event,
1289 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1290
1291 /* Output MUX controls */
df339804 1292 /* HandsfreeL/R */
5a2e9a48
PU		 1293 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1294 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1295 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1296 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1297 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1298 0, 0, NULL, 0, handsfreelpga_event,
1299 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1300 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1301 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1302 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1303 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1304 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1305 0, 0, NULL, 0, handsfreerpga_event,
1306 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1307 /* Vibra */
86139a13
JV		 1308 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1309 &twl4030_dapm_vibra_control, vibramux_event,
1310 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1311 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1312 &twl4030_dapm_vibrapath_control),
5e98a464 1313
276c6222
PU		 1314 /* Introducing four virtual ADC, since TWL4030 have four channel for
1315 capture */
7f51e7d3
PU		 1316 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1317 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1318 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1319 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1320
927a7747
PU		 1321 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1322 TWL4030_REG_VOICE_IF, 5, 0),
1323
276c6222
PU		 1324 /* Analog/Digital mic path selection.
1325 TX1 Left/Right: either analog Left/Right or Digimic0
1326 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1327 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1328 &twl4030_dapm_micpathtx1_control),
1329 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1330 &twl4030_dapm_micpathtx2_control),
276c6222 1331
97b8096d 1332 /* Analog input mixers for the capture amplifiers */
9028935d 1333 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1334 TWL4030_REG_ANAMICL, 4, 0,
1335 &twl4030_dapm_analoglmic_controls[0],
1336 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1337 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1338 TWL4030_REG_ANAMICR, 4, 0,
1339 &twl4030_dapm_analogrmic_controls[0],
1340 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1341
fb2a2f84
PU		 1342 SND_SOC_DAPM_PGA("ADC Physical Left",
1343 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1344 SND_SOC_DAPM_PGA("ADC Physical Right",
1345 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1346
01ea6ba2
PU		 1347 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1348 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1349 digimic_event, SND_SOC_DAPM_POST_PMU),
1350 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1351 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1352 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1353
bda7d2a8
PU		 1354 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1355 NULL, 0),
1356 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1357 NULL, 0),
1358
e04d6e55
PU		 1359 /* Microphone bias */
1360 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1361 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1362 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1363 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1364 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1365 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1366
927a7747 1367 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1368};
1369
1370static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1371 /* Stream -> DAC mapping */
1372 {"DAC Right1", NULL, "HiFi Playback"},
1373 {"DAC Left1", NULL, "HiFi Playback"},
1374 {"DAC Right2", NULL, "HiFi Playback"},
1375 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1376 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1377
1378 /* ADC -> Stream mapping */
1379 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1380 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1381 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1382 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1383 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1384 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1385 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1386
4005d39a
PU		 1387 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1388 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1389 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1390 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1391 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1392
7729cf74 1393 /* Supply for the digital part (APLL) */
7729cf74
PU		 1394 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1395
27eeb1fe
PU		 1396 {"DAC Left1", NULL, "AIF Enable"},
1397 {"DAC Right1", NULL, "AIF Enable"},
1398 {"DAC Left2", NULL, "AIF Enable"},
1399 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1400 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1401
c42a59ea
PU		 1402 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1403 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1404
4005d39a
PU		 1405 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1406 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1407 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1408 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1409 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1410
5e98a464
PU		 1411 /* Internal playback routings */
1412 /* Earpiece */
4005d39a
PU		 1413 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1414 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1415 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1416 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1417 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1418 /* PreDrivL */
4005d39a
PU		 1419 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1420 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1421 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1422 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1423 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1424 /* PreDrivR */
4005d39a
PU		 1425 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1426 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1427 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1428 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1429 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1430 /* HeadsetL */
4005d39a
PU		 1431 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1432 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1433 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1434 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1435 /* HeadsetR */
4005d39a
PU		 1436 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1437 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1438 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1439 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1440 /* CarkitL */
4005d39a
PU		 1441 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1442 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1443 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1444 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1445 /* CarkitR */
4005d39a
PU		 1446 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1447 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1448 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1449 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1450 /* HandsfreeL */
4005d39a
PU		 1451 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1452 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1453 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1454 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1455 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1456 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1457 /* HandsfreeR */
4005d39a
PU		 1458 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1459 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1460 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1461 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1462 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1463 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1464 /* Vibra */
1465 {"Vibra Mux", "AudioL1", "DAC Left1"},
1466 {"Vibra Mux", "AudioR1", "DAC Right1"},
1467 {"Vibra Mux", "AudioL2", "DAC Left2"},
1468 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1469
cc17557e 1470 /* outputs */
7b4c734e 1471 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1472 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1473 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1474 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1475 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1476 /* Must be always connected (for APLL) */
1477 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1478 /* Physical outputs */
9008adf9
PU		 1479 {"EARPIECE", NULL, "Earpiece PGA"},
1480 {"PREDRIVEL", NULL, "PredriveL PGA"},
1481 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1482 {"HSOL", NULL, "HeadsetL PGA"},
1483 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1484 {"CARKITL", NULL, "CarkitL PGA"},
1485 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1486 {"HFL", NULL, "HandsfreeL PGA"},
1487 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1488 {"Vibra Route", "Audio", "Vibra Mux"},
1489 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1490
276c6222 1491 /* Capture path */
7b4c734e
PU		 1492 /* Must be always connected (for AIF and APLL) */
1493 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1494 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1495 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1496 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1497 /* Physical inputs */
9028935d
PU		 1498 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1499 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1500 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1501 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1502
9028935d
PU		 1503 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1504 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1505
9028935d
PU		 1506 {"ADC Physical Left", NULL, "Analog Left"},
1507 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1508
1509 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1510 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1511
bda7d2a8
PU		 1512 {"DIGIMIC0", NULL, "micbias1 select"},
1513 {"DIGIMIC1", NULL, "micbias2 select"},
1514
276c6222 1515 /* TX1 Left capture path */
fb2a2f84 1516 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1517 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1518 /* TX1 Right capture path */
fb2a2f84 1519 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1520 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1521 /* TX2 Left capture path */
fb2a2f84 1522 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1523 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1524 /* TX2 Right capture path */
fb2a2f84 1525 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1526 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1527
1528 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1529 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1530 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1531 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1532
c42a59ea
PU		 1533 {"ADC Virtual Left1", NULL, "AIF Enable"},
1534 {"ADC Virtual Right1", NULL, "AIF Enable"},
1535 {"ADC Virtual Left2", NULL, "AIF Enable"},
1536 {"ADC Virtual Right2", NULL, "AIF Enable"},
1537
7393958f 1538 /* Analog bypass routes */
9028935d
PU		 1539 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1540 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1541 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1542 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1543 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1544
78e08e2f
PU		 1545 /* Supply for the Analog loopbacks */
1546 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1547 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1548 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1549 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1550 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1551
7393958f
PU		 1552 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1553 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1554 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1555 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1556 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1557
6bab83fd
PU		 1558 /* Digital bypass routes */
1559 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1560 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1561 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1562
4005d39a
PU		 1563 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1564 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1565 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1566
cc17557e
SS		 1567};
1568
cc17557e
SS		 1569static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1570 enum snd_soc_bias_level level)
1571{
1572 switch (level) {
1573 case SND_SOC_BIAS_ON:
cc17557e
SS		 1574 break;
1575 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1576 break;
1577 case SND_SOC_BIAS_STANDBY:
ce6120cc 1578 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1579 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1580 break;
1581 case SND_SOC_BIAS_OFF:
cbd2db12 1582 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1583 break;
1584 }
ce6120cc 1585 codec->dapm.bias_level = level;
cc17557e
SS		 1586
1587 return 0;
1588}
1589
6b87a91f
PU		 1590static void twl4030_constraints(struct twl4030_priv *twl4030,
1591 struct snd_pcm_substream *mst_substream)
1592{
1593 struct snd_pcm_substream *slv_substream;
1594
1595 /* Pick the stream, which need to be constrained */
1596 if (mst_substream == twl4030->master_substream)
1597 slv_substream = twl4030->slave_substream;
1598 else if (mst_substream == twl4030->slave_substream)
1599 slv_substream = twl4030->master_substream;
1600 else /* This should not happen.. */
1601 return;
1602
1603 /* Set the constraints according to the already configured stream */
1604 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1605 SNDRV_PCM_HW_PARAM_RATE,
1606 twl4030->rate,
1607 twl4030->rate);
1608
1609 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1610 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1611 twl4030->sample_bits,
1612 twl4030->sample_bits);
1613
1614 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1615 SNDRV_PCM_HW_PARAM_CHANNELS,
1616 twl4030->channels,
1617 twl4030->channels);
1618}
1619
8a1f936a
PU		 1620/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1621 * capture has to be enabled/disabled. */
1622static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1623 int enable)
8a1f936a
PU		 1624{
1625 u8 reg, mask;
1626
efc8acff 1627 reg = twl4030_read(codec, TWL4030_REG_OPTION);
8a1f936a
PU		 1628
1629 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1630 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1631 else
1632 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1633
1634 if (enable)
1635 reg |= mask;
1636 else
1637 reg &= ~mask;
1638
1639 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1640}
1641
d6648da1
PU		 1642static int twl4030_startup(struct snd_pcm_substream *substream,
1643 struct snd_soc_dai *dai)
7220b9f4 1644{
e6968a17 1645 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1646 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1647
7220b9f4 1648 if (twl4030->master_substream) {
7220b9f4 1649 twl4030->slave_substream = substream;
6b87a91f
PU		 1650 /* The DAI has one configuration for playback and capture, so
1651 * if the DAI has been already configured then constrain this
1652 * substream to match it. */
1653 if (twl4030->configured)
1654 twl4030_constraints(twl4030, twl4030->master_substream);
1655 } else {
efc8acff 1656 if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) &
8a1f936a
PU		 1657 TWL4030_OPTION_1)) {
1658 /* In option2 4 channel is not supported, set the
1659 * constraint for the first stream for channels, the
1660 * second stream will 'inherit' this cosntraint */
1661 snd_pcm_hw_constraint_minmax(substream->runtime,
7ded5fe0
PU		 1662 SNDRV_PCM_HW_PARAM_CHANNELS,
1663 2, 2);
8a1f936a 1664 }
7220b9f4 1665 twl4030->master_substream = substream;
6b87a91f 1666 }
7220b9f4
PU		 1667
1668 return 0;
1669}
1670
d6648da1
PU		 1671static void twl4030_shutdown(struct snd_pcm_substream *substream,
1672 struct snd_soc_dai *dai)
7220b9f4 1673{
e6968a17 1674 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1675 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1676
1677 if (twl4030->master_substream == substream)
1678 twl4030->master_substream = twl4030->slave_substream;
1679
1680 twl4030->slave_substream = NULL;
6b87a91f
PU		 1681
1682 /* If all streams are closed, or the remaining stream has not yet
1683 * been configured than set the DAI as not configured. */
1684 if (!twl4030->master_substream)
1685 twl4030->configured = 0;
1686 else if (!twl4030->master_substream->runtime->channels)
1687 twl4030->configured = 0;
8a1f936a
PU		 1688
1689 /* If the closing substream had 4 channel, do the necessary cleanup */
1690 if (substream->runtime->channels == 4)
1691 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1692}
1693
cc17557e 1694static int twl4030_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1695 struct snd_pcm_hw_params *params,
1696 struct snd_soc_dai *dai)
cc17557e 1697{
e6968a17 1698 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1699 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1700 u8 mode, old_mode, format, old_format;
1701
8a1f936a
PU		 1702 /* If the substream has 4 channel, do the necessary setup */
1703 if (params_channels(params) == 4) {
efc8acff
PU		 1704 format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
1705 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE);
eaf1ac8b
PU		 1706
1707 /* Safety check: are we in the correct operating mode and
1708 * the interface is in TDM mode? */
1709 if ((mode & TWL4030_OPTION_1) &&
1710 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1711 twl4030_tdm_enable(codec, substream->stream, 1);
1712 else
1713 return -EINVAL;
1714 }
1715
6b87a91f
PU		 1716 if (twl4030->configured)
1717 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1718 return 0;
1719
cc17557e 1720 /* bit rate */
efc8acff
PU		 1721 old_mode = twl4030_read(codec,
1722 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
cc17557e
SS		 1723 mode = old_mode & ~TWL4030_APLL_RATE;
1724
1725 switch (params_rate(params)) {
1726 case 8000:
1727 mode |= TWL4030_APLL_RATE_8000;
1728 break;
1729 case 11025:
1730 mode |= TWL4030_APLL_RATE_11025;
1731 break;
1732 case 12000:
1733 mode |= TWL4030_APLL_RATE_12000;
1734 break;
1735 case 16000:
1736 mode |= TWL4030_APLL_RATE_16000;
1737 break;
1738 case 22050:
1739 mode |= TWL4030_APLL_RATE_22050;
1740 break;
1741 case 24000:
1742 mode |= TWL4030_APLL_RATE_24000;
1743 break;
1744 case 32000:
1745 mode |= TWL4030_APLL_RATE_32000;
1746 break;
1747 case 44100:
1748 mode |= TWL4030_APLL_RATE_44100;
1749 break;
1750 case 48000:
1751 mode |= TWL4030_APLL_RATE_48000;
1752 break;
103f211d
PU		 1753 case 96000:
1754 mode |= TWL4030_APLL_RATE_96000;
1755 break;
cc17557e 1756 default:
3b8a0795 1757 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1758 params_rate(params));
1759 return -EINVAL;
1760 }
1761
cc17557e 1762 /* sample size */
efc8acff 1763 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1764 format = old_format;
1765 format &= ~TWL4030_DATA_WIDTH;
04f630d8
MB		 1766 switch (params_width(params)) {
1767 case 16:
cc17557e
SS		 1768 format |= TWL4030_DATA_WIDTH_16S_16W;
1769 break;
04f630d8 1770 case 32:
cc17557e
SS		 1771 format |= TWL4030_DATA_WIDTH_32S_24W;
1772 break;
1773 default:
04f630d8
MB		 1774 dev_err(codec->dev, "%s: unsupported bits/sample %d\n",
1775 __func__, params_width(params));
cc17557e
SS		 1776 return -EINVAL;
1777 }
1778
2046f175
PU		 1779 if (format != old_format || mode != old_mode) {
1780 if (twl4030->codec_powered) {
1781 /*
1782 * If the codec is powered, than we need to toggle the
1783 * codec power.
1784 */
1785 twl4030_codec_enable(codec, 0);
1786 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1787 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1788 twl4030_codec_enable(codec, 1);
1789 } else {
1790 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1791 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1792 }
cc17557e 1793 }
6b87a91f
PU		 1794
1795 /* Store the important parameters for the DAI configuration and set
1796 * the DAI as configured */
1797 twl4030->configured = 1;
1798 twl4030->rate = params_rate(params);
1799 twl4030->sample_bits = hw_param_interval(params,
1800 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1801 twl4030->channels = params_channels(params);
1802
1803 /* If both playback and capture streams are open, and one of them
1804 * is setting the hw parameters right now (since we are here), set
1805 * constraints to the other stream to match the current one. */
1806 if (twl4030->slave_substream)
1807 twl4030_constraints(twl4030, substream);
1808
cc17557e
SS		 1809 return 0;
1810}
1811
7ded5fe0
PU		 1812static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1813 unsigned int freq, int dir)
cc17557e
SS		 1814{
1815 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1816 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1817
1818 switch (freq) {
1819 case 19200000:
cc17557e 1820 case 26000000:
cc17557e 1821 case 38400000:
cc17557e
SS		 1822 break;
1823 default:
3b8a0795 1824 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1825 return -EINVAL;
1826 }
1827
68d01955
PU		 1828 if ((freq / 1000) != twl4030->sysclk) {
1829 dev_err(codec->dev,
3b8a0795 1830 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1831 freq, twl4030->sysclk * 1000);
1832 return -EINVAL;
1833 }
cc17557e
SS		 1834
1835 return 0;
1836}
1837
7ded5fe0 1838static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
cc17557e
SS		 1839{
1840 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1841 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1842 u8 old_format, format;
1843
1844 /* get format */
efc8acff 1845 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1846 format = old_format;
1847
1848 /* set master/slave audio interface */
1849 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1850 case SND_SOC_DAIFMT_CBM_CFM:
1851 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1852 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1853 break;
1854 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1855 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1856 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1857 break;
1858 default:
1859 return -EINVAL;
1860 }
1861
1862 /* interface format */
1863 format &= ~TWL4030_AIF_FORMAT;
1864 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1865 case SND_SOC_DAIFMT_I2S:
1866 format |= TWL4030_AIF_FORMAT_CODEC;
1867 break;
8a1f936a
PU		 1868 case SND_SOC_DAIFMT_DSP_A:
1869 format |= TWL4030_AIF_FORMAT_TDM;
1870 break;
cc17557e
SS		 1871 default:
1872 return -EINVAL;
1873 }
1874
1875 if (format != old_format) {
2046f175
PU		 1876 if (twl4030->codec_powered) {
1877 /*
1878 * If the codec is powered, than we need to toggle the
1879 * codec power.
1880 */
1881 twl4030_codec_enable(codec, 0);
1882 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1883 twl4030_codec_enable(codec, 1);
1884 } else {
1885 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1886 }
cc17557e
SS		 1887 }
1888
1889 return 0;
1890}
1891
68140443
LCM		 1892static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1893{
1894 struct snd_soc_codec *codec = dai->codec;
efc8acff 1895 u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
68140443
LCM		 1896
1897 if (tristate)
1898 reg |= TWL4030_AIF_TRI_EN;
1899 else
1900 reg &= ~TWL4030_AIF_TRI_EN;
1901
1902 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1903}
1904
b7a755a8
MLC		 1905/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1906 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1907static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1908 int enable)
b7a755a8
MLC		 1909{
1910 u8 reg, mask;
1911
efc8acff 1912 reg = twl4030_read(codec, TWL4030_REG_OPTION);
b7a755a8
MLC		 1913
1914 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1915 mask = TWL4030_ARXL1_VRX_EN;
1916 else
1917 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1918
1919 if (enable)
1920 reg |= mask;
1921 else
1922 reg &= ~mask;
1923
1924 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1925}
1926
7154b3e8 1927static int twl4030_voice_startup(struct snd_pcm_substream *substream,
7ded5fe0 1928 struct snd_soc_dai *dai)
7154b3e8 1929{
e6968a17 1930 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1931 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1932 u8 mode;
1933
1934 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 1935 * not available.
7154b3e8 1936 */
68d01955 1937 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 1938 dev_err(codec->dev,
1939 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1940 __func__, twl4030->sysclk);
7154b3e8
JS		 1941 return -EINVAL;
1942 }
1943
1944 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 1945 * available.
7154b3e8 1946 */
efc8acff 1947 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE)
7154b3e8
JS		 1948 & TWL4030_OPT_MODE;
1949
1950 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 1951 dev_err(codec->dev, "%s: the codec mode is not option2\n",
1952 __func__);
7154b3e8
JS		 1953 return -EINVAL;
1954 }
1955
1956 return 0;
1957}
1958
b7a755a8 1959static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
7ded5fe0 1960 struct snd_soc_dai *dai)
b7a755a8 1961{
e6968a17 1962 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 1963
1964 /* Enable voice digital filters */
1965 twl4030_voice_enable(codec, substream->stream, 0);
1966}
1967
7154b3e8 1968static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1969 struct snd_pcm_hw_params *params,
1970 struct snd_soc_dai *dai)
7154b3e8 1971{
e6968a17 1972 struct snd_soc_codec *codec = dai->codec;
2046f175 1973 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1974 u8 old_mode, mode;
1975
b7a755a8
MLC		 1976 /* Enable voice digital filters */
1977 twl4030_voice_enable(codec, substream->stream, 1);
1978
7154b3e8 1979 /* bit rate */
7ded5fe0
PU		 1980 old_mode = twl4030_read(codec,
1981 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
7154b3e8
JS		 1982 mode = old_mode;
1983
1984 switch (params_rate(params)) {
1985 case 8000:
1986 mode &= ~(TWL4030_SEL_16K);
1987 break;
1988 case 16000:
1989 mode |= TWL4030_SEL_16K;
1990 break;
1991 default:
3b8a0795 1992 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 1993 params_rate(params));
1994 return -EINVAL;
1995 }
1996
1997 if (mode != old_mode) {
2046f175
PU		 1998 if (twl4030->codec_powered) {
1999 /*
2000 * If the codec is powered, than we need to toggle the
2001 * codec power.
2002 */
2003 twl4030_codec_enable(codec, 0);
2004 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2005 twl4030_codec_enable(codec, 1);
2006 } else {
2007 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2008 }
7154b3e8
JS		 2009 }
2010
2011 return 0;
2012}
2013
2014static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
7ded5fe0 2015 int clk_id, unsigned int freq, int dir)
7154b3e8
JS		 2016{
2017 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2018 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2019
68d01955 2020 if (freq != 26000000) {
3b8a0795
PU		 2021 dev_err(codec->dev,
2022 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2023 __func__, freq / 1000);
68d01955
PU		 2024 return -EINVAL;
2025 }
2026 if ((freq / 1000) != twl4030->sysclk) {
2027 dev_err(codec->dev,
3b8a0795 2028 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2029 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2030 return -EINVAL;
2031 }
7154b3e8
JS		 2032 return 0;
2033}
2034
2035static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
7ded5fe0 2036 unsigned int fmt)
7154b3e8
JS		 2037{
2038 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2039 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2040 u8 old_format, format;
2041
2042 /* get format */
efc8acff 2043 old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF);
7154b3e8
JS		 2044 format = old_format;
2045
2046 /* set master/slave audio interface */
2047 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2048 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2049 format &= ~(TWL4030_VIF_SLAVE_EN);
2050 break;
2051 case SND_SOC_DAIFMT_CBS_CFS:
2052 format |= TWL4030_VIF_SLAVE_EN;
2053 break;
2054 default:
2055 return -EINVAL;
2056 }
2057
2058 /* clock inversion */
2059 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2060 case SND_SOC_DAIFMT_IB_NF:
2061 format &= ~(TWL4030_VIF_FORMAT);
2062 break;
2063 case SND_SOC_DAIFMT_NB_IF:
2064 format |= TWL4030_VIF_FORMAT;
2065 break;
2066 default:
2067 return -EINVAL;
2068 }
2069
2070 if (format != old_format) {
2046f175
PU		 2071 if (twl4030->codec_powered) {
2072 /*
2073 * If the codec is powered, than we need to toggle the
2074 * codec power.
2075 */
2076 twl4030_codec_enable(codec, 0);
2077 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2078 twl4030_codec_enable(codec, 1);
2079 } else {
2080 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2081 }
7154b3e8
JS		 2082 }
2083
2084 return 0;
2085}
2086
68140443
LCM		 2087static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2088{
2089 struct snd_soc_codec *codec = dai->codec;
efc8acff 2090 u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF);
68140443
LCM		 2091
2092 if (tristate)
2093 reg |= TWL4030_VIF_TRI_EN;
2094 else
2095 reg &= ~TWL4030_VIF_TRI_EN;
2096
2097 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2098}
2099
bbba9444 2100#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2101#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2102
85e7652d 2103static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2104 .startup = twl4030_startup,
2105 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2106 .hw_params = twl4030_hw_params,
2107 .set_sysclk = twl4030_set_dai_sysclk,
2108 .set_fmt = twl4030_set_dai_fmt,
68140443 2109 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2110};
2111
85e7652d 2112static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2113 .startup = twl4030_voice_startup,
b7a755a8 2114 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2115 .hw_params = twl4030_voice_hw_params,
2116 .set_sysclk = twl4030_voice_set_dai_sysclk,
2117 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2118 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2119};
2120
f0fba2ad 2121static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2122{
f0fba2ad 2123 .name = "twl4030-hifi",
cc17557e 2124 .playback = {
b4852b79 2125 .stream_name = "HiFi Playback",
cc17557e 2126 .channels_min = 2,
8a1f936a 2127 .channels_max = 4,
31ad0f31 2128 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2129 .formats = TWL4030_FORMATS,
2130 .sig_bits = 24,},
cc17557e 2131 .capture = {
7f51e7d3 2132 .stream_name = "HiFi Capture",
cc17557e 2133 .channels_min = 2,
8a1f936a 2134 .channels_max = 4,
cc17557e 2135 .rates = TWL4030_RATES,
8819f65c
PU		 2136 .formats = TWL4030_FORMATS,
2137 .sig_bits = 24,},
f0fba2ad 2138 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2139},
2140{
f0fba2ad 2141 .name = "twl4030-voice",
7154b3e8 2142 .playback = {
b4852b79 2143 .stream_name = "Voice Playback",
7154b3e8
JS		 2144 .channels_min = 1,
2145 .channels_max = 1,
2146 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2147 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2148 .capture = {
7f51e7d3 2149 .stream_name = "Voice Capture",
7154b3e8
JS		 2150 .channels_min = 1,
2151 .channels_max = 2,
2152 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2153 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2154 .ops = &twl4030_dai_voice_ops,
2155},
cc17557e 2156};
cc17557e 2157
f0fba2ad 2158static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2159{
f0fba2ad 2160 struct twl4030_priv *twl4030;
9da28c7b 2161
f2b1ce49
PU		 2162 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2163 GFP_KERNEL);
04cc41a8 2164 if (!twl4030)
f0fba2ad 2165 return -ENOMEM;
f0fba2ad
LG		 2166 snd_soc_codec_set_drvdata(codec, twl4030);
2167 /* Set the defaults, and power up the codec */
57fe7251 2168 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2169
2170 twl4030_init_chip(codec);
cc17557e 2171
7a1fecf5 2172 return 0;
cc17557e
SS		 2173}
2174
f0fba2ad 2175static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2176{
5b3b0fa8 2177 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2178 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2179
281ecd16
PU		 2180 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2181 gpio_free(pdata->hs_extmute_gpio);
2182
7a1fecf5
PU		 2183 return 0;
2184}
2185
f0fba2ad
LG		 2186static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2187 .probe = twl4030_soc_probe,
2188 .remove = twl4030_soc_remove,
efc8acff 2189 .read = twl4030_read,
f0fba2ad
LG		 2190 .write = twl4030_write,
2191 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2192 .idle_bias_off = true,
f7c93f01
PU		 2193
2194 .controls = twl4030_snd_controls,
2195 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2196 .dapm_widgets = twl4030_dapm_widgets,
2197 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2198 .dapm_routes = intercon,
2199 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2200};
2201
05c4c6f7 2202static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2203{
f0fba2ad 2204 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
7ded5fe0 2205 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2206}
2207
05c4c6f7 2208static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2209{
f0fba2ad 2210 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2211 return 0;
2212}
2213
f0fba2ad 2214MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2215
2216static struct platform_driver twl4030_codec_driver = {
2217 .probe = twl4030_codec_probe,
05c4c6f7 2218 .remove = twl4030_codec_remove,
7a1fecf5 2219 .driver = {
f0fba2ad 2220 .name = "twl4030-codec",
7a1fecf5 2221 },
cc17557e 2222};
cc17557e 2223
5bbcc3c0 2224module_platform_driver(twl4030_codec_driver);
64089b84 2225
cc17557e
SS		 2226MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2227MODULE_AUTHOR("Steve Sakoman");
2228MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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