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ASoC: TWL4030: Add DAPM event handler for output MUX selection
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
e8ff9c41
PU		 193static int outmixer_event(struct snd_soc_dapm_widget *w,
194 struct snd_kcontrol *kcontrol, int event)
195{
196 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
197 int ret = 0;
198 int val;
199
200 switch (e->reg) {
201 case TWL4030_REG_PREDL_CTL:
202 case TWL4030_REG_PREDR_CTL:
203 case TWL4030_REG_EAR_CTL:
204 val = w->value >> e->shift_l;
205 if (val == 3) {
206 printk(KERN_WARNING
207 "Invalid MUX setting for register 0x%02x (%d)\n",
208 e->reg, val);
209 ret = -1;
210 }
211 break;
212 }
213
214 return ret;
215}
216
b0bd53a7
PU		 217/*
218 * Some of the gain controls in TWL (mostly those which are associated with
219 * the outputs) are implemented in an interesting way:
220 * 0x0 : Power down (mute)
221 * 0x1 : 6dB
222 * 0x2 : 0 dB
223 * 0x3 : -6 dB
224 * Inverting not going to help with these.
225 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
226 */
227#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
228 xinvert, tlv_array) \
229{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
230 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
231 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
232 .tlv.p = (tlv_array), \
233 .info = snd_soc_info_volsw, \
234 .get = snd_soc_get_volsw_twl4030, \
235 .put = snd_soc_put_volsw_twl4030, \
236 .private_value = (unsigned long)&(struct soc_mixer_control) \
237 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
238 .max = xmax, .invert = xinvert} }
239#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
240 xinvert, tlv_array) \
241{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
242 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
243 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
244 .tlv.p = (tlv_array), \
245 .info = snd_soc_info_volsw_2r, \
246 .get = snd_soc_get_volsw_r2_twl4030,\
247 .put = snd_soc_put_volsw_r2_twl4030, \
248 .private_value = (unsigned long)&(struct soc_mixer_control) \
249 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
250 .max = xmax, .invert = xinvert} }
251#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
252 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
253 xinvert, tlv_array)
254
255static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
256 struct snd_ctl_elem_value *ucontrol)
257{
258 struct soc_mixer_control *mc =
259 (struct soc_mixer_control *)kcontrol->private_value;
260 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
261 unsigned int reg = mc->reg;
262 unsigned int shift = mc->shift;
263 unsigned int rshift = mc->rshift;
264 int max = mc->max;
265 int mask = (1 << fls(max)) - 1;
266
267 ucontrol->value.integer.value[0] =
268 (snd_soc_read(codec, reg) >> shift) & mask;
269 if (ucontrol->value.integer.value[0])
270 ucontrol->value.integer.value[0] =
271 max + 1 - ucontrol->value.integer.value[0];
272
273 if (shift != rshift) {
274 ucontrol->value.integer.value[1] =
275 (snd_soc_read(codec, reg) >> rshift) & mask;
276 if (ucontrol->value.integer.value[1])
277 ucontrol->value.integer.value[1] =
278 max + 1 - ucontrol->value.integer.value[1];
279 }
280
281 return 0;
282}
283
284static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
285 struct snd_ctl_elem_value *ucontrol)
286{
287 struct soc_mixer_control *mc =
288 (struct soc_mixer_control *)kcontrol->private_value;
289 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
290 unsigned int reg = mc->reg;
291 unsigned int shift = mc->shift;
292 unsigned int rshift = mc->rshift;
293 int max = mc->max;
294 int mask = (1 << fls(max)) - 1;
295 unsigned short val, val2, val_mask;
296
297 val = (ucontrol->value.integer.value[0] & mask);
298
299 val_mask = mask << shift;
300 if (val)
301 val = max + 1 - val;
302 val = val << shift;
303 if (shift != rshift) {
304 val2 = (ucontrol->value.integer.value[1] & mask);
305 val_mask |= mask << rshift;
306 if (val2)
307 val2 = max + 1 - val2;
308 val |= val2 << rshift;
309 }
310 return snd_soc_update_bits(codec, reg, val_mask, val);
311}
312
313static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
314 struct snd_ctl_elem_value *ucontrol)
315{
316 struct soc_mixer_control *mc =
317 (struct soc_mixer_control *)kcontrol->private_value;
318 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
319 unsigned int reg = mc->reg;
320 unsigned int reg2 = mc->rreg;
321 unsigned int shift = mc->shift;
322 int max = mc->max;
323 int mask = (1<<fls(max))-1;
324
325 ucontrol->value.integer.value[0] =
326 (snd_soc_read(codec, reg) >> shift) & mask;
327 ucontrol->value.integer.value[1] =
328 (snd_soc_read(codec, reg2) >> shift) & mask;
329
330 if (ucontrol->value.integer.value[0])
331 ucontrol->value.integer.value[0] =
332 max + 1 - ucontrol->value.integer.value[0];
333 if (ucontrol->value.integer.value[1])
334 ucontrol->value.integer.value[1] =
335 max + 1 - ucontrol->value.integer.value[1];
336
337 return 0;
338}
339
340static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
341 struct snd_ctl_elem_value *ucontrol)
342{
343 struct soc_mixer_control *mc =
344 (struct soc_mixer_control *)kcontrol->private_value;
345 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
346 unsigned int reg = mc->reg;
347 unsigned int reg2 = mc->rreg;
348 unsigned int shift = mc->shift;
349 int max = mc->max;
350 int mask = (1 << fls(max)) - 1;
351 int err;
352 unsigned short val, val2, val_mask;
353
354 val_mask = mask << shift;
355 val = (ucontrol->value.integer.value[0] & mask);
356 val2 = (ucontrol->value.integer.value[1] & mask);
357
358 if (val)
359 val = max + 1 - val;
360 if (val2)
361 val2 = max + 1 - val2;
362
363 val = val << shift;
364 val2 = val2 << shift;
365
366 err = snd_soc_update_bits(codec, reg, val_mask, val);
367 if (err < 0)
368 return err;
369
370 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
371 return err;
372}
373
5920b453
GI		 374static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol)
376{
377 struct snd_soc_codec *codec = kcontrol->private_data;
378 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
379 int result = 0;
380
381 /* one bit must be set a time */
382 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
383 | TWL4030_MAINMIC_EN;
384 if (reg != 0) {
385 result++;
386 while ((reg & 1) == 0) {
387 result++;
388 reg >>= 1;
389 }
390 }
391
392 ucontrol->value.integer.value[0] = result;
393 return 0;
394}
395
396static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
397 struct snd_ctl_elem_value *ucontrol)
398{
399 struct snd_soc_codec *codec = kcontrol->private_data;
400 int value = ucontrol->value.integer.value[0];
401 u8 anamicl, micbias, avadc_ctl;
402
403 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
404 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
405 | TWL4030_MAINMIC_EN);
406 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
407 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
408 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
409
410 switch (value) {
411 case 1:
412 anamicl |= TWL4030_MAINMIC_EN;
413 micbias |= TWL4030_MICBIAS1_EN;
414 break;
415 case 2:
416 anamicl |= TWL4030_HSMIC_EN;
417 micbias |= TWL4030_HSMICBIAS_EN;
418 break;
419 case 3:
420 anamicl |= TWL4030_AUXL_EN;
421 break;
422 case 4:
423 anamicl |= TWL4030_CKMIC_EN;
424 break;
425 default:
426 break;
427 }
428
429 /* If some input is selected, enable amp and ADC */
430 if (value != 0) {
431 anamicl |= TWL4030_MICAMPL_EN;
432 avadc_ctl |= TWL4030_ADCL_EN;
433 } else {
434 anamicl &= ~TWL4030_MICAMPL_EN;
435 avadc_ctl &= ~TWL4030_ADCL_EN;
436 }
437
438 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
439 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
440 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
441
442 return 1;
443}
444
445static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
446 struct snd_ctl_elem_value *ucontrol)
447{
448 struct snd_soc_codec *codec = kcontrol->private_data;
449 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
450 int value = 0;
451
452 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
453 switch (reg) {
454 case TWL4030_SUBMIC_EN:
455 value = 1;
456 break;
457 case TWL4030_AUXR_EN:
458 value = 2;
459 break;
460 default:
461 break;
462 }
463
464 ucontrol->value.integer.value[0] = value;
465 return 0;
466}
467
468static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
469 struct snd_ctl_elem_value *ucontrol)
470{
471 struct snd_soc_codec *codec = kcontrol->private_data;
472 int value = ucontrol->value.integer.value[0];
473 u8 anamicr, micbias, avadc_ctl;
474
475 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
476 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
477 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
478 micbias &= ~TWL4030_MICBIAS2_EN;
479 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
480
481 switch (value) {
482 case 1:
483 anamicr |= TWL4030_SUBMIC_EN;
484 micbias |= TWL4030_MICBIAS2_EN;
485 break;
486 case 2:
487 anamicr |= TWL4030_AUXR_EN;
488 break;
489 default:
490 break;
491 }
492
493 if (value != 0) {
494 anamicr |= TWL4030_MICAMPR_EN;
495 avadc_ctl |= TWL4030_ADCR_EN;
496 } else {
497 anamicr &= ~TWL4030_MICAMPR_EN;
498 avadc_ctl &= ~TWL4030_ADCR_EN;
499 }
500
501 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
502 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
503 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
504
505 return 1;
506}
507
508static const char *twl4030_left_in_sel[] = {
509 "None",
510 "Main Mic",
511 "Headset Mic",
512 "Line In",
513 "Carkit Mic",
514};
515
516static const char *twl4030_right_in_sel[] = {
517 "None",
518 "Sub Mic",
519 "Line In",
520};
521
522static const struct soc_enum twl4030_left_input_mux =
523 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
524 twl4030_left_in_sel);
525
526static const struct soc_enum twl4030_right_input_mux =
527 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
528 twl4030_right_in_sel);
529
c10b82cf
PU		 530/*
531 * FGAIN volume control:
532 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
533 */
d889a72c 534static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 535
0d33ea0b
PU		 536/*
537 * CGAIN volume control:
538 * 0 dB to 12 dB in 6 dB steps
539 * value 2 and 3 means 12 dB
540 */
d889a72c
PU		 541static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
542
543/*
544 * Analog playback gain
545 * -24 dB to 12 dB in 2 dB steps
546 */
547static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 548
4290239c
PU		 549/*
550 * Gain controls tied to outputs
551 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
552 */
553static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
554
381a22b5
PU		 555/*
556 * Capture gain after the ADCs
557 * from 0 dB to 31 dB in 1 dB steps
558 */
559static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
560
5920b453
GI		 561/*
562 * Gain control for input amplifiers
563 * 0 dB to 30 dB in 6 dB steps
564 */
565static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
566
cc17557e 567static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 568 /* Common playback gain controls */
569 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
570 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
571 0, 0x3f, 0, digital_fine_tlv),
572 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
573 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
574 0, 0x3f, 0, digital_fine_tlv),
575
576 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
577 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
578 6, 0x2, 0, digital_coarse_tlv),
579 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
580 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
581 6, 0x2, 0, digital_coarse_tlv),
582
583 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
584 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
585 3, 0x12, 1, analog_tlv),
586 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
587 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
588 3, 0x12, 1, analog_tlv),
44c55870
PU		 589 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
590 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
591 1, 1, 0),
592 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
593 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
594 1, 1, 0),
381a22b5 595
4290239c
PU		 596 /* Separate output gain controls */
597 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
598 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
599 4, 3, 0, output_tvl),
600
601 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
602 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
603
604 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
605 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
606 4, 3, 0, output_tvl),
607
608 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
609 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
610
381a22b5
PU		 611 /* Common capture gain controls */
612 SOC_DOUBLE_R_TLV("Capture Volume",
613 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
614 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 615
616 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
617 0, 3, 5, 0, input_gain_tlv),
618
619 /* Input source controls */
620 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
621 twl4030_get_left_input, twl4030_put_left_input),
622 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
623 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 624};
625
626/* add non dapm controls */
627static int twl4030_add_controls(struct snd_soc_codec *codec)
628{
629 int err, i;
630
631 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
632 err = snd_ctl_add(codec->card,
633 snd_soc_cnew(&twl4030_snd_controls[i],
634 codec, NULL));
635 if (err < 0)
636 return err;
637 }
638
639 return 0;
640}
641
642static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
643 SND_SOC_DAPM_INPUT("INL"),
644 SND_SOC_DAPM_INPUT("INR"),
645
646 SND_SOC_DAPM_OUTPUT("OUTL"),
647 SND_SOC_DAPM_OUTPUT("OUTR"),
648
53b5047d
PU		 649 /* DACs */
650 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
651 TWL4030_REG_AVDAC_CTL, 0, 0),
652 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
653 TWL4030_REG_AVDAC_CTL, 1, 0),
654 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
655 TWL4030_REG_AVDAC_CTL, 2, 0),
656 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
657 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 658
44c55870
PU		 659 /* Analog PGAs */
660 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
661 0, 0, NULL, 0),
662 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
663 0, 0, NULL, 0),
664 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
665 0, 0, NULL, 0),
666 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
667 0, 0, NULL, 0),
668
cc17557e
SS		 669 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
671};
672
673static const struct snd_soc_dapm_route intercon[] = {
44c55870
PU		 674 {"ARXL1_APGA", NULL, "DACL1"},
675 {"ARXR1_APGA", NULL, "DACR1"},
676 {"ARXL2_APGA", NULL, "DACL2"},
677 {"ARXR2_APGA", NULL, "DACR2"},
678
cc17557e 679 /* outputs */
44c55870
PU		 680 {"OUTL", NULL, "ARXL2_APGA"},
681 {"OUTR", NULL, "ARXR2_APGA"},
cc17557e
SS		 682
683 /* inputs */
684 {"ADCL", NULL, "INL"},
685 {"ADCR", NULL, "INR"},
686};
687
688static int twl4030_add_widgets(struct snd_soc_codec *codec)
689{
690 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
691 ARRAY_SIZE(twl4030_dapm_widgets));
692
693 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
694
695 snd_soc_dapm_new_widgets(codec);
696 return 0;
697}
698
699static void twl4030_power_up(struct snd_soc_codec *codec)
700{
701 u8 anamicl, regmisc1, byte, popn, hsgain;
702 int i = 0;
703
704 /* set CODECPDZ to turn on codec */
705 twl4030_set_codecpdz(codec);
706
707 /* initiate offset cancellation */
708 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
709 twl4030_write(codec, TWL4030_REG_ANAMICL,
710 anamicl | TWL4030_CNCL_OFFSET_START);
711
712 /* wait for offset cancellation to complete */
713 do {
714 /* this takes a little while, so don't slam i2c */
715 udelay(2000);
716 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
717 TWL4030_REG_ANAMICL);
718 } while ((i++ < 100) &&
719 ((byte & TWL4030_CNCL_OFFSET_START) ==
720 TWL4030_CNCL_OFFSET_START));
721
722 /* anti-pop when changing analog gain */
723 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
724 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
725 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
726
727 /* toggle CODECPDZ as per TRM */
728 twl4030_clear_codecpdz(codec);
729 twl4030_set_codecpdz(codec);
730
731 /* program anti-pop with bias ramp delay */
732 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
733 popn &= TWL4030_RAMP_DELAY;
734 popn |= TWL4030_RAMP_DELAY_645MS;
735 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
736 popn |= TWL4030_VMID_EN;
737 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
738
739 /* enable output stage and gain setting */
740 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
741 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
742
743 /* enable anti-pop ramp */
744 popn |= TWL4030_RAMP_EN;
745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
746}
747
748static void twl4030_power_down(struct snd_soc_codec *codec)
749{
750 u8 popn, hsgain;
751
752 /* disable anti-pop ramp */
753 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
754 popn &= ~TWL4030_RAMP_EN;
755 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
756
757 /* disable output stage and gain setting */
758 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
759 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
760
761 /* disable bias out */
762 popn &= ~TWL4030_VMID_EN;
763 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
764
765 /* power down */
766 twl4030_clear_codecpdz(codec);
767}
768
769static int twl4030_set_bias_level(struct snd_soc_codec *codec,
770 enum snd_soc_bias_level level)
771{
772 switch (level) {
773 case SND_SOC_BIAS_ON:
774 twl4030_power_up(codec);
775 break;
776 case SND_SOC_BIAS_PREPARE:
777 /* TODO: develop a twl4030_prepare function */
778 break;
779 case SND_SOC_BIAS_STANDBY:
780 /* TODO: develop a twl4030_standby function */
781 twl4030_power_down(codec);
782 break;
783 case SND_SOC_BIAS_OFF:
784 twl4030_power_down(codec);
785 break;
786 }
787 codec->bias_level = level;
788
789 return 0;
790}
791
792static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 793 struct snd_pcm_hw_params *params,
794 struct snd_soc_dai *dai)
cc17557e
SS		 795{
796 struct snd_soc_pcm_runtime *rtd = substream->private_data;
797 struct snd_soc_device *socdev = rtd->socdev;
798 struct snd_soc_codec *codec = socdev->codec;
799 u8 mode, old_mode, format, old_format;
800
801
802 /* bit rate */
803 old_mode = twl4030_read_reg_cache(codec,
804 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
805 mode = old_mode & ~TWL4030_APLL_RATE;
806
807 switch (params_rate(params)) {
808 case 8000:
809 mode |= TWL4030_APLL_RATE_8000;
810 break;
811 case 11025:
812 mode |= TWL4030_APLL_RATE_11025;
813 break;
814 case 12000:
815 mode |= TWL4030_APLL_RATE_12000;
816 break;
817 case 16000:
818 mode |= TWL4030_APLL_RATE_16000;
819 break;
820 case 22050:
821 mode |= TWL4030_APLL_RATE_22050;
822 break;
823 case 24000:
824 mode |= TWL4030_APLL_RATE_24000;
825 break;
826 case 32000:
827 mode |= TWL4030_APLL_RATE_32000;
828 break;
829 case 44100:
830 mode |= TWL4030_APLL_RATE_44100;
831 break;
832 case 48000:
833 mode |= TWL4030_APLL_RATE_48000;
834 break;
835 default:
836 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
837 params_rate(params));
838 return -EINVAL;
839 }
840
841 if (mode != old_mode) {
842 /* change rate and set CODECPDZ */
843 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
844 twl4030_set_codecpdz(codec);
845 }
846
847 /* sample size */
848 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
849 format = old_format;
850 format &= ~TWL4030_DATA_WIDTH;
851 switch (params_format(params)) {
852 case SNDRV_PCM_FORMAT_S16_LE:
853 format |= TWL4030_DATA_WIDTH_16S_16W;
854 break;
855 case SNDRV_PCM_FORMAT_S24_LE:
856 format |= TWL4030_DATA_WIDTH_32S_24W;
857 break;
858 default:
859 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
860 params_format(params));
861 return -EINVAL;
862 }
863
864 if (format != old_format) {
865
866 /* clear CODECPDZ before changing format (codec requirement) */
867 twl4030_clear_codecpdz(codec);
868
869 /* change format */
870 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
871
872 /* set CODECPDZ afterwards */
873 twl4030_set_codecpdz(codec);
874 }
875 return 0;
876}
877
878static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
879 int clk_id, unsigned int freq, int dir)
880{
881 struct snd_soc_codec *codec = codec_dai->codec;
882 u8 infreq;
883
884 switch (freq) {
885 case 19200000:
886 infreq = TWL4030_APLL_INFREQ_19200KHZ;
887 break;
888 case 26000000:
889 infreq = TWL4030_APLL_INFREQ_26000KHZ;
890 break;
891 case 38400000:
892 infreq = TWL4030_APLL_INFREQ_38400KHZ;
893 break;
894 default:
895 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
896 freq);
897 return -EINVAL;
898 }
899
900 infreq |= TWL4030_APLL_EN;
901 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
902
903 return 0;
904}
905
906static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
907 unsigned int fmt)
908{
909 struct snd_soc_codec *codec = codec_dai->codec;
910 u8 old_format, format;
911
912 /* get format */
913 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
914 format = old_format;
915
916 /* set master/slave audio interface */
917 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
918 case SND_SOC_DAIFMT_CBM_CFM:
919 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 920 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 921 break;
922 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 923 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 924 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 925 break;
926 default:
927 return -EINVAL;
928 }
929
930 /* interface format */
931 format &= ~TWL4030_AIF_FORMAT;
932 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
933 case SND_SOC_DAIFMT_I2S:
934 format |= TWL4030_AIF_FORMAT_CODEC;
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 if (format != old_format) {
941
942 /* clear CODECPDZ before changing format (codec requirement) */
943 twl4030_clear_codecpdz(codec);
944
945 /* change format */
946 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
947
948 /* set CODECPDZ afterwards */
949 twl4030_set_codecpdz(codec);
950 }
951
952 return 0;
953}
954
bbba9444 955#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 956#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
957
958struct snd_soc_dai twl4030_dai = {
959 .name = "twl4030",
960 .playback = {
961 .stream_name = "Playback",
962 .channels_min = 2,
963 .channels_max = 2,
964 .rates = TWL4030_RATES,
965 .formats = TWL4030_FORMATS,},
966 .capture = {
967 .stream_name = "Capture",
968 .channels_min = 2,
969 .channels_max = 2,
970 .rates = TWL4030_RATES,
971 .formats = TWL4030_FORMATS,},
972 .ops = {
973 .hw_params = twl4030_hw_params,
cc17557e
SS		 974 .set_sysclk = twl4030_set_dai_sysclk,
975 .set_fmt = twl4030_set_dai_fmt,
976 }
977};
978EXPORT_SYMBOL_GPL(twl4030_dai);
979
980static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
981{
982 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
983 struct snd_soc_codec *codec = socdev->codec;
984
985 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
986
987 return 0;
988}
989
990static int twl4030_resume(struct platform_device *pdev)
991{
992 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
993 struct snd_soc_codec *codec = socdev->codec;
994
995 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
996 twl4030_set_bias_level(codec, codec->suspend_bias_level);
997 return 0;
998}
999
1000/*
1001 * initialize the driver
1002 * register the mixer and dsp interfaces with the kernel
1003 */
1004
1005static int twl4030_init(struct snd_soc_device *socdev)
1006{
1007 struct snd_soc_codec *codec = socdev->codec;
1008 int ret = 0;
1009
1010 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1011
1012 codec->name = "twl4030";
1013 codec->owner = THIS_MODULE;
1014 codec->read = twl4030_read_reg_cache;
1015 codec->write = twl4030_write;
1016 codec->set_bias_level = twl4030_set_bias_level;
1017 codec->dai = &twl4030_dai;
1018 codec->num_dai = 1;
1019 codec->reg_cache_size = sizeof(twl4030_reg);
1020 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1021 GFP_KERNEL);
1022 if (codec->reg_cache == NULL)
1023 return -ENOMEM;
1024
1025 /* register pcms */
1026 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1027 if (ret < 0) {
1028 printk(KERN_ERR "twl4030: failed to create pcms\n");
1029 goto pcm_err;
1030 }
1031
1032 twl4030_init_chip(codec);
1033
1034 /* power on device */
1035 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1036
1037 twl4030_add_controls(codec);
1038 twl4030_add_widgets(codec);
1039
968a6025 1040 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1041 if (ret < 0) {
1042 printk(KERN_ERR "twl4030: failed to register card\n");
1043 goto card_err;
1044 }
1045
1046 return ret;
1047
1048card_err:
1049 snd_soc_free_pcms(socdev);
1050 snd_soc_dapm_free(socdev);
1051pcm_err:
1052 kfree(codec->reg_cache);
1053 return ret;
1054}
1055
1056static struct snd_soc_device *twl4030_socdev;
1057
1058static int twl4030_probe(struct platform_device *pdev)
1059{
1060 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1061 struct snd_soc_codec *codec;
1062
1063 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1064 if (codec == NULL)
1065 return -ENOMEM;
1066
1067 socdev->codec = codec;
1068 mutex_init(&codec->mutex);
1069 INIT_LIST_HEAD(&codec->dapm_widgets);
1070 INIT_LIST_HEAD(&codec->dapm_paths);
1071
1072 twl4030_socdev = socdev;
1073 twl4030_init(socdev);
1074
1075 return 0;
1076}
1077
1078static int twl4030_remove(struct platform_device *pdev)
1079{
1080 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1081 struct snd_soc_codec *codec = socdev->codec;
1082
1083 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1084 kfree(codec);
1085
1086 return 0;
1087}
1088
1089struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1090 .probe = twl4030_probe,
1091 .remove = twl4030_remove,
1092 .suspend = twl4030_suspend,
1093 .resume = twl4030_resume,
1094};
1095EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1096
1097MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1098MODULE_AUTHOR("Steve Sakoman");
1099MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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