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ASoC: twl4030: Convert to use devm_kzalloc
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
281ecd16 31#include <linux/gpio.h>
cc17557e
SS		 32#include <sound/core.h>
33#include <sound/pcm.h>
34#include <sound/pcm_params.h>
35#include <sound/soc.h>
cc17557e 36#include <sound/initval.h>
c10b82cf 37#include <sound/tlv.h>
cc17557e 38
f0fba2ad 39/* Register descriptions are here */
57fe7251 40#include <linux/mfd/twl4030-audio.h>
f0fba2ad
LG		 41
42/* Shadow register used by the audio driver */
43#define TWL4030_REG_SW_SHADOW 0x4A
44#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
45
46/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
47#define TWL4030_HFL_EN 0x01
48#define TWL4030_HFR_EN 0x02
cc17557e
SS		 49
50/*
51 * twl4030 register cache & default register settings
52 */
53static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
54 0x00, /* this register not used */
33f92ed4 55 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 56 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 57 0x00, /* REG_UNKNOWN (0x3) */
58 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 59 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 60 0x00, /* REG_ANAMICR (0x6) */
61 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 62 0x00, /* REG_ADCMICSEL (0x8) */
63 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 64 0x0f, /* REG_ATXL1PGA (0xA) */
65 0x0f, /* REG_ATXR1PGA (0xB) */
66 0x0f, /* REG_AVTXL2PGA (0xC) */
67 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 68 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 69 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 70 0x3f, /* REG_ARXR1PGA (0x10) */
71 0x3f, /* REG_ARXL1PGA (0x11) */
72 0x3f, /* REG_ARXR2PGA (0x12) */
73 0x3f, /* REG_ARXL2PGA (0x13) */
74 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 75 0x00, /* REG_VSTPGA (0x15) */
76 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 77 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 78 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 79 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
80 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
81 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
82 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 83 0x00, /* REG_ATX2ARXPGA (0x1D) */
84 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 85 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 86 0x00, /* REG_BTSTPGA (0x20) */
87 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 88 0x00, /* REG_HS_SEL (0x22) */
89 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 90 0x00, /* REG_HS_POPN_SET (0x24) */
91 0x00, /* REG_PREDL_CTL (0x25) */
92 0x00, /* REG_PREDR_CTL (0x26) */
93 0x00, /* REG_PRECKL_CTL (0x27) */
94 0x00, /* REG_PRECKR_CTL (0x28) */
95 0x00, /* REG_HFL_CTL (0x29) */
96 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 97 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 98 0x00, /* REG_ALC_SET1 (0x2C) */
99 0x00, /* REG_ALC_SET2 (0x2D) */
100 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 101 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 102 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 103 0x00, /* REG_DTMF_TONEXT1H (0x31) */
104 0x00, /* REG_DTMF_TONEXT1L (0x32) */
105 0x00, /* REG_DTMF_TONEXT2H (0x33) */
106 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 107 0x79, /* REG_DTMF_TONOFF (0x35) */
108 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 109 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
110 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
111 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 112 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 113 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 114 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
115 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 116 0x00, /* REG_MISC_SET_1 (0x3E) */
117 0x00, /* REG_PCMBTMUX (0x3F) */
118 0x00, /* not used (0x40) */
119 0x00, /* not used (0x41) */
120 0x00, /* not used (0x42) */
121 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 122 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 123 0x00, /* REG_VIBRA_CTL (0x45) */
124 0x00, /* REG_VIBRA_SET (0x46) */
125 0x00, /* REG_VIBRA_PWM_SET (0x47) */
126 0x00, /* REG_ANAMIC_GAIN (0x48) */
127 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 128 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 129};
130
7393958f
PU		 131/* codec private data */
132struct twl4030_priv {
7a1fecf5
PU		 133 struct snd_soc_codec codec;
134
7393958f 135 unsigned int codec_powered;
7b4c734e
PU		 136
137 /* reference counts of AIF/APLL users */
2845fa13 138 unsigned int apll_enabled;
7220b9f4
PU		 139
140 struct snd_pcm_substream *master_substream;
141 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 142
143 unsigned int configured;
144 unsigned int rate;
145 unsigned int sample_bits;
146 unsigned int channels;
6943c92e
PU		 147
148 unsigned int sysclk;
149
c96907f2
PU		 150 /* Output (with associated amp) states */
151 u8 hsl_enabled, hsr_enabled;
152 u8 earpiece_enabled;
153 u8 predrivel_enabled, predriver_enabled;
154 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2
PU		 155
156 /* Delay needed after enabling the digimic interface */
157 unsigned int digimic_delay;
7393958f
PU		 158};
159
cc17557e
SS		 160/*
161 * read twl4030 register cache
162 */
163static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
164 unsigned int reg)
165{
d08664fd 166 u8 *cache = codec->reg_cache;
cc17557e 167
91432e97
IM		 168 if (reg >= TWL4030_CACHEREGNUM)
169 return -EIO;
170
cc17557e
SS		 171 return cache[reg];
172}
173
174/*
175 * write twl4030 register cache
176 */
177static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
178 u8 reg, u8 value)
179{
180 u8 *cache = codec->reg_cache;
181
182 if (reg >= TWL4030_CACHEREGNUM)
183 return;
184 cache[reg] = value;
185}
186
187/*
188 * write to the twl4030 register space
189 */
190static int twl4030_write(struct snd_soc_codec *codec,
191 unsigned int reg, unsigned int value)
192{
b2c812e2 193 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 194 int write_to_reg = 0;
195
cc17557e 196 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 197 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
198 /* Decide if the given register can be written */
199 switch (reg) {
200 case TWL4030_REG_EAR_CTL:
201 if (twl4030->earpiece_enabled)
202 write_to_reg = 1;
203 break;
204 case TWL4030_REG_PREDL_CTL:
205 if (twl4030->predrivel_enabled)
206 write_to_reg = 1;
207 break;
208 case TWL4030_REG_PREDR_CTL:
209 if (twl4030->predriver_enabled)
210 write_to_reg = 1;
211 break;
212 case TWL4030_REG_PRECKL_CTL:
213 if (twl4030->carkitl_enabled)
214 write_to_reg = 1;
215 break;
216 case TWL4030_REG_PRECKR_CTL:
217 if (twl4030->carkitr_enabled)
218 write_to_reg = 1;
219 break;
220 case TWL4030_REG_HS_GAIN_SET:
221 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
222 write_to_reg = 1;
223 break;
224 default:
225 /* All other register can be written */
226 write_to_reg = 1;
227 break;
228 }
229 if (write_to_reg)
230 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 value, reg);
232 }
233 return 0;
cc17557e
SS		 234}
235
7e6120c5
PU		 236static inline void twl4030_wait_ms(int time)
237{
238 if (time < 60) {
239 time *= 1000;
240 usleep_range(time, time + 500);
241 } else {
242 msleep(time);
243 }
244}
245
db04e2c5 246static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 247{
b2c812e2 248 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 249 int mode;
cc17557e 250
7393958f
PU		 251 if (enable == twl4030->codec_powered)
252 return;
253
db04e2c5 254 if (enable)
57fe7251 255 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 256 else
57fe7251 257 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 258
7a1fecf5
PU		 259 if (mode >= 0) {
260 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
261 twl4030->codec_powered = enable;
262 }
cc17557e
SS		 263
264 /* REVISIT: this delay is present in TI sample drivers */
265 /* but there seems to be no TRM requirement for it */
266 udelay(10);
267}
268
9fdcc0f7 269static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 270{
9fdcc0f7
PU		 271 int i, difference = 0;
272 u8 val;
273
274 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
275 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
276 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
277 if (val != twl4030_reg[i]) {
278 difference++;
279 dev_dbg(codec->dev,
280 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
281 i, val, twl4030_reg[i]);
282 }
283 }
25985edc 284 dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
9fdcc0f7
PU		 285 difference, difference ? "Not OK" : "OK");
286}
cc17557e 287
a3a29b55
PU		 288static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
289{
290 int i;
cc17557e
SS		 291
292 /* set all audio section registers to reasonable defaults */
293 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 294 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 295 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 296
297}
298
f0fba2ad 299static void twl4030_init_chip(struct snd_soc_codec *codec)
7393958f 300{
4ae6df5e 301 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
b2c812e2 302 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 303 u8 reg, byte;
304 int i = 0;
7393958f 305
281ecd16
PU		 306 if (pdata && pdata->hs_extmute &&
307 gpio_is_valid(pdata->hs_extmute_gpio)) {
308 int ret;
309
310 if (!pdata->hs_extmute_gpio)
311 dev_warn(codec->dev,
312 "Extmute GPIO is 0 is this correct?\n");
313
314 ret = gpio_request_one(pdata->hs_extmute_gpio,
315 GPIOF_OUT_INIT_LOW, "hs_extmute");
316 if (ret) {
317 dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
318 pdata->hs_extmute_gpio = -1;
319 }
320 }
321
9fdcc0f7 322 /* Check defaults, if instructed before anything else */
f0fba2ad 323 if (pdata && pdata->check_defaults)
9fdcc0f7 324 twl4030_check_defaults(codec);
7a1fecf5 325
a3a29b55 326 /* Reset registers, if no setup data or if instructed to do so */
f0fba2ad 327 if (!pdata || (pdata && pdata->reset_registers))
a3a29b55 328 twl4030_reset_registers(codec);
7393958f 329
ee4ccac7 330 /* Refresh APLL_CTL register from HW */
9fdcc0f7 331 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 332 TWL4030_REG_APLL_CTL);
333 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 334
ee4ccac7
PU		 335 /* anti-pop when changing analog gain */
336 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
337 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
338 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 339
ee4ccac7
PU		 340 twl4030_write(codec, TWL4030_REG_OPTION,
341 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
342 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 343
3c36cc68
PU		 344 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
345 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
346
ee4ccac7 347 /* Machine dependent setup */
f0fba2ad 348 if (!pdata)
7393958f
PU		 349 return;
350
f0fba2ad 351 twl4030->digimic_delay = pdata->digimic_delay;
ee4ccac7
PU		 352
353 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
354 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 355 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 356 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 357
358 /* initiate offset cancellation */
ee4ccac7
PU		 359 twl4030_codec_enable(codec, 1);
360
361 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
362 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 363 reg |= pdata->offset_cncl_path;
006f367e 364 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 365 reg | TWL4030_CNCL_OFFSET_START);
006f367e 366
7e6120c5
PU		 367 /*
368 * Wait for offset cancellation to complete.
369 * Since this takes a while, do not slam the i2c.
370 * Start polling the status after ~20ms.
371 */
372 msleep(20);
006f367e 373 do {
7e6120c5 374 usleep_range(1000, 2000);
fc7b92fc 375 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 376 TWL4030_REG_ANAMICL);
377 } while ((i++ < 100) &&
378 ((byte & TWL4030_CNCL_OFFSET_START) ==
379 TWL4030_CNCL_OFFSET_START));
380
381 /* Make sure that the reg_cache has the same value as the HW */
382 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
383
006f367e 384 twl4030_codec_enable(codec, 0);
006f367e
PU		 385}
386
ee4ccac7 387static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 388{
ee4ccac7
PU		 389 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
390 int status = -1;
391
392 if (enable) {
393 twl4030->apll_enabled++;
394 if (twl4030->apll_enabled == 1)
57fe7251
PU		 395 status = twl4030_audio_enable_resource(
396 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 397 } else {
398 twl4030->apll_enabled--;
399 if (!twl4030->apll_enabled)
57fe7251
PU		 400 status = twl4030_audio_disable_resource(
401 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 402 }
403
404 if (status >= 0)
405 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 406}
407
5e98a464 408/* Earpiece */
1a787e7a
JS		 409static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
410 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
411 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
412 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
413 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
414};
5e98a464 415
2a6f5c58 416/* PreDrive Left */
1a787e7a
JS		 417static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
418 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
419 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
420 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
421 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
422};
2a6f5c58
PU		 423
424/* PreDrive Right */
1a787e7a
JS		 425static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
426 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
427 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
428 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
429 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
430};
2a6f5c58 431
dfad21a2 432/* Headset Left */
1a787e7a
JS		 433static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
434 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
435 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
436 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
437};
dfad21a2
PU		 438
439/* Headset Right */
1a787e7a
JS		 440static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
441 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
442 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
443 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
444};
dfad21a2 445
5152d8c2 446/* Carkit Left */
1a787e7a
JS		 447static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
448 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
449 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
450 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
451};
5152d8c2
PU		 452
453/* Carkit Right */
1a787e7a
JS		 454static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
455 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
456 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
457 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
458};
5152d8c2 459
df339804
PU		 460/* Handsfree Left */
461static const char *twl4030_handsfreel_texts[] =
1a787e7a 462 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 463
464static const struct soc_enum twl4030_handsfreel_enum =
465 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
466 ARRAY_SIZE(twl4030_handsfreel_texts),
467 twl4030_handsfreel_texts);
468
469static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
470SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
471
0f89bdca
PU		 472/* Handsfree Left virtual mute */
473static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
474 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
475
df339804
PU		 476/* Handsfree Right */
477static const char *twl4030_handsfreer_texts[] =
1a787e7a 478 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 479
480static const struct soc_enum twl4030_handsfreer_enum =
481 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
482 ARRAY_SIZE(twl4030_handsfreer_texts),
483 twl4030_handsfreer_texts);
484
485static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
486SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
487
0f89bdca
PU		 488/* Handsfree Right virtual mute */
489static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
490 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
491
376f7839
PU		 492/* Vibra */
493/* Vibra audio path selection */
494static const char *twl4030_vibra_texts[] =
495 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
496
497static const struct soc_enum twl4030_vibra_enum =
498 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
499 ARRAY_SIZE(twl4030_vibra_texts),
500 twl4030_vibra_texts);
501
502static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
503SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
504
505/* Vibra path selection: local vibrator (PWM) or audio driven */
506static const char *twl4030_vibrapath_texts[] =
507 {"Local vibrator", "Audio"};
508
509static const struct soc_enum twl4030_vibrapath_enum =
510 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
511 ARRAY_SIZE(twl4030_vibrapath_texts),
512 twl4030_vibrapath_texts);
513
514static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
515SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
516
276c6222 517/* Left analog microphone selection */
97b8096d 518static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 519 SOC_DAPM_SINGLE("Main Mic Capture Switch",
520 TWL4030_REG_ANAMICL, 0, 1, 0),
521 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
522 TWL4030_REG_ANAMICL, 1, 1, 0),
523 SOC_DAPM_SINGLE("AUXL Capture Switch",
524 TWL4030_REG_ANAMICL, 2, 1, 0),
525 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
526 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 527};
276c6222
PU		 528
529/* Right analog microphone selection */
97b8096d 530static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 531 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
532 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 533};
276c6222
PU		 534
535/* TX1 L/R Analog/Digital microphone selection */
536static const char *twl4030_micpathtx1_texts[] =
537 {"Analog", "Digimic0"};
538
539static const struct soc_enum twl4030_micpathtx1_enum =
540 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
541 ARRAY_SIZE(twl4030_micpathtx1_texts),
542 twl4030_micpathtx1_texts);
543
544static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
545SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
546
547/* TX2 L/R Analog/Digital microphone selection */
548static const char *twl4030_micpathtx2_texts[] =
549 {"Analog", "Digimic1"};
550
551static const struct soc_enum twl4030_micpathtx2_enum =
552 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
553 ARRAY_SIZE(twl4030_micpathtx2_texts),
554 twl4030_micpathtx2_texts);
555
556static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
557SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
558
7393958f
PU		 559/* Analog bypass for AudioR1 */
560static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
561 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
562
563/* Analog bypass for AudioL1 */
564static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
565 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
566
567/* Analog bypass for AudioR2 */
568static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
569 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
570
571/* Analog bypass for AudioL2 */
572static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
573 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
574
fcd274a3
LCM		 575/* Analog bypass for Voice */
576static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
577 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
578
8b0d3153 579/* Digital bypass gain, mute instead of -30dB */
6bab83fd 580static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 581 TLV_DB_RANGE_HEAD(3),
582 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
583 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 584 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
585};
586
587/* Digital bypass left (TX1L -> RX2L) */
588static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
589 SOC_DAPM_SINGLE_TLV("Volume",
590 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
591 twl4030_dapm_dbypass_tlv);
592
593/* Digital bypass right (TX1R -> RX2R) */
594static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
595 SOC_DAPM_SINGLE_TLV("Volume",
596 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
597 twl4030_dapm_dbypass_tlv);
598
ee8f6894
LCM		 599/*
600 * Voice Sidetone GAIN volume control:
601 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
602 */
603static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
604
605/* Digital bypass voice: sidetone (VUL -> VDL)*/
606static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
607 SOC_DAPM_SINGLE_TLV("Volume",
608 TWL4030_REG_VSTPGA, 0, 0x29, 0,
609 twl4030_dapm_dbypassv_tlv);
610
9008adf9
PU		 611/*
612 * Output PGA builder:
613 * Handle the muting and unmuting of the given output (turning off the
614 * amplifier associated with the output pin)
c96907f2
PU		 615 * On mute bypass the reg_cache and write 0 to the register
616 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 617 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
618 */
619#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
620static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
621 struct snd_kcontrol *kcontrol, int event) \
622{ \
b2c812e2 623 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 624 \
625 switch (event) { \
626 case SND_SOC_DAPM_POST_PMU: \
c96907f2 627 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 628 twl4030_write(w->codec, reg, \
629 twl4030_read_reg_cache(w->codec, reg)); \
630 break; \
631 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 632 twl4030->pin_name##_enabled = 0; \
633 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
634 0, reg); \
9008adf9
PU		 635 break; \
636 } \
637 return 0; \
638}
639
640TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
641TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
642TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
643TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
644TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
645
5a2e9a48 646static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 647{
49d92c7d
SM		 648 unsigned char hs_ctl;
649
5a2e9a48 650 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 651
5a2e9a48
PU		 652 if (ramp) {
653 /* HF ramp-up */
654 hs_ctl |= TWL4030_HF_CTL_REF_EN;
655 twl4030_write(codec, reg, hs_ctl);
656 udelay(10);
49d92c7d 657 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 658 twl4030_write(codec, reg, hs_ctl);
659 udelay(40);
49d92c7d 660 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 661 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 662 twl4030_write(codec, reg, hs_ctl);
49d92c7d 663 } else {
5a2e9a48
PU		 664 /* HF ramp-down */
665 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
666 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
667 twl4030_write(codec, reg, hs_ctl);
668 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
669 twl4030_write(codec, reg, hs_ctl);
670 udelay(40);
671 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
672 twl4030_write(codec, reg, hs_ctl);
49d92c7d 673 }
5a2e9a48 674}
49d92c7d 675
5a2e9a48
PU		 676static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
677 struct snd_kcontrol *kcontrol, int event)
678{
679 switch (event) {
680 case SND_SOC_DAPM_POST_PMU:
681 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
682 break;
683 case SND_SOC_DAPM_POST_PMD:
684 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
685 break;
686 }
687 return 0;
688}
689
690static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
691 struct snd_kcontrol *kcontrol, int event)
692{
693 switch (event) {
694 case SND_SOC_DAPM_POST_PMU:
695 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
696 break;
697 case SND_SOC_DAPM_POST_PMD:
698 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
699 break;
700 }
49d92c7d
SM		 701 return 0;
702}
703
86139a13
JV		 704static int vibramux_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
708 return 0;
709}
710
7729cf74
PU		 711static int apll_event(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol, int event)
713{
714 switch (event) {
715 case SND_SOC_DAPM_PRE_PMU:
716 twl4030_apll_enable(w->codec, 1);
717 break;
718 case SND_SOC_DAPM_POST_PMD:
719 twl4030_apll_enable(w->codec, 0);
720 break;
721 }
722 return 0;
723}
724
7b4c734e
PU		 725static int aif_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727{
728 u8 audio_if;
729
730 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
731 switch (event) {
732 case SND_SOC_DAPM_PRE_PMU:
733 /* Enable AIF */
734 /* enable the PLL before we use it to clock the DAI */
735 twl4030_apll_enable(w->codec, 1);
736
737 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
738 audio_if | TWL4030_AIF_EN);
739 break;
740 case SND_SOC_DAPM_POST_PMD:
741 /* disable the DAI before we stop it's source PLL */
742 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
743 audio_if & ~TWL4030_AIF_EN);
744 twl4030_apll_enable(w->codec, 0);
745 break;
746 }
747 return 0;
748}
749
6943c92e 750static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 751{
4ae6df5e 752 struct twl4030_codec_data *pdata = codec->dev->platform_data;
aad749e5 753 unsigned char hs_gain, hs_pop;
b2c812e2 754 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 755 /* Base values for ramp delay calculation: 2^19 - 2^26 */
756 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
757 8388608, 16777216, 33554432, 67108864};
7e6120c5 758 unsigned int delay;
aad749e5 759
6943c92e
PU		 760 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
761 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 762 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
763 twl4030->sysclk) + 1;
aad749e5 764
4e49ffd1
CVJ		 765 /* Enable external mute control, this dramatically reduces
766 * the pop-noise */
f0fba2ad 767 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 768 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
769 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 770 } else {
771 hs_pop |= TWL4030_EXTMUTE;
772 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
773 }
774 }
775
6943c92e
PU		 776 if (ramp) {
777 /* Headset ramp-up according to the TRM */
aad749e5 778 hs_pop |= TWL4030_VMID_EN;
6943c92e 779 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 780 /* Actually write to the register */
781 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
782 hs_gain,
783 TWL4030_REG_HS_GAIN_SET);
aad749e5 784 hs_pop |= TWL4030_RAMP_EN;
6943c92e 785 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 786 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 787 twl4030_wait_ms(delay);
6943c92e
PU		 788 } else {
789 /* Headset ramp-down _not_ according to
790 * the TRM, but in a way that it is working */
aad749e5 791 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 792 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
793 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 794 twl4030_wait_ms(delay);
aad749e5 795 /* Bypass the reg_cache to mute the headset */
fc7b92fc 796 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 797 hs_gain & (~0x0f),
798 TWL4030_REG_HS_GAIN_SET);
6943c92e 799
aad749e5 800 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 801 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
802 }
4e49ffd1
CVJ		 803
804 /* Disable external mute */
f0fba2ad 805 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 806 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
807 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 808 } else {
809 hs_pop &= ~TWL4030_EXTMUTE;
810 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
811 }
812 }
6943c92e
PU		 813}
814
815static int headsetlpga_event(struct snd_soc_dapm_widget *w,
816 struct snd_kcontrol *kcontrol, int event)
817{
b2c812e2 818 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 819
820 switch (event) {
821 case SND_SOC_DAPM_POST_PMU:
822 /* Do the ramp-up only once */
823 if (!twl4030->hsr_enabled)
824 headset_ramp(w->codec, 1);
825
826 twl4030->hsl_enabled = 1;
827 break;
828 case SND_SOC_DAPM_POST_PMD:
829 /* Do the ramp-down only if both headsetL/R is disabled */
830 if (!twl4030->hsr_enabled)
831 headset_ramp(w->codec, 0);
832
833 twl4030->hsl_enabled = 0;
834 break;
835 }
836 return 0;
837}
838
839static int headsetrpga_event(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol, int event)
841{
b2c812e2 842 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 843
844 switch (event) {
845 case SND_SOC_DAPM_POST_PMU:
846 /* Do the ramp-up only once */
847 if (!twl4030->hsl_enabled)
848 headset_ramp(w->codec, 1);
849
850 twl4030->hsr_enabled = 1;
851 break;
852 case SND_SOC_DAPM_POST_PMD:
853 /* Do the ramp-down only if both headsetL/R is disabled */
854 if (!twl4030->hsl_enabled)
855 headset_ramp(w->codec, 0);
856
857 twl4030->hsr_enabled = 0;
aad749e5
PU		 858 break;
859 }
860 return 0;
861}
862
01ea6ba2
PU		 863static int digimic_event(struct snd_soc_dapm_widget *w,
864 struct snd_kcontrol *kcontrol, int event)
865{
866 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
867
868 if (twl4030->digimic_delay)
7e6120c5 869 twl4030_wait_ms(twl4030->digimic_delay);
01ea6ba2
PU		 870 return 0;
871}
872
b0bd53a7
PU		 873/*
874 * Some of the gain controls in TWL (mostly those which are associated with
875 * the outputs) are implemented in an interesting way:
876 * 0x0 : Power down (mute)
877 * 0x1 : 6dB
878 * 0x2 : 0 dB
879 * 0x3 : -6 dB
880 * Inverting not going to help with these.
881 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
882 */
b0bd53a7
PU		 883static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
884 struct snd_ctl_elem_value *ucontrol)
885{
886 struct soc_mixer_control *mc =
887 (struct soc_mixer_control *)kcontrol->private_value;
888 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
889 unsigned int reg = mc->reg;
890 unsigned int shift = mc->shift;
891 unsigned int rshift = mc->rshift;
892 int max = mc->max;
893 int mask = (1 << fls(max)) - 1;
894
895 ucontrol->value.integer.value[0] =
896 (snd_soc_read(codec, reg) >> shift) & mask;
897 if (ucontrol->value.integer.value[0])
898 ucontrol->value.integer.value[0] =
899 max + 1 - ucontrol->value.integer.value[0];
900
901 if (shift != rshift) {
902 ucontrol->value.integer.value[1] =
903 (snd_soc_read(codec, reg) >> rshift) & mask;
904 if (ucontrol->value.integer.value[1])
905 ucontrol->value.integer.value[1] =
906 max + 1 - ucontrol->value.integer.value[1];
907 }
908
909 return 0;
910}
911
912static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
913 struct snd_ctl_elem_value *ucontrol)
914{
915 struct soc_mixer_control *mc =
916 (struct soc_mixer_control *)kcontrol->private_value;
917 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
918 unsigned int reg = mc->reg;
919 unsigned int shift = mc->shift;
920 unsigned int rshift = mc->rshift;
921 int max = mc->max;
922 int mask = (1 << fls(max)) - 1;
923 unsigned short val, val2, val_mask;
924
925 val = (ucontrol->value.integer.value[0] & mask);
926
927 val_mask = mask << shift;
928 if (val)
929 val = max + 1 - val;
930 val = val << shift;
931 if (shift != rshift) {
932 val2 = (ucontrol->value.integer.value[1] & mask);
933 val_mask |= mask << rshift;
934 if (val2)
935 val2 = max + 1 - val2;
936 val |= val2 << rshift;
937 }
938 return snd_soc_update_bits(codec, reg, val_mask, val);
939}
940
941static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
942 struct snd_ctl_elem_value *ucontrol)
943{
944 struct soc_mixer_control *mc =
945 (struct soc_mixer_control *)kcontrol->private_value;
946 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
947 unsigned int reg = mc->reg;
948 unsigned int reg2 = mc->rreg;
949 unsigned int shift = mc->shift;
950 int max = mc->max;
951 int mask = (1<<fls(max))-1;
952
953 ucontrol->value.integer.value[0] =
954 (snd_soc_read(codec, reg) >> shift) & mask;
955 ucontrol->value.integer.value[1] =
956 (snd_soc_read(codec, reg2) >> shift) & mask;
957
958 if (ucontrol->value.integer.value[0])
959 ucontrol->value.integer.value[0] =
960 max + 1 - ucontrol->value.integer.value[0];
961 if (ucontrol->value.integer.value[1])
962 ucontrol->value.integer.value[1] =
963 max + 1 - ucontrol->value.integer.value[1];
964
965 return 0;
966}
967
968static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
969 struct snd_ctl_elem_value *ucontrol)
970{
971 struct soc_mixer_control *mc =
972 (struct soc_mixer_control *)kcontrol->private_value;
973 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
974 unsigned int reg = mc->reg;
975 unsigned int reg2 = mc->rreg;
976 unsigned int shift = mc->shift;
977 int max = mc->max;
978 int mask = (1 << fls(max)) - 1;
979 int err;
980 unsigned short val, val2, val_mask;
981
982 val_mask = mask << shift;
983 val = (ucontrol->value.integer.value[0] & mask);
984 val2 = (ucontrol->value.integer.value[1] & mask);
985
986 if (val)
987 val = max + 1 - val;
988 if (val2)
989 val2 = max + 1 - val2;
990
991 val = val << shift;
992 val2 = val2 << shift;
993
994 err = snd_soc_update_bits(codec, reg, val_mask, val);
995 if (err < 0)
996 return err;
997
998 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
999 return err;
1000}
1001
b74bd40f
LCM		 1002/* Codec operation modes */
1003static const char *twl4030_op_modes_texts[] = {
1004 "Option 2 (voice/audio)", "Option 1 (audio)"
1005};
1006
1007static const struct soc_enum twl4030_op_modes_enum =
1008 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1009 ARRAY_SIZE(twl4030_op_modes_texts),
1010 twl4030_op_modes_texts);
1011
423c238d 1012static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1013 struct snd_ctl_elem_value *ucontrol)
1014{
1015 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1016 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1017 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1018 unsigned short val;
86767b7d 1019 unsigned short mask;
b74bd40f
LCM		 1020
1021 if (twl4030->configured) {
3b8a0795
PU		 1022 dev_err(codec->dev,
1023 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 1024 return -EBUSY;
1025 }
1026
b74bd40f
LCM		 1027 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1028 return -EINVAL;
1029
1030 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 1031 mask = e->mask << e->shift_l;
b74bd40f
LCM		 1032 if (e->shift_l != e->shift_r) {
1033 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1034 return -EINVAL;
1035 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 1036 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 1037 }
1038
1039 return snd_soc_update_bits(codec, e->reg, mask, val);
1040}
1041
c10b82cf
PU		 1042/*
1043 * FGAIN volume control:
1044 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1045 */
d889a72c 1046static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1047
0d33ea0b
PU		 1048/*
1049 * CGAIN volume control:
1050 * 0 dB to 12 dB in 6 dB steps
1051 * value 2 and 3 means 12 dB
1052 */
d889a72c
PU		 1053static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1054
1a787e7a
JS		 1055/*
1056 * Voice Downlink GAIN volume control:
1057 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1058 */
1059static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1060
d889a72c
PU		 1061/*
1062 * Analog playback gain
1063 * -24 dB to 12 dB in 2 dB steps
1064 */
1065static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1066
4290239c
PU		 1067/*
1068 * Gain controls tied to outputs
1069 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1070 */
1071static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1072
18cc8d8d
JS		 1073/*
1074 * Gain control for earpiece amplifier
1075 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1076 */
1077static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1078
381a22b5
PU		 1079/*
1080 * Capture gain after the ADCs
1081 * from 0 dB to 31 dB in 1 dB steps
1082 */
1083static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1084
5920b453
GI		 1085/*
1086 * Gain control for input amplifiers
1087 * 0 dB to 30 dB in 6 dB steps
1088 */
1089static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1090
328d0a13
LCM		 1091/* AVADC clock priority */
1092static const char *twl4030_avadc_clk_priority_texts[] = {
1093 "Voice high priority", "HiFi high priority"
1094};
1095
1096static const struct soc_enum twl4030_avadc_clk_priority_enum =
1097 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1098 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1099 twl4030_avadc_clk_priority_texts);
1100
89492be8
PU		 1101static const char *twl4030_rampdelay_texts[] = {
1102 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1103 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1104 "3495/2581/1748 ms"
1105};
1106
1107static const struct soc_enum twl4030_rampdelay_enum =
1108 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1109 ARRAY_SIZE(twl4030_rampdelay_texts),
1110 twl4030_rampdelay_texts);
1111
376f7839
PU		 1112/* Vibra H-bridge direction mode */
1113static const char *twl4030_vibradirmode_texts[] = {
1114 "Vibra H-bridge direction", "Audio data MSB",
1115};
1116
1117static const struct soc_enum twl4030_vibradirmode_enum =
1118 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1119 ARRAY_SIZE(twl4030_vibradirmode_texts),
1120 twl4030_vibradirmode_texts);
1121
1122/* Vibra H-bridge direction */
1123static const char *twl4030_vibradir_texts[] = {
1124 "Positive polarity", "Negative polarity",
1125};
1126
1127static const struct soc_enum twl4030_vibradir_enum =
1128 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1129 ARRAY_SIZE(twl4030_vibradir_texts),
1130 twl4030_vibradir_texts);
1131
36aeff61
PU		 1132/* Digimic Left and right swapping */
1133static const char *twl4030_digimicswap_texts[] = {
1134 "Not swapped", "Swapped",
1135};
1136
1137static const struct soc_enum twl4030_digimicswap_enum =
1138 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1139 ARRAY_SIZE(twl4030_digimicswap_texts),
1140 twl4030_digimicswap_texts);
1141
cc17557e 1142static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1143 /* Codec operation mode control */
1144 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1145 snd_soc_get_enum_double,
1146 snd_soc_put_twl4030_opmode_enum_double),
1147
d889a72c
PU		 1148 /* Common playback gain controls */
1149 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1150 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1151 0, 0x3f, 0, digital_fine_tlv),
1152 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1153 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1154 0, 0x3f, 0, digital_fine_tlv),
1155
1156 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1157 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1158 6, 0x2, 0, digital_coarse_tlv),
1159 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1160 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1161 6, 0x2, 0, digital_coarse_tlv),
1162
1163 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1164 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1165 3, 0x12, 1, analog_tlv),
1166 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1167 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1168 3, 0x12, 1, analog_tlv),
44c55870
PU		 1169 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1170 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1171 1, 1, 0),
1172 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1173 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1174 1, 1, 0),
381a22b5 1175
1a787e7a
JS		 1176 /* Common voice downlink gain controls */
1177 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1178 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1179
1180 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1181 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1182
1183 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1184 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1185
4290239c 1186 /* Separate output gain controls */
0f9887d1 1187 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1188 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1189 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1190 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1191
0f9887d1
PU		 1192 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1193 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1194 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1195
0f9887d1 1196 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1197 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1198 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1199 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1200
0f9887d1
PU		 1201 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1202 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1203 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1204
381a22b5 1205 /* Common capture gain controls */
276c6222 1206 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1207 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1208 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1209 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1210 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1211 0, 0x1f, 0, digital_capture_tlv),
5920b453 1212
276c6222 1213 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1214 0, 3, 5, 0, input_gain_tlv),
89492be8 1215
328d0a13
LCM		 1216 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1217
89492be8 1218 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1219
1220 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1221 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1222
1223 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1224};
1225
cc17557e 1226static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1227 /* Left channel inputs */
1228 SND_SOC_DAPM_INPUT("MAINMIC"),
1229 SND_SOC_DAPM_INPUT("HSMIC"),
1230 SND_SOC_DAPM_INPUT("AUXL"),
1231 SND_SOC_DAPM_INPUT("CARKITMIC"),
1232 /* Right channel inputs */
1233 SND_SOC_DAPM_INPUT("SUBMIC"),
1234 SND_SOC_DAPM_INPUT("AUXR"),
1235 /* Digital microphones (Stereo) */
1236 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1237 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1238
1239 /* Outputs */
5e98a464 1240 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1241 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1242 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1243 SND_SOC_DAPM_OUTPUT("HSOL"),
1244 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1245 SND_SOC_DAPM_OUTPUT("CARKITL"),
1246 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1247 SND_SOC_DAPM_OUTPUT("HFL"),
1248 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1249 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1250
7b4c734e
PU		 1251 /* AIF and APLL clocks for running DAIs (including loopback) */
1252 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1253 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1254 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1255
53b5047d 1256 /* DACs */
7f51e7d3
PU		 1257 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1258 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1259 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1260 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1261 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1262
7393958f 1263 /* Analog bypasses */
78e08e2f
PU		 1264 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1265 &twl4030_dapm_abypassr1_control),
1266 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1267 &twl4030_dapm_abypassl1_control),
1268 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1269 &twl4030_dapm_abypassr2_control),
1270 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_abypassl2_control),
1272 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1273 &twl4030_dapm_abypassv_control),
1274
1275 /* Master analog loopback switch */
1276 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1277 NULL, 0),
7393958f 1278
6bab83fd 1279 /* Digital bypasses */
78e08e2f
PU		 1280 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_dbypassl_control),
1282 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1283 &twl4030_dapm_dbypassr_control),
1284 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_dbypassv_control),
6bab83fd 1286
4005d39a
PU		 1287 /* Digital mixers, power control for the physical DACs */
1288 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1289 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1290 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1291 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1292 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1293 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1294 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1295 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1296 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1297 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1298
1299 /* Analog mixers, power control for the physical PGAs */
1300 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1301 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1302 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1303 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1305 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1306 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1307 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1308 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1309 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1310
7729cf74
PU		 1311 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1312 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1313
7b4c734e
PU		 1314 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1315 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1316
1a787e7a 1317 /* Output MIXER controls */
5e98a464 1318 /* Earpiece */
1a787e7a
JS		 1319 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1320 &twl4030_dapm_earpiece_controls[0],
1321 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1322 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1323 0, 0, NULL, 0, earpiecepga_event,
1324 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1325 /* PreDrivL/R */
1a787e7a
JS		 1326 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1327 &twl4030_dapm_predrivel_controls[0],
1328 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1329 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1330 0, 0, NULL, 0, predrivelpga_event,
1331 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1332 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1333 &twl4030_dapm_predriver_controls[0],
1334 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1335 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1336 0, 0, NULL, 0, predriverpga_event,
1337 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1338 /* HeadsetL/R */
6943c92e 1339 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1340 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1341 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1342 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1343 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1344 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1345 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1346 &twl4030_dapm_hsor_controls[0],
1347 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1348 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1349 0, 0, NULL, 0, headsetrpga_event,
1350 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1351 /* CarkitL/R */
1a787e7a
JS		 1352 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1353 &twl4030_dapm_carkitl_controls[0],
1354 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1355 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1356 0, 0, NULL, 0, carkitlpga_event,
1357 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1358 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1359 &twl4030_dapm_carkitr_controls[0],
1360 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1361 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1362 0, 0, NULL, 0, carkitrpga_event,
1363 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1364
1365 /* Output MUX controls */
df339804 1366 /* HandsfreeL/R */
5a2e9a48
PU		 1367 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1368 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1369 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1370 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1371 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1372 0, 0, NULL, 0, handsfreelpga_event,
1373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1374 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1375 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1376 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1377 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1378 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1379 0, 0, NULL, 0, handsfreerpga_event,
1380 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1381 /* Vibra */
86139a13
JV		 1382 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1383 &twl4030_dapm_vibra_control, vibramux_event,
1384 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1385 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1386 &twl4030_dapm_vibrapath_control),
5e98a464 1387
276c6222
PU		 1388 /* Introducing four virtual ADC, since TWL4030 have four channel for
1389 capture */
7f51e7d3
PU		 1390 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1391 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1392 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1393 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222
PU		 1394
1395 /* Analog/Digital mic path selection.
1396 TX1 Left/Right: either analog Left/Right or Digimic0
1397 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1398 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1399 &twl4030_dapm_micpathtx1_control),
1400 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1401 &twl4030_dapm_micpathtx2_control),
276c6222 1402
97b8096d 1403 /* Analog input mixers for the capture amplifiers */
9028935d 1404 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1405 TWL4030_REG_ANAMICL, 4, 0,
1406 &twl4030_dapm_analoglmic_controls[0],
1407 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1408 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1409 TWL4030_REG_ANAMICR, 4, 0,
1410 &twl4030_dapm_analogrmic_controls[0],
1411 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1412
fb2a2f84
PU		 1413 SND_SOC_DAPM_PGA("ADC Physical Left",
1414 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1415 SND_SOC_DAPM_PGA("ADC Physical Right",
1416 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1417
01ea6ba2
PU		 1418 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1419 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1420 digimic_event, SND_SOC_DAPM_POST_PMU),
1421 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1422 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1423 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1424
bda7d2a8
PU		 1425 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1426 NULL, 0),
1427 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1428 NULL, 0),
1429
276c6222
PU		 1430 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1431 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1432 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1433
cc17557e
SS		 1434};
1435
1436static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1437 /* Stream -> DAC mapping */
1438 {"DAC Right1", NULL, "HiFi Playback"},
1439 {"DAC Left1", NULL, "HiFi Playback"},
1440 {"DAC Right2", NULL, "HiFi Playback"},
1441 {"DAC Left2", NULL, "HiFi Playback"},
1442 {"DAC Voice", NULL, "Voice Playback"},
1443
1444 /* ADC -> Stream mapping */
1445 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1446 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1447 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1448 {"HiFi Capture", NULL, "ADC Virtual Right2"},
1449 {"Voice Capture", NULL, "ADC Virtual Left1"},
1450 {"Voice Capture", NULL, "ADC Virtual Right1"},
1451 {"Voice Capture", NULL, "ADC Virtual Left2"},
1452 {"Voice Capture", NULL, "ADC Virtual Right2"},
1453
4005d39a
PU		 1454 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1455 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1456 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1457 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1458 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1459
7729cf74 1460 /* Supply for the digital part (APLL) */
7729cf74
PU		 1461 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1462
27eeb1fe
PU		 1463 {"DAC Left1", NULL, "AIF Enable"},
1464 {"DAC Right1", NULL, "AIF Enable"},
1465 {"DAC Left2", NULL, "AIF Enable"},
1466 {"DAC Right1", NULL, "AIF Enable"},
1467
c42a59ea
PU		 1468 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1469 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1470
4005d39a
PU		 1471 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1472 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1473 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1474 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1475 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1476
5e98a464
PU		 1477 /* Internal playback routings */
1478 /* Earpiece */
4005d39a
PU		 1479 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1480 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1481 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1482 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1483 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1484 /* PreDrivL */
4005d39a
PU		 1485 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1486 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1487 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1488 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1489 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1490 /* PreDrivR */
4005d39a
PU		 1491 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1492 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1493 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1494 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1495 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1496 /* HeadsetL */
4005d39a
PU		 1497 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1498 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1499 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1500 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1501 /* HeadsetR */
4005d39a
PU		 1502 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1503 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1504 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1505 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1506 /* CarkitL */
4005d39a
PU		 1507 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1508 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1509 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1510 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1511 /* CarkitR */
4005d39a
PU		 1512 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1513 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1514 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1515 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1516 /* HandsfreeL */
4005d39a
PU		 1517 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1518 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1519 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1520 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1521 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1522 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1523 /* HandsfreeR */
4005d39a
PU		 1524 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1525 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1526 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1527 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1528 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1529 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1530 /* Vibra */
1531 {"Vibra Mux", "AudioL1", "DAC Left1"},
1532 {"Vibra Mux", "AudioR1", "DAC Right1"},
1533 {"Vibra Mux", "AudioL2", "DAC Left2"},
1534 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1535
cc17557e 1536 /* outputs */
7b4c734e 1537 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1538 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1539 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1540 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1541 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1542 /* Must be always connected (for APLL) */
1543 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1544 /* Physical outputs */
9008adf9
PU		 1545 {"EARPIECE", NULL, "Earpiece PGA"},
1546 {"PREDRIVEL", NULL, "PredriveL PGA"},
1547 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1548 {"HSOL", NULL, "HeadsetL PGA"},
1549 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1550 {"CARKITL", NULL, "CarkitL PGA"},
1551 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1552 {"HFL", NULL, "HandsfreeL PGA"},
1553 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1554 {"Vibra Route", "Audio", "Vibra Mux"},
1555 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1556
276c6222 1557 /* Capture path */
7b4c734e
PU		 1558 /* Must be always connected (for AIF and APLL) */
1559 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1560 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1561 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1562 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1563 /* Physical inputs */
9028935d
PU		 1564 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1565 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1566 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1567 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1568
9028935d
PU		 1569 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1570 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1571
9028935d
PU		 1572 {"ADC Physical Left", NULL, "Analog Left"},
1573 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1574
1575 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1576 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1577
bda7d2a8
PU		 1578 {"DIGIMIC0", NULL, "micbias1 select"},
1579 {"DIGIMIC1", NULL, "micbias2 select"},
1580
276c6222 1581 /* TX1 Left capture path */
fb2a2f84 1582 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1583 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1584 /* TX1 Right capture path */
fb2a2f84 1585 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1586 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1587 /* TX2 Left capture path */
fb2a2f84 1588 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1589 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1590 /* TX2 Right capture path */
fb2a2f84 1591 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1592 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1593
1594 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1595 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1596 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1597 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1598
c42a59ea
PU		 1599 {"ADC Virtual Left1", NULL, "AIF Enable"},
1600 {"ADC Virtual Right1", NULL, "AIF Enable"},
1601 {"ADC Virtual Left2", NULL, "AIF Enable"},
1602 {"ADC Virtual Right2", NULL, "AIF Enable"},
1603
7393958f 1604 /* Analog bypass routes */
9028935d
PU		 1605 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1606 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1607 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1608 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1609 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1610
78e08e2f
PU		 1611 /* Supply for the Analog loopbacks */
1612 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1613 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1614 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1615 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1616 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1617
7393958f
PU		 1618 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1619 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1620 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1621 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1622 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1623
6bab83fd
PU		 1624 /* Digital bypass routes */
1625 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1626 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1627 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1628
4005d39a
PU		 1629 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1630 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1631 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1632
cc17557e
SS		 1633};
1634
cc17557e
SS		 1635static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1636 enum snd_soc_bias_level level)
1637{
1638 switch (level) {
1639 case SND_SOC_BIAS_ON:
cc17557e
SS		 1640 break;
1641 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1642 break;
1643 case SND_SOC_BIAS_STANDBY:
ce6120cc 1644 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1645 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1646 break;
1647 case SND_SOC_BIAS_OFF:
cbd2db12 1648 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1649 break;
1650 }
ce6120cc 1651 codec->dapm.bias_level = level;
cc17557e
SS		 1652
1653 return 0;
1654}
1655
6b87a91f
PU		 1656static void twl4030_constraints(struct twl4030_priv *twl4030,
1657 struct snd_pcm_substream *mst_substream)
1658{
1659 struct snd_pcm_substream *slv_substream;
1660
1661 /* Pick the stream, which need to be constrained */
1662 if (mst_substream == twl4030->master_substream)
1663 slv_substream = twl4030->slave_substream;
1664 else if (mst_substream == twl4030->slave_substream)
1665 slv_substream = twl4030->master_substream;
1666 else /* This should not happen.. */
1667 return;
1668
1669 /* Set the constraints according to the already configured stream */
1670 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1671 SNDRV_PCM_HW_PARAM_RATE,
1672 twl4030->rate,
1673 twl4030->rate);
1674
1675 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1676 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1677 twl4030->sample_bits,
1678 twl4030->sample_bits);
1679
1680 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1681 SNDRV_PCM_HW_PARAM_CHANNELS,
1682 twl4030->channels,
1683 twl4030->channels);
1684}
1685
8a1f936a
PU		 1686/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1687 * capture has to be enabled/disabled. */
1688static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1689 int enable)
1690{
1691 u8 reg, mask;
1692
1693 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1694
1695 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1696 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1697 else
1698 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1699
1700 if (enable)
1701 reg |= mask;
1702 else
1703 reg &= ~mask;
1704
1705 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1706}
1707
d6648da1
PU		 1708static int twl4030_startup(struct snd_pcm_substream *substream,
1709 struct snd_soc_dai *dai)
7220b9f4 1710{
e6968a17 1711 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1712 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1713
7220b9f4 1714 if (twl4030->master_substream) {
7220b9f4 1715 twl4030->slave_substream = substream;
6b87a91f
PU		 1716 /* The DAI has one configuration for playback and capture, so
1717 * if the DAI has been already configured then constrain this
1718 * substream to match it. */
1719 if (twl4030->configured)
1720 twl4030_constraints(twl4030, twl4030->master_substream);
1721 } else {
8a1f936a
PU		 1722 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1723 TWL4030_OPTION_1)) {
1724 /* In option2 4 channel is not supported, set the
1725 * constraint for the first stream for channels, the
1726 * second stream will 'inherit' this cosntraint */
1727 snd_pcm_hw_constraint_minmax(substream->runtime,
1728 SNDRV_PCM_HW_PARAM_CHANNELS,
1729 2, 2);
1730 }
7220b9f4 1731 twl4030->master_substream = substream;
6b87a91f 1732 }
7220b9f4
PU		 1733
1734 return 0;
1735}
1736
d6648da1
PU		 1737static void twl4030_shutdown(struct snd_pcm_substream *substream,
1738 struct snd_soc_dai *dai)
7220b9f4 1739{
e6968a17 1740 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1741 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1742
1743 if (twl4030->master_substream == substream)
1744 twl4030->master_substream = twl4030->slave_substream;
1745
1746 twl4030->slave_substream = NULL;
6b87a91f
PU		 1747
1748 /* If all streams are closed, or the remaining stream has not yet
1749 * been configured than set the DAI as not configured. */
1750 if (!twl4030->master_substream)
1751 twl4030->configured = 0;
1752 else if (!twl4030->master_substream->runtime->channels)
1753 twl4030->configured = 0;
8a1f936a
PU		 1754
1755 /* If the closing substream had 4 channel, do the necessary cleanup */
1756 if (substream->runtime->channels == 4)
1757 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1758}
1759
cc17557e 1760static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1761 struct snd_pcm_hw_params *params,
1762 struct snd_soc_dai *dai)
cc17557e 1763{
e6968a17 1764 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1765 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1766 u8 mode, old_mode, format, old_format;
1767
8a1f936a
PU		 1768 /* If the substream has 4 channel, do the necessary setup */
1769 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1770 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1771 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1772
1773 /* Safety check: are we in the correct operating mode and
1774 * the interface is in TDM mode? */
1775 if ((mode & TWL4030_OPTION_1) &&
1776 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1777 twl4030_tdm_enable(codec, substream->stream, 1);
1778 else
1779 return -EINVAL;
1780 }
1781
6b87a91f
PU		 1782 if (twl4030->configured)
1783 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1784 return 0;
1785
cc17557e
SS		 1786 /* bit rate */
1787 old_mode = twl4030_read_reg_cache(codec,
1788 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1789 mode = old_mode & ~TWL4030_APLL_RATE;
1790
1791 switch (params_rate(params)) {
1792 case 8000:
1793 mode |= TWL4030_APLL_RATE_8000;
1794 break;
1795 case 11025:
1796 mode |= TWL4030_APLL_RATE_11025;
1797 break;
1798 case 12000:
1799 mode |= TWL4030_APLL_RATE_12000;
1800 break;
1801 case 16000:
1802 mode |= TWL4030_APLL_RATE_16000;
1803 break;
1804 case 22050:
1805 mode |= TWL4030_APLL_RATE_22050;
1806 break;
1807 case 24000:
1808 mode |= TWL4030_APLL_RATE_24000;
1809 break;
1810 case 32000:
1811 mode |= TWL4030_APLL_RATE_32000;
1812 break;
1813 case 44100:
1814 mode |= TWL4030_APLL_RATE_44100;
1815 break;
1816 case 48000:
1817 mode |= TWL4030_APLL_RATE_48000;
1818 break;
103f211d
PU		 1819 case 96000:
1820 mode |= TWL4030_APLL_RATE_96000;
1821 break;
cc17557e 1822 default:
3b8a0795 1823 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1824 params_rate(params));
1825 return -EINVAL;
1826 }
1827
cc17557e
SS		 1828 /* sample size */
1829 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1830 format = old_format;
1831 format &= ~TWL4030_DATA_WIDTH;
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 format |= TWL4030_DATA_WIDTH_16S_16W;
1835 break;
dcdeda4a 1836 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1837 format |= TWL4030_DATA_WIDTH_32S_24W;
1838 break;
1839 default:
3b8a0795 1840 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1841 params_format(params));
1842 return -EINVAL;
1843 }
1844
2046f175
PU		 1845 if (format != old_format || mode != old_mode) {
1846 if (twl4030->codec_powered) {
1847 /*
1848 * If the codec is powered, than we need to toggle the
1849 * codec power.
1850 */
1851 twl4030_codec_enable(codec, 0);
1852 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1853 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1854 twl4030_codec_enable(codec, 1);
1855 } else {
1856 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1857 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1858 }
cc17557e 1859 }
6b87a91f
PU		 1860
1861 /* Store the important parameters for the DAI configuration and set
1862 * the DAI as configured */
1863 twl4030->configured = 1;
1864 twl4030->rate = params_rate(params);
1865 twl4030->sample_bits = hw_param_interval(params,
1866 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1867 twl4030->channels = params_channels(params);
1868
1869 /* If both playback and capture streams are open, and one of them
1870 * is setting the hw parameters right now (since we are here), set
1871 * constraints to the other stream to match the current one. */
1872 if (twl4030->slave_substream)
1873 twl4030_constraints(twl4030, substream);
1874
cc17557e
SS		 1875 return 0;
1876}
1877
1878static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1879 int clk_id, unsigned int freq, int dir)
1880{
1881 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1882 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1883
1884 switch (freq) {
1885 case 19200000:
cc17557e 1886 case 26000000:
cc17557e 1887 case 38400000:
cc17557e
SS		 1888 break;
1889 default:
3b8a0795 1890 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1891 return -EINVAL;
1892 }
1893
68d01955
PU		 1894 if ((freq / 1000) != twl4030->sysclk) {
1895 dev_err(codec->dev,
3b8a0795 1896 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1897 freq, twl4030->sysclk * 1000);
1898 return -EINVAL;
1899 }
cc17557e
SS		 1900
1901 return 0;
1902}
1903
1904static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1905 unsigned int fmt)
1906{
1907 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1908 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1909 u8 old_format, format;
1910
1911 /* get format */
1912 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1913 format = old_format;
1914
1915 /* set master/slave audio interface */
1916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1917 case SND_SOC_DAIFMT_CBM_CFM:
1918 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1919 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1920 break;
1921 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1922 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1923 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1924 break;
1925 default:
1926 return -EINVAL;
1927 }
1928
1929 /* interface format */
1930 format &= ~TWL4030_AIF_FORMAT;
1931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1932 case SND_SOC_DAIFMT_I2S:
1933 format |= TWL4030_AIF_FORMAT_CODEC;
1934 break;
8a1f936a
PU		 1935 case SND_SOC_DAIFMT_DSP_A:
1936 format |= TWL4030_AIF_FORMAT_TDM;
1937 break;
cc17557e
SS		 1938 default:
1939 return -EINVAL;
1940 }
1941
1942 if (format != old_format) {
2046f175
PU		 1943 if (twl4030->codec_powered) {
1944 /*
1945 * If the codec is powered, than we need to toggle the
1946 * codec power.
1947 */
1948 twl4030_codec_enable(codec, 0);
1949 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1950 twl4030_codec_enable(codec, 1);
1951 } else {
1952 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1953 }
cc17557e
SS		 1954 }
1955
1956 return 0;
1957}
1958
68140443
LCM		 1959static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1960{
1961 struct snd_soc_codec *codec = dai->codec;
1962 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1963
1964 if (tristate)
1965 reg |= TWL4030_AIF_TRI_EN;
1966 else
1967 reg &= ~TWL4030_AIF_TRI_EN;
1968
1969 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1970}
1971
b7a755a8
MLC		 1972/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1973 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1974static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1975 int enable)
1976{
1977 u8 reg, mask;
1978
1979 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1980
1981 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1982 mask = TWL4030_ARXL1_VRX_EN;
1983 else
1984 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1985
1986 if (enable)
1987 reg |= mask;
1988 else
1989 reg &= ~mask;
1990
1991 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1992}
1993
7154b3e8
JS		 1994static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1995 struct snd_soc_dai *dai)
1996{
e6968a17 1997 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1998 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1999 u8 mode;
2000
2001 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 2002 * not available.
7154b3e8 2003 */
68d01955 2004 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 2005 dev_err(codec->dev,
2006 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2007 __func__, twl4030->sysclk);
7154b3e8
JS		 2008 return -EINVAL;
2009 }
2010
2011 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 2012 * available.
7154b3e8
JS		 2013 */
2014 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2015 & TWL4030_OPT_MODE;
2016
2017 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 2018 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2019 __func__);
7154b3e8
JS		 2020 return -EINVAL;
2021 }
2022
2023 return 0;
2024}
2025
b7a755a8
MLC		 2026static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2027 struct snd_soc_dai *dai)
2028{
e6968a17 2029 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 2030
2031 /* Enable voice digital filters */
2032 twl4030_voice_enable(codec, substream->stream, 0);
2033}
2034
7154b3e8
JS		 2035static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2036 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2037{
e6968a17 2038 struct snd_soc_codec *codec = dai->codec;
2046f175 2039 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2040 u8 old_mode, mode;
2041
b7a755a8
MLC		 2042 /* Enable voice digital filters */
2043 twl4030_voice_enable(codec, substream->stream, 1);
2044
7154b3e8
JS		 2045 /* bit rate */
2046 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2047 & ~(TWL4030_CODECPDZ);
2048 mode = old_mode;
2049
2050 switch (params_rate(params)) {
2051 case 8000:
2052 mode &= ~(TWL4030_SEL_16K);
2053 break;
2054 case 16000:
2055 mode |= TWL4030_SEL_16K;
2056 break;
2057 default:
3b8a0795 2058 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2059 params_rate(params));
2060 return -EINVAL;
2061 }
2062
2063 if (mode != old_mode) {
2046f175
PU		 2064 if (twl4030->codec_powered) {
2065 /*
2066 * If the codec is powered, than we need to toggle the
2067 * codec power.
2068 */
2069 twl4030_codec_enable(codec, 0);
2070 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2071 twl4030_codec_enable(codec, 1);
2072 } else {
2073 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2074 }
7154b3e8
JS		 2075 }
2076
2077 return 0;
2078}
2079
2080static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2081 int clk_id, unsigned int freq, int dir)
2082{
2083 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2084 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2085
68d01955 2086 if (freq != 26000000) {
3b8a0795
PU		 2087 dev_err(codec->dev,
2088 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2089 __func__, freq / 1000);
68d01955
PU		 2090 return -EINVAL;
2091 }
2092 if ((freq / 1000) != twl4030->sysclk) {
2093 dev_err(codec->dev,
3b8a0795 2094 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2095 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2096 return -EINVAL;
2097 }
7154b3e8
JS		 2098 return 0;
2099}
2100
2101static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2102 unsigned int fmt)
2103{
2104 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2105 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2106 u8 old_format, format;
2107
2108 /* get format */
2109 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2110 format = old_format;
2111
2112 /* set master/slave audio interface */
2113 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2114 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2115 format &= ~(TWL4030_VIF_SLAVE_EN);
2116 break;
2117 case SND_SOC_DAIFMT_CBS_CFS:
2118 format |= TWL4030_VIF_SLAVE_EN;
2119 break;
2120 default:
2121 return -EINVAL;
2122 }
2123
2124 /* clock inversion */
2125 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2126 case SND_SOC_DAIFMT_IB_NF:
2127 format &= ~(TWL4030_VIF_FORMAT);
2128 break;
2129 case SND_SOC_DAIFMT_NB_IF:
2130 format |= TWL4030_VIF_FORMAT;
2131 break;
2132 default:
2133 return -EINVAL;
2134 }
2135
2136 if (format != old_format) {
2046f175
PU		 2137 if (twl4030->codec_powered) {
2138 /*
2139 * If the codec is powered, than we need to toggle the
2140 * codec power.
2141 */
2142 twl4030_codec_enable(codec, 0);
2143 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2144 twl4030_codec_enable(codec, 1);
2145 } else {
2146 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2147 }
7154b3e8
JS		 2148 }
2149
2150 return 0;
2151}
2152
68140443
LCM		 2153static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2154{
2155 struct snd_soc_codec *codec = dai->codec;
2156 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2157
2158 if (tristate)
2159 reg |= TWL4030_VIF_TRI_EN;
2160 else
2161 reg &= ~TWL4030_VIF_TRI_EN;
2162
2163 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2164}
2165
bbba9444 2166#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2167#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2168
85e7652d 2169static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2170 .startup = twl4030_startup,
2171 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2172 .hw_params = twl4030_hw_params,
2173 .set_sysclk = twl4030_set_dai_sysclk,
2174 .set_fmt = twl4030_set_dai_fmt,
68140443 2175 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2176};
2177
85e7652d 2178static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2179 .startup = twl4030_voice_startup,
b7a755a8 2180 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2181 .hw_params = twl4030_voice_hw_params,
2182 .set_sysclk = twl4030_voice_set_dai_sysclk,
2183 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2184 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2185};
2186
f0fba2ad 2187static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2188{
f0fba2ad 2189 .name = "twl4030-hifi",
cc17557e 2190 .playback = {
b4852b79 2191 .stream_name = "HiFi Playback",
cc17557e 2192 .channels_min = 2,
8a1f936a 2193 .channels_max = 4,
31ad0f31 2194 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2195 .formats = TWL4030_FORMATS,
2196 .sig_bits = 24,},
cc17557e 2197 .capture = {
7f51e7d3 2198 .stream_name = "HiFi Capture",
cc17557e 2199 .channels_min = 2,
8a1f936a 2200 .channels_max = 4,
cc17557e 2201 .rates = TWL4030_RATES,
8819f65c
PU		 2202 .formats = TWL4030_FORMATS,
2203 .sig_bits = 24,},
f0fba2ad 2204 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2205},
2206{
f0fba2ad 2207 .name = "twl4030-voice",
7154b3e8 2208 .playback = {
b4852b79 2209 .stream_name = "Voice Playback",
7154b3e8
JS		 2210 .channels_min = 1,
2211 .channels_max = 1,
2212 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2213 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2214 .capture = {
7f51e7d3 2215 .stream_name = "Voice Capture",
7154b3e8
JS		 2216 .channels_min = 1,
2217 .channels_max = 2,
2218 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2219 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2220 .ops = &twl4030_dai_voice_ops,
2221},
cc17557e 2222};
cc17557e 2223
84b315ee 2224static int twl4030_soc_suspend(struct snd_soc_codec *codec)
cc17557e 2225{
cc17557e 2226 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
cc17557e
SS		 2227 return 0;
2228}
2229
f0fba2ad 2230static int twl4030_soc_resume(struct snd_soc_codec *codec)
cc17557e 2231{
cc17557e 2232 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2233 return 0;
2234}
2235
f0fba2ad 2236static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2237{
f0fba2ad 2238 struct twl4030_priv *twl4030;
9da28c7b 2239
f2b1ce49
PU		 2240 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2241 GFP_KERNEL);
f0fba2ad 2242 if (twl4030 == NULL) {
3b8a0795 2243 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2244 return -ENOMEM;
cc17557e 2245 }
f0fba2ad
LG		 2246 snd_soc_codec_set_drvdata(codec, twl4030);
2247 /* Set the defaults, and power up the codec */
57fe7251 2248 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2249
2250 twl4030_init_chip(codec);
cc17557e 2251
7a1fecf5 2252 return 0;
cc17557e
SS		 2253}
2254
f0fba2ad 2255static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2256{
281ecd16 2257 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
5b3b0fa8
AL		 2258 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2259
5dcba5d6
PU		 2260 /* Reset registers to their chip default before leaving */
2261 twl4030_reset_registers(codec);
7a1fecf5 2262 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2263
2264 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2265 gpio_free(pdata->hs_extmute_gpio);
2266
7a1fecf5
PU		 2267 return 0;
2268}
2269
f0fba2ad
LG		 2270static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2271 .probe = twl4030_soc_probe,
2272 .remove = twl4030_soc_remove,
2273 .suspend = twl4030_soc_suspend,
2274 .resume = twl4030_soc_resume,
2275 .read = twl4030_read_reg_cache,
2276 .write = twl4030_write,
2277 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2278 .idle_bias_off = true,
f0fba2ad
LG		 2279 .reg_cache_size = sizeof(twl4030_reg),
2280 .reg_word_size = sizeof(u8),
2281 .reg_cache_default = twl4030_reg,
f7c93f01
PU		 2282
2283 .controls = twl4030_snd_controls,
2284 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2285 .dapm_widgets = twl4030_dapm_widgets,
2286 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2287 .dapm_routes = intercon,
2288 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2289};
2290
7a1fecf5
PU		 2291static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2292{
4ae6df5e 2293 struct twl4030_codec_data *pdata = pdev->dev.platform_data;
cc17557e 2294
68d01955
PU		 2295 if (!pdata) {
2296 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2297 return -EINVAL;
2298 }
cc17557e 2299
f0fba2ad
LG		 2300 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2301 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2302}
2303
7a1fecf5 2304static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2305{
f0fba2ad 2306 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2307 return 0;
2308}
2309
f0fba2ad 2310MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2311
2312static struct platform_driver twl4030_codec_driver = {
2313 .probe = twl4030_codec_probe,
2314 .remove = __devexit_p(twl4030_codec_remove),
2315 .driver = {
f0fba2ad 2316 .name = "twl4030-codec",
7a1fecf5
PU		 2317 .owner = THIS_MODULE,
2318 },
cc17557e 2319};
cc17557e 2320
5bbcc3c0 2321module_platform_driver(twl4030_codec_driver);
64089b84 2322
cc17557e
SS		 2323MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2324MODULE_AUTHOR("Steve Sakoman");
2325MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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