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ASoC: TWL4030: Make the enum filter generic for twl4030
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
5e98a464
PU		 193/* Earpiece */
194static const char *twl4030_earpiece_texts[] =
d4a73131 195 {"Off", "DACL1", "DACL2", "Invalid", "DACR1"};
5e98a464
PU		 196
197static const struct soc_enum twl4030_earpiece_enum =
198 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
199 ARRAY_SIZE(twl4030_earpiece_texts),
200 twl4030_earpiece_texts);
201
202static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
203SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
204
2a6f5c58
PU		 205/* PreDrive Left */
206static const char *twl4030_predrivel_texts[] =
d4a73131 207 {"Off", "DACL1", "DACL2", "Invalid", "DACR2"};
2a6f5c58
PU		 208
209static const struct soc_enum twl4030_predrivel_enum =
210 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
211 ARRAY_SIZE(twl4030_predrivel_texts),
212 twl4030_predrivel_texts);
213
214static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
215SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
216
217/* PreDrive Right */
218static const char *twl4030_predriver_texts[] =
d4a73131 219 {"Off", "DACR1", "DACR2", "Invalid", "DACL2"};
2a6f5c58
PU		 220
221static const struct soc_enum twl4030_predriver_enum =
222 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
223 ARRAY_SIZE(twl4030_predriver_texts),
224 twl4030_predriver_texts);
225
226static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
227SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
228
dfad21a2
PU		 229/* Headset Left */
230static const char *twl4030_hsol_texts[] =
231 {"Off", "DACL1", "DACL2"};
232
233static const struct soc_enum twl4030_hsol_enum =
234 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
235 ARRAY_SIZE(twl4030_hsol_texts),
236 twl4030_hsol_texts);
237
238static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
239SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
240
241/* Headset Right */
242static const char *twl4030_hsor_texts[] =
243 {"Off", "DACR1", "DACR2"};
244
245static const struct soc_enum twl4030_hsor_enum =
246 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
247 ARRAY_SIZE(twl4030_hsor_texts),
248 twl4030_hsor_texts);
249
250static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
251SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
252
5152d8c2
PU		 253/* Carkit Left */
254static const char *twl4030_carkitl_texts[] =
255 {"Off", "DACL1", "DACL2"};
256
257static const struct soc_enum twl4030_carkitl_enum =
258 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
259 ARRAY_SIZE(twl4030_carkitl_texts),
260 twl4030_carkitl_texts);
261
262static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
263SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
264
265/* Carkit Right */
266static const char *twl4030_carkitr_texts[] =
267 {"Off", "DACR1", "DACR2"};
268
269static const struct soc_enum twl4030_carkitr_enum =
270 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
271 ARRAY_SIZE(twl4030_carkitr_texts),
272 twl4030_carkitr_texts);
273
274static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
275SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
276
df339804
PU		 277/* Handsfree Left */
278static const char *twl4030_handsfreel_texts[] =
279 {"Voice", "DACL1", "DACL2", "DACR2"};
280
281static const struct soc_enum twl4030_handsfreel_enum =
282 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
283 ARRAY_SIZE(twl4030_handsfreel_texts),
284 twl4030_handsfreel_texts);
285
286static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
287SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
288
289/* Handsfree Right */
290static const char *twl4030_handsfreer_texts[] =
291 {"Voice", "DACR1", "DACR2", "DACL2"};
292
293static const struct soc_enum twl4030_handsfreer_enum =
294 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
295 ARRAY_SIZE(twl4030_handsfreer_texts),
296 twl4030_handsfreer_texts);
297
298static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
299SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
300
f9a3fba2
PU		 301/*
302 * This function filters out the non valid mux settings, named as "Invalid"
303 * in the enum texts.
304 * Just refuse to set an invalid mux mode.
305 */
306static int twl4030_enum_event(struct snd_soc_dapm_widget *w,
e8ff9c41
PU		 307 struct snd_kcontrol *kcontrol, int event)
308{
309 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
310 int ret = 0;
311 int val;
312
f9a3fba2
PU		 313 val = w->value >> e->shift_l;
314 if (!strcmp("Invalid", e->texts[val])) {
315 printk(KERN_WARNING "Invalid MUX setting on 0x%02x (%d)\n",
316 e->reg, val);
317 ret = -1;
e8ff9c41
PU		 318 }
319
320 return ret;
321}
322
49d92c7d
SM		 323static int handsfree_event(struct snd_soc_dapm_widget *w,
324 struct snd_kcontrol *kcontrol, int event)
325{
326 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
327 unsigned char hs_ctl;
328
329 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
330
331 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
332 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
333 twl4030_write(w->codec, e->reg, hs_ctl);
334 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
335 twl4030_write(w->codec, e->reg, hs_ctl);
336 hs_ctl |= TWL4030_HF_CTL_HB_EN;
337 twl4030_write(w->codec, e->reg, hs_ctl);
338 } else {
339 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
340 | TWL4030_HF_CTL_HB_EN);
341 twl4030_write(w->codec, e->reg, hs_ctl);
342 }
343
344 return 0;
345}
346
b0bd53a7
PU		 347/*
348 * Some of the gain controls in TWL (mostly those which are associated with
349 * the outputs) are implemented in an interesting way:
350 * 0x0 : Power down (mute)
351 * 0x1 : 6dB
352 * 0x2 : 0 dB
353 * 0x3 : -6 dB
354 * Inverting not going to help with these.
355 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
356 */
357#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
358 xinvert, tlv_array) \
359{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
360 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
361 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
362 .tlv.p = (tlv_array), \
363 .info = snd_soc_info_volsw, \
364 .get = snd_soc_get_volsw_twl4030, \
365 .put = snd_soc_put_volsw_twl4030, \
366 .private_value = (unsigned long)&(struct soc_mixer_control) \
367 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
368 .max = xmax, .invert = xinvert} }
369#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
370 xinvert, tlv_array) \
371{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
372 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
373 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
374 .tlv.p = (tlv_array), \
375 .info = snd_soc_info_volsw_2r, \
376 .get = snd_soc_get_volsw_r2_twl4030,\
377 .put = snd_soc_put_volsw_r2_twl4030, \
378 .private_value = (unsigned long)&(struct soc_mixer_control) \
379 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 380 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 381#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
382 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
383 xinvert, tlv_array)
384
385static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
386 struct snd_ctl_elem_value *ucontrol)
387{
388 struct soc_mixer_control *mc =
389 (struct soc_mixer_control *)kcontrol->private_value;
390 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
391 unsigned int reg = mc->reg;
392 unsigned int shift = mc->shift;
393 unsigned int rshift = mc->rshift;
394 int max = mc->max;
395 int mask = (1 << fls(max)) - 1;
396
397 ucontrol->value.integer.value[0] =
398 (snd_soc_read(codec, reg) >> shift) & mask;
399 if (ucontrol->value.integer.value[0])
400 ucontrol->value.integer.value[0] =
401 max + 1 - ucontrol->value.integer.value[0];
402
403 if (shift != rshift) {
404 ucontrol->value.integer.value[1] =
405 (snd_soc_read(codec, reg) >> rshift) & mask;
406 if (ucontrol->value.integer.value[1])
407 ucontrol->value.integer.value[1] =
408 max + 1 - ucontrol->value.integer.value[1];
409 }
410
411 return 0;
412}
413
414static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
415 struct snd_ctl_elem_value *ucontrol)
416{
417 struct soc_mixer_control *mc =
418 (struct soc_mixer_control *)kcontrol->private_value;
419 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
420 unsigned int reg = mc->reg;
421 unsigned int shift = mc->shift;
422 unsigned int rshift = mc->rshift;
423 int max = mc->max;
424 int mask = (1 << fls(max)) - 1;
425 unsigned short val, val2, val_mask;
426
427 val = (ucontrol->value.integer.value[0] & mask);
428
429 val_mask = mask << shift;
430 if (val)
431 val = max + 1 - val;
432 val = val << shift;
433 if (shift != rshift) {
434 val2 = (ucontrol->value.integer.value[1] & mask);
435 val_mask |= mask << rshift;
436 if (val2)
437 val2 = max + 1 - val2;
438 val |= val2 << rshift;
439 }
440 return snd_soc_update_bits(codec, reg, val_mask, val);
441}
442
443static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
444 struct snd_ctl_elem_value *ucontrol)
445{
446 struct soc_mixer_control *mc =
447 (struct soc_mixer_control *)kcontrol->private_value;
448 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
449 unsigned int reg = mc->reg;
450 unsigned int reg2 = mc->rreg;
451 unsigned int shift = mc->shift;
452 int max = mc->max;
453 int mask = (1<<fls(max))-1;
454
455 ucontrol->value.integer.value[0] =
456 (snd_soc_read(codec, reg) >> shift) & mask;
457 ucontrol->value.integer.value[1] =
458 (snd_soc_read(codec, reg2) >> shift) & mask;
459
460 if (ucontrol->value.integer.value[0])
461 ucontrol->value.integer.value[0] =
462 max + 1 - ucontrol->value.integer.value[0];
463 if (ucontrol->value.integer.value[1])
464 ucontrol->value.integer.value[1] =
465 max + 1 - ucontrol->value.integer.value[1];
466
467 return 0;
468}
469
470static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
471 struct snd_ctl_elem_value *ucontrol)
472{
473 struct soc_mixer_control *mc =
474 (struct soc_mixer_control *)kcontrol->private_value;
475 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
476 unsigned int reg = mc->reg;
477 unsigned int reg2 = mc->rreg;
478 unsigned int shift = mc->shift;
479 int max = mc->max;
480 int mask = (1 << fls(max)) - 1;
481 int err;
482 unsigned short val, val2, val_mask;
483
484 val_mask = mask << shift;
485 val = (ucontrol->value.integer.value[0] & mask);
486 val2 = (ucontrol->value.integer.value[1] & mask);
487
488 if (val)
489 val = max + 1 - val;
490 if (val2)
491 val2 = max + 1 - val2;
492
493 val = val << shift;
494 val2 = val2 << shift;
495
496 err = snd_soc_update_bits(codec, reg, val_mask, val);
497 if (err < 0)
498 return err;
499
500 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
501 return err;
502}
503
5920b453
GI		 504static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_codec *codec = kcontrol->private_data;
508 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
509 int result = 0;
510
511 /* one bit must be set a time */
512 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
513 | TWL4030_MAINMIC_EN;
514 if (reg != 0) {
515 result++;
516 while ((reg & 1) == 0) {
517 result++;
518 reg >>= 1;
519 }
520 }
521
522 ucontrol->value.integer.value[0] = result;
523 return 0;
524}
525
526static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
527 struct snd_ctl_elem_value *ucontrol)
528{
529 struct snd_soc_codec *codec = kcontrol->private_data;
530 int value = ucontrol->value.integer.value[0];
531 u8 anamicl, micbias, avadc_ctl;
532
533 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
534 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
535 | TWL4030_MAINMIC_EN);
536 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
537 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
538 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
539
540 switch (value) {
541 case 1:
542 anamicl |= TWL4030_MAINMIC_EN;
543 micbias |= TWL4030_MICBIAS1_EN;
544 break;
545 case 2:
546 anamicl |= TWL4030_HSMIC_EN;
547 micbias |= TWL4030_HSMICBIAS_EN;
548 break;
549 case 3:
550 anamicl |= TWL4030_AUXL_EN;
551 break;
552 case 4:
553 anamicl |= TWL4030_CKMIC_EN;
554 break;
555 default:
556 break;
557 }
558
559 /* If some input is selected, enable amp and ADC */
560 if (value != 0) {
561 anamicl |= TWL4030_MICAMPL_EN;
562 avadc_ctl |= TWL4030_ADCL_EN;
563 } else {
564 anamicl &= ~TWL4030_MICAMPL_EN;
565 avadc_ctl &= ~TWL4030_ADCL_EN;
566 }
567
568 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
569 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
570 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
571
572 return 1;
573}
574
575static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
576 struct snd_ctl_elem_value *ucontrol)
577{
578 struct snd_soc_codec *codec = kcontrol->private_data;
579 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
580 int value = 0;
581
582 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
583 switch (reg) {
584 case TWL4030_SUBMIC_EN:
585 value = 1;
586 break;
587 case TWL4030_AUXR_EN:
588 value = 2;
589 break;
590 default:
591 break;
592 }
593
594 ucontrol->value.integer.value[0] = value;
595 return 0;
596}
597
598static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
599 struct snd_ctl_elem_value *ucontrol)
600{
601 struct snd_soc_codec *codec = kcontrol->private_data;
602 int value = ucontrol->value.integer.value[0];
603 u8 anamicr, micbias, avadc_ctl;
604
605 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
606 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
607 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
608 micbias &= ~TWL4030_MICBIAS2_EN;
609 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
610
611 switch (value) {
612 case 1:
613 anamicr |= TWL4030_SUBMIC_EN;
614 micbias |= TWL4030_MICBIAS2_EN;
615 break;
616 case 2:
617 anamicr |= TWL4030_AUXR_EN;
618 break;
619 default:
620 break;
621 }
622
623 if (value != 0) {
624 anamicr |= TWL4030_MICAMPR_EN;
625 avadc_ctl |= TWL4030_ADCR_EN;
626 } else {
627 anamicr &= ~TWL4030_MICAMPR_EN;
628 avadc_ctl &= ~TWL4030_ADCR_EN;
629 }
630
631 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
632 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
633 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
634
635 return 1;
636}
637
638static const char *twl4030_left_in_sel[] = {
639 "None",
640 "Main Mic",
641 "Headset Mic",
642 "Line In",
643 "Carkit Mic",
644};
645
646static const char *twl4030_right_in_sel[] = {
647 "None",
648 "Sub Mic",
649 "Line In",
650};
651
652static const struct soc_enum twl4030_left_input_mux =
653 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
654 twl4030_left_in_sel);
655
656static const struct soc_enum twl4030_right_input_mux =
657 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
658 twl4030_right_in_sel);
659
c10b82cf
PU		 660/*
661 * FGAIN volume control:
662 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
663 */
d889a72c 664static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 665
0d33ea0b
PU		 666/*
667 * CGAIN volume control:
668 * 0 dB to 12 dB in 6 dB steps
669 * value 2 and 3 means 12 dB
670 */
d889a72c
PU		 671static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
672
673/*
674 * Analog playback gain
675 * -24 dB to 12 dB in 2 dB steps
676 */
677static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 678
4290239c
PU		 679/*
680 * Gain controls tied to outputs
681 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
682 */
683static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
684
381a22b5
PU		 685/*
686 * Capture gain after the ADCs
687 * from 0 dB to 31 dB in 1 dB steps
688 */
689static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
690
5920b453
GI		 691/*
692 * Gain control for input amplifiers
693 * 0 dB to 30 dB in 6 dB steps
694 */
695static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
696
cc17557e 697static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 698 /* Common playback gain controls */
699 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
700 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
701 0, 0x3f, 0, digital_fine_tlv),
702 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
703 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
704 0, 0x3f, 0, digital_fine_tlv),
705
706 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
707 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
708 6, 0x2, 0, digital_coarse_tlv),
709 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
710 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
711 6, 0x2, 0, digital_coarse_tlv),
712
713 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
714 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
715 3, 0x12, 1, analog_tlv),
716 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
717 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
718 3, 0x12, 1, analog_tlv),
44c55870
PU		 719 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
720 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
721 1, 1, 0),
722 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
723 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
724 1, 1, 0),
381a22b5 725
4290239c
PU		 726 /* Separate output gain controls */
727 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
728 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
729 4, 3, 0, output_tvl),
730
731 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
732 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
733
734 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
735 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
736 4, 3, 0, output_tvl),
737
738 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
739 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
740
381a22b5
PU		 741 /* Common capture gain controls */
742 SOC_DOUBLE_R_TLV("Capture Volume",
743 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
744 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 745
746 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
747 0, 3, 5, 0, input_gain_tlv),
748
749 /* Input source controls */
750 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
751 twl4030_get_left_input, twl4030_put_left_input),
752 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
753 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 754};
755
756/* add non dapm controls */
757static int twl4030_add_controls(struct snd_soc_codec *codec)
758{
759 int err, i;
760
761 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
762 err = snd_ctl_add(codec->card,
763 snd_soc_cnew(&twl4030_snd_controls[i],
764 codec, NULL));
765 if (err < 0)
766 return err;
767 }
768
769 return 0;
770}
771
772static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
773 SND_SOC_DAPM_INPUT("INL"),
774 SND_SOC_DAPM_INPUT("INR"),
775
776 SND_SOC_DAPM_OUTPUT("OUTL"),
777 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 778 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 779 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
780 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 781 SND_SOC_DAPM_OUTPUT("HSOL"),
782 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 783 SND_SOC_DAPM_OUTPUT("CARKITL"),
784 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 785 SND_SOC_DAPM_OUTPUT("HFL"),
786 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 787
53b5047d 788 /* DACs */
1e5fa31f 789 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
53b5047d 790 TWL4030_REG_AVDAC_CTL, 0, 0),
1e5fa31f 791 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
53b5047d 792 TWL4030_REG_AVDAC_CTL, 1, 0),
1e5fa31f 793 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
53b5047d 794 TWL4030_REG_AVDAC_CTL, 2, 0),
1e5fa31f 795 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
53b5047d 796 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 797
44c55870
PU		 798 /* Analog PGAs */
799 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
800 0, 0, NULL, 0),
801 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
802 0, 0, NULL, 0),
803 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
804 0, 0, NULL, 0),
805 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
806 0, 0, NULL, 0),
807
5e98a464
PU		 808 /* Output MUX controls */
809 /* Earpiece */
810 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
f9a3fba2 811 &twl4030_dapm_earpiece_control, twl4030_enum_event,
5e98a464 812 SND_SOC_DAPM_PRE_REG),
2a6f5c58
PU		 813 /* PreDrivL/R */
814 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
f9a3fba2 815 &twl4030_dapm_predrivel_control, twl4030_enum_event,
2a6f5c58
PU		 816 SND_SOC_DAPM_PRE_REG),
817 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
f9a3fba2 818 &twl4030_dapm_predriver_control, twl4030_enum_event,
2a6f5c58 819 SND_SOC_DAPM_PRE_REG),
dfad21a2
PU		 820 /* HeadsetL/R */
821 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
822 &twl4030_dapm_hsol_control),
823 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
824 &twl4030_dapm_hsor_control),
5152d8c2
PU		 825 /* CarkitL/R */
826 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
827 &twl4030_dapm_carkitl_control),
828 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
829 &twl4030_dapm_carkitr_control),
df339804 830 /* HandsfreeL/R */
49d92c7d
SM		 831 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
832 &twl4030_dapm_handsfreel_control, handsfree_event,
833 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
834 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
835 &twl4030_dapm_handsfreer_control, handsfree_event,
836 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 837
cc17557e
SS		 838 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
839 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
840};
841
842static const struct snd_soc_dapm_route intercon[] = {
1e5fa31f
PU		 843 {"ARXL1_APGA", NULL, "DAC Left1"},
844 {"ARXR1_APGA", NULL, "DAC Right1"},
845 {"ARXL2_APGA", NULL, "DAC Left2"},
846 {"ARXR2_APGA", NULL, "DAC Right2"},
44c55870 847
5e98a464
PU		 848 /* Internal playback routings */
849 /* Earpiece */
850 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
851 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
852 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 853 /* PreDrivL */
854 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
855 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
856 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
857 /* PreDrivR */
858 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
859 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
860 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 861 /* HeadsetL */
862 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
863 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
864 /* HeadsetR */
865 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
866 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 867 /* CarkitL */
868 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
869 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
870 /* CarkitR */
871 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
872 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 873 /* HandsfreeL */
874 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
875 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
876 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
877 /* HandsfreeR */
878 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
879 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
880 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 881
cc17557e 882 /* outputs */
44c55870
PU		 883 {"OUTL", NULL, "ARXL2_APGA"},
884 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 885 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 886 {"PREDRIVEL", NULL, "PredriveL Mux"},
887 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 888 {"HSOL", NULL, "HeadsetL Mux"},
889 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 890 {"CARKITL", NULL, "CarkitL Mux"},
891 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 892 {"HFL", NULL, "HandsfreeL Mux"},
893 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e
SS		 894
895 /* inputs */
896 {"ADCL", NULL, "INL"},
897 {"ADCR", NULL, "INR"},
898};
899
900static int twl4030_add_widgets(struct snd_soc_codec *codec)
901{
902 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
903 ARRAY_SIZE(twl4030_dapm_widgets));
904
905 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
906
907 snd_soc_dapm_new_widgets(codec);
908 return 0;
909}
910
911static void twl4030_power_up(struct snd_soc_codec *codec)
912{
ca4513fe 913 u8 anamicl, regmisc1, byte, popn;
cc17557e
SS		 914 int i = 0;
915
916 /* set CODECPDZ to turn on codec */
917 twl4030_set_codecpdz(codec);
918
919 /* initiate offset cancellation */
920 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
921 twl4030_write(codec, TWL4030_REG_ANAMICL,
922 anamicl | TWL4030_CNCL_OFFSET_START);
923
924 /* wait for offset cancellation to complete */
925 do {
926 /* this takes a little while, so don't slam i2c */
927 udelay(2000);
928 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
929 TWL4030_REG_ANAMICL);
930 } while ((i++ < 100) &&
931 ((byte & TWL4030_CNCL_OFFSET_START) ==
932 TWL4030_CNCL_OFFSET_START));
933
934 /* anti-pop when changing analog gain */
935 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
936 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
937 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
938
939 /* toggle CODECPDZ as per TRM */
940 twl4030_clear_codecpdz(codec);
941 twl4030_set_codecpdz(codec);
942
943 /* program anti-pop with bias ramp delay */
944 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
945 popn &= TWL4030_RAMP_DELAY;
946 popn |= TWL4030_RAMP_DELAY_645MS;
947 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
948 popn |= TWL4030_VMID_EN;
949 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
950
cc17557e
SS		 951 /* enable anti-pop ramp */
952 popn |= TWL4030_RAMP_EN;
953 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
954}
955
956static void twl4030_power_down(struct snd_soc_codec *codec)
957{
ca4513fe 958 u8 popn;
cc17557e
SS		 959
960 /* disable anti-pop ramp */
961 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
962 popn &= ~TWL4030_RAMP_EN;
963 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
964
cc17557e
SS		 965 /* disable bias out */
966 popn &= ~TWL4030_VMID_EN;
967 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
968
969 /* power down */
970 twl4030_clear_codecpdz(codec);
971}
972
973static int twl4030_set_bias_level(struct snd_soc_codec *codec,
974 enum snd_soc_bias_level level)
975{
976 switch (level) {
977 case SND_SOC_BIAS_ON:
978 twl4030_power_up(codec);
979 break;
980 case SND_SOC_BIAS_PREPARE:
981 /* TODO: develop a twl4030_prepare function */
982 break;
983 case SND_SOC_BIAS_STANDBY:
984 /* TODO: develop a twl4030_standby function */
985 twl4030_power_down(codec);
986 break;
987 case SND_SOC_BIAS_OFF:
988 twl4030_power_down(codec);
989 break;
990 }
991 codec->bias_level = level;
992
993 return 0;
994}
995
996static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 997 struct snd_pcm_hw_params *params,
998 struct snd_soc_dai *dai)
cc17557e
SS		 999{
1000 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1001 struct snd_soc_device *socdev = rtd->socdev;
1002 struct snd_soc_codec *codec = socdev->codec;
1003 u8 mode, old_mode, format, old_format;
1004
1005
1006 /* bit rate */
1007 old_mode = twl4030_read_reg_cache(codec,
1008 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1009 mode = old_mode & ~TWL4030_APLL_RATE;
1010
1011 switch (params_rate(params)) {
1012 case 8000:
1013 mode |= TWL4030_APLL_RATE_8000;
1014 break;
1015 case 11025:
1016 mode |= TWL4030_APLL_RATE_11025;
1017 break;
1018 case 12000:
1019 mode |= TWL4030_APLL_RATE_12000;
1020 break;
1021 case 16000:
1022 mode |= TWL4030_APLL_RATE_16000;
1023 break;
1024 case 22050:
1025 mode |= TWL4030_APLL_RATE_22050;
1026 break;
1027 case 24000:
1028 mode |= TWL4030_APLL_RATE_24000;
1029 break;
1030 case 32000:
1031 mode |= TWL4030_APLL_RATE_32000;
1032 break;
1033 case 44100:
1034 mode |= TWL4030_APLL_RATE_44100;
1035 break;
1036 case 48000:
1037 mode |= TWL4030_APLL_RATE_48000;
1038 break;
1039 default:
1040 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1041 params_rate(params));
1042 return -EINVAL;
1043 }
1044
1045 if (mode != old_mode) {
1046 /* change rate and set CODECPDZ */
1047 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1048 twl4030_set_codecpdz(codec);
1049 }
1050
1051 /* sample size */
1052 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1053 format = old_format;
1054 format &= ~TWL4030_DATA_WIDTH;
1055 switch (params_format(params)) {
1056 case SNDRV_PCM_FORMAT_S16_LE:
1057 format |= TWL4030_DATA_WIDTH_16S_16W;
1058 break;
1059 case SNDRV_PCM_FORMAT_S24_LE:
1060 format |= TWL4030_DATA_WIDTH_32S_24W;
1061 break;
1062 default:
1063 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1064 params_format(params));
1065 return -EINVAL;
1066 }
1067
1068 if (format != old_format) {
1069
1070 /* clear CODECPDZ before changing format (codec requirement) */
1071 twl4030_clear_codecpdz(codec);
1072
1073 /* change format */
1074 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1075
1076 /* set CODECPDZ afterwards */
1077 twl4030_set_codecpdz(codec);
1078 }
1079 return 0;
1080}
1081
1082static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1083 int clk_id, unsigned int freq, int dir)
1084{
1085 struct snd_soc_codec *codec = codec_dai->codec;
1086 u8 infreq;
1087
1088 switch (freq) {
1089 case 19200000:
1090 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1091 break;
1092 case 26000000:
1093 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1094 break;
1095 case 38400000:
1096 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1097 break;
1098 default:
1099 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1100 freq);
1101 return -EINVAL;
1102 }
1103
1104 infreq |= TWL4030_APLL_EN;
1105 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1106
1107 return 0;
1108}
1109
1110static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1111 unsigned int fmt)
1112{
1113 struct snd_soc_codec *codec = codec_dai->codec;
1114 u8 old_format, format;
1115
1116 /* get format */
1117 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1118 format = old_format;
1119
1120 /* set master/slave audio interface */
1121 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1122 case SND_SOC_DAIFMT_CBM_CFM:
1123 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1124 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1125 break;
1126 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1127 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1128 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1129 break;
1130 default:
1131 return -EINVAL;
1132 }
1133
1134 /* interface format */
1135 format &= ~TWL4030_AIF_FORMAT;
1136 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1137 case SND_SOC_DAIFMT_I2S:
1138 format |= TWL4030_AIF_FORMAT_CODEC;
1139 break;
1140 default:
1141 return -EINVAL;
1142 }
1143
1144 if (format != old_format) {
1145
1146 /* clear CODECPDZ before changing format (codec requirement) */
1147 twl4030_clear_codecpdz(codec);
1148
1149 /* change format */
1150 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1151
1152 /* set CODECPDZ afterwards */
1153 twl4030_set_codecpdz(codec);
1154 }
1155
1156 return 0;
1157}
1158
bbba9444 1159#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1160#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1161
1162struct snd_soc_dai twl4030_dai = {
1163 .name = "twl4030",
1164 .playback = {
1165 .stream_name = "Playback",
1166 .channels_min = 2,
1167 .channels_max = 2,
1168 .rates = TWL4030_RATES,
1169 .formats = TWL4030_FORMATS,},
1170 .capture = {
1171 .stream_name = "Capture",
1172 .channels_min = 2,
1173 .channels_max = 2,
1174 .rates = TWL4030_RATES,
1175 .formats = TWL4030_FORMATS,},
1176 .ops = {
1177 .hw_params = twl4030_hw_params,
cc17557e
SS		 1178 .set_sysclk = twl4030_set_dai_sysclk,
1179 .set_fmt = twl4030_set_dai_fmt,
1180 }
1181};
1182EXPORT_SYMBOL_GPL(twl4030_dai);
1183
1184static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1185{
1186 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1187 struct snd_soc_codec *codec = socdev->codec;
1188
1189 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1190
1191 return 0;
1192}
1193
1194static int twl4030_resume(struct platform_device *pdev)
1195{
1196 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1197 struct snd_soc_codec *codec = socdev->codec;
1198
1199 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1200 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1201 return 0;
1202}
1203
1204/*
1205 * initialize the driver
1206 * register the mixer and dsp interfaces with the kernel
1207 */
1208
1209static int twl4030_init(struct snd_soc_device *socdev)
1210{
1211 struct snd_soc_codec *codec = socdev->codec;
1212 int ret = 0;
1213
1214 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1215
1216 codec->name = "twl4030";
1217 codec->owner = THIS_MODULE;
1218 codec->read = twl4030_read_reg_cache;
1219 codec->write = twl4030_write;
1220 codec->set_bias_level = twl4030_set_bias_level;
1221 codec->dai = &twl4030_dai;
1222 codec->num_dai = 1;
1223 codec->reg_cache_size = sizeof(twl4030_reg);
1224 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1225 GFP_KERNEL);
1226 if (codec->reg_cache == NULL)
1227 return -ENOMEM;
1228
1229 /* register pcms */
1230 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1231 if (ret < 0) {
1232 printk(KERN_ERR "twl4030: failed to create pcms\n");
1233 goto pcm_err;
1234 }
1235
1236 twl4030_init_chip(codec);
1237
1238 /* power on device */
1239 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1240
1241 twl4030_add_controls(codec);
1242 twl4030_add_widgets(codec);
1243
968a6025 1244 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1245 if (ret < 0) {
1246 printk(KERN_ERR "twl4030: failed to register card\n");
1247 goto card_err;
1248 }
1249
1250 return ret;
1251
1252card_err:
1253 snd_soc_free_pcms(socdev);
1254 snd_soc_dapm_free(socdev);
1255pcm_err:
1256 kfree(codec->reg_cache);
1257 return ret;
1258}
1259
1260static struct snd_soc_device *twl4030_socdev;
1261
1262static int twl4030_probe(struct platform_device *pdev)
1263{
1264 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1265 struct snd_soc_codec *codec;
1266
1267 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1268 if (codec == NULL)
1269 return -ENOMEM;
1270
1271 socdev->codec = codec;
1272 mutex_init(&codec->mutex);
1273 INIT_LIST_HEAD(&codec->dapm_widgets);
1274 INIT_LIST_HEAD(&codec->dapm_paths);
1275
1276 twl4030_socdev = socdev;
1277 twl4030_init(socdev);
1278
1279 return 0;
1280}
1281
1282static int twl4030_remove(struct platform_device *pdev)
1283{
1284 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1285 struct snd_soc_codec *codec = socdev->codec;
1286
1287 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1288 kfree(codec);
1289
1290 return 0;
1291}
1292
1293struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1294 .probe = twl4030_probe,
1295 .remove = twl4030_remove,
1296 .suspend = twl4030_suspend,
1297 .resume = twl4030_resume,
1298};
1299EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1300
24e07db8 1301static int __init twl4030_modinit(void)
64089b84
MB		 1302{
1303 return snd_soc_register_dai(&twl4030_dai);
1304}
24e07db8 1305module_init(twl4030_modinit);
64089b84
MB		 1306
1307static void __exit twl4030_exit(void)
1308{
1309 snd_soc_unregister_dai(&twl4030_dai);
1310}
1311module_exit(twl4030_exit);
1312
cc17557e
SS		 1313MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1314MODULE_AUTHOR("Steve Sakoman");
1315MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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