Commit | Line | Data |
---|---|---|
cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/i2c/twl4030.h> | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
45 | 0x93, /* REG_CODEC_MODE (0x1) */ | |
46 | 0xc3, /* REG_OPTION (0x2) */ | |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
49 | 0x24, /* REG_ANAMICL (0x5) */ | |
50 | 0x04, /* REG_ANAMICR (0x6) */ | |
51 | 0x0a, /* REG_AVADC_CTL (0x7) */ | |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ | |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
58 | 0x01, /* REG_AUDIO_IF (0xE) */ | |
59 | 0x00, /* REG_VOICE_IF (0xF) */ | |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
67 | 0x0c, /* REG_AVDAC_CTL (0x17) */ | |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ | |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
71 | 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ | |
72 | 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ | |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
78 | 0x24, /* REG_HS_SEL (0x22) */ | |
79 | 0x0a, /* REG_HS_GAIN_SET (0x23) */ | |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ | |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
102 | 0x16, /* REG_APLL_CTL (0x3A) */ | |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ | |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
118 | }; | |
119 | ||
120 | /* | |
121 | * read twl4030 register cache | |
122 | */ | |
123 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
124 | unsigned int reg) | |
125 | { | |
126 | u8 *cache = codec->reg_cache; | |
127 | ||
128 | return cache[reg]; | |
129 | } | |
130 | ||
131 | /* | |
132 | * write twl4030 register cache | |
133 | */ | |
134 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
135 | u8 reg, u8 value) | |
136 | { | |
137 | u8 *cache = codec->reg_cache; | |
138 | ||
139 | if (reg >= TWL4030_CACHEREGNUM) | |
140 | return; | |
141 | cache[reg] = value; | |
142 | } | |
143 | ||
144 | /* | |
145 | * write to the twl4030 register space | |
146 | */ | |
147 | static int twl4030_write(struct snd_soc_codec *codec, | |
148 | unsigned int reg, unsigned int value) | |
149 | { | |
150 | twl4030_write_reg_cache(codec, reg, value); | |
151 | return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); | |
152 | } | |
153 | ||
154 | static void twl4030_clear_codecpdz(struct snd_soc_codec *codec) | |
155 | { | |
156 | u8 mode; | |
157 | ||
158 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
159 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, | |
160 | mode & ~TWL4030_CODECPDZ); | |
161 | ||
162 | /* REVISIT: this delay is present in TI sample drivers */ | |
163 | /* but there seems to be no TRM requirement for it */ | |
164 | udelay(10); | |
165 | } | |
166 | ||
167 | static void twl4030_set_codecpdz(struct snd_soc_codec *codec) | |
168 | { | |
169 | u8 mode; | |
170 | ||
171 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
172 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, | |
173 | mode | TWL4030_CODECPDZ); | |
174 | ||
175 | /* REVISIT: this delay is present in TI sample drivers */ | |
176 | /* but there seems to be no TRM requirement for it */ | |
177 | udelay(10); | |
178 | } | |
179 | ||
180 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
181 | { | |
182 | int i; | |
183 | ||
184 | /* clear CODECPDZ prior to setting register defaults */ | |
185 | twl4030_clear_codecpdz(codec); | |
186 | ||
187 | /* set all audio section registers to reasonable defaults */ | |
188 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
189 | twl4030_write(codec, i, twl4030_reg[i]); | |
190 | ||
191 | } | |
192 | ||
b0bd53a7 PU |
193 | /* |
194 | * Some of the gain controls in TWL (mostly those which are associated with | |
195 | * the outputs) are implemented in an interesting way: | |
196 | * 0x0 : Power down (mute) | |
197 | * 0x1 : 6dB | |
198 | * 0x2 : 0 dB | |
199 | * 0x3 : -6 dB | |
200 | * Inverting not going to help with these. | |
201 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
202 | */ | |
203 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
204 | xinvert, tlv_array) \ | |
205 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
206 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
207 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
208 | .tlv.p = (tlv_array), \ | |
209 | .info = snd_soc_info_volsw, \ | |
210 | .get = snd_soc_get_volsw_twl4030, \ | |
211 | .put = snd_soc_put_volsw_twl4030, \ | |
212 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
213 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
214 | .max = xmax, .invert = xinvert} } | |
215 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
216 | xinvert, tlv_array) \ | |
217 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
218 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
219 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
220 | .tlv.p = (tlv_array), \ | |
221 | .info = snd_soc_info_volsw_2r, \ | |
222 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
223 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
224 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
225 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
226 | .max = xmax, .invert = xinvert} } | |
227 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ | |
228 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
229 | xinvert, tlv_array) | |
230 | ||
231 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
232 | struct snd_ctl_elem_value *ucontrol) | |
233 | { | |
234 | struct soc_mixer_control *mc = | |
235 | (struct soc_mixer_control *)kcontrol->private_value; | |
236 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
237 | unsigned int reg = mc->reg; | |
238 | unsigned int shift = mc->shift; | |
239 | unsigned int rshift = mc->rshift; | |
240 | int max = mc->max; | |
241 | int mask = (1 << fls(max)) - 1; | |
242 | ||
243 | ucontrol->value.integer.value[0] = | |
244 | (snd_soc_read(codec, reg) >> shift) & mask; | |
245 | if (ucontrol->value.integer.value[0]) | |
246 | ucontrol->value.integer.value[0] = | |
247 | max + 1 - ucontrol->value.integer.value[0]; | |
248 | ||
249 | if (shift != rshift) { | |
250 | ucontrol->value.integer.value[1] = | |
251 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
252 | if (ucontrol->value.integer.value[1]) | |
253 | ucontrol->value.integer.value[1] = | |
254 | max + 1 - ucontrol->value.integer.value[1]; | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
261 | struct snd_ctl_elem_value *ucontrol) | |
262 | { | |
263 | struct soc_mixer_control *mc = | |
264 | (struct soc_mixer_control *)kcontrol->private_value; | |
265 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
266 | unsigned int reg = mc->reg; | |
267 | unsigned int shift = mc->shift; | |
268 | unsigned int rshift = mc->rshift; | |
269 | int max = mc->max; | |
270 | int mask = (1 << fls(max)) - 1; | |
271 | unsigned short val, val2, val_mask; | |
272 | ||
273 | val = (ucontrol->value.integer.value[0] & mask); | |
274 | ||
275 | val_mask = mask << shift; | |
276 | if (val) | |
277 | val = max + 1 - val; | |
278 | val = val << shift; | |
279 | if (shift != rshift) { | |
280 | val2 = (ucontrol->value.integer.value[1] & mask); | |
281 | val_mask |= mask << rshift; | |
282 | if (val2) | |
283 | val2 = max + 1 - val2; | |
284 | val |= val2 << rshift; | |
285 | } | |
286 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
287 | } | |
288 | ||
289 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
290 | struct snd_ctl_elem_value *ucontrol) | |
291 | { | |
292 | struct soc_mixer_control *mc = | |
293 | (struct soc_mixer_control *)kcontrol->private_value; | |
294 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
295 | unsigned int reg = mc->reg; | |
296 | unsigned int reg2 = mc->rreg; | |
297 | unsigned int shift = mc->shift; | |
298 | int max = mc->max; | |
299 | int mask = (1<<fls(max))-1; | |
300 | ||
301 | ucontrol->value.integer.value[0] = | |
302 | (snd_soc_read(codec, reg) >> shift) & mask; | |
303 | ucontrol->value.integer.value[1] = | |
304 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
305 | ||
306 | if (ucontrol->value.integer.value[0]) | |
307 | ucontrol->value.integer.value[0] = | |
308 | max + 1 - ucontrol->value.integer.value[0]; | |
309 | if (ucontrol->value.integer.value[1]) | |
310 | ucontrol->value.integer.value[1] = | |
311 | max + 1 - ucontrol->value.integer.value[1]; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
317 | struct snd_ctl_elem_value *ucontrol) | |
318 | { | |
319 | struct soc_mixer_control *mc = | |
320 | (struct soc_mixer_control *)kcontrol->private_value; | |
321 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
322 | unsigned int reg = mc->reg; | |
323 | unsigned int reg2 = mc->rreg; | |
324 | unsigned int shift = mc->shift; | |
325 | int max = mc->max; | |
326 | int mask = (1 << fls(max)) - 1; | |
327 | int err; | |
328 | unsigned short val, val2, val_mask; | |
329 | ||
330 | val_mask = mask << shift; | |
331 | val = (ucontrol->value.integer.value[0] & mask); | |
332 | val2 = (ucontrol->value.integer.value[1] & mask); | |
333 | ||
334 | if (val) | |
335 | val = max + 1 - val; | |
336 | if (val2) | |
337 | val2 = max + 1 - val2; | |
338 | ||
339 | val = val << shift; | |
340 | val2 = val2 << shift; | |
341 | ||
342 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
343 | if (err < 0) | |
344 | return err; | |
345 | ||
346 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
347 | return err; | |
348 | } | |
349 | ||
c10b82cf PU |
350 | /* |
351 | * FGAIN volume control: | |
352 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
353 | */ | |
354 | static DECLARE_TLV_DB_SCALE(master_tlv, -6300, 100, 1); | |
355 | ||
0d33ea0b PU |
356 | /* |
357 | * CGAIN volume control: | |
358 | * 0 dB to 12 dB in 6 dB steps | |
359 | * value 2 and 3 means 12 dB | |
360 | */ | |
361 | static DECLARE_TLV_DB_SCALE(master_coarse_tlv, 0, 600, 0); | |
362 | ||
cc17557e | 363 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
c10b82cf | 364 | SOC_DOUBLE_R_TLV("Master Playback Volume", |
cc17557e | 365 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, |
c10b82cf | 366 | 0, 0x3f, 0, master_tlv), |
0d33ea0b PU |
367 | SOC_DOUBLE_R_TLV("Master PCM Playback Volume", |
368 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
369 | 6, 0x2, 0, master_coarse_tlv), | |
cc17557e SS |
370 | SOC_DOUBLE_R("Capture Volume", |
371 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, | |
6e5d9db2 | 372 | 0, 0x1f, 0), |
cc17557e SS |
373 | }; |
374 | ||
375 | /* add non dapm controls */ | |
376 | static int twl4030_add_controls(struct snd_soc_codec *codec) | |
377 | { | |
378 | int err, i; | |
379 | ||
380 | for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { | |
381 | err = snd_ctl_add(codec->card, | |
382 | snd_soc_cnew(&twl4030_snd_controls[i], | |
383 | codec, NULL)); | |
384 | if (err < 0) | |
385 | return err; | |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { | |
392 | SND_SOC_DAPM_INPUT("INL"), | |
393 | SND_SOC_DAPM_INPUT("INR"), | |
394 | ||
395 | SND_SOC_DAPM_OUTPUT("OUTL"), | |
396 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
397 | ||
398 | SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), | |
399 | SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), | |
400 | ||
401 | SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), | |
402 | SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), | |
403 | }; | |
404 | ||
405 | static const struct snd_soc_dapm_route intercon[] = { | |
406 | /* outputs */ | |
407 | {"OUTL", NULL, "DACL"}, | |
408 | {"OUTR", NULL, "DACR"}, | |
409 | ||
410 | /* inputs */ | |
411 | {"ADCL", NULL, "INL"}, | |
412 | {"ADCR", NULL, "INR"}, | |
413 | }; | |
414 | ||
415 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
416 | { | |
417 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
418 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
419 | ||
420 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
421 | ||
422 | snd_soc_dapm_new_widgets(codec); | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static void twl4030_power_up(struct snd_soc_codec *codec) | |
427 | { | |
428 | u8 anamicl, regmisc1, byte, popn, hsgain; | |
429 | int i = 0; | |
430 | ||
431 | /* set CODECPDZ to turn on codec */ | |
432 | twl4030_set_codecpdz(codec); | |
433 | ||
434 | /* initiate offset cancellation */ | |
435 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
436 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
437 | anamicl | TWL4030_CNCL_OFFSET_START); | |
438 | ||
439 | /* wait for offset cancellation to complete */ | |
440 | do { | |
441 | /* this takes a little while, so don't slam i2c */ | |
442 | udelay(2000); | |
443 | twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, | |
444 | TWL4030_REG_ANAMICL); | |
445 | } while ((i++ < 100) && | |
446 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
447 | TWL4030_CNCL_OFFSET_START)); | |
448 | ||
449 | /* anti-pop when changing analog gain */ | |
450 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
451 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
452 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
453 | ||
454 | /* toggle CODECPDZ as per TRM */ | |
455 | twl4030_clear_codecpdz(codec); | |
456 | twl4030_set_codecpdz(codec); | |
457 | ||
458 | /* program anti-pop with bias ramp delay */ | |
459 | popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
460 | popn &= TWL4030_RAMP_DELAY; | |
461 | popn |= TWL4030_RAMP_DELAY_645MS; | |
462 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); | |
463 | popn |= TWL4030_VMID_EN; | |
464 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); | |
465 | ||
466 | /* enable output stage and gain setting */ | |
467 | hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB; | |
468 | twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain); | |
469 | ||
470 | /* enable anti-pop ramp */ | |
471 | popn |= TWL4030_RAMP_EN; | |
472 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); | |
473 | } | |
474 | ||
475 | static void twl4030_power_down(struct snd_soc_codec *codec) | |
476 | { | |
477 | u8 popn, hsgain; | |
478 | ||
479 | /* disable anti-pop ramp */ | |
480 | popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
481 | popn &= ~TWL4030_RAMP_EN; | |
482 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); | |
483 | ||
484 | /* disable output stage and gain setting */ | |
485 | hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN; | |
486 | twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain); | |
487 | ||
488 | /* disable bias out */ | |
489 | popn &= ~TWL4030_VMID_EN; | |
490 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); | |
491 | ||
492 | /* power down */ | |
493 | twl4030_clear_codecpdz(codec); | |
494 | } | |
495 | ||
496 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, | |
497 | enum snd_soc_bias_level level) | |
498 | { | |
499 | switch (level) { | |
500 | case SND_SOC_BIAS_ON: | |
501 | twl4030_power_up(codec); | |
502 | break; | |
503 | case SND_SOC_BIAS_PREPARE: | |
504 | /* TODO: develop a twl4030_prepare function */ | |
505 | break; | |
506 | case SND_SOC_BIAS_STANDBY: | |
507 | /* TODO: develop a twl4030_standby function */ | |
508 | twl4030_power_down(codec); | |
509 | break; | |
510 | case SND_SOC_BIAS_OFF: | |
511 | twl4030_power_down(codec); | |
512 | break; | |
513 | } | |
514 | codec->bias_level = level; | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | static int twl4030_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
520 | struct snd_pcm_hw_params *params, |
521 | struct snd_soc_dai *dai) | |
cc17557e SS |
522 | { |
523 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
524 | struct snd_soc_device *socdev = rtd->socdev; | |
525 | struct snd_soc_codec *codec = socdev->codec; | |
526 | u8 mode, old_mode, format, old_format; | |
527 | ||
528 | ||
529 | /* bit rate */ | |
530 | old_mode = twl4030_read_reg_cache(codec, | |
531 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
532 | mode = old_mode & ~TWL4030_APLL_RATE; | |
533 | ||
534 | switch (params_rate(params)) { | |
535 | case 8000: | |
536 | mode |= TWL4030_APLL_RATE_8000; | |
537 | break; | |
538 | case 11025: | |
539 | mode |= TWL4030_APLL_RATE_11025; | |
540 | break; | |
541 | case 12000: | |
542 | mode |= TWL4030_APLL_RATE_12000; | |
543 | break; | |
544 | case 16000: | |
545 | mode |= TWL4030_APLL_RATE_16000; | |
546 | break; | |
547 | case 22050: | |
548 | mode |= TWL4030_APLL_RATE_22050; | |
549 | break; | |
550 | case 24000: | |
551 | mode |= TWL4030_APLL_RATE_24000; | |
552 | break; | |
553 | case 32000: | |
554 | mode |= TWL4030_APLL_RATE_32000; | |
555 | break; | |
556 | case 44100: | |
557 | mode |= TWL4030_APLL_RATE_44100; | |
558 | break; | |
559 | case 48000: | |
560 | mode |= TWL4030_APLL_RATE_48000; | |
561 | break; | |
562 | default: | |
563 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
564 | params_rate(params)); | |
565 | return -EINVAL; | |
566 | } | |
567 | ||
568 | if (mode != old_mode) { | |
569 | /* change rate and set CODECPDZ */ | |
570 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
571 | twl4030_set_codecpdz(codec); | |
572 | } | |
573 | ||
574 | /* sample size */ | |
575 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
576 | format = old_format; | |
577 | format &= ~TWL4030_DATA_WIDTH; | |
578 | switch (params_format(params)) { | |
579 | case SNDRV_PCM_FORMAT_S16_LE: | |
580 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
581 | break; | |
582 | case SNDRV_PCM_FORMAT_S24_LE: | |
583 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
584 | break; | |
585 | default: | |
586 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
587 | params_format(params)); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | if (format != old_format) { | |
592 | ||
593 | /* clear CODECPDZ before changing format (codec requirement) */ | |
594 | twl4030_clear_codecpdz(codec); | |
595 | ||
596 | /* change format */ | |
597 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
598 | ||
599 | /* set CODECPDZ afterwards */ | |
600 | twl4030_set_codecpdz(codec); | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | ||
605 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
606 | int clk_id, unsigned int freq, int dir) | |
607 | { | |
608 | struct snd_soc_codec *codec = codec_dai->codec; | |
609 | u8 infreq; | |
610 | ||
611 | switch (freq) { | |
612 | case 19200000: | |
613 | infreq = TWL4030_APLL_INFREQ_19200KHZ; | |
614 | break; | |
615 | case 26000000: | |
616 | infreq = TWL4030_APLL_INFREQ_26000KHZ; | |
617 | break; | |
618 | case 38400000: | |
619 | infreq = TWL4030_APLL_INFREQ_38400KHZ; | |
620 | break; | |
621 | default: | |
622 | printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", | |
623 | freq); | |
624 | return -EINVAL; | |
625 | } | |
626 | ||
627 | infreq |= TWL4030_APLL_EN; | |
628 | twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
634 | unsigned int fmt) | |
635 | { | |
636 | struct snd_soc_codec *codec = codec_dai->codec; | |
637 | u8 old_format, format; | |
638 | ||
639 | /* get format */ | |
640 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
641 | format = old_format; | |
642 | ||
643 | /* set master/slave audio interface */ | |
644 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
645 | case SND_SOC_DAIFMT_CBM_CFM: | |
646 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 647 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
648 | break; |
649 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 650 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 651 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
652 | break; |
653 | default: | |
654 | return -EINVAL; | |
655 | } | |
656 | ||
657 | /* interface format */ | |
658 | format &= ~TWL4030_AIF_FORMAT; | |
659 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
660 | case SND_SOC_DAIFMT_I2S: | |
661 | format |= TWL4030_AIF_FORMAT_CODEC; | |
662 | break; | |
663 | default: | |
664 | return -EINVAL; | |
665 | } | |
666 | ||
667 | if (format != old_format) { | |
668 | ||
669 | /* clear CODECPDZ before changing format (codec requirement) */ | |
670 | twl4030_clear_codecpdz(codec); | |
671 | ||
672 | /* change format */ | |
673 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
674 | ||
675 | /* set CODECPDZ afterwards */ | |
676 | twl4030_set_codecpdz(codec); | |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
bbba9444 | 682 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
683 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
684 | ||
685 | struct snd_soc_dai twl4030_dai = { | |
686 | .name = "twl4030", | |
687 | .playback = { | |
688 | .stream_name = "Playback", | |
689 | .channels_min = 2, | |
690 | .channels_max = 2, | |
691 | .rates = TWL4030_RATES, | |
692 | .formats = TWL4030_FORMATS,}, | |
693 | .capture = { | |
694 | .stream_name = "Capture", | |
695 | .channels_min = 2, | |
696 | .channels_max = 2, | |
697 | .rates = TWL4030_RATES, | |
698 | .formats = TWL4030_FORMATS,}, | |
699 | .ops = { | |
700 | .hw_params = twl4030_hw_params, | |
cc17557e SS |
701 | .set_sysclk = twl4030_set_dai_sysclk, |
702 | .set_fmt = twl4030_set_dai_fmt, | |
703 | } | |
704 | }; | |
705 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
706 | ||
707 | static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) | |
708 | { | |
709 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
710 | struct snd_soc_codec *codec = socdev->codec; | |
711 | ||
712 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | static int twl4030_resume(struct platform_device *pdev) | |
718 | { | |
719 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
720 | struct snd_soc_codec *codec = socdev->codec; | |
721 | ||
722 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
723 | twl4030_set_bias_level(codec, codec->suspend_bias_level); | |
724 | return 0; | |
725 | } | |
726 | ||
727 | /* | |
728 | * initialize the driver | |
729 | * register the mixer and dsp interfaces with the kernel | |
730 | */ | |
731 | ||
732 | static int twl4030_init(struct snd_soc_device *socdev) | |
733 | { | |
734 | struct snd_soc_codec *codec = socdev->codec; | |
735 | int ret = 0; | |
736 | ||
737 | printk(KERN_INFO "TWL4030 Audio Codec init \n"); | |
738 | ||
739 | codec->name = "twl4030"; | |
740 | codec->owner = THIS_MODULE; | |
741 | codec->read = twl4030_read_reg_cache; | |
742 | codec->write = twl4030_write; | |
743 | codec->set_bias_level = twl4030_set_bias_level; | |
744 | codec->dai = &twl4030_dai; | |
745 | codec->num_dai = 1; | |
746 | codec->reg_cache_size = sizeof(twl4030_reg); | |
747 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
748 | GFP_KERNEL); | |
749 | if (codec->reg_cache == NULL) | |
750 | return -ENOMEM; | |
751 | ||
752 | /* register pcms */ | |
753 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
754 | if (ret < 0) { | |
755 | printk(KERN_ERR "twl4030: failed to create pcms\n"); | |
756 | goto pcm_err; | |
757 | } | |
758 | ||
759 | twl4030_init_chip(codec); | |
760 | ||
761 | /* power on device */ | |
762 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
763 | ||
764 | twl4030_add_controls(codec); | |
765 | twl4030_add_widgets(codec); | |
766 | ||
968a6025 | 767 | ret = snd_soc_init_card(socdev); |
cc17557e SS |
768 | if (ret < 0) { |
769 | printk(KERN_ERR "twl4030: failed to register card\n"); | |
770 | goto card_err; | |
771 | } | |
772 | ||
773 | return ret; | |
774 | ||
775 | card_err: | |
776 | snd_soc_free_pcms(socdev); | |
777 | snd_soc_dapm_free(socdev); | |
778 | pcm_err: | |
779 | kfree(codec->reg_cache); | |
780 | return ret; | |
781 | } | |
782 | ||
783 | static struct snd_soc_device *twl4030_socdev; | |
784 | ||
785 | static int twl4030_probe(struct platform_device *pdev) | |
786 | { | |
787 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
788 | struct snd_soc_codec *codec; | |
789 | ||
790 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | |
791 | if (codec == NULL) | |
792 | return -ENOMEM; | |
793 | ||
794 | socdev->codec = codec; | |
795 | mutex_init(&codec->mutex); | |
796 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
797 | INIT_LIST_HEAD(&codec->dapm_paths); | |
798 | ||
799 | twl4030_socdev = socdev; | |
800 | twl4030_init(socdev); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | static int twl4030_remove(struct platform_device *pdev) | |
806 | { | |
807 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
808 | struct snd_soc_codec *codec = socdev->codec; | |
809 | ||
810 | printk(KERN_INFO "TWL4030 Audio Codec remove\n"); | |
811 | kfree(codec); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { | |
817 | .probe = twl4030_probe, | |
818 | .remove = twl4030_remove, | |
819 | .suspend = twl4030_suspend, | |
820 | .resume = twl4030_resume, | |
821 | }; | |
822 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
823 | ||
824 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); | |
825 | MODULE_AUTHOR("Steve Sakoman"); | |
826 | MODULE_LICENSE("GPL"); |