Commit | Line | Data |
---|---|---|
cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __TWL4030_AUDIO_H__ | |
23 | #define __TWL4030_AUDIO_H__ | |
24 | ||
25 | #define TWL4030_REG_CODEC_MODE 0x1 | |
26 | #define TWL4030_REG_OPTION 0x2 | |
27 | #define TWL4030_REG_UNKNOWN 0x3 | |
28 | #define TWL4030_REG_MICBIAS_CTL 0x4 | |
29 | #define TWL4030_REG_ANAMICL 0x5 | |
30 | #define TWL4030_REG_ANAMICR 0x6 | |
31 | #define TWL4030_REG_AVADC_CTL 0x7 | |
32 | #define TWL4030_REG_ADCMICSEL 0x8 | |
33 | #define TWL4030_REG_DIGMIXING 0x9 | |
34 | #define TWL4030_REG_ATXL1PGA 0xA | |
35 | #define TWL4030_REG_ATXR1PGA 0xB | |
36 | #define TWL4030_REG_AVTXL2PGA 0xC | |
37 | #define TWL4030_REG_AVTXR2PGA 0xD | |
38 | #define TWL4030_REG_AUDIO_IF 0xE | |
39 | #define TWL4030_REG_VOICE_IF 0xF | |
40 | #define TWL4030_REG_ARXR1PGA 0x10 | |
41 | #define TWL4030_REG_ARXL1PGA 0x11 | |
42 | #define TWL4030_REG_ARXR2PGA 0x12 | |
43 | #define TWL4030_REG_ARXL2PGA 0x13 | |
44 | #define TWL4030_REG_VRXPGA 0x14 | |
45 | #define TWL4030_REG_VSTPGA 0x15 | |
46 | #define TWL4030_REG_VRX2ARXPGA 0x16 | |
47 | #define TWL4030_REG_AVDAC_CTL 0x17 | |
48 | #define TWL4030_REG_ARX2VTXPGA 0x18 | |
49 | #define TWL4030_REG_ARXL1_APGA_CTL 0x19 | |
50 | #define TWL4030_REG_ARXR1_APGA_CTL 0x1A | |
51 | #define TWL4030_REG_ARXL2_APGA_CTL 0x1B | |
52 | #define TWL4030_REG_ARXR2_APGA_CTL 0x1C | |
53 | #define TWL4030_REG_ATX2ARXPGA 0x1D | |
54 | #define TWL4030_REG_BT_IF 0x1E | |
55 | #define TWL4030_REG_BTPGA 0x1F | |
56 | #define TWL4030_REG_BTSTPGA 0x20 | |
57 | #define TWL4030_REG_EAR_CTL 0x21 | |
58 | #define TWL4030_REG_HS_SEL 0x22 | |
59 | #define TWL4030_REG_HS_GAIN_SET 0x23 | |
60 | #define TWL4030_REG_HS_POPN_SET 0x24 | |
61 | #define TWL4030_REG_PREDL_CTL 0x25 | |
62 | #define TWL4030_REG_PREDR_CTL 0x26 | |
63 | #define TWL4030_REG_PRECKL_CTL 0x27 | |
64 | #define TWL4030_REG_PRECKR_CTL 0x28 | |
65 | #define TWL4030_REG_HFL_CTL 0x29 | |
66 | #define TWL4030_REG_HFR_CTL 0x2A | |
67 | #define TWL4030_REG_ALC_CTL 0x2B | |
68 | #define TWL4030_REG_ALC_SET1 0x2C | |
69 | #define TWL4030_REG_ALC_SET2 0x2D | |
70 | #define TWL4030_REG_BOOST_CTL 0x2E | |
71 | #define TWL4030_REG_SOFTVOL_CTL 0x2F | |
72 | #define TWL4030_REG_DTMF_FREQSEL 0x30 | |
73 | #define TWL4030_REG_DTMF_TONEXT1H 0x31 | |
74 | #define TWL4030_REG_DTMF_TONEXT1L 0x32 | |
75 | #define TWL4030_REG_DTMF_TONEXT2H 0x33 | |
76 | #define TWL4030_REG_DTMF_TONEXT2L 0x34 | |
77 | #define TWL4030_REG_DTMF_TONOFF 0x35 | |
78 | #define TWL4030_REG_DTMF_WANONOFF 0x36 | |
79 | #define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 | |
80 | #define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 | |
81 | #define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 | |
82 | #define TWL4030_REG_APLL_CTL 0x3A | |
83 | #define TWL4030_REG_DTMF_CTL 0x3B | |
84 | #define TWL4030_REG_DTMF_PGA_CTL2 0x3C | |
85 | #define TWL4030_REG_DTMF_PGA_CTL1 0x3D | |
86 | #define TWL4030_REG_MISC_SET_1 0x3E | |
87 | #define TWL4030_REG_PCMBTMUX 0x3F | |
88 | #define TWL4030_REG_RX_PATH_SEL 0x43 | |
89 | #define TWL4030_REG_VDL_APGA_CTL 0x44 | |
90 | #define TWL4030_REG_VIBRA_CTL 0x45 | |
91 | #define TWL4030_REG_VIBRA_SET 0x46 | |
92 | #define TWL4030_REG_VIBRA_PWM_SET 0x47 | |
93 | #define TWL4030_REG_ANAMIC_GAIN 0x48 | |
94 | #define TWL4030_REG_MISC_SET_2 0x49 | |
95 | ||
96 | #define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1) | |
97 | ||
98 | /* Bitfield Definitions */ | |
99 | ||
100 | /* TWL4030_CODEC_MODE (0x01) Fields */ | |
101 | ||
102 | #define TWL4030_APLL_RATE 0xF0 | |
103 | #define TWL4030_APLL_RATE_8000 0x00 | |
104 | #define TWL4030_APLL_RATE_11025 0x10 | |
105 | #define TWL4030_APLL_RATE_12000 0x20 | |
106 | #define TWL4030_APLL_RATE_16000 0x40 | |
107 | #define TWL4030_APLL_RATE_22050 0x50 | |
108 | #define TWL4030_APLL_RATE_24000 0x60 | |
109 | #define TWL4030_APLL_RATE_32000 0x80 | |
110 | #define TWL4030_APLL_RATE_44100 0x90 | |
111 | #define TWL4030_APLL_RATE_48000 0xA0 | |
112 | #define TWL4030_SEL_16K 0x04 | |
113 | #define TWL4030_CODECPDZ 0x02 | |
114 | #define TWL4030_OPT_MODE 0x01 | |
115 | ||
5920b453 GI |
116 | /* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ |
117 | ||
118 | #define TWL4030_MICBIAS2_CTL 0x40 | |
119 | #define TWL4030_MICBIAS1_CTL 0x20 | |
120 | #define TWL4030_HSMICBIAS_EN 0x04 | |
121 | #define TWL4030_MICBIAS2_EN 0x02 | |
122 | #define TWL4030_MICBIAS1_EN 0x01 | |
123 | ||
cc17557e | 124 | /* ANAMICL (0x05) Fields */ |
5920b453 | 125 | |
cc17557e SS |
126 | #define TWL4030_CNCL_OFFSET_START 0x80 |
127 | #define TWL4030_OFFSET_CNCL_SEL 0x60 | |
128 | #define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 | |
129 | #define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 | |
130 | #define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 | |
131 | #define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 | |
132 | #define TWL4030_MICAMPL_EN 0x10 | |
133 | #define TWL4030_CKMIC_EN 0x08 | |
134 | #define TWL4030_AUXL_EN 0x04 | |
135 | #define TWL4030_HSMIC_EN 0x02 | |
136 | #define TWL4030_MAINMIC_EN 0x01 | |
137 | ||
138 | /* ANAMICR (0x06) Fields */ | |
5920b453 | 139 | |
cc17557e SS |
140 | #define TWL4030_MICAMPR_EN 0x10 |
141 | #define TWL4030_AUXR_EN 0x04 | |
142 | #define TWL4030_SUBMIC_EN 0x01 | |
143 | ||
5920b453 GI |
144 | /* AVADC_CTL (0x07) Fields */ |
145 | ||
146 | #define TWL4030_ADCL_EN 0x08 | |
147 | #define TWL4030_AVADC_CLK_PRIORITY 0x04 | |
148 | #define TWL4030_ADCR_EN 0x02 | |
149 | ||
276c6222 PU |
150 | /* TWL4030_REG_ADCMICSEL (0x08) Fields */ |
151 | ||
152 | #define TWL4030_DIGMIC1_EN 0x08 | |
153 | #define TWL4030_TX2IN_SEL 0x04 | |
154 | #define TWL4030_DIGMIC0_EN 0x02 | |
155 | #define TWL4030_TX1IN_SEL 0x01 | |
156 | ||
cc17557e SS |
157 | /* AUDIO_IF (0x0E) Fields */ |
158 | ||
159 | #define TWL4030_AIF_SLAVE_EN 0x80 | |
160 | #define TWL4030_DATA_WIDTH 0x60 | |
161 | #define TWL4030_DATA_WIDTH_16S_16W 0x00 | |
162 | #define TWL4030_DATA_WIDTH_32S_16W 0x40 | |
163 | #define TWL4030_DATA_WIDTH_32S_24W 0x60 | |
164 | #define TWL4030_AIF_FORMAT 0x18 | |
165 | #define TWL4030_AIF_FORMAT_CODEC 0x00 | |
166 | #define TWL4030_AIF_FORMAT_LEFT 0x08 | |
167 | #define TWL4030_AIF_FORMAT_RIGHT 0x10 | |
168 | #define TWL4030_AIF_FORMAT_TDM 0x18 | |
169 | #define TWL4030_AIF_TRI_EN 0x04 | |
170 | #define TWL4030_CLK256FS_EN 0x02 | |
171 | #define TWL4030_AIF_EN 0x01 | |
172 | ||
173 | /* HS_GAIN_SET (0x23) Fields */ | |
174 | ||
175 | #define TWL4030_HSR_GAIN 0x0C | |
176 | #define TWL4030_HSR_GAIN_PWR_DOWN 0x00 | |
177 | #define TWL4030_HSR_GAIN_PLUS_6DB 0x04 | |
178 | #define TWL4030_HSR_GAIN_0DB 0x08 | |
179 | #define TWL4030_HSR_GAIN_MINUS_6DB 0x0C | |
180 | #define TWL4030_HSL_GAIN 0x03 | |
181 | #define TWL4030_HSL_GAIN_PWR_DOWN 0x00 | |
182 | #define TWL4030_HSL_GAIN_PLUS_6DB 0x01 | |
183 | #define TWL4030_HSL_GAIN_0DB 0x02 | |
184 | #define TWL4030_HSL_GAIN_MINUS_6DB 0x03 | |
185 | ||
186 | /* HS_POPN_SET (0x24) Fields */ | |
187 | ||
188 | #define TWL4030_VMID_EN 0x40 | |
189 | #define TWL4030_EXTMUTE 0x20 | |
190 | #define TWL4030_RAMP_DELAY 0x1C | |
191 | #define TWL4030_RAMP_DELAY_20MS 0x00 | |
192 | #define TWL4030_RAMP_DELAY_40MS 0x04 | |
193 | #define TWL4030_RAMP_DELAY_81MS 0x08 | |
194 | #define TWL4030_RAMP_DELAY_161MS 0x0C | |
195 | #define TWL4030_RAMP_DELAY_323MS 0x10 | |
196 | #define TWL4030_RAMP_DELAY_645MS 0x14 | |
197 | #define TWL4030_RAMP_DELAY_1291MS 0x18 | |
198 | #define TWL4030_RAMP_DELAY_2581MS 0x1C | |
199 | #define TWL4030_RAMP_EN 0x02 | |
200 | ||
49d92c7d SM |
201 | /* HFL_CTL (0x29, 0x2A) Fields */ |
202 | #define TWL4030_HF_CTL_HB_EN 0x04 | |
203 | #define TWL4030_HF_CTL_LOOP_EN 0x08 | |
204 | #define TWL4030_HF_CTL_RAMP_EN 0x10 | |
205 | #define TWL4030_HF_CTL_REF_EN 0x20 | |
206 | ||
cc17557e SS |
207 | /* APLL_CTL (0x3A) Fields */ |
208 | ||
209 | #define TWL4030_APLL_EN 0x10 | |
210 | #define TWL4030_APLL_INFREQ 0x0F | |
211 | #define TWL4030_APLL_INFREQ_19200KHZ 0x05 | |
212 | #define TWL4030_APLL_INFREQ_26000KHZ 0x06 | |
213 | #define TWL4030_APLL_INFREQ_38400KHZ 0x0F | |
214 | ||
215 | /* REG_MISC_SET_1 (0x3E) Fields */ | |
216 | ||
217 | #define TWL4030_CLK64_EN 0x80 | |
218 | #define TWL4030_SCRAMBLE_EN 0x40 | |
219 | #define TWL4030_FMLOOP_EN 0x20 | |
220 | #define TWL4030_SMOOTH_ANAVOL_EN 0x02 | |
221 | #define TWL4030_DIGMIC_LR_SWAP_EN 0x01 | |
222 | ||
223 | extern struct snd_soc_dai twl4030_dai; | |
224 | extern struct snd_soc_codec_device soc_codec_dev_twl4030; | |
225 | ||
226 | #endif /* End of __TWL4030_AUDIO_H__ */ |