[deliverable/linux.git] / sound / soc / codecs / uda134x.c

/*
 * uda134x.c  --  UDA134X ALSA SoC Codec driver
 *
 * Modifications by Christian Pellegrin <chripell@evolware.org>
 *
 * Copyright 2007 Dension Audio Systems Ltd.
 * Author: Zoltan Devai
 *
 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>

#include <sound/uda134x.h>
#include <sound/l3.h>

#include "uda134x.h"


#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)

struct uda134x_priv {
	int sysclk;
	int dai_fmt;

	struct snd_pcm_substream *master_substream;
	struct snd_pcm_substream *slave_substream;

	struct regmap *regmap;
	struct uda134x_platform_data *pd;
};

static const struct reg_default uda134x_reg_defaults[] = {
	{ UDA134X_EA000, 0x04 },
	{ UDA134X_EA001, 0x04 },
	{ UDA134X_EA010, 0x04 },
	{ UDA134X_EA011, 0x00 },
	{ UDA134X_EA100, 0x00 },
	{ UDA134X_EA101, 0x00 },
	{ UDA134X_EA110, 0x00 },
	{ UDA134X_EA111, 0x00 },
	{ UDA134X_STATUS0, 0x00 },
	{ UDA134X_STATUS1, 0x03 },
	{ UDA134X_DATA000, 0x00 },
	{ UDA134X_DATA001, 0x00 },
	{ UDA134X_DATA010, 0x00 },
	{ UDA134X_DATA011, 0x00 },
	{ UDA134X_DATA1, 0x00 },
};

/*
 * Write to the uda134x registers
 *
 */
static int uda134x_regmap_write(void *context, unsigned int reg,
	unsigned int value)
{
	struct uda134x_platform_data *pd = context;
	int ret;
	u8 addr;
	u8 data = value;

	switch (reg) {
	case UDA134X_STATUS0:
	case UDA134X_STATUS1:
		addr = UDA134X_STATUS_ADDR;
		data |= (reg - UDA134X_STATUS0) << 7;
		break;
	case UDA134X_DATA000:
	case UDA134X_DATA001:
	case UDA134X_DATA010:
	case UDA134X_DATA011:
		addr = UDA134X_DATA0_ADDR;
		data |= (reg - UDA134X_DATA000) << 6;
		break;
	case UDA134X_DATA1:
		addr = UDA134X_DATA1_ADDR;
		break;
	default:
		/* It's an extended address register */
		addr =  (reg | UDA134X_EXTADDR_PREFIX);

		ret = l3_write(&pd->l3,
			       UDA134X_DATA0_ADDR, &addr, 1);
		if (ret != 1)
			return -EIO;

		addr = UDA134X_DATA0_ADDR;
		data = (value | UDA134X_EXTDATA_PREFIX);
		break;
	}

	ret = l3_write(&pd->l3,
		       addr, &data, 1);
	if (ret != 1)
		return -EIO;

	return 0;
}

static inline void uda134x_reset(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	unsigned int mask = 1<<6;

	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, mask);
	msleep(1);
	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, 0);
}

static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(dai->codec);
	unsigned int mask = 1<<2;
	unsigned int val;

	pr_debug("%s mute: %d\n", __func__, mute);

	if (mute)
		val = mask;
	else
		val = 0;

	return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val);
}

static int uda134x_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct snd_pcm_runtime *master_runtime;

	if (uda134x->master_substream) {
		master_runtime = uda134x->master_substream->runtime;

		pr_debug("%s constraining to %d bits at %d\n", __func__,
			 master_runtime->sample_bits,
			 master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_RATE,
					     master_runtime->rate,
					     master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     master_runtime->sample_bits,
					     master_runtime->sample_bits);

		uda134x->slave_substream = substream;
	} else
		uda134x->master_substream = substream;

	return 0;
}

static void uda134x_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	if (uda134x->master_substream == substream)
		uda134x->master_substream = uda134x->slave_substream;

	uda134x->slave_substream = NULL;
}

static int uda134x_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	unsigned int hw_params = 0;

	if (substream == uda134x->slave_substream) {
		pr_debug("%s ignoring hw_params for slave substream\n",
			 __func__);
		return 0;
	}

	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
		 uda134x->sysclk, params_rate(params));

	/* set SYSCLK / fs ratio */
	switch (uda134x->sysclk / params_rate(params)) {
	case 512:
		break;
	case 384:
		hw_params |= (1<<4);
		break;
	case 256:
		hw_params |= (1<<5);
		break;
	default:
		printk(KERN_ERR "%s unsupported fs\n", __func__);
		return -EINVAL;
	}

	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
		 uda134x->dai_fmt, params_format(params));

	/* set DAI format and word length */
	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		switch (params_width(params)) {
		case 16:
			hw_params |= (1<<1);
			break;
		case 18:
			hw_params |= (1<<2);
			break;
		case 20:
			hw_params |= ((1<<2) | (1<<1));
			break;
		default:
			printk(KERN_ERR "%s unsupported format (right)\n",
			       __func__);
			return -EINVAL;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		hw_params |= (1<<3);
		break;
	default:
		printk(KERN_ERR "%s unsupported format\n", __func__);
		return -EINVAL;
	}

	return regmap_update_bits(uda134x->regmap, UDA134X_STATUS0,
		STATUS0_SYSCLK_MASK | STATUS0_DAIFMT_MASK, hw_params);
}

static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
		 clk_id, freq, dir);

	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
	   because the codec is slave. Of course limitations of the clock
	   master (the IIS controller) apply.
	   We'll error out on set_hw_params if it's not OK */
	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
		uda134x->sysclk = freq;
		return 0;
	}

	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	return -EINVAL;
}

static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
			       unsigned int fmt)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s fmt: %08X\n", __func__, fmt);

	/* codec supports only full slave mode */
	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
		return -EINVAL;
	}

	/* no support for clock inversion */
	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
		return -EINVAL;
	}

	/* We can't setup DAI format here as it depends on the word bit num */
	/* so let's just store the value for later */
	uda134x->dai_fmt = fmt;

	return 0;
}

static int uda134x_set_bias_level(struct snd_soc_codec *codec,
				  enum snd_soc_bias_level level)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct uda134x_platform_data *pd = uda134x->pd;
	pr_debug("%s bias level %d\n", __func__, level);

	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		/* power on */
		if (pd->power) {
			pd->power(1);
			regcache_sync(uda134x->regmap);
		}
		break;
	case SND_SOC_BIAS_STANDBY:
		break;
	case SND_SOC_BIAS_OFF:
		/* power off */
		if (pd->power) {
			pd->power(0);
			regcache_mark_dirty(uda134x->regmap);
		}
		break;
	}
	return 0;
}

static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
					    "Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
					"Analog2", "Both"};

static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};

static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),

SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),

SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),

SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1345_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

/* UDA1341 has the DAC/ADC power down in STATUS1 */
static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
};

/* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
};

/* Common DAPM widgets */
static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
	SND_SOC_DAPM_INPUT("VINL1"),
	SND_SOC_DAPM_INPUT("VINR1"),
	SND_SOC_DAPM_INPUT("VINL2"),
	SND_SOC_DAPM_INPUT("VINR2"),
	SND_SOC_DAPM_OUTPUT("VOUTL"),
	SND_SOC_DAPM_OUTPUT("VOUTR"),
};

static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
	{ "ADC", NULL, "VINL1" },
	{ "ADC", NULL, "VINR1" },
	{ "ADC", NULL, "VINL2" },
	{ "ADC", NULL, "VINR2" },
	{ "VOUTL", NULL, "DAC" },
	{ "VOUTR", NULL, "DAC" },
};

static const struct snd_soc_dai_ops uda134x_dai_ops = {
	.startup	= uda134x_startup,
	.shutdown	= uda134x_shutdown,
	.hw_params	= uda134x_hw_params,
	.digital_mute	= uda134x_mute,
	.set_sysclk	= uda134x_set_dai_sysclk,
	.set_fmt	= uda134x_set_dai_fmt,
};

static struct snd_soc_dai_driver uda134x_dai = {
	.name = "uda134x-hifi",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* capture capabilities */
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* pcm operations */
	.ops = &uda134x_dai_ops,
};

static int uda134x_soc_probe(struct snd_soc_codec *codec)
{
	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct uda134x_platform_data *pd = uda134x->pd;
	const struct snd_soc_dapm_widget *widgets;
	unsigned num_widgets;
	int ret;

	printk(KERN_INFO "UDA134X SoC Audio Codec\n");

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1341:
	case UDA134X_UDA1344:
	case UDA134X_UDA1345:
		break;
	default:
		printk(KERN_ERR "UDA134X SoC codec: "
		       "unsupported model %d\n",
			pd->model);
		return -EINVAL;
	}

	if (pd->power)
		pd->power(1);

	uda134x_reset(codec);

	if (pd->model == UDA134X_UDA1341) {
		widgets = uda1341_dapm_widgets;
		num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
	} else {
		widgets = uda1340_dapm_widgets;
		num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
	}

	ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
	if (ret) {
		printk(KERN_ERR "%s failed to register dapm controls: %d",
			__func__, ret);
		return ret;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1344:
		ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
					ARRAY_SIZE(uda1340_snd_controls));
	break;
	case UDA134X_UDA1341:
		ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
					ARRAY_SIZE(uda1341_snd_controls));
	break;
	case UDA134X_UDA1345:
		ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
					ARRAY_SIZE(uda1345_snd_controls));
	break;
	default:
		printk(KERN_ERR "%s unknown codec type: %d",
			__func__, pd->model);
		return -EINVAL;
	}

	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register controls\n");
		return ret;
	}

	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
	.probe =        uda134x_soc_probe,
	.set_bias_level = uda134x_set_bias_level,
	.suspend_bias_off = true,

	.dapm_widgets = uda134x_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
	.dapm_routes = uda134x_dapm_routes,
	.num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
};

static const struct regmap_config uda134x_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = UDA134X_DATA1,
	.reg_defaults = uda134x_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(uda134x_reg_defaults),
	.cache_type = REGCACHE_RBTREE,

	.reg_write = uda134x_regmap_write,
};

static int uda134x_codec_probe(struct platform_device *pdev)
{
	struct uda134x_platform_data *pd = pdev->dev.platform_data;
	struct uda134x_priv *uda134x;

	if (!pd) {
		dev_err(&pdev->dev, "Missing L3 bitbang function\n");
		return -ENODEV;
	}

	uda134x = devm_kzalloc(&pdev->dev, sizeof(*uda134x), GFP_KERNEL);
	if (!uda134x)
		return -ENOMEM;

	uda134x->pd = pd;
	platform_set_drvdata(pdev, uda134x);

	uda134x->regmap = devm_regmap_init(&pdev->dev, NULL, pd,
		&uda134x_regmap_config);
	if (IS_ERR(uda134x->regmap))
		return PTR_ERR(uda134x->regmap);

	return snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_uda134x, &uda134x_dai, 1);
}

static int uda134x_codec_remove(struct platform_device *pdev)
{
	snd_soc_unregister_codec(&pdev->dev);
	return 0;
}

static struct platform_driver uda134x_codec_driver = {
	.driver = {
		.name = "uda134x-codec",
	},
	.probe = uda134x_codec_probe,
	.remove = uda134x_codec_remove,
};

module_platform_driver(uda134x_codec_driver);

MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1cad1de1 CP	1	/*
	2	* uda134x.c -- UDA134X ALSA SoC Codec driver
	3	*
	4	* Modifications by Christian Pellegrin <chripell@evolware.org>
	5	*
	6	* Copyright 2007 Dension Audio Systems Ltd.
	7	* Author: Zoltan Devai
	8	*
	9	* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/delay.h>
5a0e3ad6	18	#include <linux/slab.h>
1cad1de1 CP	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
1cad1de1 CP	22	#include <sound/initval.h>
	23
	24	#include <sound/uda134x.h>
	25	#include <sound/l3.h>
	26
72f2b894	27	#include "uda134x.h"
1cad1de1 CP	28
1cad1de1 CP	29
1cad1de1 CP	30	#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
	31	#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE \| \
	32	SNDRV_PCM_FMTBIT_S18_3LE \| SNDRV_PCM_FMTBIT_S20_3LE)
	33
	34	struct uda134x_priv {
	35	int sysclk;
	36	int dai_fmt;
	37
	38	struct snd_pcm_substream *master_substream;
	39	struct snd_pcm_substream *slave_substream;
f33c340a LPC	40
	41	struct regmap *regmap;
	42	struct uda134x_platform_data *pd;
1cad1de1 CP	43	};
1cad1de1 CP	44
f33c340a LPC	45	static const struct reg_default uda134x_reg_defaults[] = {
	46	{ UDA134X_EA000, 0x04 },
	47	{ UDA134X_EA001, 0x04 },
	48	{ UDA134X_EA010, 0x04 },
	49	{ UDA134X_EA011, 0x00 },
	50	{ UDA134X_EA100, 0x00 },
	51	{ UDA134X_EA101, 0x00 },
	52	{ UDA134X_EA110, 0x00 },
	53	{ UDA134X_EA111, 0x00 },
	54	{ UDA134X_STATUS0, 0x00 },
	55	{ UDA134X_STATUS1, 0x03 },
	56	{ UDA134X_DATA000, 0x00 },
	57	{ UDA134X_DATA001, 0x00 },
	58	{ UDA134X_DATA010, 0x00 },
	59	{ UDA134X_DATA011, 0x00 },
	60	{ UDA134X_DATA1, 0x00 },
1cad1de1 CP	61	};
1cad1de1 CP	62
1cad1de1 CP	63	/*
	64	* Write to the uda134x registers
	65	*
	66	*/
f33c340a	67	static int uda134x_regmap_write(void *context, unsigned int reg,
1cad1de1 CP	68	unsigned int value)
1cad1de1 CP	69	{
f33c340a	70	struct uda134x_platform_data *pd = context;
1cad1de1 CP	71	int ret;
	72	u8 addr;
	73	u8 data = value;
1cad1de1 CP	74
	75	switch (reg) {
	76	case UDA134X_STATUS0:
	77	case UDA134X_STATUS1:
	78	addr = UDA134X_STATUS_ADDR;
82c7b531	79	data \|= (reg - UDA134X_STATUS0) << 7;
1cad1de1 CP	80	break;
	81	case UDA134X_DATA000:
	82	case UDA134X_DATA001:
	83	case UDA134X_DATA010:
ed632ad3	84	case UDA134X_DATA011:
1cad1de1	85	addr = UDA134X_DATA0_ADDR;
82c7b531	86	data \|= (reg - UDA134X_DATA000) << 6;
1cad1de1 CP	87	break;
	88	case UDA134X_DATA1:
	89	addr = UDA134X_DATA1_ADDR;
	90	break;
	91	default:
	92	/* It's an extended address register */
	93	addr = (reg \| UDA134X_EXTADDR_PREFIX);
	94
	95	ret = l3_write(&pd->l3,
	96	UDA134X_DATA0_ADDR, &addr, 1);
	97	if (ret != 1)
	98	return -EIO;
	99
	100	addr = UDA134X_DATA0_ADDR;
	101	data = (value \| UDA134X_EXTDATA_PREFIX);
	102	break;
	103	}
	104
	105	ret = l3_write(&pd->l3,
	106	addr, &data, 1);
	107	if (ret != 1)
	108	return -EIO;
	109
	110	return 0;
	111	}
	112
	113	static inline void uda134x_reset(struct snd_soc_codec *codec)
	114	{
ef3355d2 LPC	115	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	116	unsigned int mask = 1<<6;
	117
	118	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, mask);
1cad1de1	119	msleep(1);
ef3355d2	120	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, 0);
1cad1de1 CP	121	}
	122
	123	static int uda134x_mute(struct snd_soc_dai *dai, int mute)
	124	{
ef3355d2 LPC	125	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(dai->codec);
	126	unsigned int mask = 1<<2;
	127	unsigned int val;
1cad1de1 CP	128
	129	pr_debug("%s mute: %d\n", __func__, mute);
	130
	131	if (mute)
ef3355d2	132	val = mask;
1cad1de1	133	else
ef3355d2	134	val = 0;
1cad1de1	135
ef3355d2	136	return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val);
1cad1de1 CP	137	}
1cad1de1 CP	138
dee89c4d MB	139	static int uda134x_startup(struct snd_pcm_substream *substream,
dee89c4d MB	140	struct snd_soc_dai *dai)
1cad1de1	141	{
e6968a17	142	struct snd_soc_codec *codec = dai->codec;
b2c812e2	143	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	144	struct snd_pcm_runtime *master_runtime;
	145
	146	if (uda134x->master_substream) {
	147	master_runtime = uda134x->master_substream->runtime;
	148
	149	pr_debug("%s constraining to %d bits at %d\n", __func__,
	150	master_runtime->sample_bits,
	151	master_runtime->rate);
	152
	153	snd_pcm_hw_constraint_minmax(substream->runtime,
	154	SNDRV_PCM_HW_PARAM_RATE,
	155	master_runtime->rate,
	156	master_runtime->rate);
	157
	158	snd_pcm_hw_constraint_minmax(substream->runtime,
	159	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
	160	master_runtime->sample_bits,
	161	master_runtime->sample_bits);
	162
	163	uda134x->slave_substream = substream;
	164	} else
	165	uda134x->master_substream = substream;
	166
	167	return 0;
	168	}
	169
dee89c4d MB	170	static void uda134x_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	171	struct snd_soc_dai *dai)
1cad1de1	172	{
e6968a17	173	struct snd_soc_codec *codec = dai->codec;
b2c812e2	174	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	175
	176	if (uda134x->master_substream == substream)
	177	uda134x->master_substream = uda134x->slave_substream;
	178
	179	uda134x->slave_substream = NULL;
	180	}
	181
	182	static int uda134x_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	183	struct snd_pcm_hw_params *params,
dee89c4d MB	184	struct snd_soc_dai *dai)
1cad1de1	185	{
ab64246c	186	struct snd_soc_codec *codec = dai->codec;
b2c812e2	187	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
ef3355d2	188	unsigned int hw_params = 0;
1cad1de1 CP	189
	190	if (substream == uda134x->slave_substream) {
	191	pr_debug("%s ignoring hw_params for slave substream\n",
	192	__func__);
	193	return 0;
	194	}
	195
1cad1de1 CP	196	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
	197	uda134x->sysclk, params_rate(params));
	198
	199	/* set SYSCLK / fs ratio */
	200	switch (uda134x->sysclk / params_rate(params)) {
	201	case 512:
	202	break;
	203	case 384:
	204	hw_params \|= (1<<4);
	205	break;
	206	case 256:
	207	hw_params \|= (1<<5);
	208	break;
	209	default:
	210	printk(KERN_ERR "%s unsupported fs\n", __func__);
	211	return -EINVAL;
	212	}
	213
	214	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
	215	uda134x->dai_fmt, params_format(params));
	216
	217	/* set DAI format and word length */
	218	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	219	case SND_SOC_DAIFMT_I2S:
	220	break;
	221	case SND_SOC_DAIFMT_RIGHT_J:
aa9ffad6 MB	222	switch (params_width(params)) {
aa9ffad6 MB	223	case 16:
1cad1de1 CP	224	hw_params \|= (1<<1);
1cad1de1 CP	225	break;
aa9ffad6	226	case 18:
1cad1de1 CP	227	hw_params \|= (1<<2);
1cad1de1 CP	228	break;
aa9ffad6	229	case 20:
1cad1de1 CP	230	hw_params \|= ((1<<2) \| (1<<1));
	231	break;
	232	default:
	233	printk(KERN_ERR "%s unsupported format (right)\n",
	234	__func__);
	235	return -EINVAL;
	236	}
	237	break;
	238	case SND_SOC_DAIFMT_LEFT_J:
	239	hw_params \|= (1<<3);
	240	break;
	241	default:
	242	printk(KERN_ERR "%s unsupported format\n", __func__);
	243	return -EINVAL;
	244	}
	245
ef3355d2 LPC	246	return regmap_update_bits(uda134x->regmap, UDA134X_STATUS0,
ef3355d2 LPC	247	STATUS0_SYSCLK_MASK \| STATUS0_DAIFMT_MASK, hw_params);
1cad1de1 CP	248	}
	249
	250	static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
	251	int clk_id, unsigned int freq, int dir)
	252	{
	253	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	254	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	255
449bd54d	256	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
1cad1de1 CP	257	clk_id, freq, dir);
	258
	259	/* Anything between 256fs8Khz and 512fs48Khz should be acceptable
	260	because the codec is slave. Of course limitations of the clock
	261	master (the IIS controller) apply.
	262	We'll error out on set_hw_params if it's not OK */
	263	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
	264	uda134x->sysclk = freq;
	265	return 0;
	266	}
	267
	268	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	269	return -EINVAL;
	270	}
	271
	272	static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
	273	unsigned int fmt)
	274	{
	275	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	276	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	277
	278	pr_debug("%s fmt: %08X\n", __func__, fmt);
	279
	280	/* codec supports only full slave mode */
	281	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
	282	printk(KERN_ERR "%s unsupported slave mode\n", __func__);
	283	return -EINVAL;
	284	}
	285
	286	/* no support for clock inversion */
	287	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
	288	printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
	289	return -EINVAL;
	290	}
	291
	292	/* We can't setup DAI format here as it depends on the word bit num */
	293	/* so let's just store the value for later */
	294	uda134x->dai_fmt = fmt;
	295
	296	return 0;
	297	}
	298
	299	static int uda134x_set_bias_level(struct snd_soc_codec *codec,
	300	enum snd_soc_bias_level level)
	301	{
f33c340a LPC	302	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
f33c340a LPC	303	struct uda134x_platform_data *pd = uda134x->pd;
1cad1de1 CP	304	pr_debug("%s bias level %d\n", __func__, level);
	305
	306	switch (level) {
	307	case SND_SOC_BIAS_ON:
1cad1de1 CP	308	break;
	309	case SND_SOC_BIAS_PREPARE:
	310	/* power on */
	311	if (pd->power) {
	312	pd->power(1);
f33c340a	313	regcache_sync(uda134x->regmap);
1cad1de1 CP	314	}
	315	break;
	316	case SND_SOC_BIAS_STANDBY:
1cad1de1 CP	317	break;
	318	case SND_SOC_BIAS_OFF:
	319	/* power off */
f33c340a	320	if (pd->power) {
1cad1de1	321	pd->power(0);
f33c340a LPC	322	regcache_mark_dirty(uda134x->regmap);
f33c340a LPC	323	}
1cad1de1 CP	324	break;
1cad1de1 CP	325	}
1cad1de1 CP	326	return 0;
	327	}
	328
	329	static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
	330	"Minimum2", "Maximum"};
	331	static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
	332	static const char *uda134x_mixmode[] = {"Differential", "Analog1",
	333	"Analog2", "Both"};
	334
	335	static const struct soc_enum uda134x_mixer_enum[] = {
	336	SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
	337	SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
	338	SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
	339	};
	340
	341	static const struct snd_kcontrol_new uda1341_snd_controls[] = {
	342	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	343	SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
	344	SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
	345	SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
	346
	347	SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
	348	SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
	349
	350	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	351	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	352
	353	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	354	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	355	SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
	356
	357	SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
	358	SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
	359	SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
	360
	361	SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
	362	SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
	363	SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
	364	SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
	365	SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
	366	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	367	};
	368
	369	static const struct snd_kcontrol_new uda1340_snd_controls[] = {
	370	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	371
	372	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	373	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	374
	375	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	376	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	377
	378	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	379	};
	380
b28528a1 VZ	381	static const struct snd_kcontrol_new uda1345_snd_controls[] = {
	382	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	383
	384	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	385
	386	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	387	};
	388
113591e4 RK	389	/* UDA1341 has the DAC/ADC power down in STATUS1 */
	390	static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
	391	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
	392	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
	393	};
	394
	395	/* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
	396	static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
	397	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
	398	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
	399	};
	400
	401	/* Common DAPM widgets */
	402	static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
	403	SND_SOC_DAPM_INPUT("VINL1"),
	404	SND_SOC_DAPM_INPUT("VINR1"),
	405	SND_SOC_DAPM_INPUT("VINL2"),
	406	SND_SOC_DAPM_INPUT("VINR2"),
	407	SND_SOC_DAPM_OUTPUT("VOUTL"),
	408	SND_SOC_DAPM_OUTPUT("VOUTR"),
	409	};
	410
	411	static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
	412	{ "ADC", NULL, "VINL1" },
	413	{ "ADC", NULL, "VINR1" },
	414	{ "ADC", NULL, "VINL2" },
	415	{ "ADC", NULL, "VINR2" },
	416	{ "VOUTL", NULL, "DAC" },
	417	{ "VOUTR", NULL, "DAC" },
	418	};
	419
85e7652d	420	static const struct snd_soc_dai_ops uda134x_dai_ops = {
6335d055 EM	421	.startup = uda134x_startup,
	422	.shutdown = uda134x_shutdown,
	423	.hw_params = uda134x_hw_params,
	424	.digital_mute = uda134x_mute,
	425	.set_sysclk = uda134x_set_dai_sysclk,
	426	.set_fmt = uda134x_set_dai_fmt,
	427	};
	428
f0fba2ad LG	429	static struct snd_soc_dai_driver uda134x_dai = {
f0fba2ad LG	430	.name = "uda134x-hifi",
1cad1de1 CP	431	/* playback capabilities */
	432	.playback = {
	433	.stream_name = "Playback",
	434	.channels_min = 1,
	435	.channels_max = 2,
	436	.rates = UDA134X_RATES,
	437	.formats = UDA134X_FORMATS,
	438	},
	439	/* capture capabilities */
	440	.capture = {
	441	.stream_name = "Capture",
	442	.channels_min = 1,
	443	.channels_max = 2,
	444	.rates = UDA134X_RATES,
	445	.formats = UDA134X_FORMATS,
	446	},
	447	/* pcm operations */
6335d055	448	.ops = &uda134x_dai_ops,
1cad1de1	449	};
1cad1de1	450
f0fba2ad	451	static int uda134x_soc_probe(struct snd_soc_codec *codec)
1cad1de1	452	{
81024b11	453	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f15c444e	454	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
f33c340a	455	struct uda134x_platform_data *pd = uda134x->pd;
113591e4 RK	456	const struct snd_soc_dapm_widget *widgets;
113591e4 RK	457	unsigned num_widgets;
f0fba2ad	458	int ret;
1cad1de1 CP	459
	460	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
	461
1cad1de1 CP	462	switch (pd->model) {
	463	case UDA134X_UDA1340:
	464	case UDA134X_UDA1341:
	465	case UDA134X_UDA1344:
b28528a1	466	case UDA134X_UDA1345:
1cad1de1 CP	467	break;
	468	default:
	469	printk(KERN_ERR "UDA134X SoC codec: "
	470	"unsupported model %d\n",
	471	pd->model);
	472	return -EINVAL;
	473	}
	474
1cad1de1 CP	475	if (pd->power)
	476	pd->power(1);
	477
	478	uda134x_reset(codec);
	479
113591e4 RK	480	if (pd->model == UDA134X_UDA1341) {
	481	widgets = uda1341_dapm_widgets;
	482	num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
	483	} else {
	484	widgets = uda1340_dapm_widgets;
	485	num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
	486	}
	487
81024b11	488	ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
113591e4 RK	489	if (ret) {
	490	printk(KERN_ERR "%s failed to register dapm controls: %d",
	491	__func__, ret);
113591e4 RK	492	return ret;
	493	}
	494
3e8e1952 IM	495	switch (pd->model) {
	496	case UDA134X_UDA1340:
	497	case UDA134X_UDA1344:
022658be	498	ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
3e8e1952 IM	499	ARRAY_SIZE(uda1340_snd_controls));
	500	break;
	501	case UDA134X_UDA1341:
022658be	502	ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
3e8e1952 IM	503	ARRAY_SIZE(uda1341_snd_controls));
3e8e1952 IM	504	break;
b28528a1	505	case UDA134X_UDA1345:
022658be	506	ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
b28528a1 VZ	507	ARRAY_SIZE(uda1345_snd_controls));
b28528a1 VZ	508	break;
3e8e1952	509	default:
af901ca1	510	printk(KERN_ERR "%s unknown codec type: %d",
3e8e1952	511	__func__, pd->model);
f0fba2ad	512	return -EINVAL;
3e8e1952 IM	513	}
3e8e1952 IM	514
1cad1de1 CP	515	if (ret < 0) {
1cad1de1 CP	516	printk(KERN_ERR "UDA134X: failed to register controls\n");
f0fba2ad	517	return ret;
1cad1de1 CP	518	}
1cad1de1 CP	519
1cad1de1	520	return 0;
1cad1de1 CP	521	}
1cad1de1 CP	522
f0fba2ad	523	static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
1cad1de1	524	.probe = uda134x_soc_probe,
f0fba2ad	525	.set_bias_level = uda134x_set_bias_level,
e03b9755 LPC	526	.suspend_bias_off = true,
e03b9755 LPC	527
113591e4 RK	528	.dapm_widgets = uda134x_dapm_widgets,
	529	.num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
	530	.dapm_routes = uda134x_dapm_routes,
	531	.num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
f0fba2ad LG	532	};
f0fba2ad LG	533
f33c340a LPC	534	static const struct regmap_config uda134x_regmap_config = {
	535	.reg_bits = 8,
	536	.val_bits = 8,
	537	.max_register = UDA134X_DATA1,
	538	.reg_defaults = uda134x_reg_defaults,
	539	.num_reg_defaults = ARRAY_SIZE(uda134x_reg_defaults),
	540	.cache_type = REGCACHE_RBTREE,
	541
	542	.reg_write = uda134x_regmap_write,
	543	};
	544
7a79e94e	545	static int uda134x_codec_probe(struct platform_device *pdev)
f0fba2ad	546	{
f33c340a	547	struct uda134x_platform_data *pd = pdev->dev.platform_data;
f15c444e LPC	548	struct uda134x_priv *uda134x;
f15c444e LPC	549
f33c340a LPC	550	if (!pd) {
	551	dev_err(&pdev->dev, "Missing L3 bitbang function\n");
	552	return -ENODEV;
	553	}
	554
f15c444e LPC	555	uda134x = devm_kzalloc(&pdev->dev, sizeof(*uda134x), GFP_KERNEL);
	556	if (!uda134x)
	557	return -ENOMEM;
	558
f33c340a	559	uda134x->pd = pd;
f15c444e LPC	560	platform_set_drvdata(pdev, uda134x);
f15c444e LPC	561
f33c340a LPC	562	uda134x->regmap = devm_regmap_init(&pdev->dev, NULL, pd,
	563	&uda134x_regmap_config);
	564	if (IS_ERR(uda134x->regmap))
	565	return PTR_ERR(uda134x->regmap);
	566
f0fba2ad LG	567	return snd_soc_register_codec(&pdev->dev,
	568	&soc_codec_dev_uda134x, &uda134x_dai, 1);
	569	}
	570
7a79e94e	571	static int uda134x_codec_remove(struct platform_device *pdev)
f0fba2ad LG	572	{
	573	snd_soc_unregister_codec(&pdev->dev);
	574	return 0;
	575	}
	576
	577	static struct platform_driver uda134x_codec_driver = {
	578	.driver = {
	579	.name = "uda134x-codec",
f0fba2ad LG	580	},
f0fba2ad LG	581	.probe = uda134x_codec_probe,
7a79e94e	582	.remove = uda134x_codec_remove,
1cad1de1	583	};
1cad1de1	584
5bbcc3c0	585	module_platform_driver(uda134x_codec_driver);
64089b84	586
1cad1de1 CP	587	MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
	588	MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
	589	MODULE_LICENSE("GPL");